3 Sensoray s626 Comedi driver, header file
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 Driver: s626.o (s626.ko)
29 Description: Sensoray 626 driver
30 Devices: Sensoray s626
31 Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32 Updated: Thu, 12 Jul 2005
35 Configuration Options:
43 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
44 supported configuration options:
50 Every channel must be configured before reading.
54 insn.insn=INSN_CONFIG; // configuration instruction
55 insn.n=1; // number of operation (must be 1)
56 insn.data=&initialvalue; // initial value loaded into encoder
57 // during configuration
58 insn.subdev=5; // encoder subdevice
59 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); // encoder_channel
62 comedi_do_insn(cf,&insn); // executing configuration
73 #include <linux/slab.h>
75 #define S626_SIZE 0x0200
76 #define DMABUF_SIZE 4096 /* 4k pages */
78 #define S626_ADC_CHANNELS 16
79 #define S626_DAC_CHANNELS 4
80 #define S626_ENCODER_CHANNELS 6
81 #define S626_DIO_CHANNELS 48
82 #define S626_DIO_BANKS 3 /* Number of DIO groups. */
83 #define S626_DIO_EXTCHANS 40 /* Number of */
84 /* extended-capability */
87 #define NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */
89 /* PCI bus interface types. */
90 #define INTEL 1 /* Intel bus type. */
91 #define MOTOROLA 2 /* Motorola bus type. */
93 #define PLATFORM INTEL /* *** SELECT PLATFORM TYPE *** */
95 #define RANGE_5V 0x10 /* +/-5V range */
96 #define RANGE_10V 0x00 /* +/-10V range */
98 #define EOPL 0x80 /* End of ADC poll list marker. */
99 #define GSEL_BIPOLAR5V 0x00F0 /* LP_GSEL setting for 5V bipolar range. */
100 #define GSEL_BIPOLAR10V 0x00A0 /* LP_GSEL setting for 10V bipolar range. */
102 /* Error codes that must be visible to this base class. */
103 #define ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter value was specified. */
104 #define ERR_I2C 0x00020000 /* I2C error. */
105 #define ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for counter channel. */
106 #define ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */
108 /* Organization (physical order) and size (in DWORDs) of logical DMA buffers contained by ANA_DMABUF. */
109 #define ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, plus pre/post garbage samples. */
110 #define DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single sample. */
112 /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */
114 /* Address offsets, in DWORDS, from base of DMA buffer. */
115 #define DAC_WDMABUF_OS ADC_DMABUF_DWORDS
117 /* Interrupt enab bit in ISR and IER. */
118 #define IRQ_GPIO3 0x00000040 /* IRQ enable for GPIO3. */
119 #define IRQ_RPS1 0x10000000
120 #define ISR_AFOU 0x00000800
121 /* Audio fifo under/overflow detected. */
123 #define IRQ_COINT1A 0x0400 /* conter 1A overflow interrupt mask */
124 #define IRQ_COINT1B 0x0800 /* conter 1B overflow interrupt mask */
125 #define IRQ_COINT2A 0x1000 /* conter 2A overflow interrupt mask */
126 #define IRQ_COINT2B 0x2000 /* conter 2B overflow interrupt mask */
127 #define IRQ_COINT3A 0x4000 /* conter 3A overflow interrupt mask */
128 #define IRQ_COINT3B 0x8000 /* conter 3B overflow interrupt mask */
130 /* RPS command codes. */
131 #define RPS_CLRSIGNAL 0x00000000 /* CLEAR SIGNAL */
132 #define RPS_SETSIGNAL 0x10000000 /* SET SIGNAL */
133 #define RPS_NOP 0x00000000 /* NOP */
134 #define RPS_PAUSE 0x20000000 /* PAUSE */
135 #define RPS_UPLOAD 0x40000000 /* UPLOAD */
136 #define RPS_JUMP 0x80000000 /* JUMP */
137 #define RPS_LDREG 0x90000100 /* LDREG (1 uint32_t only) */
138 #define RPS_STREG 0xA0000100 /* STREG (1 uint32_t only) */
139 #define RPS_STOP 0x50000000 /* STOP */
140 #define RPS_IRQ 0x60000000 /* IRQ */
142 #define RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */
143 #define RPS_INVERT 0x04000000 /* Test for negated semaphores. */
144 #define RPS_DEBI 0x00000002 /* DEBI done */
146 #define RPS_SIG0 0x00200000 /* RPS semaphore 0 (used by ADC). */
147 #define RPS_SIG1 0x00400000 /* RPS semaphore 1 (used by DAC). */
148 #define RPS_SIG2 0x00800000 /* RPS semaphore 2 (not used). */
149 #define RPS_GPIO2 0x00080000 /* RPS GPIO2 */
150 #define RPS_GPIO3 0x00100000 /* RPS GPIO3 */
152 #define RPS_SIGADC RPS_SIG0 /* Trigger/status for ADC's RPS program. */
153 #define RPS_SIGDAC RPS_SIG1 /* Trigger/status for DAC's RPS program. */
155 /* RPS clock parameters. */
156 #define RPSCLK_SCALAR 8 /* This is apparent ratio of PCI/RPS clks (undocumented!!). */
157 #define RPSCLK_PER_US (33 / RPSCLK_SCALAR) /* Number of RPS clocks in one microsecond. */
159 /* Event counter source addresses. */
160 #define SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */
162 /* GPIO constants. */
163 #define GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out. */
164 #define GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */
165 #define GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */
167 /* Primary Status Register (PSR) constants. */
168 #define PSR_DEBI_E 0x00040000 /* DEBI event flag. */
169 #define PSR_DEBI_S 0x00080000 /* DEBI status flag. */
170 #define PSR_A2_IN 0x00008000 /* Audio output DMA2 protection address reached. */
171 #define PSR_AFOU 0x00000800 /* Audio FIFO under/overflow detected. */
172 #define PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, 1=AdcIdle. */
173 #define PSR_EC0S 0x00000001 /* Event counter 0 threshold reached. */
175 /* Secondary Status Register (SSR) constants. */
176 #define SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO under/overflow detected. */
178 /* Master Control Register 1 (MC1) constants. */
179 #define MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */
180 #define MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled enables. */
182 #define MC1_ERPS1 0x2000 /* enab/disable RPS task 1. */
183 #define MC1_ERPS0 0x1000 /* enab/disable RPS task 0. */
184 #define MC1_DEBI 0x0800 /* enab/disable DEBI pins. */
185 #define MC1_AUDIO 0x0200 /* enab/disable audio port pins. */
186 #define MC1_I2C 0x0100 /* enab/disable I2C interface. */
187 #define MC1_A2OUT 0x0008 /* enab/disable transfer on A2 out. */
188 #define MC1_A2IN 0x0004 /* enab/disable transfer on A2 in. */
189 #define MC1_A1IN 0x0001 /* enab/disable transfer on A1 in. */
191 /* Master Control Register 2 (MC2) constants. */
192 #define MC2_UPLD_DEBIq 0x00020002 /* Upload DEBI registers. */
193 #define MC2_UPLD_IICq 0x00010001 /* Upload I2C registers. */
194 #define MC2_RPSSIG2_ONq 0x20002000 /* Assert RPS_SIG2. */
195 #define MC2_RPSSIG1_ONq 0x10001000 /* Assert RPS_SIG1. */
196 #define MC2_RPSSIG0_ONq 0x08000800 /* Assert RPS_SIG0. */
197 #define MC2_UPLD_DEBI_MASKq 0x00000002 /* Upload DEBI mask. */
198 #define MC2_UPLD_IIC_MASKq 0x00000001 /* Upload I2C mask. */
199 #define MC2_RPSSIG2_MASKq 0x00002000 /* RPS_SIG2 bit mask. */
200 #define MC2_RPSSIG1_MASKq 0x00001000 /* RPS_SIG1 bit mask. */
201 #define MC2_RPSSIG0_MASKq 0x00000800 /* RPS_SIG0 bit mask. */
203 #define MC2_DELAYTRIG_4USq MC2_RPSSIG1_ON
204 #define MC2_DELAYBUSY_4USq MC2_RPSSIG1_MASK
206 #define MC2_DELAYTRIG_6USq MC2_RPSSIG2_ON
207 #define MC2_DELAYBUSY_6USq MC2_RPSSIG2_MASK
209 #define MC2_UPLD_DEBI 0x0002 /* Upload DEBI. */
210 #define MC2_UPLD_IIC 0x0001 /* Upload I2C. */
211 #define MC2_RPSSIG2 0x2000 /* RPS signal 2 (not used). */
212 #define MC2_RPSSIG1 0x1000 /* RPS signal 1 (DAC RPS busy). */
213 #define MC2_RPSSIG0 0x0800 /* RPS signal 0 (ADC RPS busy). */
215 #define MC2_ADC_RPS MC2_RPSSIG0 /* ADC RPS busy. */
216 #define MC2_DAC_RPS MC2_RPSSIG1 /* DAC RPS busy. */
218 /* ***** oldies ***** */
219 #define MC2_UPLD_DEBIQ 0x00020002 /* Upload DEBI registers. */
220 #define MC2_UPLD_IICQ 0x00010001 /* Upload I2C registers. */
222 /* PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS */
223 #define P_PCI_BT_A 0x004C /* Audio DMA burst/threshold control. */
224 #define P_DEBICFG 0x007C /* DEBI configuration. */
225 #define P_DEBICMD 0x0080 /* DEBI command. */
226 #define P_DEBIPAGE 0x0084 /* DEBI page. */
227 #define P_DEBIAD 0x0088 /* DEBI target address. */
228 #define P_I2CCTRL 0x008C /* I2C control. */
229 #define P_I2CSTAT 0x0090 /* I2C status. */
230 #define P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf
232 #define P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf
233 * protection address. */
234 #define P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */
235 #define P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf
237 #define P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf
238 * protection address. */
239 #define P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */
240 #define P_RPSPAGE0 0x00C4 /* RPS0 page. */
241 #define P_RPSPAGE1 0x00C8 /* RPS1 page. */
242 #define P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
243 #define P_RPS1_TOUT 0x00D8 /* RPS1 time-out. */
244 #define P_IER 0x00DC /* Interrupt enable. */
245 #define P_GPIO 0x00E0 /* General-purpose I/O. */
246 #define P_EC1SSR 0x00E4 /* Event counter set 1 source select. */
247 #define P_ECT1R 0x00EC /* Event counter threshold set 1. */
248 #define P_ACON1 0x00F4 /* Audio control 1. */
249 #define P_ACON2 0x00F8 /* Audio control 2. */
250 #define P_MC1 0x00FC /* Master control 1. */
251 #define P_MC2 0x0100 /* Master control 2. */
252 #define P_RPSADDR0 0x0104 /* RPS0 instruction pointer. */
253 #define P_RPSADDR1 0x0108 /* RPS1 instruction pointer. */
254 #define P_ISR 0x010C /* Interrupt status. */
255 #define P_PSR 0x0110 /* Primary status. */
256 #define P_SSR 0x0114 /* Secondary status. */
257 #define P_EC1R 0x0118 /* Event counter set 1. */
258 #define P_ADP4 0x0138 /* Logical audio DMA pointer of audio
259 * input FIFO A2_IN. */
260 #define P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */
261 #define P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */
262 #define P_TSL1 0x0180 /* Audio time slot list 1. */
263 #define P_TSL2 0x01C0 /* Audio time slot list 2. */
265 /* LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS */
266 /* Analog I/O registers: */
267 #define LP_DACPOL 0x0082 /* Write DAC polarity. */
268 #define LP_GSEL 0x0084 /* Write ADC gain. */
269 #define LP_ISEL 0x0086 /* Write ADC channel select. */
271 /* Digital I/O registers */
272 #define LP_RDDIN(x) (0x0040 + (x) * 0x10) /* R: digital input */
273 #define LP_WRINTSEL(x) (0x0042 + (x) * 0x10) /* W: int enable */
274 #define LP_WREDGSEL(x) (0x0044 + (x) * 0x10) /* W: edge selection */
275 #define LP_WRCAPSEL(x) (0x0046 + (x) * 0x10) /* W: capture enable */
276 #define LP_RDCAPFLG(x) (0x0048 + (x) * 0x10) /* R: edges captured */
277 #define LP_WRDOUT(x) (0x0048 + (x) * 0x10) /* W: digital output */
278 #define LP_RDINTSEL(x) (0x004a + (x) * 0x10) /* R: int enable */
279 #define LP_RDEDGSEL(x) (0x004c + (x) * 0x10) /* R: edge selection */
280 #define LP_RDCAPSEL(x) (0x004e + (x) * 0x10) /* R: capture enable */
282 /* Counter Registers (read/write): */
283 #define LP_CR0A 0x0000 /* 0A setup register. */
284 #define LP_CR0B 0x0002 /* 0B setup register. */
285 #define LP_CR1A 0x0004 /* 1A setup register. */
286 #define LP_CR1B 0x0006 /* 1B setup register. */
287 #define LP_CR2A 0x0008 /* 2A setup register. */
288 #define LP_CR2B 0x000A /* 2B setup register. */
290 /* Counter PreLoad (write) and Latch (read) Registers: */
291 #define LP_CNTR0ALSW 0x000C /* 0A lsw. */
292 #define LP_CNTR0AMSW 0x000E /* 0A msw. */
293 #define LP_CNTR0BLSW 0x0010 /* 0B lsw. */
294 #define LP_CNTR0BMSW 0x0012 /* 0B msw. */
295 #define LP_CNTR1ALSW 0x0014 /* 1A lsw. */
296 #define LP_CNTR1AMSW 0x0016 /* 1A msw. */
297 #define LP_CNTR1BLSW 0x0018 /* 1B lsw. */
298 #define LP_CNTR1BMSW 0x001A /* 1B msw. */
299 #define LP_CNTR2ALSW 0x001C /* 2A lsw. */
300 #define LP_CNTR2AMSW 0x001E /* 2A msw. */
301 #define LP_CNTR2BLSW 0x0020 /* 2B lsw. */
302 #define LP_CNTR2BMSW 0x0022 /* 2B msw. */
304 /* Miscellaneous Registers (read/write): */
305 #define LP_MISC1 0x0088 /* Read/write Misc1. */
306 #define LP_WRMISC2 0x0090 /* Write Misc2. */
307 #define LP_RDMISC2 0x0082 /* Read Misc2. */
309 /* Bit masks for MISC1 register that are the same for reads and writes. */
310 #define MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear
312 #define MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */
313 #define MISC1_EDCAP 0x1000 /* enab edge capture on DIO chans
314 * specified by LP_WRCAPSELx. */
315 #define MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified
318 /* Bit masks for MISC1 register reads. */
319 #define RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */
321 /* Bit masks for MISC2 register writes. */
322 #define WRMISC2_WDCLEAR 0x8000 /* Reset watchdog timer to zero. */
323 #define WRMISC2_CHARGE_ENABLE 0x4000 /* enab battery trickle charging. */
325 /* Bit masks for MISC2 register that are the same for reads and writes. */
326 #define MISC2_BATT_ENABLE 0x0008 /* Backup battery enable. */
327 #define MISC2_WDENABLE 0x0004 /* Watchdog timer enable. */
328 #define MISC2_WDPERIOD_MASK 0x0003 /* Watchdog interval */
331 /* Bit masks for ACON1 register. */
332 #define A2_RUN 0x40000000 /* Run A2 based on TSL2. */
333 #define A1_RUN 0x20000000 /* Run A1 based on TSL1. */
334 #define A1_SWAP 0x00200000 /* Use big-endian for A1. */
335 #define A2_SWAP 0x00100000 /* Use big-endian for A2. */
336 #define WS_MODES 0x00019999 /* WS0 = TSL1 trigger */
337 /* input, WS1-WS4 = */
340 #if PLATFORM == INTEL /* Base ACON1 config: always run A1 based
342 #define ACON1_BASE (WS_MODES | A1_RUN)
343 #elif PLATFORM == MOTOROLA
344 #define ACON1_BASE (WS_MODES | A1_RUN | A1_SWAP | A2_SWAP)
347 #define ACON1_ADCSTART ACON1_BASE /* Start ADC: run A1
349 #define ACON1_DACSTART (ACON1_BASE | A2_RUN)
350 /* Start transmit to DAC: run A2 based on TSL2. */
351 #define ACON1_DACSTOP ACON1_BASE /* Halt A2. */
353 /* Bit masks for ACON2 register. */
354 #define A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */
355 #define A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 (DACs). */
356 #define A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 (DACs). */
357 #define A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 (DACs). */
358 #define INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */
359 #define BCLK2_OE 0x00040000 /* enab BCLK2 (DACs). */
360 #define ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 */
361 /* active-low bits. */
363 #define ACON2_INIT (ACON2_XORMASK ^ (A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE))
365 /* Bit masks for timeslot records. */
366 #define WS1 0x40000000 /* WS output to assert. */
367 #define WS2 0x20000000
368 #define WS3 0x10000000
369 #define WS4 0x08000000
370 #define RSD1 0x01000000 /* Shift A1 data in on SD1. */
371 #define SDW_A1 0x00800000 /* Store rcv'd char at next
372 * char slot of DWORD1 buffer. */
373 #define SIB_A1 0x00400000 /* Store rcv'd char at next
374 * char slot of FB1 buffer. */
375 #define SF_A1 0x00200000 /* Write unsigned long
376 * buffer to input FIFO. */
378 /* Select parallel-to-serial converter's data source: */
379 #define XFIFO_0 0x00000000 /* Data fifo byte 0. */
380 #define XFIFO_1 0x00000010 /* Data fifo byte 1. */
381 #define XFIFO_2 0x00000020 /* Data fifo byte 2. */
382 #define XFIFO_3 0x00000030 /* Data fifo byte 3. */
383 #define XFB0 0x00000040 /* FB_BUFFER byte 0. */
384 #define XFB1 0x00000050 /* FB_BUFFER byte 1. */
385 #define XFB2 0x00000060 /* FB_BUFFER byte 2. */
386 #define XFB3 0x00000070 /* FB_BUFFER byte 3. */
387 #define SIB_A2 0x00000200 /* Store next dword from A2's
388 * input shifter to FB2 buffer. */
389 #define SF_A2 0x00000100 /* Store next dword from A2's
390 * input shifter to its input
392 #define LF_A2 0x00000080 /* Load next dword from A2's
393 * output fifo into its
394 * output dword buffer. */
395 #define XSD2 0x00000008 /* Shift data out on SD2. */
396 #define RSD3 0x00001800 /* Shift data in on SD3. */
397 #define RSD2 0x00001000 /* Shift data in on SD2. */
398 #define LOW_A2 0x00000002 /* Drive last SD low */
399 /* for 7 clks, then */
401 #define EOS 0x00000001 /* End of superframe. */
403 /* I2C configuration constants. */
404 #define I2C_CLKSEL 0x0400
405 /* I2C bit rate = PCIclk/480 = 68.75 KHz. */
407 #define I2C_BITRATE 68.75
408 /* I2C bus data bit rate (determined by I2C_CLKSEL) in KHz. */
410 #define I2C_WRTIME 15.0
411 /* Worst case time, in msec, for EEPROM internal write op. */
413 /* I2C manifest constants. */
415 /* Max retries to wait for EEPROM write. */
416 #define I2C_RETRIES (I2C_WRTIME * I2C_BITRATE / 9.0)
417 #define I2C_ERR 0x0002 /* I2C control/status */
419 #define I2C_BUSY 0x0001 /* I2C control/status */
421 #define I2C_ABORT 0x0080 /* I2C status flag ABORT. */
422 #define I2C_ATTRSTART 0x3 /* I2C attribute START. */
423 #define I2C_ATTRCONT 0x2 /* I2C attribute CONT. */
424 #define I2C_ATTRSTOP 0x1 /* I2C attribute STOP. */
425 #define I2C_ATTRNOP 0x0 /* I2C attribute NOP. */
427 /* I2C read command | EEPROM address. */
428 #define I2CR (devpriv->I2CAdrs | 1)
430 /* I2C write command | EEPROM address. */
431 #define I2CW (devpriv->I2CAdrs)
433 /* Code macros used for constructing I2C command bytes. */
434 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
435 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
436 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
439 #define P_DEBICFGq 0x007C /* DEBI configuration. */
440 #define P_DEBICMDq 0x0080 /* DEBI command. */
441 #define P_DEBIPAGEq 0x0084 /* DEBI page. */
442 #define P_DEBIADq 0x0088 /* DEBI target address. */
444 #define DEBI_CFG_TOQ 0x03C00000 /* timeout (15 PCI cycles) */
445 #define DEBI_CFG_FASTQ 0x10000000 /* fast mode enable */
446 #define DEBI_CFG_16Q 0x00080000 /* 16-bit access enable */
447 #define DEBI_CFG_INCQ 0x00040000 /* enable address increment */
448 #define DEBI_CFG_TIMEROFFQ 0x00010000 /* disable timer */
449 #define DEBI_CMD_RDQ 0x00050000 /* read immediate 2 bytes */
450 #define DEBI_CMD_WRQ 0x00040000 /* write immediate 2 bytes */
451 #define DEBI_PAGE_DISABLEQ 0x00000000 /* paging disable */
453 /* DEBI command constants. */
454 #define DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is */
455 /* always 2 bytes. */
456 #define DEBI_CMD_READ 0x00010000 /* Read operation. */
457 #define DEBI_CMD_WRITE 0x00000000 /* Write operation. */
459 /* Read immediate 2 bytes. */
460 #define DEBI_CMD_RDWORD (DEBI_CMD_READ | DEBI_CMD_SIZE16)
462 /* Write immediate 2 bytes. */
463 #define DEBI_CMD_WRWORD (DEBI_CMD_WRITE | DEBI_CMD_SIZE16)
465 /* DEBI configuration constants. */
466 #define DEBI_CFG_XIRQ_EN 0x80000000 /* enab external */
467 /* interrupt on GPIO3. */
468 #define DEBI_CFG_XRESUME 0x40000000 /* Resume block */
469 /* transfer when XIRQ */
471 #define DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */
473 /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */
474 #define DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after */
475 /* this many clocks. */
477 /* 2-bit field that specifies Endian byte lane steering: */
478 #define DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't */
481 #define DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */
482 #define DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */
483 #define DEBI_CFG_16 0x00080000 /* Slave is able to */
487 #define DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to */
490 #define DEBI_CFG_INC 0x00040000 /* enab address */
491 /* increment for block */
493 #define DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */
494 #define DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */
496 #if PLATFORM == INTEL
498 #define DEBI_TOUT 7 /* Wait 7 PCI clocks */
499 /* (212 ns) before */
502 /* Intel byte lane steering (pass through all byte lanes). */
503 #define DEBI_SWAP DEBI_CFG_SWAP_NONE
505 #elif PLATFORM == MOTOROLA
507 #define DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) */
508 /* maximum before timing out. */
509 #define DEBI_SWAP DEBI_CFG_SWAP_2 /* Motorola byte lane steering. */
513 /* DEBI page table constants. */
514 #define DEBI_PAGE_DISABLE 0x00000000 /* Paging disable. */
516 /* ******* EXTRA FROM OTHER SANSORAY * .h ******* */
518 /* LoadSrc values: */
519 #define LOADSRC_INDX 0 /* Preload core in response to */
521 #define LOADSRC_OVER 1 /* Preload core in response to */
523 #define LOADSRCB_OVERA 2 /* Preload B core in response */
525 #define LOADSRC_NONE 3 /* Never preload core. */
528 #define INTSRC_NONE 0 /* Interrupts disabled. */
529 #define INTSRC_OVER 1 /* Interrupt on Overflow. */
530 #define INTSRC_INDX 2 /* Interrupt on Index. */
531 #define INTSRC_BOTH 3 /* Interrupt on Index or Overflow. */
533 /* LatchSrc values: */
534 #define LATCHSRC_AB_READ 0 /* Latch on read. */
535 #define LATCHSRC_A_INDXA 1 /* Latch A on A Index. */
536 #define LATCHSRC_B_INDXB 2 /* Latch B on B Index. */
537 #define LATCHSRC_B_OVERA 3 /* Latch B on A Overflow. */
539 /* IndxSrc values: */
540 #define INDXSRC_HARD 0 /* Hardware or software index. */
541 #define INDXSRC_SOFT 1 /* Software index only. */
543 /* IndxPol values: */
544 #define INDXPOL_POS 0 /* Index input is active high. */
545 #define INDXPOL_NEG 1 /* Index input is active low. */
548 #define CLKSRC_COUNTER 0 /* Counter mode. */
549 #define CLKSRC_TIMER 2 /* Timer mode. */
550 #define CLKSRC_EXTENDER 3 /* Extender mode. */
553 #define CLKPOL_POS 0 /* Counter/Extender clock is */
555 #define CLKPOL_NEG 1 /* Counter/Extender clock is */
557 #define CNTDIR_UP 0 /* Timer counts up. */
558 #define CNTDIR_DOWN 1 /* Timer counts down. */
560 /* ClkEnab values: */
561 #define CLKENAB_ALWAYS 0 /* Clock always enabled. */
562 #define CLKENAB_INDEX 1 /* Clock is enabled by index. */
564 /* ClkMult values: */
565 #define CLKMULT_4X 0 /* 4x clock multiplier. */
566 #define CLKMULT_2X 1 /* 2x clock multiplier. */
567 #define CLKMULT_1X 2 /* 1x clock multiplier. */
569 /* Bit Field positions in COUNTER_SETUP structure: */
570 #define BF_LOADSRC 9 /* Preload trigger. */
571 #define BF_INDXSRC 7 /* Index source. */
572 #define BF_INDXPOL 6 /* Index polarity. */
573 #define BF_CLKSRC 4 /* Clock source. */
574 #define BF_CLKPOL 3 /* Clock polarity/count direction. */
575 #define BF_CLKMULT 1 /* Clock multiplier. */
576 #define BF_CLKENAB 0 /* Clock enable. */
578 /* Enumerated counter operating modes specified by ClkSrc bit field in */
579 /* a COUNTER_SETUP. */
581 #define CLKSRC_COUNTER 0 /* Counter: ENC_C clock, ENC_D */
583 #define CLKSRC_TIMER 2 /* Timer: SYS_C clock, */
584 /* direction specified by */
586 #define CLKSRC_EXTENDER 3 /* Extender: OVR_A clock, */
587 /* ENC_D direction. */
589 /* Enumerated counter clock multipliers. */
591 #define MULT_X0 0x0003 /* Supports no multipliers; */
592 /* fixed physical multiplier = */
594 #define MULT_X1 0x0002 /* Supports multiplier x1; */
595 /* fixed physical multiplier = */
597 #define MULT_X2 0x0001 /* Supports multipliers x1, */
598 /* x2; physical multipliers = */
600 #define MULT_X4 0x0000 /* Supports multipliers x1, */
601 /* x2, x4; physical */
602 /* multipliers = 0, 1 or 2. */
604 /* Sanity-check limits for parameters. */
606 #define NUM_COUNTERS 6 /* Maximum valid counter */
607 /* logical channel number. */
608 #define NUM_INTSOURCES 4
609 #define NUM_LATCHSOURCES 4
610 #define NUM_CLKMULTS 4
611 #define NUM_CLKSOURCES 4
612 #define NUM_CLKPOLS 2
613 #define NUM_INDEXPOLS 2
614 #define NUM_INDEXSOURCES 2
615 #define NUM_LOADTRIGS 4
617 /* Bit field positions in CRA and CRB counter control registers. */
619 /* Bit field positions in CRA: */
620 #define CRABIT_INDXSRC_B 14 /* B index source. */
621 #define CRABIT_CLKSRC_B 12 /* B clock source. */
622 #define CRABIT_INDXPOL_A 11 /* A index polarity. */
623 #define CRABIT_LOADSRC_A 9 /* A preload trigger. */
624 #define CRABIT_CLKMULT_A 7 /* A clock multiplier. */
625 #define CRABIT_INTSRC_A 5 /* A interrupt source. */
626 #define CRABIT_CLKPOL_A 4 /* A clock polarity. */
627 #define CRABIT_INDXSRC_A 2 /* A index source. */
628 #define CRABIT_CLKSRC_A 0 /* A clock source. */
630 /* Bit field positions in CRB: */
631 #define CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */
632 #define CRBBIT_INTRESET_B 14 /* B interrupt reset enable. */
633 #define CRBBIT_INTRESET_A 13 /* A interrupt reset enable. */
634 #define CRBBIT_CLKENAB_A 12 /* A clock enable. */
635 #define CRBBIT_INTSRC_B 10 /* B interrupt source. */
636 #define CRBBIT_LATCHSRC 8 /* A/B latch source. */
637 #define CRBBIT_LOADSRC_B 6 /* B preload trigger. */
638 #define CRBBIT_CLKMULT_B 3 /* B clock multiplier. */
639 #define CRBBIT_CLKENAB_B 2 /* B clock enable. */
640 #define CRBBIT_INDXPOL_B 1 /* B index polarity. */
641 #define CRBBIT_CLKPOL_B 0 /* B clock polarity. */
643 /* Bit field masks for CRA and CRB. */
645 #define CRAMSK_INDXSRC_B (3 << CRABIT_INDXSRC_B)
646 #define CRAMSK_CLKSRC_B (3 << CRABIT_CLKSRC_B)
647 #define CRAMSK_INDXPOL_A (1 << CRABIT_INDXPOL_A)
648 #define CRAMSK_LOADSRC_A (3 << CRABIT_LOADSRC_A)
649 #define CRAMSK_CLKMULT_A (3 << CRABIT_CLKMULT_A)
650 #define CRAMSK_INTSRC_A (3 << CRABIT_INTSRC_A)
651 #define CRAMSK_CLKPOL_A (3 << CRABIT_CLKPOL_A)
652 #define CRAMSK_INDXSRC_A (3 << CRABIT_INDXSRC_A)
653 #define CRAMSK_CLKSRC_A (3 << CRABIT_CLKSRC_A)
655 #define CRBMSK_INTRESETCMD (1 << CRBBIT_INTRESETCMD)
656 #define CRBMSK_INTRESET_B (1 << CRBBIT_INTRESET_B)
657 #define CRBMSK_INTRESET_A (1 << CRBBIT_INTRESET_A)
658 #define CRBMSK_CLKENAB_A (1 << CRBBIT_CLKENAB_A)
659 #define CRBMSK_INTSRC_B (3 << CRBBIT_INTSRC_B)
660 #define CRBMSK_LATCHSRC (3 << CRBBIT_LATCHSRC)
661 #define CRBMSK_LOADSRC_B (3 << CRBBIT_LOADSRC_B)
662 #define CRBMSK_CLKMULT_B (3 << CRBBIT_CLKMULT_B)
663 #define CRBMSK_CLKENAB_B (1 << CRBBIT_CLKENAB_B)
664 #define CRBMSK_INDXPOL_B (1 << CRBBIT_INDXPOL_B)
665 #define CRBMSK_CLKPOL_B (1 << CRBBIT_CLKPOL_B)
667 #define CRBMSK_INTCTRL (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B) /* Interrupt reset control bits. */
669 /* Bit field positions for standardized SETUP structure. */
671 #define STDBIT_INTSRC 13
672 #define STDBIT_LATCHSRC 11
673 #define STDBIT_LOADSRC 9
674 #define STDBIT_INDXSRC 7
675 #define STDBIT_INDXPOL 6
676 #define STDBIT_CLKSRC 4
677 #define STDBIT_CLKPOL 3
678 #define STDBIT_CLKMULT 1
679 #define STDBIT_CLKENAB 0
681 /* Bit field masks for standardized SETUP structure. */
683 #define STDMSK_INTSRC (3 << STDBIT_INTSRC)
684 #define STDMSK_LATCHSRC (3 << STDBIT_LATCHSRC)
685 #define STDMSK_LOADSRC (3 << STDBIT_LOADSRC)
686 #define STDMSK_INDXSRC (1 << STDBIT_INDXSRC)
687 #define STDMSK_INDXPOL (1 << STDBIT_INDXPOL)
688 #define STDMSK_CLKSRC (3 << STDBIT_CLKSRC)
689 #define STDMSK_CLKPOL (1 << STDBIT_CLKPOL)
690 #define STDMSK_CLKMULT (3 << STDBIT_CLKMULT)
691 #define STDMSK_CLKENAB (1 << STDBIT_CLKENAB)
694 dma_addr_t PhysicalBase
;
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob