drivers/staging/comedi/drivers/ni_tiocmd.c

   1 /*
   2   comedi/drivers/ni_tiocmd.c
   3   Command support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16
  17   You should have received a copy of the GNU General Public License
  18   along with this program; if not, write to the Free Software
  19   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23 Driver: ni_tiocmd
  24 Description: National Instruments general purpose counters command support
  25 Devices:
  26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  27         Herman.Bruyninckx@mech.kuleuven.ac.be,
  28         Wim.Meeussen@mech.kuleuven.ac.be,
  29         Klaas.Gadeyne@mech.kuleuven.ac.be,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Updated: Fri, 11 Apr 2008 12:32:35 +0100
  32 Status: works
  33
  34 This module is not used directly by end-users.  Rather, it
  35 is used by other drivers (for example ni_660x and ni_pcimio)
  36 to provide command support for NI's general purpose counters.
  37 It was originally split out of ni_tio.c to stop the 'ni_tio'
  38 module depending on the 'mite' module.
  39
  40 References:
  41 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  42 DAQ 6601/6602 User Manual (NI 322137B-01)
  43 340934b.pdf  DAQ-STC reference manual
  44
  45 */
  46 /*
  47 TODO:
  48         Support use of both banks X and Y
  49 */
  50
  51 #include "comedi_fc.h"
  52 #include "ni_tio_internal.h"
  53 #include "mite.h"
  54
  55 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
  56 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
  57 MODULE_LICENSE("GPL");
  58
  59 static void ni_tio_configure_dma(struct ni_gpct *counter, short enable,
  60                                  short read_not_write)
  61 {
  62         struct ni_gpct_device *counter_dev = counter->counter_dev;
  63         unsigned input_select_bits = 0;
  64
  65         if (enable) {
  66                 if (read_not_write)
  67                         input_select_bits |= Gi_Read_Acknowledges_Irq;
  68                 else
  69                         input_select_bits |= Gi_Write_Acknowledges_Irq;
  70         }
  71         ni_tio_set_bits(counter,
  72                         NITIO_Gi_Input_Select_Reg(counter->counter_index),
  73                         Gi_Read_Acknowledges_Irq | Gi_Write_Acknowledges_Irq,
  74                         input_select_bits);
  75         switch (counter_dev->variant) {
  76         case ni_gpct_variant_e_series:
  77                 break;
  78         case ni_gpct_variant_m_series:
  79         case ni_gpct_variant_660x:
  80                 {
  81                         unsigned gi_dma_config_bits = 0;
  82
  83                         if (enable) {
  84                                 gi_dma_config_bits |= Gi_DMA_Enable_Bit;
  85                                 gi_dma_config_bits |= Gi_DMA_Int_Bit;
  86                         }
  87                         if (read_not_write == 0)
  88                                 gi_dma_config_bits |= Gi_DMA_Write_Bit;
  89                         ni_tio_set_bits(counter,
  90                                         NITIO_Gi_DMA_Config_Reg(counter->
  91                                                                 counter_index),
  92                                         Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit |
  93                                         Gi_DMA_Write_Bit, gi_dma_config_bits);
  94                 }
  95                 break;
  96         }
  97 }
  98
  99 static int ni_tio_input_inttrig(struct comedi_device *dev,
 100                                 struct comedi_subdevice *s,
 101                                 unsigned int trignum)
 102 {
 103         unsigned long flags;
 104         int retval = 0;
 105         struct ni_gpct *counter = s->private;
 106
 107         BUG_ON(counter == NULL);
 108         if (trignum != 0)
 109                 return -EINVAL;
 110
 111         spin_lock_irqsave(&counter->lock, flags);
 112         if (counter->mite_chan)
 113                 mite_dma_arm(counter->mite_chan);
 114         else
 115                 retval = -EIO;
 116         spin_unlock_irqrestore(&counter->lock, flags);
 117         if (retval < 0)
 118                 return retval;
 119         retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
 120         s->async->inttrig = NULL;
 121
 122         return retval;
 123 }
 124
 125 static int ni_tio_input_cmd(struct ni_gpct *counter, struct comedi_async *async)
 126 {
 127         struct ni_gpct_device *counter_dev = counter->counter_dev;
 128         struct comedi_cmd *cmd = &async->cmd;
 129         int retval = 0;
 130
 131         /* write alloc the entire buffer */
 132         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 133         counter->mite_chan->dir = COMEDI_INPUT;
 134         switch (counter_dev->variant) {
 135         case ni_gpct_variant_m_series:
 136         case ni_gpct_variant_660x:
 137                 mite_prep_dma(counter->mite_chan, 32, 32);
 138                 break;
 139         case ni_gpct_variant_e_series:
 140                 mite_prep_dma(counter->mite_chan, 16, 32);
 141                 break;
 142         default:
 143                 BUG();
 144                 break;
 145         }
 146         ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
 147                         Gi_Save_Trace_Bit, 0);
 148         ni_tio_configure_dma(counter, 1, 1);
 149         switch (cmd->start_src) {
 150         case TRIG_NOW:
 151                 async->inttrig = NULL;
 152                 mite_dma_arm(counter->mite_chan);
 153                 retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
 154                 break;
 155         case TRIG_INT:
 156                 async->inttrig = &ni_tio_input_inttrig;
 157                 break;
 158         case TRIG_EXT:
 159                 async->inttrig = NULL;
 160                 mite_dma_arm(counter->mite_chan);
 161                 retval = ni_tio_arm(counter, 1, cmd->start_arg);
 162                 break;
 163         case TRIG_OTHER:
 164                 async->inttrig = NULL;
 165                 mite_dma_arm(counter->mite_chan);
 166                 break;
 167         default:
 168                 BUG();
 169                 break;
 170         }
 171         return retval;
 172 }
 173
 174 static int ni_tio_output_cmd(struct ni_gpct *counter,
 175                              struct comedi_async *async)
 176 {
 177         dev_err(counter->counter_dev->dev->class_dev,
 178                 "output commands not yet implemented.\n");
 179         return -ENOTSUPP;
 180
 181         counter->mite_chan->dir = COMEDI_OUTPUT;
 182         mite_prep_dma(counter->mite_chan, 32, 32);
 183         ni_tio_configure_dma(counter, 1, 0);
 184         mite_dma_arm(counter->mite_chan);
 185         return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
 186 }
 187
 188 static int ni_tio_cmd_setup(struct ni_gpct *counter, struct comedi_async *async)
 189 {
 190         struct comedi_cmd *cmd = &async->cmd;
 191         int set_gate_source = 0;
 192         unsigned gate_source;
 193         int retval = 0;
 194
 195         if (cmd->scan_begin_src == TRIG_EXT) {
 196                 set_gate_source = 1;
 197                 gate_source = cmd->scan_begin_arg;
 198         } else if (cmd->convert_src == TRIG_EXT) {
 199                 set_gate_source = 1;
 200                 gate_source = cmd->convert_arg;
 201         }
 202         if (set_gate_source)
 203                 retval = ni_tio_set_gate_src(counter, 0, gate_source);
 204         if (cmd->flags & TRIG_WAKE_EOS) {
 205                 ni_tio_set_bits(counter,
 206                                 NITIO_Gi_Interrupt_Enable_Reg(counter->
 207                                                               counter_index),
 208                                 Gi_Gate_Interrupt_Enable_Bit(counter->
 209                                                              counter_index),
 210                                 Gi_Gate_Interrupt_Enable_Bit(counter->
 211                                                              counter_index));
 212         }
 213         return retval;
 214 }
 215
 216 int ni_tio_cmd(struct ni_gpct *counter, struct comedi_async *async)
 217 {
 218         struct comedi_cmd *cmd = &async->cmd;
 219         int retval = 0;
 220         unsigned long flags;
 221
 222         spin_lock_irqsave(&counter->lock, flags);
 223         if (counter->mite_chan == NULL) {
 224                 dev_err(counter->counter_dev->dev->class_dev,
 225                         "commands only supported with DMA.  ");
 226                 dev_err(counter->counter_dev->dev->class_dev,
 227                         "Interrupt-driven commands not yet implemented.\n");
 228                 retval = -EIO;
 229         } else {
 230                 retval = ni_tio_cmd_setup(counter, async);
 231                 if (retval == 0) {
 232                         if (cmd->flags & CMDF_WRITE)
 233                                 retval = ni_tio_output_cmd(counter, async);
 234                         else
 235                                 retval = ni_tio_input_cmd(counter, async);
 236                 }
 237         }
 238         spin_unlock_irqrestore(&counter->lock, flags);
 239         return retval;
 240 }
 241 EXPORT_SYMBOL_GPL(ni_tio_cmd);
 242
 243 int ni_tio_cmdtest(struct ni_gpct *counter, struct comedi_cmd *cmd)
 244 {
 245         int err = 0;
 246         unsigned int sources;
 247
 248         /* Step 1 : check if triggers are trivially valid */
 249
 250         sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
 251         if (ni_tio_counting_mode_registers_present(counter->counter_dev))
 252                 sources |= TRIG_EXT;
 253         err |= cfc_check_trigger_src(&cmd->start_src, sources);
 254
 255         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
 256                                         TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
 257         err |= cfc_check_trigger_src(&cmd->convert_src,
 258                                         TRIG_NOW | TRIG_EXT | TRIG_OTHER);
 259         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 260         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
 261
 262         if (err)
 263                 return 1;
 264
 265         /* Step 2a : make sure trigger sources are unique */
 266
 267         err |= cfc_check_trigger_is_unique(cmd->start_src);
 268         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
 269         err |= cfc_check_trigger_is_unique(cmd->convert_src);
 270
 271         /* Step 2b : and mutually compatible */
 272
 273         if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
 274                 err |= -EINVAL;
 275
 276         if (err)
 277                 return 2;
 278
 279         /* Step 3: check if arguments are trivially valid */
 280
 281         if (cmd->start_src != TRIG_EXT)
 282                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
 283
 284         if (cmd->scan_begin_src != TRIG_EXT)
 285                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 286
 287         if (cmd->convert_src != TRIG_EXT)
 288                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
 289
 290         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
 291         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
 292
 293         if (err)
 294                 return 3;
 295
 296         /* step 4: fix up any arguments */
 297
 298         if (err)
 299                 return 4;
 300
 301         return 0;
 302 }
 303 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
 304
 305 int ni_tio_cancel(struct ni_gpct *counter)
 306 {
 307         unsigned long flags;
 308
 309         ni_tio_arm(counter, 0, 0);
 310         spin_lock_irqsave(&counter->lock, flags);
 311         if (counter->mite_chan)
 312                 mite_dma_disarm(counter->mite_chan);
 313         spin_unlock_irqrestore(&counter->lock, flags);
 314         ni_tio_configure_dma(counter, 0, 0);
 315
 316         ni_tio_set_bits(counter,
 317                         NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
 318                         Gi_Gate_Interrupt_Enable_Bit(counter->counter_index),
 319                         0x0);
 320         return 0;
 321 }
 322 EXPORT_SYMBOL_GPL(ni_tio_cancel);
 323
 324         /* During buffered input counter operation for e-series, the gate
 325            interrupt is acked automatically by the dma controller, due to the
 326            Gi_Read/Write_Acknowledges_IRQ bits in the input select register.  */
 327 static int should_ack_gate(struct ni_gpct *counter)
 328 {
 329         unsigned long flags;
 330         int retval = 0;
 331
 332         switch (counter->counter_dev->variant) {
 333         case ni_gpct_variant_m_series:
 334         /*  not sure if 660x really supports gate
 335             interrupts (the bits are not listed
 336             in register-level manual) */
 337         case ni_gpct_variant_660x:
 338                 return 1;
 339                 break;
 340         case ni_gpct_variant_e_series:
 341                 spin_lock_irqsave(&counter->lock, flags);
 342                 {
 343                         if (counter->mite_chan == NULL ||
 344                             counter->mite_chan->dir != COMEDI_INPUT ||
 345                             (mite_done(counter->mite_chan))) {
 346                                 retval = 1;
 347                         }
 348                 }
 349                 spin_unlock_irqrestore(&counter->lock, flags);
 350                 break;
 351         }
 352         return retval;
 353 }
 354
 355 void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
 356                                     int *tc_error, int *perm_stale_data,
 357                                     int *stale_data)
 358 {
 359         const unsigned short gxx_status = read_register(counter,
 360                                                         NITIO_Gxx_Status_Reg
 361                                                         (counter->
 362                                                          counter_index));
 363         const unsigned short gi_status = read_register(counter,
 364                                                        NITIO_Gi_Status_Reg
 365                                                        (counter->
 366                                                         counter_index));
 367         unsigned ack = 0;
 368
 369         if (gate_error)
 370                 *gate_error = 0;
 371         if (tc_error)
 372                 *tc_error = 0;
 373         if (perm_stale_data)
 374                 *perm_stale_data = 0;
 375         if (stale_data)
 376                 *stale_data = 0;
 377
 378         if (gxx_status & Gi_Gate_Error_Bit(counter->counter_index)) {
 379                 ack |= Gi_Gate_Error_Confirm_Bit(counter->counter_index);
 380                 if (gate_error) {
 381                         /*660x don't support automatic acknowledgement
 382                           of gate interrupt via dma read/write
 383                            and report bogus gate errors */
 384                         if (counter->counter_dev->variant !=
 385                             ni_gpct_variant_660x) {
 386                                 *gate_error = 1;
 387                         }
 388                 }
 389         }
 390         if (gxx_status & Gi_TC_Error_Bit(counter->counter_index)) {
 391                 ack |= Gi_TC_Error_Confirm_Bit(counter->counter_index);
 392                 if (tc_error)
 393                         *tc_error = 1;
 394         }
 395         if (gi_status & Gi_TC_Bit)
 396                 ack |= Gi_TC_Interrupt_Ack_Bit;
 397         if (gi_status & Gi_Gate_Interrupt_Bit) {
 398                 if (should_ack_gate(counter))
 399                         ack |= Gi_Gate_Interrupt_Ack_Bit;
 400         }
 401         if (ack)
 402                 write_register(counter, ack,
 403                                NITIO_Gi_Interrupt_Acknowledge_Reg
 404                                (counter->counter_index));
 405         if (ni_tio_get_soft_copy
 406             (counter,
 407              NITIO_Gi_Mode_Reg(counter->counter_index)) &
 408             Gi_Loading_On_Gate_Bit) {
 409                 if (gxx_status & Gi_Stale_Data_Bit(counter->counter_index)) {
 410                         if (stale_data)
 411                                 *stale_data = 1;
 412                 }
 413                 if (read_register(counter,
 414                                   NITIO_Gxx_Joint_Status2_Reg
 415                                   (counter->counter_index)) &
 416                     Gi_Permanent_Stale_Bit(counter->counter_index)) {
 417                         dev_info(counter->counter_dev->dev->class_dev,
 418                                  "%s: Gi_Permanent_Stale_Data detected.\n",
 419                                  __func__);
 420                         if (perm_stale_data)
 421                                 *perm_stale_data = 1;
 422                 }
 423         }
 424 }
 425 EXPORT_SYMBOL_GPL(ni_tio_acknowledge_and_confirm);
 426
 427 void ni_tio_handle_interrupt(struct ni_gpct *counter,
 428                              struct comedi_subdevice *s)
 429 {
 430         unsigned gpct_mite_status;
 431         unsigned long flags;
 432         int gate_error;
 433         int tc_error;
 434         int perm_stale_data;
 435
 436         ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
 437                                        &perm_stale_data, NULL);
 438         if (gate_error) {
 439                 dev_notice(counter->counter_dev->dev->class_dev,
 440                            "%s: Gi_Gate_Error detected.\n", __func__);
 441                 s->async->events |= COMEDI_CB_OVERFLOW;
 442         }
 443         if (perm_stale_data)
 444                 s->async->events |= COMEDI_CB_ERROR;
 445         switch (counter->counter_dev->variant) {
 446         case ni_gpct_variant_m_series:
 447         case ni_gpct_variant_660x:
 448                 if (read_register(counter,
 449                                 NITIO_Gi_DMA_Status_Reg
 450                                 (counter->counter_index)) & Gi_DRQ_Error_Bit) {
 451                         dev_notice(counter->counter_dev->dev->class_dev,
 452                                    "%s: Gi_DRQ_Error detected.\n", __func__);
 453                         s->async->events |= COMEDI_CB_OVERFLOW;
 454                 }
 455                 break;
 456         case ni_gpct_variant_e_series:
 457                 break;
 458         }
 459         spin_lock_irqsave(&counter->lock, flags);
 460         if (counter->mite_chan == NULL) {
 461                 spin_unlock_irqrestore(&counter->lock, flags);
 462                 return;
 463         }
 464         gpct_mite_status = mite_get_status(counter->mite_chan);
 465         if (gpct_mite_status & CHSR_LINKC) {
 466                 writel(CHOR_CLRLC,
 467                        counter->mite_chan->mite->mite_io_addr +
 468                        MITE_CHOR(counter->mite_chan->channel));
 469         }
 470         mite_sync_input_dma(counter->mite_chan, s->async);
 471         spin_unlock_irqrestore(&counter->lock, flags);
 472 }
 473 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
 474
 475 void ni_tio_set_mite_channel(struct ni_gpct *counter,
 476                              struct mite_channel *mite_chan)
 477 {
 478         unsigned long flags;
 479
 480         spin_lock_irqsave(&counter->lock, flags);
 481         counter->mite_chan = mite_chan;
 482         spin_unlock_irqrestore(&counter->lock, flags);
 483 }
 484 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
 485
 486 static int __init ni_tiocmd_init_module(void)
 487 {
 488         return 0;
 489 }
 490
 491 module_init(ni_tiocmd_init_module);
 492
 493 static void __exit ni_tiocmd_cleanup_module(void)
 494 {
 495 }
 496
 497 module_exit(ni_tiocmd_cleanup_module);