2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
39 Updated: Wed, 03 Dec 2008 10:51:47 +0000
41 These boards are almost identical to the AT-MIO E series, except that
42 they use the PCI bus instead of ISA (i.e., AT). See the notes for
43 the ni_atmio.o driver for additional information about these boards.
45 Autocalibration is supported on many of the devices, using the
46 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47 M-Series boards do analog input and analog output calibration entirely
48 in software. The software calibration corrects
49 the analog input for offset, gain and
50 nonlinearity. The analog outputs are corrected for offset and gain.
51 See the comedilib documentation on comedi_get_softcal_converter() for
54 By default, the driver uses DMA to transfer analog input data to
55 memory. When DMA is enabled, not all triggering features are
58 Digital I/O may not work on 673x.
60 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61 With this board all of the convertors perform one simultaineous sample during
62 a scan interval. The period for a scan is used for the convert time in a
63 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
65 The RTSI trigger bus is supported on these cards on
66 subdevice 10. See the comedilib documentation for details.
68 Information (number of channels, bits, etc.) for some devices may be
69 incorrect. Please check this and submit a bug if there are problems
72 SCXI is probably broken for m-series boards.
75 - When DMA is enabled, COMEDI_EV_CONVERT does
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
88 322080b.pdf 6711/6713/6715 User Manual
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
98 deal with at-mio-16de-10 revision D to N changes, etc.
100 need to add other CALDAC type
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use udelay(). Timing specs: (clock)
112 #include "../comedidev.h"
114 #include <asm/byteorder.h>
115 #include <linux/delay.h>
120 /* #define PCI_DEBUG */
127 #define MAX_N_CALDACS (16+16+2)
129 #define DRV_NAME "ni_pcimio"
131 /* The following two tables must be in the same order */
132 static DEFINE_PCI_DEVICE_TABLE(ni_pci_table
) = {
133 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x0162)},
134 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1170)},
135 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1180)},
136 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1190)},
137 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x11b0)},
138 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x11c0)},
139 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x11d0)},
140 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1270)},
141 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1330)},
142 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1340)},
143 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1350)},
144 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x14e0)},
145 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x14f0)},
146 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1580)},
147 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x15b0)},
148 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1880)},
149 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x1870)},
150 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x18b0)},
151 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x18c0)},
152 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2410)},
153 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2420)},
154 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2430)},
155 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2890)},
156 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x28c0)},
157 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2a60)},
158 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2a70)},
159 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2a80)},
160 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2ab0)},
161 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2b80)},
162 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2b90)},
163 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2c80)},
164 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x2ca0)},
165 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70aa)},
166 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70ab)},
167 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70ac)},
168 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70af)},
169 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70b0)},
170 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70b4)},
171 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70b6)},
172 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70b7)},
173 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70b8)},
174 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70bc)},
175 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70bd)},
176 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70bf)},
177 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70c0)},
178 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x70f2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x710d)},
180 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x716c)},
181 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x716d)},
182 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x717f)},
183 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x71bc)},
184 {PCI_DEVICE(PCI_VENDOR_ID_NI
, 0x717d)},
188 MODULE_DEVICE_TABLE(pci
, ni_pci_table
);
190 /* These are not all the possible ao ranges for 628x boards.
191 They can do OFFSET +- REFERENCE where OFFSET can be
192 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
193 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
194 63 different possibilities. An AO channel
195 can not act as it's own OFFSET or REFERENCE.
197 static const struct comedi_lrange range_ni_M_628x_ao
= { 8, {
210 static const struct comedi_lrange range_ni_M_625x_ao
= { 3, {
217 static const struct comedi_lrange range_ni_M_622x_ao
= { 1, {
222 static const struct ni_board_struct ni_boards
[] = {
224 .device_id
= 0x0162, /* NI also says 0x1620. typo? */
225 .name
= "pci-mio-16xe-50",
228 .ai_fifo_depth
= 2048,
230 .gainlkup
= ai_gain_8
,
235 .ao_range_table
= &range_bipolar10
,
238 .num_p0_dio_channels
= 8,
239 .caldac
= {dac8800
, dac8043
},
244 .name
= "pci-mio-16xe-10", /* aka pci-6030E */
247 .ai_fifo_depth
= 512,
249 .gainlkup
= ai_gain_14
,
253 .ao_fifo_depth
= 2048,
254 .ao_range_table
= &range_ni_E_ao_ext
,
257 .num_p0_dio_channels
= 8,
258 .caldac
= {dac8800
, dac8043
, ad8522
},
266 .ai_fifo_depth
= 512,
268 .gainlkup
= ai_gain_4
,
273 .ao_range_table
= &range_bipolar10
,
276 .num_p0_dio_channels
= 8,
277 .caldac
= {ad8804_debug
},
285 .ai_fifo_depth
= 512,
287 .gainlkup
= ai_gain_14
,
291 .ao_fifo_depth
= 2048,
292 .ao_range_table
= &range_ni_E_ao_ext
,
295 .num_p0_dio_channels
= 8,
296 .caldac
= {dac8800
, dac8043
, ad8522
},
301 .name
= "pci-mio-16e-1", /* aka pci-6070e */
304 .ai_fifo_depth
= 512,
306 .gainlkup
= ai_gain_16
,
310 .ao_fifo_depth
= 2048,
311 .ao_range_table
= &range_ni_E_ao_ext
,
314 .num_p0_dio_channels
= 8,
320 .name
= "pci-mio-16e-4", /* aka pci-6040e */
323 .ai_fifo_depth
= 512,
325 .gainlkup
= ai_gain_16
,
326 /* .Note = there have been reported problems with full speed
331 .ao_fifo_depth
= 512,
332 .ao_range_table
= &range_ni_E_ao_ext
,
335 .num_p0_dio_channels
= 8,
336 .caldac
= {ad8804_debug
}, /* doc says mb88341 */
344 .ai_fifo_depth
= 512,
346 .gainlkup
= ai_gain_16
,
350 .ao_fifo_depth
= 512,
351 .ao_range_table
= &range_ni_E_ao_ext
,
354 .num_p0_dio_channels
= 8,
364 .ai_fifo_depth
= 512,
366 .gainlkup
= ai_gain_14
,
370 .ao_fifo_depth
= 2048,
371 .ao_range_table
= &range_ni_E_ao_ext
,
374 .num_p0_dio_channels
= 8,
375 .caldac
= {dac8800
, dac8043
, ad8522
},
383 .ai_fifo_depth
= 512,
385 .gainlkup
= ai_gain_14
,
391 .num_p0_dio_channels
= 8,
392 .caldac
= {dac8800
, dac8043
, ad8522
},
400 .ai_fifo_depth
= 512,
402 .gainlkup
= ai_gain_14
,
408 .num_p0_dio_channels
= 8,
409 .caldac
= {dac8800
, dac8043
, ad8522
},
417 .ai_fifo_depth
= 512,
419 .gainlkup
= ai_gain_16
,
423 .ao_fifo_depth
= 2048,
424 .ao_range_table
= &range_ni_E_ao_ext
,
427 .num_p0_dio_channels
= 8,
428 .caldac
= {ad8804_debug
},
436 .ai_fifo_depth
= 512,
438 .gainlkup
= ai_gain_4
,
443 .num_p0_dio_channels
= 8,
444 .caldac
= {ad8804_debug
}, /* manual is wrong */
452 .ai_fifo_depth
= 512,
454 .gainlkup
= ai_gain_4
,
459 .ao_range_table
= &range_bipolar10
,
462 .num_p0_dio_channels
= 8,
463 .caldac
= {ad8804_debug
}, /* manual is wrong */
471 .ai_fifo_depth
= 512,
473 .gainlkup
= ai_gain_4
,
478 .ao_range_table
= &range_bipolar10
,
481 .num_p0_dio_channels
= 8,
482 .caldac
= {ad8804_debug
}, /* manual is wrong */
490 .ai_fifo_depth
= 512,
492 .gainlkup
= ai_gain_4
,
497 .ao_range_table
= &range_ni_E_ao_ext
,
500 .num_p0_dio_channels
= 8,
501 .caldac
= {ad8804_debug
}, /* manual is wrong */
510 .ai_fifo_depth
= 512,
512 .gainlkup
= ai_gain_4
,
518 .num_p0_dio_channels
= 8,
519 .caldac
= {ad8804_debug
},
527 .ai_fifo_depth
= 512,
529 .gainlkup
= ai_gain_4
,
534 .ao_range_table
= &range_bipolar10
,
537 .num_p0_dio_channels
= 8,
538 .caldac
= {ad8804_debug
},
546 .ai_fifo_depth
= 512,
548 .gainlkup
= ai_gain_16
,
553 .ao_fifo_depth
= 2048,
554 .ao_range_table
= &range_ni_E_ao_ext
,
556 .num_p0_dio_channels
= 8,
557 .caldac
= {ad8804_debug
, ad8804_debug
, ad8522
}, /* manual is wrong */
559 {.device_id
= 0x14e0,
563 .ai_fifo_depth
= 8192,
565 .gainlkup
= ai_gain_611x
,
569 .reg_type
= ni_reg_611x
,
570 .ao_range_table
= &range_bipolar10
,
572 .ao_fifo_depth
= 2048,
574 .num_p0_dio_channels
= 8,
575 .caldac
= {ad8804
, ad8804
},
582 .ai_fifo_depth
= 8192,
584 .gainlkup
= ai_gain_611x
,
588 .reg_type
= ni_reg_611x
,
589 .ao_range_table
= &range_bipolar10
,
591 .ao_fifo_depth
= 2048,
593 .num_p0_dio_channels
= 8,
594 .caldac
= {ad8804
, ad8804
},
597 /* The 6115 boards probably need their own driver */
603 .ai_fifo_depth
= 8192,
605 .gainlkup
= ai_gain_611x
,
611 .ao_fifo_depth
= 2048,
613 .num_p0_dio_channels
= 8,
615 .caldac
= {ad8804_debug
, ad8804_debug
, ad8804_debug
}, /* XXX */
624 .ai_fifo_depth
= 8192,
626 .gainlkup
= ai_gain_611x
,
632 .ao_fifo_depth
= 2048,
635 .num_p0_dio_channels
= 8,
636 caldac
= {ad8804_debug
, ad8804_debug
, ad8804_debug
}, /* XXX */
642 .n_adchan
= 0, /* no analog input */
646 .ao_fifo_depth
= 16384,
647 /* data sheet says 8192, but fifo really holds 16384 samples */
648 .ao_range_table
= &range_bipolar10
,
650 .num_p0_dio_channels
= 8,
651 .reg_type
= ni_reg_6711
,
652 .caldac
= {ad8804_debug
},
657 .n_adchan
= 0, /* no analog input */
661 .ao_fifo_depth
= 16384,
662 .ao_range_table
= &range_bipolar10
,
664 .num_p0_dio_channels
= 8,
665 .reg_type
= ni_reg_6711
,
666 .caldac
= {ad8804_debug
},
671 .n_adchan
= 0, /* no analog input */
675 .ao_fifo_depth
= 16384,
676 .ao_range_table
= &range_bipolar10
,
678 .num_p0_dio_channels
= 8,
679 .reg_type
= ni_reg_6713
,
680 .caldac
= {ad8804_debug
, ad8804_debug
},
685 .n_adchan
= 0, /* no analog input */
689 .ao_fifo_depth
= 16384,
690 .ao_range_table
= &range_bipolar10
,
692 .num_p0_dio_channels
= 8,
693 .reg_type
= ni_reg_6713
,
694 .caldac
= {ad8804_debug
, ad8804_debug
},
699 .n_adchan
= 0, /* no analog input */
703 .ao_fifo_depth
= 8192,
704 .ao_range_table
= &range_bipolar10
,
706 .num_p0_dio_channels
= 8,
707 .reg_type
= ni_reg_6711
,
708 .caldac
= {ad8804_debug
},
710 #if 0 /* need device ids */
714 .n_adchan
= 0, /* no analog input */
718 .ao_fifo_depth
= 8192,
719 .ao_range_table
= &range_bipolar10
,
720 .num_p0_dio_channels
= 8,
721 .reg_type
= ni_reg_6711
,
722 .caldac
= {ad8804_debug
},
728 .n_adchan
= 0, /* no analog input */
732 .ao_fifo_depth
= 16384,
733 .ao_range_table
= &range_bipolar10
,
735 .num_p0_dio_channels
= 8,
736 .reg_type
= ni_reg_6713
,
737 .caldac
= {ad8804_debug
, ad8804_debug
},
742 .n_adchan
= 0, /* no analog input */
746 .ao_fifo_depth
= 16384,
747 .ao_range_table
= &range_bipolar10
,
749 .num_p0_dio_channels
= 8,
750 .reg_type
= ni_reg_6713
,
751 .caldac
= {ad8804_debug
, ad8804_debug
},
758 .ai_fifo_depth
= 512,
760 .gainlkup
= ai_gain_16
,
764 .ao_fifo_depth
= 2048,
765 .ao_range_table
= &range_ni_E_ao_ext
,
768 .num_p0_dio_channels
= 8,
769 .caldac
= {ad8804_debug
},
777 .ai_fifo_depth
= 512,
779 .gainlkup
= ai_gain_16
,
783 .ao_fifo_depth
= 2048,
784 .ao_range_table
= &range_ni_E_ao_ext
,
787 .num_p0_dio_channels
= 8,
788 .caldac
= {ad8804_debug
},
796 .ai_fifo_depth
= 512,
798 .gainlkup
= ai_gain_16
,
803 .ao_fifo_depth
= 2048,
804 .ao_range_table
= &range_ni_E_ao_ext
,
806 .num_p0_dio_channels
= 8,
807 .caldac
= {mb88341
, mb88341
, ad8522
},
814 .ai_fifo_depth
= 512,
816 .gainlkup
= ai_gain_14
,
820 .ao_fifo_depth
= 2048,
821 .ao_range_table
= &range_ni_E_ao_ext
,
824 .num_p0_dio_channels
= 8,
825 .caldac
= {dac8800
, dac8043
, ad8522
},
832 .ai_fifo_depth
= 512,
834 .gainlkup
= ai_gain_4
,
839 .ao_range_table
= &range_bipolar10
,
842 .num_p0_dio_channels
= 8,
843 .caldac
= {ad8804_debug
},
851 .ai_fifo_depth
= 512,
853 .gainlkup
= ai_gain_622x
,
858 .num_p0_dio_channels
= 8,
859 .reg_type
= ni_reg_622x
,
861 .caldac
= {caldac_none
},
869 .ai_fifo_depth
= 4095,
870 .gainlkup
= ai_gain_622x
,
874 .ao_fifo_depth
= 8191,
875 .ao_range_table
= &range_ni_M_622x_ao
,
876 .reg_type
= ni_reg_622x
,
879 .num_p0_dio_channels
= 8,
880 .caldac
= {caldac_none
},
885 .name
= "pci-6221_37pin",
888 .ai_fifo_depth
= 4095,
889 .gainlkup
= ai_gain_622x
,
893 .ao_fifo_depth
= 8191,
894 .ao_range_table
= &range_ni_M_622x_ao
,
895 .reg_type
= ni_reg_622x
,
898 .num_p0_dio_channels
= 8,
899 .caldac
= {caldac_none
},
907 .ai_fifo_depth
= 4095,
908 .gainlkup
= ai_gain_622x
,
913 .reg_type
= ni_reg_622x
,
915 .num_p0_dio_channels
= 32,
916 .caldac
= {caldac_none
},
924 .ai_fifo_depth
= 4095,
925 .gainlkup
= ai_gain_622x
,
930 .reg_type
= ni_reg_622x
,
932 .num_p0_dio_channels
= 32,
933 .caldac
= {caldac_none
},
941 .ai_fifo_depth
= 4095,
942 .gainlkup
= ai_gain_622x
,
946 .ao_fifo_depth
= 8191,
947 .ao_range_table
= &range_ni_M_622x_ao
,
948 .reg_type
= ni_reg_622x
,
951 .num_p0_dio_channels
= 32,
952 .caldac
= {caldac_none
},
960 .ai_fifo_depth
= 4095,
961 .gainlkup
= ai_gain_622x
,
965 .ao_fifo_depth
= 8191,
966 .ao_range_table
= &range_ni_M_622x_ao
,
967 .reg_type
= ni_reg_622x
,
970 .num_p0_dio_channels
= 32,
971 .caldac
= {caldac_none
},
979 .ai_fifo_depth
= 4095,
980 .gainlkup
= ai_gain_622x
,
984 .ao_fifo_depth
= 8191,
985 .ao_range_table
= &range_ni_M_622x_ao
,
986 .reg_type
= ni_reg_622x
,
989 .num_p0_dio_channels
= 32,
990 .caldac
= {caldac_none
},
998 .ai_fifo_depth
= 4095,
999 .gainlkup
= ai_gain_628x
,
1004 .reg_type
= ni_reg_625x
,
1006 .num_p0_dio_channels
= 8,
1007 .caldac
= {caldac_none
},
1011 .device_id
= 0x70b8,
1015 .ai_fifo_depth
= 4095,
1016 .gainlkup
= ai_gain_628x
,
1020 .ao_fifo_depth
= 8191,
1021 .ao_range_table
= &range_ni_M_625x_ao
,
1022 .reg_type
= ni_reg_625x
,
1025 .num_p0_dio_channels
= 8,
1026 .caldac
= {caldac_none
},
1030 .device_id
= 0x717d,
1031 .name
= "pcie-6251",
1034 .ai_fifo_depth
= 4095,
1035 .gainlkup
= ai_gain_628x
,
1039 .ao_fifo_depth
= 8191,
1040 .ao_range_table
= &range_ni_M_625x_ao
,
1041 .reg_type
= ni_reg_625x
,
1044 .num_p0_dio_channels
= 8,
1045 .caldac
= {caldac_none
},
1049 .device_id
= 0x70b7,
1053 .ai_fifo_depth
= 4095,
1054 .gainlkup
= ai_gain_628x
,
1059 .reg_type
= ni_reg_625x
,
1061 .num_p0_dio_channels
= 32,
1062 .caldac
= {caldac_none
},
1066 .device_id
= 0x70ab,
1070 .ai_fifo_depth
= 4095,
1071 .gainlkup
= ai_gain_628x
,
1075 .ao_fifo_depth
= 8191,
1076 .ao_range_table
= &range_ni_M_625x_ao
,
1077 .reg_type
= ni_reg_625x
,
1080 .num_p0_dio_channels
= 32,
1081 .caldac
= {caldac_none
},
1085 .device_id
= 0x717f,
1086 .name
= "pcie-6259",
1089 .ai_fifo_depth
= 4095,
1090 .gainlkup
= ai_gain_628x
,
1094 .ao_fifo_depth
= 8191,
1095 .ao_range_table
= &range_ni_M_625x_ao
,
1096 .reg_type
= ni_reg_625x
,
1099 .num_p0_dio_channels
= 32,
1100 .caldac
= {caldac_none
},
1104 .device_id
= 0x70b6,
1108 .ai_fifo_depth
= 2047,
1109 .gainlkup
= ai_gain_628x
,
1113 .ao_fifo_depth
= 8191,
1114 .reg_type
= ni_reg_628x
,
1116 .num_p0_dio_channels
= 8,
1117 .caldac
= {caldac_none
},
1121 .device_id
= 0x70bd,
1125 .ai_fifo_depth
= 2047,
1126 .gainlkup
= ai_gain_628x
,
1130 .ao_fifo_depth
= 8191,
1131 .ao_range_table
= &range_ni_M_628x_ao
,
1132 .reg_type
= ni_reg_628x
,
1135 .num_p0_dio_channels
= 8,
1136 .caldac
= {caldac_none
},
1140 .device_id
= 0x70bf,
1144 .ai_fifo_depth
= 2047,
1145 .gainlkup
= ai_gain_628x
,
1149 .ao_fifo_depth
= 8191,
1150 .ao_range_table
= &range_ni_M_628x_ao
,
1151 .reg_type
= ni_reg_628x
,
1154 .num_p0_dio_channels
= 8,
1155 .caldac
= {caldac_none
},
1159 .device_id
= 0x70bc,
1163 .ai_fifo_depth
= 2047,
1164 .gainlkup
= ai_gain_628x
,
1169 .reg_type
= ni_reg_628x
,
1171 .num_p0_dio_channels
= 32,
1172 .caldac
= {caldac_none
},
1176 .device_id
= 0x70ac,
1180 .ai_fifo_depth
= 2047,
1181 .gainlkup
= ai_gain_628x
,
1185 .ao_fifo_depth
= 8191,
1186 .ao_range_table
= &range_ni_M_628x_ao
,
1187 .reg_type
= ni_reg_628x
,
1190 .num_p0_dio_channels
= 32,
1191 .caldac
= {caldac_none
},
1195 .device_id
= 0x70C0,
1199 .ai_fifo_depth
= 1024,
1201 .gainlkup
= ai_gain_6143
,
1205 .reg_type
= ni_reg_6143
,
1208 .num_p0_dio_channels
= 8,
1209 .caldac
= {ad8804_debug
, ad8804_debug
},
1212 .device_id
= 0x710D,
1216 .ai_fifo_depth
= 1024,
1218 .gainlkup
= ai_gain_6143
,
1222 .reg_type
= ni_reg_6143
,
1225 .num_p0_dio_channels
= 8,
1226 .caldac
= {ad8804_debug
, ad8804_debug
},
1230 #define n_pcimio_boards ARRAY_SIZE(ni_boards)
1232 static int pcimio_attach(struct comedi_device
*dev
,
1233 struct comedi_devconfig
*it
);
1234 static int pcimio_detach(struct comedi_device
*dev
);
1235 static struct comedi_driver driver_pcimio
= {
1236 .driver_name
= DRV_NAME
,
1237 .module
= THIS_MODULE
,
1238 .attach
= pcimio_attach
,
1239 .detach
= pcimio_detach
,
1242 static int __devinit
driver_pcimio_pci_probe(struct pci_dev
*dev
,
1243 const struct pci_device_id
*ent
)
1245 return comedi_pci_auto_config(dev
, driver_pcimio
.driver_name
);
1248 static void __devexit
driver_pcimio_pci_remove(struct pci_dev
*dev
)
1250 comedi_pci_auto_unconfig(dev
);
1253 static struct pci_driver driver_pcimio_pci_driver
= {
1254 .id_table
= ni_pci_table
,
1255 .probe
= &driver_pcimio_pci_probe
,
1256 .remove
= __devexit_p(&driver_pcimio_pci_remove
)
1259 static int __init
driver_pcimio_init_module(void)
1263 retval
= comedi_driver_register(&driver_pcimio
);
1267 driver_pcimio_pci_driver
.name
= (char *)driver_pcimio
.driver_name
;
1268 return pci_register_driver(&driver_pcimio_pci_driver
);
1271 static void __exit
driver_pcimio_cleanup_module(void)
1273 pci_unregister_driver(&driver_pcimio_pci_driver
);
1274 comedi_driver_unregister(&driver_pcimio
);
1277 module_init(driver_pcimio_init_module
);
1278 module_exit(driver_pcimio_cleanup_module
);
1282 #define devpriv ((struct ni_private *)dev->private)
1284 /* How we access registers */
1286 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1287 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1288 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1289 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1290 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1291 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1293 /* How we access STC registers */
1295 /* We automatically take advantage of STC registers that can be
1296 * read/written directly in the I/O space of the board. Most
1297 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1298 * The 611x devices map the write registers to iobase+addr*2, and
1299 * the read registers to iobase+(addr-1)*2. */
1300 /* However, the 611x boards still aren't working, so I'm disabling
1301 * non-windowed STC access temporarily */
1303 static void e_series_win_out(struct comedi_device
*dev
, uint16_t data
, int reg
)
1305 unsigned long flags
;
1307 spin_lock_irqsave(&devpriv
->window_lock
, flags
);
1308 ni_writew(reg
, Window_Address
);
1309 ni_writew(data
, Window_Data
);
1310 spin_unlock_irqrestore(&devpriv
->window_lock
, flags
);
1313 static uint16_t e_series_win_in(struct comedi_device
*dev
, int reg
)
1315 unsigned long flags
;
1318 spin_lock_irqsave(&devpriv
->window_lock
, flags
);
1319 ni_writew(reg
, Window_Address
);
1320 ret
= ni_readw(Window_Data
);
1321 spin_unlock_irqrestore(&devpriv
->window_lock
, flags
);
1326 static void m_series_stc_writew(struct comedi_device
*dev
, uint16_t data
,
1331 case ADC_FIFO_Clear
:
1332 offset
= M_Offset_AI_FIFO_Clear
;
1334 case AI_Command_1_Register
:
1335 offset
= M_Offset_AI_Command_1
;
1337 case AI_Command_2_Register
:
1338 offset
= M_Offset_AI_Command_2
;
1340 case AI_Mode_1_Register
:
1341 offset
= M_Offset_AI_Mode_1
;
1343 case AI_Mode_2_Register
:
1344 offset
= M_Offset_AI_Mode_2
;
1346 case AI_Mode_3_Register
:
1347 offset
= M_Offset_AI_Mode_3
;
1349 case AI_Output_Control_Register
:
1350 offset
= M_Offset_AI_Output_Control
;
1352 case AI_Personal_Register
:
1353 offset
= M_Offset_AI_Personal
;
1355 case AI_SI2_Load_A_Register
:
1356 /* this is actually a 32 bit register on m series boards */
1357 ni_writel(data
, M_Offset_AI_SI2_Load_A
);
1360 case AI_SI2_Load_B_Register
:
1361 /* this is actually a 32 bit register on m series boards */
1362 ni_writel(data
, M_Offset_AI_SI2_Load_B
);
1365 case AI_START_STOP_Select_Register
:
1366 offset
= M_Offset_AI_START_STOP_Select
;
1368 case AI_Trigger_Select_Register
:
1369 offset
= M_Offset_AI_Trigger_Select
;
1371 case Analog_Trigger_Etc_Register
:
1372 offset
= M_Offset_Analog_Trigger_Etc
;
1374 case AO_Command_1_Register
:
1375 offset
= M_Offset_AO_Command_1
;
1377 case AO_Command_2_Register
:
1378 offset
= M_Offset_AO_Command_2
;
1380 case AO_Mode_1_Register
:
1381 offset
= M_Offset_AO_Mode_1
;
1383 case AO_Mode_2_Register
:
1384 offset
= M_Offset_AO_Mode_2
;
1386 case AO_Mode_3_Register
:
1387 offset
= M_Offset_AO_Mode_3
;
1389 case AO_Output_Control_Register
:
1390 offset
= M_Offset_AO_Output_Control
;
1392 case AO_Personal_Register
:
1393 offset
= M_Offset_AO_Personal
;
1395 case AO_Start_Select_Register
:
1396 offset
= M_Offset_AO_Start_Select
;
1398 case AO_Trigger_Select_Register
:
1399 offset
= M_Offset_AO_Trigger_Select
;
1401 case Clock_and_FOUT_Register
:
1402 offset
= M_Offset_Clock_and_FOUT
;
1404 case Configuration_Memory_Clear
:
1405 offset
= M_Offset_Configuration_Memory_Clear
;
1407 case DAC_FIFO_Clear
:
1408 offset
= M_Offset_AO_FIFO_Clear
;
1410 case DIO_Control_Register
:
1412 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1416 case G_Autoincrement_Register(0):
1417 offset
= M_Offset_G0_Autoincrement
;
1419 case G_Autoincrement_Register(1):
1420 offset
= M_Offset_G1_Autoincrement
;
1422 case G_Command_Register(0):
1423 offset
= M_Offset_G0_Command
;
1425 case G_Command_Register(1):
1426 offset
= M_Offset_G1_Command
;
1428 case G_Input_Select_Register(0):
1429 offset
= M_Offset_G0_Input_Select
;
1431 case G_Input_Select_Register(1):
1432 offset
= M_Offset_G1_Input_Select
;
1434 case G_Mode_Register(0):
1435 offset
= M_Offset_G0_Mode
;
1437 case G_Mode_Register(1):
1438 offset
= M_Offset_G1_Mode
;
1440 case Interrupt_A_Ack_Register
:
1441 offset
= M_Offset_Interrupt_A_Ack
;
1443 case Interrupt_A_Enable_Register
:
1444 offset
= M_Offset_Interrupt_A_Enable
;
1446 case Interrupt_B_Ack_Register
:
1447 offset
= M_Offset_Interrupt_B_Ack
;
1449 case Interrupt_B_Enable_Register
:
1450 offset
= M_Offset_Interrupt_B_Enable
;
1452 case Interrupt_Control_Register
:
1453 offset
= M_Offset_Interrupt_Control
;
1455 case IO_Bidirection_Pin_Register
:
1456 offset
= M_Offset_IO_Bidirection_Pin
;
1458 case Joint_Reset_Register
:
1459 offset
= M_Offset_Joint_Reset
;
1461 case RTSI_Trig_A_Output_Register
:
1462 offset
= M_Offset_RTSI_Trig_A_Output
;
1464 case RTSI_Trig_B_Output_Register
:
1465 offset
= M_Offset_RTSI_Trig_B_Output
;
1467 case RTSI_Trig_Direction_Register
:
1468 offset
= M_Offset_RTSI_Trig_Direction
;
1470 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1471 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1473 printk("%s: bug! unhandled register=0x%x in switch.\n",
1479 ni_writew(data
, offset
);
1482 static uint16_t m_series_stc_readw(struct comedi_device
*dev
, int reg
)
1486 case AI_Status_1_Register
:
1487 offset
= M_Offset_AI_Status_1
;
1489 case AO_Status_1_Register
:
1490 offset
= M_Offset_AO_Status_1
;
1492 case AO_Status_2_Register
:
1493 offset
= M_Offset_AO_Status_2
;
1495 case DIO_Serial_Input_Register
:
1496 return ni_readb(M_Offset_SCXI_Serial_Data_In
);
1498 case Joint_Status_1_Register
:
1499 offset
= M_Offset_Joint_Status_1
;
1501 case Joint_Status_2_Register
:
1502 offset
= M_Offset_Joint_Status_2
;
1504 case G_Status_Register
:
1505 offset
= M_Offset_G01_Status
;
1508 printk("%s: bug! unhandled register=0x%x in switch.\n",
1514 return ni_readw(offset
);
1517 static void m_series_stc_writel(struct comedi_device
*dev
, uint32_t data
,
1522 case AI_SC_Load_A_Registers
:
1523 offset
= M_Offset_AI_SC_Load_A
;
1525 case AI_SI_Load_A_Registers
:
1526 offset
= M_Offset_AI_SI_Load_A
;
1528 case AO_BC_Load_A_Register
:
1529 offset
= M_Offset_AO_BC_Load_A
;
1531 case AO_UC_Load_A_Register
:
1532 offset
= M_Offset_AO_UC_Load_A
;
1534 case AO_UI_Load_A_Register
:
1535 offset
= M_Offset_AO_UI_Load_A
;
1537 case G_Load_A_Register(0):
1538 offset
= M_Offset_G0_Load_A
;
1540 case G_Load_A_Register(1):
1541 offset
= M_Offset_G1_Load_A
;
1543 case G_Load_B_Register(0):
1544 offset
= M_Offset_G0_Load_B
;
1546 case G_Load_B_Register(1):
1547 offset
= M_Offset_G1_Load_B
;
1550 printk("%s: bug! unhandled register=0x%x in switch.\n",
1556 ni_writel(data
, offset
);
1559 static uint32_t m_series_stc_readl(struct comedi_device
*dev
, int reg
)
1563 case G_HW_Save_Register(0):
1564 offset
= M_Offset_G0_HW_Save
;
1566 case G_HW_Save_Register(1):
1567 offset
= M_Offset_G1_HW_Save
;
1569 case G_Save_Register(0):
1570 offset
= M_Offset_G0_Save
;
1572 case G_Save_Register(1):
1573 offset
= M_Offset_G1_Save
;
1576 printk("%s: bug! unhandled register=0x%x in switch.\n",
1582 return ni_readl(offset
);
1585 #define interrupt_pin(a) 0
1586 #define IRQ_POLARITY 1
1588 #define NI_E_IRQ_FLAGS IRQF_SHARED
1590 #include "ni_mio_common.c"
1592 static int pcimio_find_device(struct comedi_device
*dev
, int bus
, int slot
);
1593 static int pcimio_ai_change(struct comedi_device
*dev
,
1594 struct comedi_subdevice
*s
, unsigned long new_size
);
1595 static int pcimio_ao_change(struct comedi_device
*dev
,
1596 struct comedi_subdevice
*s
, unsigned long new_size
);
1597 static int pcimio_gpct0_change(struct comedi_device
*dev
,
1598 struct comedi_subdevice
*s
,
1599 unsigned long new_size
);
1600 static int pcimio_gpct1_change(struct comedi_device
*dev
,
1601 struct comedi_subdevice
*s
,
1602 unsigned long new_size
);
1603 static int pcimio_dio_change(struct comedi_device
*dev
,
1604 struct comedi_subdevice
*s
,
1605 unsigned long new_size
);
1607 static void m_series_init_eeprom_buffer(struct comedi_device
*dev
)
1609 static const int Start_Cal_EEPROM
= 0x400;
1610 static const unsigned window_size
= 10;
1611 static const int serial_number_eeprom_offset
= 0x4;
1612 static const int serial_number_eeprom_length
= 0x4;
1613 unsigned old_iodwbsr_bits
;
1614 unsigned old_iodwbsr1_bits
;
1615 unsigned old_iodwcr1_bits
;
1618 old_iodwbsr_bits
= readl(devpriv
->mite
->mite_io_addr
+ MITE_IODWBSR
);
1619 old_iodwbsr1_bits
= readl(devpriv
->mite
->mite_io_addr
+ MITE_IODWBSR_1
);
1620 old_iodwcr1_bits
= readl(devpriv
->mite
->mite_io_addr
+ MITE_IODWCR_1
);
1621 writel(0x0, devpriv
->mite
->mite_io_addr
+ MITE_IODWBSR
);
1622 writel(((0x80 | window_size
) | devpriv
->mite
->daq_phys_addr
),
1623 devpriv
->mite
->mite_io_addr
+ MITE_IODWBSR_1
);
1624 writel(0x1 | old_iodwcr1_bits
,
1625 devpriv
->mite
->mite_io_addr
+ MITE_IODWCR_1
);
1626 writel(0xf, devpriv
->mite
->mite_io_addr
+ 0x30);
1628 BUG_ON(serial_number_eeprom_length
> sizeof(devpriv
->serial_number
));
1629 for (i
= 0; i
< serial_number_eeprom_length
; ++i
) {
1630 char *byte_ptr
= (char *)&devpriv
->serial_number
+ i
;
1631 *byte_ptr
= ni_readb(serial_number_eeprom_offset
+ i
);
1633 devpriv
->serial_number
= be32_to_cpu(devpriv
->serial_number
);
1635 for (i
= 0; i
< M_SERIES_EEPROM_SIZE
; ++i
) {
1636 devpriv
->eeprom_buffer
[i
] = ni_readb(Start_Cal_EEPROM
+ i
);
1639 writel(old_iodwbsr1_bits
, devpriv
->mite
->mite_io_addr
+ MITE_IODWBSR_1
);
1640 writel(old_iodwbsr_bits
, devpriv
->mite
->mite_io_addr
+ MITE_IODWBSR
);
1641 writel(old_iodwcr1_bits
, devpriv
->mite
->mite_io_addr
+ MITE_IODWCR_1
);
1642 writel(0x0, devpriv
->mite
->mite_io_addr
+ 0x30);
1645 static void init_6143(struct comedi_device
*dev
)
1647 /* Disable interrupts */
1648 devpriv
->stc_writew(dev
, 0, Interrupt_Control_Register
);
1650 /* Initialise 6143 AI specific bits */
1651 ni_writeb(0x00, Magic_6143
); /* Set G0,G1 DMA mode to E series version */
1652 ni_writeb(0x80, PipelineDelay_6143
); /* Set EOCMode, ADCMode and pipelinedelay */
1653 ni_writeb(0x00, EOC_Set_6143
); /* Set EOC Delay */
1655 ni_writel(boardtype
.ai_fifo_depth
/ 2, AIFIFO_Flag_6143
); /* Set the FIFO half full level */
1657 /* Strobe Relay disable bit */
1658 devpriv
->ai_calib_source_enabled
= 0;
1659 ni_writew(devpriv
->ai_calib_source
| Calibration_Channel_6143_RelayOff
,
1660 Calibration_Channel_6143
);
1661 ni_writew(devpriv
->ai_calib_source
, Calibration_Channel_6143
);
1664 /* cleans up allocated resources */
1665 static int pcimio_detach(struct comedi_device
*dev
)
1667 mio_common_detach(dev
);
1669 free_irq(dev
->irq
, dev
);
1672 mite_free_ring(devpriv
->ai_mite_ring
);
1673 mite_free_ring(devpriv
->ao_mite_ring
);
1674 mite_free_ring(devpriv
->cdo_mite_ring
);
1675 mite_free_ring(devpriv
->gpct_mite_ring
[0]);
1676 mite_free_ring(devpriv
->gpct_mite_ring
[1]);
1678 mite_unsetup(devpriv
->mite
);
1684 static int pcimio_attach(struct comedi_device
*dev
, struct comedi_devconfig
*it
)
1688 printk("comedi%d: ni_pcimio:", dev
->minor
);
1690 ret
= ni_alloc_private(dev
);
1694 ret
= pcimio_find_device(dev
, it
->options
[0], it
->options
[1]);
1698 printk(" %s", boardtype
.name
);
1699 dev
->board_name
= boardtype
.name
;
1701 if (boardtype
.reg_type
& ni_reg_m_series_mask
) {
1702 devpriv
->stc_writew
= &m_series_stc_writew
;
1703 devpriv
->stc_readw
= &m_series_stc_readw
;
1704 devpriv
->stc_writel
= &m_series_stc_writel
;
1705 devpriv
->stc_readl
= &m_series_stc_readl
;
1707 devpriv
->stc_writew
= &e_series_win_out
;
1708 devpriv
->stc_readw
= &e_series_win_in
;
1709 devpriv
->stc_writel
= &win_out2
;
1710 devpriv
->stc_readl
= &win_in2
;
1713 ret
= mite_setup(devpriv
->mite
);
1715 printk(" error setting up mite\n");
1718 comedi_set_hw_dev(dev
, &devpriv
->mite
->pcidev
->dev
);
1719 devpriv
->ai_mite_ring
= mite_alloc_ring(devpriv
->mite
);
1720 if (devpriv
->ai_mite_ring
== NULL
)
1722 devpriv
->ao_mite_ring
= mite_alloc_ring(devpriv
->mite
);
1723 if (devpriv
->ao_mite_ring
== NULL
)
1725 devpriv
->cdo_mite_ring
= mite_alloc_ring(devpriv
->mite
);
1726 if (devpriv
->cdo_mite_ring
== NULL
)
1728 devpriv
->gpct_mite_ring
[0] = mite_alloc_ring(devpriv
->mite
);
1729 if (devpriv
->gpct_mite_ring
[0] == NULL
)
1731 devpriv
->gpct_mite_ring
[1] = mite_alloc_ring(devpriv
->mite
);
1732 if (devpriv
->gpct_mite_ring
[1] == NULL
)
1735 if (boardtype
.reg_type
& ni_reg_m_series_mask
)
1736 m_series_init_eeprom_buffer(dev
);
1737 if (boardtype
.reg_type
== ni_reg_6143
)
1740 dev
->irq
= mite_irq(devpriv
->mite
);
1742 if (dev
->irq
== 0) {
1743 printk(" unknown irq (bad)\n");
1745 printk(" ( irq = %u )", dev
->irq
);
1746 ret
= request_irq(dev
->irq
, ni_E_interrupt
, NI_E_IRQ_FLAGS
,
1749 printk(" irq not available\n");
1754 ret
= ni_E_init(dev
, it
);
1758 dev
->subdevices
[NI_AI_SUBDEV
].buf_change
= &pcimio_ai_change
;
1759 dev
->subdevices
[NI_AO_SUBDEV
].buf_change
= &pcimio_ao_change
;
1760 dev
->subdevices
[NI_GPCT_SUBDEV(0)].buf_change
= &pcimio_gpct0_change
;
1761 dev
->subdevices
[NI_GPCT_SUBDEV(1)].buf_change
= &pcimio_gpct1_change
;
1762 dev
->subdevices
[NI_DIO_SUBDEV
].buf_change
= &pcimio_dio_change
;
1767 static int pcimio_find_device(struct comedi_device
*dev
, int bus
, int slot
)
1769 struct mite_struct
*mite
;
1772 for (mite
= mite_devices
; mite
; mite
= mite
->next
) {
1776 if (bus
!= mite
->pcidev
->bus
->number
||
1777 slot
!= PCI_SLOT(mite
->pcidev
->devfn
))
1781 for (i
= 0; i
< n_pcimio_boards
; i
++) {
1782 if (mite_device_id(mite
) == ni_boards
[i
].device_id
) {
1783 dev
->board_ptr
= ni_boards
+ i
;
1784 devpriv
->mite
= mite
;
1790 printk("no device found\n");
1791 mite_list_devices();
1795 static int pcimio_ai_change(struct comedi_device
*dev
,
1796 struct comedi_subdevice
*s
, unsigned long new_size
)
1800 ret
= mite_buf_change(devpriv
->ai_mite_ring
, s
->async
);
1807 static int pcimio_ao_change(struct comedi_device
*dev
,
1808 struct comedi_subdevice
*s
, unsigned long new_size
)
1812 ret
= mite_buf_change(devpriv
->ao_mite_ring
, s
->async
);
1819 static int pcimio_gpct0_change(struct comedi_device
*dev
,
1820 struct comedi_subdevice
*s
,
1821 unsigned long new_size
)
1825 ret
= mite_buf_change(devpriv
->gpct_mite_ring
[0], s
->async
);
1832 static int pcimio_gpct1_change(struct comedi_device
*dev
,
1833 struct comedi_subdevice
*s
,
1834 unsigned long new_size
)
1838 ret
= mite_buf_change(devpriv
->gpct_mite_ring
[1], s
->async
);
1845 static int pcimio_dio_change(struct comedi_device
*dev
,
1846 struct comedi_subdevice
*s
, unsigned long new_size
)
1850 ret
= mite_buf_change(devpriv
->cdo_mite_ring
, s
->async
);