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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / gsc_hpdi.c
1 /*
2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
8
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25
26 ************************************************************************/
27
28 /*
29 * Driver: gsc_hpdi
30 * Description: General Standards Corporation High
31 * Speed Parallel Digital Interface rs485 boards
32 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
33 * Status: only receive mode works, transmit not supported
34 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
35 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
36 * PMC-HPDI32
37 *
38 * Configuration options:
39 * None.
40 *
41 * Manual configuration of supported devices is not supported; they are
42 * configured automatically.
43 *
44 * There are some additional hpdi models available from GSC for which
45 * support could be added to this driver.
46 */
47
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50 #include <linux/pci.h>
51 #include <linux/delay.h>
52 #include <linux/interrupt.h>
53
54 #include "../comedidev.h"
55
56 #include "plx9080.h"
57 #include "comedi_fc.h"
58
59 static void abort_dma(struct comedi_device *dev, unsigned int channel);
60 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
61 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
62 struct comedi_cmd *cmd);
63 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
64 static irqreturn_t handle_interrupt(int irq, void *d);
65 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data);
66
67 #undef HPDI_DEBUG /* disable debugging messages */
68 /* #define HPDI_DEBUG enable debugging code */
69
70 #ifdef HPDI_DEBUG
71 #define DEBUG_PRINT(format, args...) pr_debug(format , ## args)
72 #else
73 #define DEBUG_PRINT(format, args...) no_printk(pr_fmt(format), ## args)
74 #endif
75
76 #define TIMER_BASE 50 /* 20MHz master clock */
77 #define DMA_BUFFER_SIZE 0x10000
78 #define NUM_DMA_BUFFERS 4
79 #define NUM_DMA_DESCRIPTORS 256
80
81 enum hpdi_registers {
82 FIRMWARE_REV_REG = 0x0,
83 BOARD_CONTROL_REG = 0x4,
84 BOARD_STATUS_REG = 0x8,
85 TX_PROG_ALMOST_REG = 0xc,
86 RX_PROG_ALMOST_REG = 0x10,
87 FEATURES_REG = 0x14,
88 FIFO_REG = 0x18,
89 TX_STATUS_COUNT_REG = 0x1c,
90 TX_LINE_VALID_COUNT_REG = 0x20,
91 TX_LINE_INVALID_COUNT_REG = 0x24,
92 RX_STATUS_COUNT_REG = 0x28,
93 RX_LINE_COUNT_REG = 0x2c,
94 INTERRUPT_CONTROL_REG = 0x30,
95 INTERRUPT_STATUS_REG = 0x34,
96 TX_CLOCK_DIVIDER_REG = 0x38,
97 TX_FIFO_SIZE_REG = 0x40,
98 RX_FIFO_SIZE_REG = 0x44,
99 TX_FIFO_WORDS_REG = 0x48,
100 RX_FIFO_WORDS_REG = 0x4c,
101 INTERRUPT_EDGE_LEVEL_REG = 0x50,
102 INTERRUPT_POLARITY_REG = 0x54,
103 };
104
105 /* bit definitions */
106
107 enum firmware_revision_bits {
108 FEATURES_REG_PRESENT_BIT = 0x8000,
109 };
110
111 enum board_control_bits {
112 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
113 TX_FIFO_RESET_BIT = 0x2,
114 RX_FIFO_RESET_BIT = 0x4,
115 TX_ENABLE_BIT = 0x10,
116 RX_ENABLE_BIT = 0x20,
117 DEMAND_DMA_DIRECTION_TX_BIT = 0x40,
118 /* for ch 0, ch 1 can only transmit (when present) */
119 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
120 START_TX_BIT = 0x10,
121 CABLE_THROTTLE_ENABLE_BIT = 0x20,
122 TEST_MODE_ENABLE_BIT = 0x80000000,
123 };
124
125 enum board_status_bits {
126 COMMAND_LINE_STATUS_MASK = 0x7f,
127 TX_IN_PROGRESS_BIT = 0x80,
128 TX_NOT_EMPTY_BIT = 0x100,
129 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
130 TX_NOT_ALMOST_FULL_BIT = 0x400,
131 TX_NOT_FULL_BIT = 0x800,
132 RX_NOT_EMPTY_BIT = 0x1000,
133 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
134 RX_NOT_ALMOST_FULL_BIT = 0x4000,
135 RX_NOT_FULL_BIT = 0x8000,
136 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
137 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
138 TX_OVERRUN_BIT = 0x200000,
139 RX_UNDERRUN_BIT = 0x400000,
140 RX_OVERRUN_BIT = 0x800000,
141 };
142
143 static uint32_t almost_full_bits(unsigned int num_words)
144 {
145 /* XXX need to add or subtract one? */
146 return (num_words << 16) & 0xff0000;
147 }
148
149 static uint32_t almost_empty_bits(unsigned int num_words)
150 {
151 return num_words & 0xffff;
152 }
153
154 enum features_bits {
155 FIFO_SIZE_PRESENT_BIT = 0x1,
156 FIFO_WORDS_PRESENT_BIT = 0x2,
157 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
158 GPIO_SUPPORTED_BIT = 0x8,
159 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
160 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
161 };
162
163 enum interrupt_sources {
164 FRAME_VALID_START_INTR = 0,
165 FRAME_VALID_END_INTR = 1,
166 TX_FIFO_EMPTY_INTR = 8,
167 TX_FIFO_ALMOST_EMPTY_INTR = 9,
168 TX_FIFO_ALMOST_FULL_INTR = 10,
169 TX_FIFO_FULL_INTR = 11,
170 RX_EMPTY_INTR = 12,
171 RX_ALMOST_EMPTY_INTR = 13,
172 RX_ALMOST_FULL_INTR = 14,
173 RX_FULL_INTR = 15,
174 };
175
176 static uint32_t intr_bit(int interrupt_source)
177 {
178 return 0x1 << interrupt_source;
179 }
180
181 static unsigned int fifo_size(uint32_t fifo_size_bits)
182 {
183 return fifo_size_bits & 0xfffff;
184 }
185
186 struct hpdi_board {
187 const char *name; /* board name */
188 int device_id; /* pci device id */
189 int subdevice_id; /* pci subdevice id */
190 };
191
192 static const struct hpdi_board hpdi_boards[] = {
193 {
194 .name = "pci-hpdi32",
195 .device_id = PCI_DEVICE_ID_PLX_9080,
196 .subdevice_id = 0x2400,
197 },
198 #if 0
199 {
200 .name = "pxi-hpdi32",
201 .device_id = 0x9656,
202 .subdevice_id = 0x2705,
203 },
204 #endif
205 };
206
207 struct hpdi_private {
208 /* base addresses (ioremapped) */
209 void __iomem *plx9080_iobase;
210 void __iomem *hpdi_iobase;
211 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
212 /* physical addresses of dma buffers */
213 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
214 /* array of dma descriptors read by plx9080, allocated to get proper
215 * alignment */
216 struct plx_dma_desc *dma_desc;
217 /* physical address of dma descriptor array */
218 dma_addr_t dma_desc_phys_addr;
219 unsigned int num_dma_descriptors;
220 /* pointer to start of buffers indexed by descriptor */
221 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
222 /* index of the dma descriptor that is currently being used */
223 volatile unsigned int dma_desc_index;
224 unsigned int tx_fifo_size;
225 unsigned int rx_fifo_size;
226 volatile unsigned long dio_count;
227 /* software copies of values written to hpdi registers */
228 volatile uint32_t bits[24];
229 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
230 volatile unsigned int block_size;
231 unsigned dio_config_output:1;
232 };
233
234 static int dio_config_insn(struct comedi_device *dev,
235 struct comedi_subdevice *s, struct comedi_insn *insn,
236 unsigned int *data)
237 {
238 struct hpdi_private *devpriv = dev->private;
239
240 switch (data[0]) {
241 case INSN_CONFIG_DIO_OUTPUT:
242 devpriv->dio_config_output = 1;
243 return insn->n;
244 break;
245 case INSN_CONFIG_DIO_INPUT:
246 devpriv->dio_config_output = 0;
247 return insn->n;
248 break;
249 case INSN_CONFIG_DIO_QUERY:
250 data[1] =
251 devpriv->dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
252 return insn->n;
253 break;
254 case INSN_CONFIG_BLOCK_SIZE:
255 return dio_config_block_size(dev, data);
256 break;
257 default:
258 break;
259 }
260
261 return -EINVAL;
262 }
263
264 static void disable_plx_interrupts(struct comedi_device *dev)
265 {
266 struct hpdi_private *devpriv = dev->private;
267
268 writel(0, devpriv->plx9080_iobase + PLX_INTRCS_REG);
269 }
270
271 /* initialize plx9080 chip */
272 static void init_plx9080(struct comedi_device *dev)
273 {
274 struct hpdi_private *devpriv = dev->private;
275 uint32_t bits;
276 void __iomem *plx_iobase = devpriv->plx9080_iobase;
277
278 /* plx9080 dump */
279 DEBUG_PRINT(" plx interrupt status 0x%x\n",
280 readl(plx_iobase + PLX_INTRCS_REG));
281 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
282 DEBUG_PRINT(" plx control reg 0x%x\n",
283 readl(devpriv->plx9080_iobase + PLX_CONTROL_REG));
284
285 DEBUG_PRINT(" plx revision 0x%x\n",
286 readl(plx_iobase + PLX_REVISION_REG));
287 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
288 readl(plx_iobase + PLX_DMA0_MODE_REG));
289 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
290 readl(plx_iobase + PLX_DMA1_MODE_REG));
291 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
292 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
293 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
294 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
295 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
296 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
297 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
298 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
299 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
300 readb(plx_iobase + PLX_DMA0_CS_REG));
301 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
302 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
303 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
304 #ifdef __BIG_ENDIAN
305 bits = BIGEND_DMA0 | BIGEND_DMA1;
306 #else
307 bits = 0;
308 #endif
309 writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
310
311 disable_plx_interrupts(dev);
312
313 abort_dma(dev, 0);
314 abort_dma(dev, 1);
315
316 /* configure dma0 mode */
317 bits = 0;
318 /* enable ready input */
319 bits |= PLX_DMA_EN_READYIN_BIT;
320 /* enable dma chaining */
321 bits |= PLX_EN_CHAIN_BIT;
322 /* enable interrupt on dma done
323 * (probably don't need this, since chain never finishes) */
324 bits |= PLX_EN_DMA_DONE_INTR_BIT;
325 /* don't increment local address during transfers
326 * (we are transferring from a fixed fifo register) */
327 bits |= PLX_LOCAL_ADDR_CONST_BIT;
328 /* route dma interrupt to pci bus */
329 bits |= PLX_DMA_INTR_PCI_BIT;
330 /* enable demand mode */
331 bits |= PLX_DEMAND_MODE_BIT;
332 /* enable local burst mode */
333 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
334 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
335 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
336 }
337
338 /* Allocate and initialize the subdevice structures.
339 */
340 static int setup_subdevices(struct comedi_device *dev)
341 {
342 struct comedi_subdevice *s;
343 int ret;
344
345 ret = comedi_alloc_subdevices(dev, 1);
346 if (ret)
347 return ret;
348
349 s = &dev->subdevices[0];
350 /* analog input subdevice */
351 dev->read_subdev = s;
352 /* dev->write_subdev = s; */
353 s->type = COMEDI_SUBD_DIO;
354 s->subdev_flags =
355 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
356 s->n_chan = 32;
357 s->len_chanlist = 32;
358 s->maxdata = 1;
359 s->range_table = &range_digital;
360 s->insn_config = dio_config_insn;
361 s->do_cmd = hpdi_cmd;
362 s->do_cmdtest = hpdi_cmd_test;
363 s->cancel = hpdi_cancel;
364
365 return 0;
366 }
367
368 static int init_hpdi(struct comedi_device *dev)
369 {
370 struct hpdi_private *devpriv = dev->private;
371 uint32_t plx_intcsr_bits;
372
373 writel(BOARD_RESET_BIT, devpriv->hpdi_iobase + BOARD_CONTROL_REG);
374 udelay(10);
375
376 writel(almost_empty_bits(32) | almost_full_bits(32),
377 devpriv->hpdi_iobase + RX_PROG_ALMOST_REG);
378 writel(almost_empty_bits(32) | almost_full_bits(32),
379 devpriv->hpdi_iobase + TX_PROG_ALMOST_REG);
380
381 devpriv->tx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
382 TX_FIFO_SIZE_REG));
383 devpriv->rx_fifo_size = fifo_size(readl(devpriv->hpdi_iobase +
384 RX_FIFO_SIZE_REG));
385
386 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
387
388 /* enable interrupts */
389 plx_intcsr_bits =
390 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
391 ICS_DMA0_E;
392 writel(plx_intcsr_bits, devpriv->plx9080_iobase + PLX_INTRCS_REG);
393
394 return 0;
395 }
396
397 /* setup dma descriptors so a link completes every 'transfer_size' bytes */
398 static int setup_dma_descriptors(struct comedi_device *dev,
399 unsigned int transfer_size)
400 {
401 struct hpdi_private *devpriv = dev->private;
402 unsigned int buffer_index, buffer_offset;
403 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
404 PLX_XFER_LOCAL_TO_PCI;
405 unsigned int i;
406
407 if (transfer_size > DMA_BUFFER_SIZE)
408 transfer_size = DMA_BUFFER_SIZE;
409 transfer_size -= transfer_size % sizeof(uint32_t);
410 if (transfer_size == 0)
411 return -1;
412
413 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
414 DEBUG_PRINT(" descriptors at 0x%lx\n",
415 (unsigned long)devpriv->dma_desc_phys_addr);
416
417 buffer_offset = 0;
418 buffer_index = 0;
419 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
420 buffer_index < NUM_DMA_BUFFERS; i++) {
421 devpriv->dma_desc[i].pci_start_addr =
422 cpu_to_le32(devpriv->dio_buffer_phys_addr[buffer_index] +
423 buffer_offset);
424 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
425 devpriv->dma_desc[i].transfer_size =
426 cpu_to_le32(transfer_size);
427 devpriv->dma_desc[i].next =
428 cpu_to_le32((devpriv->dma_desc_phys_addr + (i +
429 1) *
430 sizeof(devpriv->dma_desc[0])) | next_bits);
431
432 devpriv->desc_dio_buffer[i] =
433 devpriv->dio_buffer[buffer_index] +
434 (buffer_offset / sizeof(uint32_t));
435
436 buffer_offset += transfer_size;
437 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
438 buffer_offset = 0;
439 buffer_index++;
440 }
441
442 DEBUG_PRINT(" desc %i\n", i);
443 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
444 devpriv->desc_dio_buffer[i],
445 (unsigned long)devpriv->dma_desc[i].
446 pci_start_addr);
447 DEBUG_PRINT(" next 0x%lx\n",
448 (unsigned long)devpriv->dma_desc[i].next);
449 }
450 devpriv->num_dma_descriptors = i;
451 /* fix last descriptor to point back to first */
452 devpriv->dma_desc[i - 1].next =
453 cpu_to_le32(devpriv->dma_desc_phys_addr | next_bits);
454 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
455 (unsigned long)devpriv->dma_desc[i - 1].next);
456
457 devpriv->block_size = transfer_size;
458
459 return transfer_size;
460 }
461
462 static const struct hpdi_board *hpdi_find_board(struct pci_dev *pcidev)
463 {
464 unsigned int i;
465
466 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
467 if (pcidev->device == hpdi_boards[i].device_id &&
468 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
469 return &hpdi_boards[i];
470 return NULL;
471 }
472
473 static int hpdi_auto_attach(struct comedi_device *dev,
474 unsigned long context_unused)
475 {
476 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
477 const struct hpdi_board *thisboard;
478 struct hpdi_private *devpriv;
479 int i;
480 int retval;
481
482 thisboard = hpdi_find_board(pcidev);
483 if (!thisboard) {
484 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
485 pci_name(pcidev));
486 return -EINVAL;
487 }
488 dev->board_ptr = thisboard;
489 dev->board_name = thisboard->name;
490
491 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
492 if (!devpriv)
493 return -ENOMEM;
494 dev->private = devpriv;
495
496 retval = comedi_pci_enable(dev);
497 if (retval)
498 return retval;
499 pci_set_master(pcidev);
500
501 devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
502 devpriv->hpdi_iobase = pci_ioremap_bar(pcidev, 2);
503 if (!devpriv->plx9080_iobase || !devpriv->hpdi_iobase) {
504 dev_warn(dev->class_dev, "failed to remap io memory\n");
505 return -ENOMEM;
506 }
507
508 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", devpriv->plx9080_iobase);
509 DEBUG_PRINT(" hpdi remapped to 0x%p\n", devpriv->hpdi_iobase);
510
511 init_plx9080(dev);
512
513 /* get irq */
514 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
515 dev->board_name, dev)) {
516 dev_warn(dev->class_dev,
517 "unable to allocate irq %u\n", pcidev->irq);
518 return -EINVAL;
519 }
520 dev->irq = pcidev->irq;
521
522 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
523
524 /* allocate pci dma buffers */
525 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
526 devpriv->dio_buffer[i] =
527 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
528 &devpriv->dio_buffer_phys_addr[i]);
529 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
530 devpriv->dio_buffer[i],
531 (unsigned long)devpriv->dio_buffer_phys_addr[i]);
532 }
533 /* allocate dma descriptors */
534 devpriv->dma_desc = pci_alloc_consistent(pcidev,
535 sizeof(struct plx_dma_desc) *
536 NUM_DMA_DESCRIPTORS,
537 &devpriv->dma_desc_phys_addr);
538 if (devpriv->dma_desc_phys_addr & 0xf) {
539 dev_warn(dev->class_dev,
540 " dma descriptors not quad-word aligned (bug)\n");
541 return -EIO;
542 }
543
544 retval = setup_dma_descriptors(dev, 0x1000);
545 if (retval < 0)
546 return retval;
547
548 retval = setup_subdevices(dev);
549 if (retval < 0)
550 return retval;
551
552 return init_hpdi(dev);
553 }
554
555 static void hpdi_detach(struct comedi_device *dev)
556 {
557 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
558 struct hpdi_private *devpriv = dev->private;
559 unsigned int i;
560
561 if (dev->irq)
562 free_irq(dev->irq, dev);
563 if (devpriv) {
564 if (devpriv->plx9080_iobase) {
565 disable_plx_interrupts(dev);
566 iounmap(devpriv->plx9080_iobase);
567 }
568 if (devpriv->hpdi_iobase)
569 iounmap(devpriv->hpdi_iobase);
570 /* free pci dma buffers */
571 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
572 if (devpriv->dio_buffer[i])
573 pci_free_consistent(pcidev,
574 DMA_BUFFER_SIZE,
575 devpriv->dio_buffer[i],
576 devpriv->
577 dio_buffer_phys_addr[i]);
578 }
579 /* free dma descriptors */
580 if (devpriv->dma_desc)
581 pci_free_consistent(pcidev,
582 sizeof(struct plx_dma_desc) *
583 NUM_DMA_DESCRIPTORS,
584 devpriv->dma_desc,
585 devpriv->dma_desc_phys_addr);
586 }
587 comedi_pci_disable(dev);
588 }
589
590 static int dio_config_block_size(struct comedi_device *dev, unsigned int *data)
591 {
592 unsigned int requested_block_size;
593 int retval;
594
595 requested_block_size = data[1];
596
597 retval = setup_dma_descriptors(dev, requested_block_size);
598 if (retval < 0)
599 return retval;
600
601 data[1] = retval;
602
603 return 2;
604 }
605
606 static int di_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
607 struct comedi_cmd *cmd)
608 {
609 int err = 0;
610 int i;
611
612 /* Step 1 : check if triggers are trivially valid */
613
614 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
615 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
616 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
617 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
618 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
619
620 if (err)
621 return 1;
622
623 /* Step 2a : make sure trigger sources are unique */
624
625 err |= cfc_check_trigger_is_unique(cmd->stop_src);
626
627 /* Step 2b : and mutually compatible */
628
629 if (err)
630 return 2;
631
632 /* Step 3: check if arguments are trivially valid */
633
634 if (!cmd->chanlist_len) {
635 cmd->chanlist_len = 32;
636 err |= -EINVAL;
637 }
638 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
639
640 switch (cmd->stop_src) {
641 case TRIG_COUNT:
642 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
643 break;
644 case TRIG_NONE:
645 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
646 break;
647 default:
648 break;
649 }
650
651 if (err)
652 return 3;
653
654 /* step 4: fix up any arguments */
655
656 if (err)
657 return 4;
658
659 if (!cmd->chanlist)
660 return 0;
661
662 for (i = 1; i < cmd->chanlist_len; i++) {
663 if (CR_CHAN(cmd->chanlist[i]) != i) {
664 /* XXX could support 8 or 16 channels */
665 comedi_error(dev,
666 "chanlist must be ch 0 to 31 in order");
667 err++;
668 break;
669 }
670 }
671
672 if (err)
673 return 5;
674
675 return 0;
676 }
677
678 static int hpdi_cmd_test(struct comedi_device *dev, struct comedi_subdevice *s,
679 struct comedi_cmd *cmd)
680 {
681 struct hpdi_private *devpriv = dev->private;
682
683 if (devpriv->dio_config_output)
684 return -EINVAL;
685 else
686 return di_cmd_test(dev, s, cmd);
687 }
688
689 static inline void hpdi_writel(struct comedi_device *dev, uint32_t bits,
690 unsigned int offset)
691 {
692 struct hpdi_private *devpriv = dev->private;
693
694 writel(bits | devpriv->bits[offset / sizeof(uint32_t)],
695 devpriv->hpdi_iobase + offset);
696 }
697
698 static int di_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
699 {
700 struct hpdi_private *devpriv = dev->private;
701 uint32_t bits;
702 unsigned long flags;
703 struct comedi_async *async = s->async;
704 struct comedi_cmd *cmd = &async->cmd;
705
706 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
707
708 DEBUG_PRINT("hpdi: in di_cmd\n");
709
710 abort_dma(dev, 0);
711
712 devpriv->dma_desc_index = 0;
713
714 /* These register are supposedly unused during chained dma,
715 * but I have found that left over values from last operation
716 * occasionally cause problems with transfer of first dma
717 * block. Initializing them to zero seems to fix the problem. */
718 writel(0, devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
719 writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
720 writel(0, devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
721 /* give location of first dma descriptor */
722 bits =
723 devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
724 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
725 writel(bits, devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
726
727 /* spinlock for plx dma control/status reg */
728 spin_lock_irqsave(&dev->spinlock, flags);
729 /* enable dma transfer */
730 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
731 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
732 spin_unlock_irqrestore(&dev->spinlock, flags);
733
734 if (cmd->stop_src == TRIG_COUNT)
735 devpriv->dio_count = cmd->stop_arg;
736 else
737 devpriv->dio_count = 1;
738
739 /* clear over/under run status flags */
740 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
741 devpriv->hpdi_iobase + BOARD_STATUS_REG);
742 /* enable interrupts */
743 writel(intr_bit(RX_FULL_INTR),
744 devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
745
746 DEBUG_PRINT("hpdi: starting rx\n");
747 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
748
749 return 0;
750 }
751
752 static int hpdi_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
753 {
754 struct hpdi_private *devpriv = dev->private;
755
756 if (devpriv->dio_config_output)
757 return -EINVAL;
758 else
759 return di_cmd(dev, s);
760 }
761
762 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
763 {
764 struct hpdi_private *devpriv = dev->private;
765 struct comedi_async *async = dev->read_subdev->async;
766 uint32_t next_transfer_addr;
767 int j;
768 int num_samples = 0;
769 void __iomem *pci_addr_reg;
770
771 if (channel)
772 pci_addr_reg =
773 devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
774 else
775 pci_addr_reg =
776 devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
777
778 /* loop until we have read all the full buffers */
779 j = 0;
780 for (next_transfer_addr = readl(pci_addr_reg);
781 (next_transfer_addr <
782 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
783 pci_start_addr)
784 || next_transfer_addr >=
785 le32_to_cpu(devpriv->dma_desc[devpriv->dma_desc_index].
786 pci_start_addr) + devpriv->block_size)
787 && j < devpriv->num_dma_descriptors; j++) {
788 /* transfer data from dma buffer to comedi buffer */
789 num_samples = devpriv->block_size / sizeof(uint32_t);
790 if (async->cmd.stop_src == TRIG_COUNT) {
791 if (num_samples > devpriv->dio_count)
792 num_samples = devpriv->dio_count;
793 devpriv->dio_count -= num_samples;
794 }
795 cfc_write_array_to_buffer(dev->read_subdev,
796 devpriv->desc_dio_buffer[devpriv->
797 dma_desc_index],
798 num_samples * sizeof(uint32_t));
799 devpriv->dma_desc_index++;
800 devpriv->dma_desc_index %= devpriv->num_dma_descriptors;
801
802 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
803 devpriv->dma_desc[devpriv->dma_desc_index].
804 next);
805 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
806 }
807 /* XXX check for buffer overrun somehow */
808 }
809
810 static irqreturn_t handle_interrupt(int irq, void *d)
811 {
812 struct comedi_device *dev = d;
813 struct hpdi_private *devpriv = dev->private;
814 struct comedi_subdevice *s = dev->read_subdev;
815 struct comedi_async *async = s->async;
816 uint32_t hpdi_intr_status, hpdi_board_status;
817 uint32_t plx_status;
818 uint32_t plx_bits;
819 uint8_t dma0_status, dma1_status;
820 unsigned long flags;
821
822 if (!dev->attached)
823 return IRQ_NONE;
824
825 plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
826 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
827 return IRQ_NONE;
828
829 hpdi_intr_status = readl(devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
830 hpdi_board_status = readl(devpriv->hpdi_iobase + BOARD_STATUS_REG);
831
832 async->events = 0;
833
834 if (hpdi_intr_status) {
835 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
836 writel(hpdi_intr_status,
837 devpriv->hpdi_iobase + INTERRUPT_STATUS_REG);
838 }
839 /* spin lock makes sure no one else changes plx dma control reg */
840 spin_lock_irqsave(&dev->spinlock, flags);
841 dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
842 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
843 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
844 devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
845
846 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
847 if (dma0_status & PLX_DMA_EN_BIT)
848 drain_dma_buffers(dev, 0);
849 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
850 }
851 spin_unlock_irqrestore(&dev->spinlock, flags);
852
853 /* spin lock makes sure no one else changes plx dma control reg */
854 spin_lock_irqsave(&dev->spinlock, flags);
855 dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
856 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
857 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
858 devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
859 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
860
861 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
862 }
863 spin_unlock_irqrestore(&dev->spinlock, flags);
864
865 /* clear possible plx9080 interrupt sources */
866 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
867 plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
868 writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
869 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
870 }
871
872 if (hpdi_board_status & RX_OVERRUN_BIT) {
873 comedi_error(dev, "rx fifo overrun");
874 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
875 DEBUG_PRINT("dma0_status 0x%x\n",
876 (int)readb(devpriv->plx9080_iobase +
877 PLX_DMA0_CS_REG));
878 }
879
880 if (hpdi_board_status & RX_UNDERRUN_BIT) {
881 comedi_error(dev, "rx fifo underrun");
882 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
883 }
884
885 if (devpriv->dio_count == 0)
886 async->events |= COMEDI_CB_EOA;
887
888 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
889 DEBUG_PRINT("plx status 0x%x\n", plx_status);
890 if (async->events)
891 DEBUG_PRINT(" events 0x%x\n", async->events);
892
893 cfc_handle_events(dev, s);
894
895 return IRQ_HANDLED;
896 }
897
898 static void abort_dma(struct comedi_device *dev, unsigned int channel)
899 {
900 struct hpdi_private *devpriv = dev->private;
901 unsigned long flags;
902
903 /* spinlock for plx dma control/status reg */
904 spin_lock_irqsave(&dev->spinlock, flags);
905
906 plx9080_abort_dma(devpriv->plx9080_iobase, channel);
907
908 spin_unlock_irqrestore(&dev->spinlock, flags);
909 }
910
911 static int hpdi_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
912 {
913 struct hpdi_private *devpriv = dev->private;
914
915 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
916
917 writel(0, devpriv->hpdi_iobase + INTERRUPT_CONTROL_REG);
918
919 abort_dma(dev, 0);
920
921 return 0;
922 }
923
924 static struct comedi_driver gsc_hpdi_driver = {
925 .driver_name = "gsc_hpdi",
926 .module = THIS_MODULE,
927 .auto_attach = hpdi_auto_attach,
928 .detach = hpdi_detach,
929 };
930
931 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
932 const struct pci_device_id *id)
933 {
934 return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
935 }
936
937 static DEFINE_PCI_DEVICE_TABLE(gsc_hpdi_pci_table) = {
938 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
939 0x2400, 0, 0, 0},
940 { 0 }
941 };
942 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
943
944 static struct pci_driver gsc_hpdi_pci_driver = {
945 .name = "gsc_hpdi",
946 .id_table = gsc_hpdi_pci_table,
947 .probe = gsc_hpdi_pci_probe,
948 .remove = comedi_pci_auto_unconfig,
949 };
950 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
951
952 MODULE_AUTHOR("Comedi http://www.comedi.org");
953 MODULE_DESCRIPTION("Comedi low-level driver");
954 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)