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Merge branch 'for-3.8' of git://linux-nfs.org/~bfields/linux
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / adv_pci_dio.c
1 /*
2 * comedi/drivers/adv_pci_dio.c
3 *
4 * Author: Michal Dobes <dobes@tesnet.cz>
5 *
6 * Hardware driver for Advantech PCI DIO cards.
7 */
8 /*
9 Driver: adv_pci_dio
10 Description: Advantech PCI-1730, PCI-1733, PCI-1734, PCI-1735U,
11 PCI-1736UP, PCI-1739U, PCI-1750, PCI-1751, PCI-1752,
12 PCI-1753/E, PCI-1754, PCI-1756, PCI-1760, PCI-1762
13 Author: Michal Dobes <dobes@tesnet.cz>
14 Devices: [Advantech] PCI-1730 (adv_pci_dio), PCI-1733,
15 PCI-1734, PCI-1735U, PCI-1736UP, PCI-1739U, PCI-1750,
16 PCI-1751, PCI-1752, PCI-1753,
17 PCI-1753+PCI-1753E, PCI-1754, PCI-1756,
18 PCI-1760, PCI-1762
19 Status: untested
20 Updated: Mon, 09 Jan 2012 12:40:46 +0000
21
22 This driver supports now only insn interface for DI/DO/DIO.
23
24 Configuration options:
25 [0] - PCI bus of device (optional)
26 [1] - PCI slot of device (optional)
27 If bus/slot is not specified, the first available PCI
28 device will be used.
29
30 */
31
32 #include "../comedidev.h"
33
34 #include <linux/delay.h>
35
36 #include "8255.h"
37 #include "8253.h"
38
39 /* hardware types of the cards */
40 enum hw_cards_id {
41 TYPE_PCI1730, TYPE_PCI1733, TYPE_PCI1734, TYPE_PCI1735, TYPE_PCI1736,
42 TYPE_PCI1739,
43 TYPE_PCI1750,
44 TYPE_PCI1751,
45 TYPE_PCI1752,
46 TYPE_PCI1753, TYPE_PCI1753E,
47 TYPE_PCI1754, TYPE_PCI1756,
48 TYPE_PCI1760,
49 TYPE_PCI1762
50 };
51
52 /* which I/O instructions to use */
53 enum hw_io_access {
54 IO_8b, IO_16b
55 };
56
57 #define MAX_DI_SUBDEVS 2 /* max number of DI subdevices per card */
58 #define MAX_DO_SUBDEVS 2 /* max number of DO subdevices per card */
59 #define MAX_DIO_SUBDEVG 2 /* max number of DIO subdevices group per
60 * card */
61 #define MAX_8254_SUBDEVS 1 /* max number of 8254 counter subdevs per
62 * card */
63 /* (could be more than one 8254 per
64 * subdevice) */
65
66 #define SIZE_8254 4 /* 8254 IO space length */
67 #define SIZE_8255 4 /* 8255 IO space length */
68
69 #define PCIDIO_MAINREG 2 /* main I/O region for all Advantech cards? */
70
71 /* Register offset definitions */
72 /* Advantech PCI-1730/3/4 */
73 #define PCI1730_IDI 0 /* R: Isolated digital input 0-15 */
74 #define PCI1730_IDO 0 /* W: Isolated digital output 0-15 */
75 #define PCI1730_DI 2 /* R: Digital input 0-15 */
76 #define PCI1730_DO 2 /* W: Digital output 0-15 */
77 #define PCI1733_IDI 0 /* R: Isolated digital input 0-31 */
78 #define PCI1730_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
79 #define PCI1730_3_INT_RF 0x0c /* R/W: set falling/raising edge for
80 * interrupts */
81 #define PCI1730_3_INT_CLR 0x10 /* R/W: clear interrupts */
82 #define PCI1734_IDO 0 /* W: Isolated digital output 0-31 */
83 #define PCI173x_BOARDID 4 /* R: Board I/D switch for 1730/3/4 */
84
85 /* Advantech PCI-1735U */
86 #define PCI1735_DI 0 /* R: Digital input 0-31 */
87 #define PCI1735_DO 0 /* W: Digital output 0-31 */
88 #define PCI1735_C8254 4 /* R/W: 8254 counter */
89 #define PCI1735_BOARDID 8 /* R: Board I/D switch for 1735U */
90
91 /* Advantech PCI-1736UP */
92 #define PCI1736_IDI 0 /* R: Isolated digital input 0-15 */
93 #define PCI1736_IDO 0 /* W: Isolated digital output 0-15 */
94 #define PCI1736_3_INT_EN 0x08 /* R/W: enable/disable interrupts */
95 #define PCI1736_3_INT_RF 0x0c /* R/W: set falling/raising edge for
96 * interrupts */
97 #define PCI1736_3_INT_CLR 0x10 /* R/W: clear interrupts */
98 #define PCI1736_BOARDID 4 /* R: Board I/D switch for 1736UP */
99 #define PCI1736_MAINREG 0 /* Normal register (2) doesn't work */
100
101 /* Advantech PCI-1739U */
102 #define PCI1739_DIO 0 /* R/W: begin of 8255 registers block */
103 #define PCI1739_ICR 32 /* W: Interrupt control register */
104 #define PCI1739_ISR 32 /* R: Interrupt status register */
105 #define PCI1739_BOARDID 8 /* R: Board I/D switch for 1739U */
106
107 /* Advantech PCI-1750 */
108 #define PCI1750_IDI 0 /* R: Isolated digital input 0-15 */
109 #define PCI1750_IDO 0 /* W: Isolated digital output 0-15 */
110 #define PCI1750_ICR 32 /* W: Interrupt control register */
111 #define PCI1750_ISR 32 /* R: Interrupt status register */
112
113 /* Advantech PCI-1751/3/3E */
114 #define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
115 #define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
116 #define PCI1751_ICR 32 /* W: Interrupt control register */
117 #define PCI1751_ISR 32 /* R: Interrupt status register */
118 #define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
119 #define PCI1753_ICR0 16 /* R/W: Interrupt control register group 0 */
120 #define PCI1753_ICR1 17 /* R/W: Interrupt control register group 1 */
121 #define PCI1753_ICR2 18 /* R/W: Interrupt control register group 2 */
122 #define PCI1753_ICR3 19 /* R/W: Interrupt control register group 3 */
123 #define PCI1753E_DIO 32 /* R/W: begin of 8255 registers block */
124 #define PCI1753E_ICR0 48 /* R/W: Interrupt control register group 0 */
125 #define PCI1753E_ICR1 49 /* R/W: Interrupt control register group 1 */
126 #define PCI1753E_ICR2 50 /* R/W: Interrupt control register group 2 */
127 #define PCI1753E_ICR3 51 /* R/W: Interrupt control register group 3 */
128
129 /* Advantech PCI-1752/4/6 */
130 #define PCI1752_IDO 0 /* R/W: Digital output 0-31 */
131 #define PCI1752_IDO2 4 /* R/W: Digital output 32-63 */
132 #define PCI1754_IDI 0 /* R: Digital input 0-31 */
133 #define PCI1754_IDI2 4 /* R: Digital input 32-64 */
134 #define PCI1756_IDI 0 /* R: Digital input 0-31 */
135 #define PCI1756_IDO 4 /* R/W: Digital output 0-31 */
136 #define PCI1754_6_ICR0 0x08 /* R/W: Interrupt control register group 0 */
137 #define PCI1754_6_ICR1 0x0a /* R/W: Interrupt control register group 1 */
138 #define PCI1754_ICR2 0x0c /* R/W: Interrupt control register group 2 */
139 #define PCI1754_ICR3 0x0e /* R/W: Interrupt control register group 3 */
140 #define PCI1752_6_CFC 0x12 /* R/W: set/read channel freeze function */
141 #define PCI175x_BOARDID 0x10 /* R: Board I/D switch for 1752/4/6 */
142
143 /* Advantech PCI-1762 registers */
144 #define PCI1762_RO 0 /* R/W: Relays status/output */
145 #define PCI1762_IDI 2 /* R: Isolated input status */
146 #define PCI1762_BOARDID 4 /* R: Board I/D switch */
147 #define PCI1762_ICR 6 /* W: Interrupt control register */
148 #define PCI1762_ISR 6 /* R: Interrupt status register */
149
150 /* Advantech PCI-1760 registers */
151 #define OMB0 0x0c /* W: Mailbox outgoing registers */
152 #define OMB1 0x0d
153 #define OMB2 0x0e
154 #define OMB3 0x0f
155 #define IMB0 0x1c /* R: Mailbox incoming registers */
156 #define IMB1 0x1d
157 #define IMB2 0x1e
158 #define IMB3 0x1f
159 #define INTCSR0 0x38 /* R/W: Interrupt control registers */
160 #define INTCSR1 0x39
161 #define INTCSR2 0x3a
162 #define INTCSR3 0x3b
163
164 /* PCI-1760 mailbox commands */
165 #define CMD_ClearIMB2 0x00 /* Clear IMB2 status and return actual
166 * DI status in IMB3 */
167 #define CMD_SetRelaysOutput 0x01 /* Set relay output from OMB0 */
168 #define CMD_GetRelaysStatus 0x02 /* Get relay status to IMB0 */
169 #define CMD_ReadCurrentStatus 0x07 /* Read the current status of the
170 * register in OMB0, result in IMB0 */
171 #define CMD_ReadFirmwareVersion 0x0e /* Read the firmware ver., result in
172 * IMB1.IMB0 */
173 #define CMD_ReadHardwareVersion 0x0f /* Read the hardware ver., result in
174 * IMB1.IMB0 */
175 #define CMD_EnableIDIFilters 0x20 /* Enable IDI filters based on bits in
176 * OMB0 */
177 #define CMD_EnableIDIPatternMatch 0x21 /* Enable IDI pattern match based on
178 * bits in OMB0 */
179 #define CMD_SetIDIPatternMatch 0x22 /* Enable IDI pattern match based on
180 * bits in OMB0 */
181 #define CMD_EnableIDICounters 0x28 /* Enable IDI counters based on bits in
182 * OMB0 */
183 #define CMD_ResetIDICounters 0x29 /* Reset IDI counters based on bits in
184 * OMB0 to its reset values */
185 #define CMD_OverflowIDICounters 0x2a /* Enable IDI counters overflow
186 * interrupts based on bits in OMB0 */
187 #define CMD_MatchIntIDICounters 0x2b /* Enable IDI counters match value
188 * interrupts based on bits in OMB0 */
189 #define CMD_EdgeIDICounters 0x2c /* Set IDI up counters count edge (bit=0
190 * - rising, =1 - falling) */
191 #define CMD_GetIDICntCurValue 0x2f /* Read IDI{OMB0} up counter current
192 * value */
193 #define CMD_SetIDI0CntResetValue 0x40 /* Set IDI0 Counter Reset Value
194 * 256*OMB1+OMB0 */
195 #define CMD_SetIDI1CntResetValue 0x41 /* Set IDI1 Counter Reset Value
196 * 256*OMB1+OMB0 */
197 #define CMD_SetIDI2CntResetValue 0x42 /* Set IDI2 Counter Reset Value
198 * 256*OMB1+OMB0 */
199 #define CMD_SetIDI3CntResetValue 0x43 /* Set IDI3 Counter Reset Value
200 * 256*OMB1+OMB0 */
201 #define CMD_SetIDI4CntResetValue 0x44 /* Set IDI4 Counter Reset Value
202 * 256*OMB1+OMB0 */
203 #define CMD_SetIDI5CntResetValue 0x45 /* Set IDI5 Counter Reset Value
204 * 256*OMB1+OMB0 */
205 #define CMD_SetIDI6CntResetValue 0x46 /* Set IDI6 Counter Reset Value
206 * 256*OMB1+OMB0 */
207 #define CMD_SetIDI7CntResetValue 0x47 /* Set IDI7 Counter Reset Value
208 * 256*OMB1+OMB0 */
209 #define CMD_SetIDI0CntMatchValue 0x48 /* Set IDI0 Counter Match Value
210 * 256*OMB1+OMB0 */
211 #define CMD_SetIDI1CntMatchValue 0x49 /* Set IDI1 Counter Match Value
212 * 256*OMB1+OMB0 */
213 #define CMD_SetIDI2CntMatchValue 0x4a /* Set IDI2 Counter Match Value
214 * 256*OMB1+OMB0 */
215 #define CMD_SetIDI3CntMatchValue 0x4b /* Set IDI3 Counter Match Value
216 * 256*OMB1+OMB0 */
217 #define CMD_SetIDI4CntMatchValue 0x4c /* Set IDI4 Counter Match Value
218 * 256*OMB1+OMB0 */
219 #define CMD_SetIDI5CntMatchValue 0x4d /* Set IDI5 Counter Match Value
220 * 256*OMB1+OMB0 */
221 #define CMD_SetIDI6CntMatchValue 0x4e /* Set IDI6 Counter Match Value
222 * 256*OMB1+OMB0 */
223 #define CMD_SetIDI7CntMatchValue 0x4f /* Set IDI7 Counter Match Value
224 * 256*OMB1+OMB0 */
225
226 #define OMBCMD_RETRY 0x03 /* 3 times try request before error */
227
228 struct diosubd_data {
229 int chans; /* num of chans */
230 int addr; /* PCI address ofset */
231 int regs; /* number of registers to read or 8255
232 subdevices or 8254 chips */
233 unsigned int specflags; /* addon subdevice flags */
234 };
235
236 struct dio_boardtype {
237 const char *name; /* board name */
238 int vendor_id; /* vendor/device PCI ID */
239 int device_id;
240 int main_pci_region; /* main I/O PCI region */
241 enum hw_cards_id cardtype;
242 int nsubdevs;
243 struct diosubd_data sdi[MAX_DI_SUBDEVS]; /* DI chans */
244 struct diosubd_data sdo[MAX_DO_SUBDEVS]; /* DO chans */
245 struct diosubd_data sdio[MAX_DIO_SUBDEVG]; /* DIO 8255 chans */
246 struct diosubd_data boardid; /* card supports board ID switch */
247 struct diosubd_data s8254[MAX_8254_SUBDEVS]; /* 8254 subdevices */
248 enum hw_io_access io_access;
249 };
250
251 static const struct dio_boardtype boardtypes[] = {
252 {
253 .name = "pci1730",
254 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
255 .device_id = 0x1730,
256 .main_pci_region = PCIDIO_MAINREG,
257 .cardtype = TYPE_PCI1730,
258 .nsubdevs = 5,
259 .sdi[0] = { 16, PCI1730_DI, 2, 0, },
260 .sdi[1] = { 16, PCI1730_IDI, 2, 0, },
261 .sdo[0] = { 16, PCI1730_DO, 2, 0, },
262 .sdo[1] = { 16, PCI1730_IDO, 2, 0, },
263 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
264 .io_access = IO_8b,
265 }, {
266 .name = "pci1733",
267 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
268 .device_id = 0x1733,
269 .main_pci_region = PCIDIO_MAINREG,
270 .cardtype = TYPE_PCI1733,
271 .nsubdevs = 2,
272 .sdi[1] = { 32, PCI1733_IDI, 4, 0, },
273 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
274 .io_access = IO_8b,
275 }, {
276 .name = "pci1734",
277 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
278 .device_id = 0x1734,
279 .main_pci_region = PCIDIO_MAINREG,
280 .cardtype = TYPE_PCI1734,
281 .nsubdevs = 2,
282 .sdo[1] = { 32, PCI1734_IDO, 4, 0, },
283 .boardid = { 4, PCI173x_BOARDID, 1, SDF_INTERNAL, },
284 .io_access = IO_8b,
285 }, {
286 .name = "pci1735",
287 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
288 .device_id = 0x1735,
289 .main_pci_region = PCIDIO_MAINREG,
290 .cardtype = TYPE_PCI1735,
291 .nsubdevs = 4,
292 .sdi[0] = { 32, PCI1735_DI, 4, 0, },
293 .sdo[0] = { 32, PCI1735_DO, 4, 0, },
294 .boardid = { 4, PCI1735_BOARDID, 1, SDF_INTERNAL, },
295 .s8254[0] = { 3, PCI1735_C8254, 1, 0, },
296 .io_access = IO_8b,
297 }, {
298 .name = "pci1736",
299 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
300 .device_id = 0x1736,
301 .main_pci_region = PCI1736_MAINREG,
302 .cardtype = TYPE_PCI1736,
303 .nsubdevs = 3,
304 .sdi[1] = { 16, PCI1736_IDI, 2, 0, },
305 .sdo[1] = { 16, PCI1736_IDO, 2, 0, },
306 .boardid = { 4, PCI1736_BOARDID, 1, SDF_INTERNAL, },
307 .io_access = IO_8b,
308 }, {
309 .name = "pci1739",
310 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
311 .device_id = 0x1739,
312 .main_pci_region = PCIDIO_MAINREG,
313 .cardtype = TYPE_PCI1739,
314 .nsubdevs = 2,
315 .sdio[0] = { 48, PCI1739_DIO, 2, 0, },
316 .io_access = IO_8b,
317 }, {
318 .name = "pci1750",
319 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
320 .device_id = 0x1750,
321 .main_pci_region = PCIDIO_MAINREG,
322 .cardtype = TYPE_PCI1750,
323 .nsubdevs = 2,
324 .sdi[1] = { 16, PCI1750_IDI, 2, 0, },
325 .sdo[1] = { 16, PCI1750_IDO, 2, 0, },
326 .io_access = IO_8b,
327 }, {
328 .name = "pci1751",
329 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
330 .device_id = 0x1751,
331 .main_pci_region = PCIDIO_MAINREG,
332 .cardtype = TYPE_PCI1751,
333 .nsubdevs = 3,
334 .sdio[0] = { 48, PCI1751_DIO, 2, 0, },
335 .s8254[0] = { 3, PCI1751_CNT, 1, 0, },
336 .io_access = IO_8b,
337 }, {
338 .name = "pci1752",
339 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
340 .device_id = 0x1752,
341 .main_pci_region = PCIDIO_MAINREG,
342 .cardtype = TYPE_PCI1752,
343 .nsubdevs = 3,
344 .sdo[0] = { 32, PCI1752_IDO, 2, 0, },
345 .sdo[1] = { 32, PCI1752_IDO2, 2, 0, },
346 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
347 .io_access = IO_16b,
348 }, {
349 .name = "pci1753",
350 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
351 .device_id = 0x1753,
352 .main_pci_region = PCIDIO_MAINREG,
353 .cardtype = TYPE_PCI1753,
354 .nsubdevs = 4,
355 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
356 .io_access = IO_8b,
357 }, {
358 .name = "pci1753e",
359 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
360 .device_id = 0x1753,
361 .main_pci_region = PCIDIO_MAINREG,
362 .cardtype = TYPE_PCI1753E,
363 .nsubdevs = 8,
364 .sdio[0] = { 96, PCI1753_DIO, 4, 0, },
365 .sdio[1] = { 96, PCI1753E_DIO, 4, 0, },
366 .io_access = IO_8b,
367 }, {
368 .name = "pci1754",
369 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
370 .device_id = 0x1754,
371 .main_pci_region = PCIDIO_MAINREG,
372 .cardtype = TYPE_PCI1754,
373 .nsubdevs = 3,
374 .sdi[0] = { 32, PCI1754_IDI, 2, 0, },
375 .sdi[1] = { 32, PCI1754_IDI2, 2, 0, },
376 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
377 .io_access = IO_16b,
378 }, {
379 .name = "pci1756",
380 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
381 .device_id = 0x1756,
382 .main_pci_region = PCIDIO_MAINREG,
383 .cardtype = TYPE_PCI1756,
384 .nsubdevs = 3,
385 .sdi[1] = { 32, PCI1756_IDI, 2, 0, },
386 .sdo[1] = { 32, PCI1756_IDO, 2, 0, },
387 .boardid = { 4, PCI175x_BOARDID, 1, SDF_INTERNAL, },
388 .io_access = IO_16b,
389 }, {
390 /* This card has its own 'attach' */
391 .name = "pci1760",
392 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
393 .device_id = 0x1760,
394 .main_pci_region = 0,
395 .cardtype = TYPE_PCI1760,
396 .nsubdevs = 4,
397 .io_access = IO_8b,
398 }, {
399 .name = "pci1762",
400 .vendor_id = PCI_VENDOR_ID_ADVANTECH,
401 .device_id = 0x1762,
402 .main_pci_region = PCIDIO_MAINREG,
403 .cardtype = TYPE_PCI1762,
404 .nsubdevs = 3,
405 .sdi[1] = { 16, PCI1762_IDI, 1, 0, },
406 .sdo[1] = { 16, PCI1762_RO, 1, 0, },
407 .boardid = { 4, PCI1762_BOARDID, 1, SDF_INTERNAL, },
408 .io_access = IO_16b,
409 },
410 };
411
412 struct pci_dio_private {
413 char valid; /* card is usable */
414 char GlobalIrqEnabled; /* 1= any IRQ source is enabled */
415 /* PCI-1760 specific data */
416 unsigned char IDICntEnable; /* counter's counting enable status */
417 unsigned char IDICntOverEnable; /* counter's overflow interrupts enable
418 * status */
419 unsigned char IDICntMatchEnable; /* counter's match interrupts
420 * enable status */
421 unsigned char IDICntEdge; /* counter's count edge value
422 * (bit=0 - rising, =1 - falling) */
423 unsigned short CntResValue[8]; /* counters' reset value */
424 unsigned short CntMatchValue[8]; /* counters' match interrupt value */
425 unsigned char IDIFiltersEn; /* IDI's digital filters enable status */
426 unsigned char IDIPatMatchEn; /* IDI's pattern match enable status */
427 unsigned char IDIPatMatchValue; /* IDI's pattern match value */
428 unsigned short IDIFiltrLow[8]; /* IDI's filter value low signal */
429 unsigned short IDIFiltrHigh[8]; /* IDI's filter value high signal */
430 };
431
432 /*
433 ==============================================================================
434 */
435 static int pci_dio_insn_bits_di_b(struct comedi_device *dev,
436 struct comedi_subdevice *s,
437 struct comedi_insn *insn, unsigned int *data)
438 {
439 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
440 int i;
441
442 data[1] = 0;
443 for (i = 0; i < d->regs; i++)
444 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i);
445
446
447 return insn->n;
448 }
449
450 /*
451 ==============================================================================
452 */
453 static int pci_dio_insn_bits_di_w(struct comedi_device *dev,
454 struct comedi_subdevice *s,
455 struct comedi_insn *insn, unsigned int *data)
456 {
457 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
458 int i;
459
460 data[1] = 0;
461 for (i = 0; i < d->regs; i++)
462 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i);
463
464 return insn->n;
465 }
466
467 /*
468 ==============================================================================
469 */
470 static int pci_dio_insn_bits_do_b(struct comedi_device *dev,
471 struct comedi_subdevice *s,
472 struct comedi_insn *insn, unsigned int *data)
473 {
474 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
475 int i;
476
477 if (data[0]) {
478 s->state &= ~data[0];
479 s->state |= (data[0] & data[1]);
480 for (i = 0; i < d->regs; i++)
481 outb((s->state >> (8 * i)) & 0xff,
482 dev->iobase + d->addr + i);
483 }
484 data[1] = s->state;
485
486 return insn->n;
487 }
488
489 /*
490 ==============================================================================
491 */
492 static int pci_dio_insn_bits_do_w(struct comedi_device *dev,
493 struct comedi_subdevice *s,
494 struct comedi_insn *insn, unsigned int *data)
495 {
496 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
497 int i;
498
499 if (data[0]) {
500 s->state &= ~data[0];
501 s->state |= (data[0] & data[1]);
502 for (i = 0; i < d->regs; i++)
503 outw((s->state >> (16 * i)) & 0xffff,
504 dev->iobase + d->addr + 2 * i);
505 }
506 data[1] = s->state;
507
508 return insn->n;
509 }
510
511 /*
512 ==============================================================================
513 */
514 static int pci_8254_insn_read(struct comedi_device *dev,
515 struct comedi_subdevice *s,
516 struct comedi_insn *insn, unsigned int *data)
517 {
518 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
519 unsigned int chan, chip, chipchan;
520 unsigned long flags;
521
522 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
523 chip = chan / 3; /* chip on subdevice */
524 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
525 spin_lock_irqsave(&s->spin_lock, flags);
526 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip),
527 0, chipchan);
528 spin_unlock_irqrestore(&s->spin_lock, flags);
529 return 1;
530 }
531
532 /*
533 ==============================================================================
534 */
535 static int pci_8254_insn_write(struct comedi_device *dev,
536 struct comedi_subdevice *s,
537 struct comedi_insn *insn, unsigned int *data)
538 {
539 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
540 unsigned int chan, chip, chipchan;
541 unsigned long flags;
542
543 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
544 chip = chan / 3; /* chip on subdevice */
545 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
546 spin_lock_irqsave(&s->spin_lock, flags);
547 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip),
548 0, chipchan, data[0]);
549 spin_unlock_irqrestore(&s->spin_lock, flags);
550 return 1;
551 }
552
553 /*
554 ==============================================================================
555 */
556 static int pci_8254_insn_config(struct comedi_device *dev,
557 struct comedi_subdevice *s,
558 struct comedi_insn *insn, unsigned int *data)
559 {
560 const struct diosubd_data *d = (const struct diosubd_data *)s->private;
561 unsigned int chan, chip, chipchan;
562 unsigned long iobase;
563 int ret = 0;
564 unsigned long flags;
565
566 chan = CR_CHAN(insn->chanspec); /* channel on subdevice */
567 chip = chan / 3; /* chip on subdevice */
568 chipchan = chan - (3 * chip); /* channel on chip on subdevice */
569 iobase = dev->iobase + d->addr + (SIZE_8254 * chip);
570 spin_lock_irqsave(&s->spin_lock, flags);
571 switch (data[0]) {
572 case INSN_CONFIG_SET_COUNTER_MODE:
573 ret = i8254_set_mode(iobase, 0, chipchan, data[1]);
574 if (ret < 0)
575 ret = -EINVAL;
576 break;
577 case INSN_CONFIG_8254_READ_STATUS:
578 data[1] = i8254_status(iobase, 0, chipchan);
579 break;
580 default:
581 ret = -EINVAL;
582 break;
583 }
584 spin_unlock_irqrestore(&s->spin_lock, flags);
585 return ret < 0 ? ret : insn->n;
586 }
587
588 /*
589 ==============================================================================
590 */
591 static int pci1760_unchecked_mbxrequest(struct comedi_device *dev,
592 unsigned char *omb, unsigned char *imb,
593 int repeats)
594 {
595 int cnt, tout, ok = 0;
596
597 for (cnt = 0; cnt < repeats; cnt++) {
598 outb(omb[0], dev->iobase + OMB0);
599 outb(omb[1], dev->iobase + OMB1);
600 outb(omb[2], dev->iobase + OMB2);
601 outb(omb[3], dev->iobase + OMB3);
602 for (tout = 0; tout < 251; tout++) {
603 imb[2] = inb(dev->iobase + IMB2);
604 if (imb[2] == omb[2]) {
605 imb[0] = inb(dev->iobase + IMB0);
606 imb[1] = inb(dev->iobase + IMB1);
607 imb[3] = inb(dev->iobase + IMB3);
608 ok = 1;
609 break;
610 }
611 udelay(1);
612 }
613 if (ok)
614 return 0;
615 }
616
617 comedi_error(dev, "PCI-1760 mailbox request timeout!");
618 return -ETIME;
619 }
620
621 static int pci1760_clear_imb2(struct comedi_device *dev)
622 {
623 unsigned char omb[4] = { 0x0, 0x0, CMD_ClearIMB2, 0x0 };
624 unsigned char imb[4];
625 /* check if imb2 is already clear */
626 if (inb(dev->iobase + IMB2) == CMD_ClearIMB2)
627 return 0;
628 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
629 }
630
631 static int pci1760_mbxrequest(struct comedi_device *dev,
632 unsigned char *omb, unsigned char *imb)
633 {
634 if (omb[2] == CMD_ClearIMB2) {
635 comedi_error(dev,
636 "bug! this function should not be used for CMD_ClearIMB2 command");
637 return -EINVAL;
638 }
639 if (inb(dev->iobase + IMB2) == omb[2]) {
640 int retval;
641 retval = pci1760_clear_imb2(dev);
642 if (retval < 0)
643 return retval;
644 }
645 return pci1760_unchecked_mbxrequest(dev, omb, imb, OMBCMD_RETRY);
646 }
647
648 /*
649 ==============================================================================
650 */
651 static int pci1760_insn_bits_di(struct comedi_device *dev,
652 struct comedi_subdevice *s,
653 struct comedi_insn *insn, unsigned int *data)
654 {
655 data[1] = inb(dev->iobase + IMB3);
656
657 return insn->n;
658 }
659
660 /*
661 ==============================================================================
662 */
663 static int pci1760_insn_bits_do(struct comedi_device *dev,
664 struct comedi_subdevice *s,
665 struct comedi_insn *insn, unsigned int *data)
666 {
667 int ret;
668 unsigned char omb[4] = {
669 0x00,
670 0x00,
671 CMD_SetRelaysOutput,
672 0x00
673 };
674 unsigned char imb[4];
675
676 if (data[0]) {
677 s->state &= ~data[0];
678 s->state |= (data[0] & data[1]);
679 omb[0] = s->state;
680 ret = pci1760_mbxrequest(dev, omb, imb);
681 if (!ret)
682 return ret;
683 }
684 data[1] = s->state;
685
686 return insn->n;
687 }
688
689 /*
690 ==============================================================================
691 */
692 static int pci1760_insn_cnt_read(struct comedi_device *dev,
693 struct comedi_subdevice *s,
694 struct comedi_insn *insn, unsigned int *data)
695 {
696 int ret, n;
697 unsigned char omb[4] = {
698 CR_CHAN(insn->chanspec) & 0x07,
699 0x00,
700 CMD_GetIDICntCurValue,
701 0x00
702 };
703 unsigned char imb[4];
704
705 for (n = 0; n < insn->n; n++) {
706 ret = pci1760_mbxrequest(dev, omb, imb);
707 if (!ret)
708 return ret;
709 data[n] = (imb[1] << 8) + imb[0];
710 }
711
712 return n;
713 }
714
715 /*
716 ==============================================================================
717 */
718 static int pci1760_insn_cnt_write(struct comedi_device *dev,
719 struct comedi_subdevice *s,
720 struct comedi_insn *insn, unsigned int *data)
721 {
722 struct pci_dio_private *devpriv = dev->private;
723 int ret;
724 unsigned char chan = CR_CHAN(insn->chanspec) & 0x07;
725 unsigned char bitmask = 1 << chan;
726 unsigned char omb[4] = {
727 data[0] & 0xff,
728 (data[0] >> 8) & 0xff,
729 CMD_SetIDI0CntResetValue + chan,
730 0x00
731 };
732 unsigned char imb[4];
733
734 /* Set reset value if different */
735 if (devpriv->CntResValue[chan] != (data[0] & 0xffff)) {
736 ret = pci1760_mbxrequest(dev, omb, imb);
737 if (!ret)
738 return ret;
739 devpriv->CntResValue[chan] = data[0] & 0xffff;
740 }
741
742 omb[0] = bitmask; /* reset counter to it reset value */
743 omb[2] = CMD_ResetIDICounters;
744 ret = pci1760_mbxrequest(dev, omb, imb);
745 if (!ret)
746 return ret;
747
748 /* start counter if it don't run */
749 if (!(bitmask & devpriv->IDICntEnable)) {
750 omb[0] = bitmask;
751 omb[2] = CMD_EnableIDICounters;
752 ret = pci1760_mbxrequest(dev, omb, imb);
753 if (!ret)
754 return ret;
755 devpriv->IDICntEnable |= bitmask;
756 }
757 return 1;
758 }
759
760 /*
761 ==============================================================================
762 */
763 static int pci1760_reset(struct comedi_device *dev)
764 {
765 struct pci_dio_private *devpriv = dev->private;
766 int i;
767 unsigned char omb[4] = { 0x00, 0x00, 0x00, 0x00 };
768 unsigned char imb[4];
769
770 outb(0, dev->iobase + INTCSR0); /* disable IRQ */
771 outb(0, dev->iobase + INTCSR1);
772 outb(0, dev->iobase + INTCSR2);
773 outb(0, dev->iobase + INTCSR3);
774 devpriv->GlobalIrqEnabled = 0;
775
776 omb[0] = 0x00;
777 omb[2] = CMD_SetRelaysOutput; /* reset relay outputs */
778 pci1760_mbxrequest(dev, omb, imb);
779
780 omb[0] = 0x00;
781 omb[2] = CMD_EnableIDICounters; /* disable IDI up counters */
782 pci1760_mbxrequest(dev, omb, imb);
783 devpriv->IDICntEnable = 0;
784
785 omb[0] = 0x00;
786 omb[2] = CMD_OverflowIDICounters; /* disable counters overflow
787 * interrupts */
788 pci1760_mbxrequest(dev, omb, imb);
789 devpriv->IDICntOverEnable = 0;
790
791 omb[0] = 0x00;
792 omb[2] = CMD_MatchIntIDICounters; /* disable counters match value
793 * interrupts */
794 pci1760_mbxrequest(dev, omb, imb);
795 devpriv->IDICntMatchEnable = 0;
796
797 omb[0] = 0x00;
798 omb[1] = 0x80;
799 for (i = 0; i < 8; i++) { /* set IDI up counters match value */
800 omb[2] = CMD_SetIDI0CntMatchValue + i;
801 pci1760_mbxrequest(dev, omb, imb);
802 devpriv->CntMatchValue[i] = 0x8000;
803 }
804
805 omb[0] = 0x00;
806 omb[1] = 0x00;
807 for (i = 0; i < 8; i++) { /* set IDI up counters reset value */
808 omb[2] = CMD_SetIDI0CntResetValue + i;
809 pci1760_mbxrequest(dev, omb, imb);
810 devpriv->CntResValue[i] = 0x0000;
811 }
812
813 omb[0] = 0xff;
814 omb[2] = CMD_ResetIDICounters; /* reset IDI up counters to reset
815 * values */
816 pci1760_mbxrequest(dev, omb, imb);
817
818 omb[0] = 0x00;
819 omb[2] = CMD_EdgeIDICounters; /* set IDI up counters count edge */
820 pci1760_mbxrequest(dev, omb, imb);
821 devpriv->IDICntEdge = 0x00;
822
823 omb[0] = 0x00;
824 omb[2] = CMD_EnableIDIFilters; /* disable all digital in filters */
825 pci1760_mbxrequest(dev, omb, imb);
826 devpriv->IDIFiltersEn = 0x00;
827
828 omb[0] = 0x00;
829 omb[2] = CMD_EnableIDIPatternMatch; /* disable pattern matching */
830 pci1760_mbxrequest(dev, omb, imb);
831 devpriv->IDIPatMatchEn = 0x00;
832
833 omb[0] = 0x00;
834 omb[2] = CMD_SetIDIPatternMatch; /* set pattern match value */
835 pci1760_mbxrequest(dev, omb, imb);
836 devpriv->IDIPatMatchValue = 0x00;
837
838 return 0;
839 }
840
841 /*
842 ==============================================================================
843 */
844 static int pci_dio_reset(struct comedi_device *dev)
845 {
846 const struct dio_boardtype *this_board = comedi_board(dev);
847
848 switch (this_board->cardtype) {
849 case TYPE_PCI1730:
850 outb(0, dev->iobase + PCI1730_DO); /* clear outputs */
851 outb(0, dev->iobase + PCI1730_DO + 1);
852 outb(0, dev->iobase + PCI1730_IDO);
853 outb(0, dev->iobase + PCI1730_IDO + 1);
854 /* NO break there! */
855 case TYPE_PCI1733:
856 /* disable interrupts */
857 outb(0, dev->iobase + PCI1730_3_INT_EN);
858 /* clear interrupts */
859 outb(0x0f, dev->iobase + PCI1730_3_INT_CLR);
860 /* set rising edge trigger */
861 outb(0, dev->iobase + PCI1730_3_INT_RF);
862 break;
863 case TYPE_PCI1734:
864 outb(0, dev->iobase + PCI1734_IDO); /* clear outputs */
865 outb(0, dev->iobase + PCI1734_IDO + 1);
866 outb(0, dev->iobase + PCI1734_IDO + 2);
867 outb(0, dev->iobase + PCI1734_IDO + 3);
868 break;
869 case TYPE_PCI1735:
870 outb(0, dev->iobase + PCI1735_DO); /* clear outputs */
871 outb(0, dev->iobase + PCI1735_DO + 1);
872 outb(0, dev->iobase + PCI1735_DO + 2);
873 outb(0, dev->iobase + PCI1735_DO + 3);
874 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 0, I8254_MODE0);
875 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 1, I8254_MODE0);
876 i8254_set_mode(dev->iobase + PCI1735_C8254, 0, 2, I8254_MODE0);
877 break;
878
879 case TYPE_PCI1736:
880 outb(0, dev->iobase + PCI1736_IDO);
881 outb(0, dev->iobase + PCI1736_IDO + 1);
882 /* disable interrupts */
883 outb(0, dev->iobase + PCI1736_3_INT_EN);
884 /* clear interrupts */
885 outb(0x0f, dev->iobase + PCI1736_3_INT_CLR);
886 /* set rising edge trigger */
887 outb(0, dev->iobase + PCI1736_3_INT_RF);
888 break;
889
890 case TYPE_PCI1739:
891 /* disable & clear interrupts */
892 outb(0x88, dev->iobase + PCI1739_ICR);
893 break;
894
895 case TYPE_PCI1750:
896 case TYPE_PCI1751:
897 /* disable & clear interrupts */
898 outb(0x88, dev->iobase + PCI1750_ICR);
899 break;
900 case TYPE_PCI1752:
901 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
902 * function */
903 outw(0, dev->iobase + PCI1752_IDO); /* clear outputs */
904 outw(0, dev->iobase + PCI1752_IDO + 2);
905 outw(0, dev->iobase + PCI1752_IDO2);
906 outw(0, dev->iobase + PCI1752_IDO2 + 2);
907 break;
908 case TYPE_PCI1753E:
909 outb(0x88, dev->iobase + PCI1753E_ICR0); /* disable & clear
910 * interrupts */
911 outb(0x80, dev->iobase + PCI1753E_ICR1);
912 outb(0x80, dev->iobase + PCI1753E_ICR2);
913 outb(0x80, dev->iobase + PCI1753E_ICR3);
914 /* NO break there! */
915 case TYPE_PCI1753:
916 outb(0x88, dev->iobase + PCI1753_ICR0); /* disable & clear
917 * interrupts */
918 outb(0x80, dev->iobase + PCI1753_ICR1);
919 outb(0x80, dev->iobase + PCI1753_ICR2);
920 outb(0x80, dev->iobase + PCI1753_ICR3);
921 break;
922 case TYPE_PCI1754:
923 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
924 * interrupts */
925 outw(0x08, dev->iobase + PCI1754_6_ICR1);
926 outw(0x08, dev->iobase + PCI1754_ICR2);
927 outw(0x08, dev->iobase + PCI1754_ICR3);
928 break;
929 case TYPE_PCI1756:
930 outw(0, dev->iobase + PCI1752_6_CFC); /* disable channel freeze
931 * function */
932 outw(0x08, dev->iobase + PCI1754_6_ICR0); /* disable and clear
933 * interrupts */
934 outw(0x08, dev->iobase + PCI1754_6_ICR1);
935 outw(0, dev->iobase + PCI1756_IDO); /* clear outputs */
936 outw(0, dev->iobase + PCI1756_IDO + 2);
937 break;
938 case TYPE_PCI1760:
939 pci1760_reset(dev);
940 break;
941 case TYPE_PCI1762:
942 outw(0x0101, dev->iobase + PCI1762_ICR); /* disable & clear
943 * interrupts */
944 break;
945 }
946
947 return 0;
948 }
949
950 /*
951 ==============================================================================
952 */
953 static int pci1760_attach(struct comedi_device *dev)
954 {
955 struct comedi_subdevice *s;
956
957 s = &dev->subdevices[0];
958 s->type = COMEDI_SUBD_DI;
959 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
960 s->n_chan = 8;
961 s->maxdata = 1;
962 s->len_chanlist = 8;
963 s->range_table = &range_digital;
964 s->insn_bits = pci1760_insn_bits_di;
965
966 s = &dev->subdevices[1];
967 s->type = COMEDI_SUBD_DO;
968 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
969 s->n_chan = 8;
970 s->maxdata = 1;
971 s->len_chanlist = 8;
972 s->range_table = &range_digital;
973 s->state = 0;
974 s->insn_bits = pci1760_insn_bits_do;
975
976 s = &dev->subdevices[2];
977 s->type = COMEDI_SUBD_TIMER;
978 s->subdev_flags = SDF_WRITABLE | SDF_LSAMPL;
979 s->n_chan = 2;
980 s->maxdata = 0xffffffff;
981 s->len_chanlist = 2;
982 /* s->insn_config=pci1760_insn_pwm_cfg; */
983
984 s = &dev->subdevices[3];
985 s->type = COMEDI_SUBD_COUNTER;
986 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
987 s->n_chan = 8;
988 s->maxdata = 0xffff;
989 s->len_chanlist = 8;
990 s->insn_read = pci1760_insn_cnt_read;
991 s->insn_write = pci1760_insn_cnt_write;
992 /* s->insn_config=pci1760_insn_cnt_cfg; */
993
994 return 0;
995 }
996
997 /*
998 ==============================================================================
999 */
1000 static int pci_dio_add_di(struct comedi_device *dev,
1001 struct comedi_subdevice *s,
1002 const struct diosubd_data *d)
1003 {
1004 const struct dio_boardtype *this_board = comedi_board(dev);
1005
1006 s->type = COMEDI_SUBD_DI;
1007 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | d->specflags;
1008 if (d->chans > 16)
1009 s->subdev_flags |= SDF_LSAMPL;
1010 s->n_chan = d->chans;
1011 s->maxdata = 1;
1012 s->len_chanlist = d->chans;
1013 s->range_table = &range_digital;
1014 switch (this_board->io_access) {
1015 case IO_8b:
1016 s->insn_bits = pci_dio_insn_bits_di_b;
1017 break;
1018 case IO_16b:
1019 s->insn_bits = pci_dio_insn_bits_di_w;
1020 break;
1021 }
1022 s->private = (void *)d;
1023
1024 return 0;
1025 }
1026
1027 /*
1028 ==============================================================================
1029 */
1030 static int pci_dio_add_do(struct comedi_device *dev,
1031 struct comedi_subdevice *s,
1032 const struct diosubd_data *d)
1033 {
1034 const struct dio_boardtype *this_board = comedi_board(dev);
1035
1036 s->type = COMEDI_SUBD_DO;
1037 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_COMMON;
1038 if (d->chans > 16)
1039 s->subdev_flags |= SDF_LSAMPL;
1040 s->n_chan = d->chans;
1041 s->maxdata = 1;
1042 s->len_chanlist = d->chans;
1043 s->range_table = &range_digital;
1044 s->state = 0;
1045 switch (this_board->io_access) {
1046 case IO_8b:
1047 s->insn_bits = pci_dio_insn_bits_do_b;
1048 break;
1049 case IO_16b:
1050 s->insn_bits = pci_dio_insn_bits_do_w;
1051 break;
1052 }
1053 s->private = (void *)d;
1054
1055 return 0;
1056 }
1057
1058 /*
1059 ==============================================================================
1060 */
1061 static int pci_dio_add_8254(struct comedi_device *dev,
1062 struct comedi_subdevice *s,
1063 const struct diosubd_data *d)
1064 {
1065 s->type = COMEDI_SUBD_COUNTER;
1066 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1067 s->n_chan = d->chans;
1068 s->maxdata = 65535;
1069 s->len_chanlist = d->chans;
1070 s->insn_read = pci_8254_insn_read;
1071 s->insn_write = pci_8254_insn_write;
1072 s->insn_config = pci_8254_insn_config;
1073 s->private = (void *)d;
1074
1075 return 0;
1076 }
1077
1078 static const void *pci_dio_find_boardinfo(struct comedi_device *dev,
1079 struct pci_dev *pcidev)
1080 {
1081 const struct dio_boardtype *this_board;
1082 int i;
1083
1084 for (i = 0; i < ARRAY_SIZE(boardtypes); ++i) {
1085 this_board = &boardtypes[i];
1086 if (this_board->vendor_id == pcidev->vendor &&
1087 this_board->device_id == pcidev->device)
1088 return this_board;
1089 }
1090 return NULL;
1091 }
1092
1093 static int pci_dio_auto_attach(struct comedi_device *dev,
1094 unsigned long context_unused)
1095 {
1096 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1097 const struct dio_boardtype *this_board;
1098 struct pci_dio_private *devpriv;
1099 struct comedi_subdevice *s;
1100 int ret, subdev, i, j;
1101
1102 this_board = pci_dio_find_boardinfo(dev, pcidev);
1103 if (!this_board)
1104 return -ENODEV;
1105 dev->board_ptr = this_board;
1106 dev->board_name = this_board->name;
1107
1108 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1109 if (!devpriv)
1110 return -ENOMEM;
1111 dev->private = devpriv;
1112
1113 ret = comedi_pci_enable(pcidev, dev->board_name);
1114 if (ret)
1115 return ret;
1116 dev->iobase = pci_resource_start(pcidev, this_board->main_pci_region);
1117
1118 ret = comedi_alloc_subdevices(dev, this_board->nsubdevs);
1119 if (ret)
1120 return ret;
1121
1122 subdev = 0;
1123 for (i = 0; i < MAX_DI_SUBDEVS; i++)
1124 if (this_board->sdi[i].chans) {
1125 s = &dev->subdevices[subdev];
1126 pci_dio_add_di(dev, s, &this_board->sdi[i]);
1127 subdev++;
1128 }
1129
1130 for (i = 0; i < MAX_DO_SUBDEVS; i++)
1131 if (this_board->sdo[i].chans) {
1132 s = &dev->subdevices[subdev];
1133 pci_dio_add_do(dev, s, &this_board->sdo[i]);
1134 subdev++;
1135 }
1136
1137 for (i = 0; i < MAX_DIO_SUBDEVG; i++)
1138 for (j = 0; j < this_board->sdio[i].regs; j++) {
1139 s = &dev->subdevices[subdev];
1140 subdev_8255_init(dev, s, NULL,
1141 dev->iobase +
1142 this_board->sdio[i].addr +
1143 SIZE_8255 * j);
1144 subdev++;
1145 }
1146
1147 if (this_board->boardid.chans) {
1148 s = &dev->subdevices[subdev];
1149 s->type = COMEDI_SUBD_DI;
1150 pci_dio_add_di(dev, s, &this_board->boardid);
1151 subdev++;
1152 }
1153
1154 for (i = 0; i < MAX_8254_SUBDEVS; i++)
1155 if (this_board->s8254[i].chans) {
1156 s = &dev->subdevices[subdev];
1157 pci_dio_add_8254(dev, s, &this_board->s8254[i]);
1158 subdev++;
1159 }
1160
1161 if (this_board->cardtype == TYPE_PCI1760)
1162 pci1760_attach(dev);
1163
1164 devpriv->valid = 1;
1165
1166 pci_dio_reset(dev);
1167
1168 return 0;
1169 }
1170
1171 static void pci_dio_detach(struct comedi_device *dev)
1172 {
1173 struct pci_dio_private *devpriv = dev->private;
1174 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1175 struct comedi_subdevice *s;
1176 int i;
1177
1178 if (devpriv) {
1179 if (devpriv->valid)
1180 pci_dio_reset(dev);
1181 }
1182 if (dev->subdevices) {
1183 for (i = 0; i < dev->n_subdevices; i++) {
1184 s = &dev->subdevices[i];
1185 if (s->type == COMEDI_SUBD_DIO)
1186 subdev_8255_cleanup(dev, s);
1187 s->private = NULL;
1188 }
1189 }
1190 if (pcidev) {
1191 if (dev->iobase)
1192 comedi_pci_disable(pcidev);
1193 }
1194 }
1195
1196 static struct comedi_driver adv_pci_dio_driver = {
1197 .driver_name = "adv_pci_dio",
1198 .module = THIS_MODULE,
1199 .auto_attach = pci_dio_auto_attach,
1200 .detach = pci_dio_detach,
1201 };
1202
1203 static int adv_pci_dio_pci_probe(struct pci_dev *dev,
1204 const struct pci_device_id *ent)
1205 {
1206 return comedi_pci_auto_config(dev, &adv_pci_dio_driver);
1207 }
1208
1209 static void adv_pci_dio_pci_remove(struct pci_dev *dev)
1210 {
1211 comedi_pci_auto_unconfig(dev);
1212 }
1213
1214 static DEFINE_PCI_DEVICE_TABLE(adv_pci_dio_pci_table) = {
1215 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1730) },
1216 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1733) },
1217 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1734) },
1218 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1735) },
1219 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1736) },
1220 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1739) },
1221 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1750) },
1222 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1751) },
1223 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1752) },
1224 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1753) },
1225 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1754) },
1226 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1756) },
1227 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
1228 { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1762) },
1229 { 0 }
1230 };
1231 MODULE_DEVICE_TABLE(pci, adv_pci_dio_pci_table);
1232
1233 static struct pci_driver adv_pci_dio_pci_driver = {
1234 .name = "adv_pci_dio",
1235 .id_table = adv_pci_dio_pci_table,
1236 .probe = adv_pci_dio_pci_probe,
1237 .remove = adv_pci_dio_pci_remove,
1238 };
1239 module_comedi_pci_driver(adv_pci_dio_driver, adv_pci_dio_pci_driver);
1240
1241 MODULE_AUTHOR("Comedi http://www.comedi.org");
1242 MODULE_DESCRIPTION("Comedi low-level driver");
1243 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)