drivers/staging/comedi/comedi.h

   1 /*
   2     include/comedi.h (installed as /usr/include/comedi.h)
   3     header file for comedi
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU Lesser General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 #ifndef _COMEDI_H
  25 #define _COMEDI_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #define COMEDI_MAJORVERSION     0
  32 #define COMEDI_MINORVERSION     7
  33 #define COMEDI_MICROVERSION     76
  34 #define VERSION "0.7.76"
  35
  36 /* comedi's major device number */
  37 #define COMEDI_MAJOR 98
  38
  39 /*
  40    maximum number of minor devices.  This can be increased, although
  41    kernel structures are currently statically allocated, thus you
  42    don't want this to be much more than you actually use.
  43  */
  44 #define COMEDI_NDEVICES 16
  45
  46 /* number of config options in the config structure */
  47 #define COMEDI_NDEVCONFOPTS 32
  48 /*length of nth chunk of firmware data*/
  49 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH         25
  50 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH         26
  51 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH         27
  52 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH         28
  53 #define COMEDI_DEVCONF_AUX_DATA_HI              29      /* most significant 32 bits of pointer address (if needed) */
  54 #define COMEDI_DEVCONF_AUX_DATA_LO              30      /* least significant 32 bits of pointer address */
  55 #define COMEDI_DEVCONF_AUX_DATA_LENGTH          31      /* total data length */
  56
  57 /* max length of device and driver names */
  58 #define COMEDI_NAMELEN 20
  59
  60 /* packs and unpacks a channel/range number */
  61
  62 #define CR_PACK(chan, rng, aref)                ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
  63 #define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
  64
  65 #define CR_CHAN(a)      ((a)&0xffff)
  66 #define CR_RANGE(a)     (((a)>>16)&0xff)
  67 #define CR_AREF(a)      (((a)>>24)&0x03)
  68
  69 #define CR_FLAGS_MASK   0xfc000000
  70 #define CR_ALT_FILTER   (1<<26)
  71 #define CR_DITHER       CR_ALT_FILTER
  72 #define CR_DEGLITCH     CR_ALT_FILTER
  73 #define CR_ALT_SOURCE   (1<<27)
  74 #define CR_EDGE         (1<<30)
  75 #define CR_INVERT       (1<<31)
  76
  77 #define AREF_GROUND     0x00    /* analog ref = analog ground */
  78 #define AREF_COMMON     0x01    /* analog ref = analog common */
  79 #define AREF_DIFF       0x02    /* analog ref = differential */
  80 #define AREF_OTHER      0x03    /* analog ref = other (undefined) */
  81
  82 /* counters -- these are arbitrary values */
  83 #define GPCT_RESET              0x0001
  84 #define GPCT_SET_SOURCE         0x0002
  85 #define GPCT_SET_GATE           0x0004
  86 #define GPCT_SET_DIRECTION      0x0008
  87 #define GPCT_SET_OPERATION      0x0010
  88 #define GPCT_ARM                0x0020
  89 #define GPCT_DISARM             0x0040
  90 #define GPCT_GET_INT_CLK_FRQ    0x0080
  91
  92 #define GPCT_INT_CLOCK          0x0001
  93 #define GPCT_EXT_PIN            0x0002
  94 #define GPCT_NO_GATE            0x0004
  95 #define GPCT_UP                 0x0008
  96 #define GPCT_DOWN               0x0010
  97 #define GPCT_HWUD               0x0020
  98 #define GPCT_SIMPLE_EVENT       0x0040
  99 #define GPCT_SINGLE_PERIOD      0x0080
 100 #define GPCT_SINGLE_PW          0x0100
 101 #define GPCT_CONT_PULSE_OUT     0x0200
 102 #define GPCT_SINGLE_PULSE_OUT   0x0400
 103
 104 /* instructions */
 105
 106 #define INSN_MASK_WRITE         0x8000000
 107 #define INSN_MASK_READ          0x4000000
 108 #define INSN_MASK_SPECIAL       0x2000000
 109
 110 #define INSN_READ               (0 | INSN_MASK_READ)
 111 #define INSN_WRITE              (1 | INSN_MASK_WRITE)
 112 #define INSN_BITS               (2 | INSN_MASK_READ|INSN_MASK_WRITE)
 113 #define INSN_CONFIG             (3 | INSN_MASK_READ|INSN_MASK_WRITE)
 114 #define INSN_GTOD               (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
 115 #define INSN_WAIT               (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 116 #define INSN_INTTRIG            (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 117
 118 /* trigger flags */
 119 /* These flags are used in comedi_trig structures */
 120
 121 #define TRIG_BOGUS      0x0001  /* do the motions */
 122 #define TRIG_DITHER     0x0002  /* enable dithering */
 123 #define TRIG_DEGLITCH   0x0004  /* enable deglitching */
 124 /*#define TRIG_RT       0x0008 */       /* perform op in real time */
 125 #define TRIG_CONFIG     0x0010  /* perform configuration, not triggering */
 126 #define TRIG_WAKE_EOS   0x0020  /* wake up on end-of-scan events */
 127 /*#define TRIG_WRITE    0x0040*/        /* write to bidirectional devices */
 128
 129 /* command flags */
 130 /* These flags are used in comedi_cmd structures */
 131
 132 #define CMDF_PRIORITY           0x00000008      /* try to use a real-time interrupt while performing command */
 133
 134 #define TRIG_RT         CMDF_PRIORITY   /* compatibility definition */
 135
 136 #define CMDF_WRITE              0x00000040
 137 #define TRIG_WRITE      CMDF_WRITE      /* compatibility definition */
 138
 139 #define CMDF_RAWDATA            0x00000080
 140
 141 #define COMEDI_EV_START         0x00040000
 142 #define COMEDI_EV_SCAN_BEGIN    0x00080000
 143 #define COMEDI_EV_CONVERT       0x00100000
 144 #define COMEDI_EV_SCAN_END      0x00200000
 145 #define COMEDI_EV_STOP          0x00400000
 146
 147 #define TRIG_ROUND_MASK         0x00030000
 148 #define TRIG_ROUND_NEAREST      0x00000000
 149 #define TRIG_ROUND_DOWN         0x00010000
 150 #define TRIG_ROUND_UP           0x00020000
 151 #define TRIG_ROUND_UP_NEXT      0x00030000
 152
 153 /* trigger sources */
 154
 155 #define TRIG_ANY        0xffffffff
 156 #define TRIG_INVALID    0x00000000
 157
 158 #define TRIG_NONE       0x00000001      /* never trigger */
 159 #define TRIG_NOW        0x00000002      /* trigger now + N ns */
 160 #define TRIG_FOLLOW     0x00000004      /* trigger on next lower level trig */
 161 #define TRIG_TIME       0x00000008      /* trigger at time N ns */
 162 #define TRIG_TIMER      0x00000010      /* trigger at rate N ns */
 163 #define TRIG_COUNT      0x00000020      /* trigger when count reaches N */
 164 #define TRIG_EXT        0x00000040      /* trigger on external signal N */
 165 #define TRIG_INT        0x00000080      /* trigger on comedi-internal signal N */
 166 #define TRIG_OTHER      0x00000100      /* driver defined */
 167
 168 /* subdevice flags */
 169
 170 #define SDF_BUSY        0x0001  /* device is busy */
 171 #define SDF_BUSY_OWNER  0x0002  /* device is busy with your job */
 172 #define SDF_LOCKED      0x0004  /* subdevice is locked */
 173 #define SDF_LOCK_OWNER  0x0008  /* you own lock */
 174 #define SDF_MAXDATA     0x0010  /* maxdata depends on channel */
 175 #define SDF_FLAGS       0x0020  /* flags depend on channel */
 176 #define SDF_RANGETYPE   0x0040  /* range type depends on channel */
 177 #define SDF_MODE0       0x0080  /* can do mode 0 */
 178 #define SDF_MODE1       0x0100  /* can do mode 1 */
 179 #define SDF_MODE2       0x0200  /* can do mode 2 */
 180 #define SDF_MODE3       0x0400  /* can do mode 3 */
 181 #define SDF_MODE4       0x0800  /* can do mode 4 */
 182 #define SDF_CMD         0x1000  /* can do commands (deprecated) */
 183 #define SDF_SOFT_CALIBRATED     0x2000  /* subdevice uses software calibration */
 184 #define SDF_CMD_WRITE           0x4000  /* can do output commands */
 185 #define SDF_CMD_READ            0x8000  /* can do input commands */
 186
 187 #define SDF_READABLE    0x00010000      /* subdevice can be read (e.g. analog input) */
 188 #define SDF_WRITABLE    0x00020000      /* subdevice can be written (e.g. analog output) */
 189 #define SDF_WRITEABLE   SDF_WRITABLE    /* spelling error in API */
 190 #define SDF_INTERNAL    0x00040000      /* subdevice does not have externally visible lines */
 191 #define SDF_RT          0x00080000      /* DEPRECATED: subdevice is RT capable */
 192 #define SDF_GROUND      0x00100000      /* can do aref=ground */
 193 #define SDF_COMMON      0x00200000      /* can do aref=common */
 194 #define SDF_DIFF        0x00400000      /* can do aref=diff */
 195 #define SDF_OTHER       0x00800000      /* can do aref=other */
 196 #define SDF_DITHER      0x01000000      /* can do dithering */
 197 #define SDF_DEGLITCH    0x02000000      /* can do deglitching */
 198 #define SDF_MMAP        0x04000000      /* can do mmap() */
 199 #define SDF_RUNNING     0x08000000      /* subdevice is acquiring data */
 200 #define SDF_LSAMPL      0x10000000      /* subdevice uses 32-bit samples */
 201 #define SDF_PACKED      0x20000000      /* subdevice can do packed DIO */
 202 /* re recyle these flags for PWM */
 203 #define SDF_PWM_COUNTER SDF_MODE0       /* PWM can automatically switch off */
 204 #define SDF_PWM_HBRIDGE SDF_MODE1       /* PWM is signed (H-bridge) */
 205
 206
 207
 208 /* subdevice types */
 209
 210 enum comedi_subdevice_type {
 211         COMEDI_SUBD_UNUSED,     /* unused by driver */
 212         COMEDI_SUBD_AI, /* analog input */
 213         COMEDI_SUBD_AO, /* analog output */
 214         COMEDI_SUBD_DI, /* digital input */
 215         COMEDI_SUBD_DO, /* digital output */
 216         COMEDI_SUBD_DIO,        /* digital input/output */
 217         COMEDI_SUBD_COUNTER,    /* counter */
 218         COMEDI_SUBD_TIMER,      /* timer */
 219         COMEDI_SUBD_MEMORY,     /* memory, EEPROM, DPRAM */
 220         COMEDI_SUBD_CALIB,      /* calibration DACs */
 221         COMEDI_SUBD_PROC,       /* processor, DSP */
 222         COMEDI_SUBD_SERIAL,     /* serial IO */
 223         COMEDI_SUBD_PWM         /* PWM */
 224 };
 225
 226 /* configuration instructions */
 227
 228 enum configuration_ids {
 229         INSN_CONFIG_DIO_INPUT = 0,
 230         INSN_CONFIG_DIO_OUTPUT = 1,
 231         INSN_CONFIG_DIO_OPENDRAIN = 2,
 232         INSN_CONFIG_ANALOG_TRIG = 16,
 233 /*      INSN_CONFIG_WAVEFORM = 17, */
 234 /*      INSN_CONFIG_TRIG = 18, */
 235 /*      INSN_CONFIG_COUNTER = 19, */
 236         INSN_CONFIG_ALT_SOURCE = 20,
 237         INSN_CONFIG_DIGITAL_TRIG = 21,
 238         INSN_CONFIG_BLOCK_SIZE = 22,
 239         INSN_CONFIG_TIMER_1 = 23,
 240         INSN_CONFIG_FILTER = 24,
 241         INSN_CONFIG_CHANGE_NOTIFY = 25,
 242
 243          /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
 244         INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
 245         INSN_CONFIG_DIO_QUERY = 28,
 246         INSN_CONFIG_PWM_OUTPUT = 29,
 247         INSN_CONFIG_GET_PWM_OUTPUT = 30,
 248         INSN_CONFIG_ARM = 31,
 249         INSN_CONFIG_DISARM = 32,
 250         INSN_CONFIG_GET_COUNTER_STATUS = 33,
 251         INSN_CONFIG_RESET = 34,
 252         INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, /* Use CTR as single pulsegenerator */
 253         INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,  /* Use CTR as pulsetraingenerator */
 254         INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,     /* Use the counter as encoder */
 255         INSN_CONFIG_SET_GATE_SRC = 2001,        /* Set gate source */
 256         INSN_CONFIG_GET_GATE_SRC = 2002,        /* Get gate source */
 257         INSN_CONFIG_SET_CLOCK_SRC = 2003,       /* Set master clock source */
 258         INSN_CONFIG_GET_CLOCK_SRC = 2004,       /* Get master clock source */
 259         INSN_CONFIG_SET_OTHER_SRC = 2005,       /* Set other source */
 260 /*      INSN_CONFIG_GET_OTHER_SRC = 2006,*/     /* Get other source */
 261         INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,    /* Get size in bytes of
 262                                                            subdevice's on-board
 263                                                            fifos used during
 264                                                            streaming
 265                                                            input/output */
 266         INSN_CONFIG_SET_COUNTER_MODE = 4097,
 267         INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,       /* deprecated */
 268         INSN_CONFIG_8254_READ_STATUS = 4098,
 269         INSN_CONFIG_SET_ROUTING = 4099,
 270         INSN_CONFIG_GET_ROUTING = 4109,
 271 /* PWM */
 272         INSN_CONFIG_PWM_SET_PERIOD = 5000,   /* sets frequency */
 273         INSN_CONFIG_PWM_GET_PERIOD = 5001,   /* gets frequency */
 274         INSN_CONFIG_GET_PWM_STATUS = 5002,          /* is it running? */
 275         INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay  at the same time*/
 276         INSN_CONFIG_PWM_GET_H_BRIDGE = 5004  /* gets H bridge data: duty cycle and the sign bit */
 277 };
 278
 279 enum comedi_io_direction {
 280         COMEDI_INPUT = 0,
 281         COMEDI_OUTPUT = 1,
 282         COMEDI_OPENDRAIN = 2
 283 };
 284
 285 enum comedi_support_level {
 286         COMEDI_UNKNOWN_SUPPORT = 0,
 287         COMEDI_SUPPORTED,
 288         COMEDI_UNSUPPORTED
 289 };
 290
 291 /* ioctls */
 292
 293 #define CIO 'd'
 294 #define COMEDI_DEVCONFIG _IOW(CIO, 0, comedi_devconfig)
 295 #define COMEDI_DEVINFO _IOR(CIO, 1, comedi_devinfo)
 296 #define COMEDI_SUBDINFO _IOR(CIO, 2, comedi_subdinfo)
 297 #define COMEDI_CHANINFO _IOR(CIO, 3, comedi_chaninfo)
 298 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
 299 #define COMEDI_LOCK _IO(CIO, 5)
 300 #define COMEDI_UNLOCK _IO(CIO, 6)
 301 #define COMEDI_CANCEL _IO(CIO, 7)
 302 #define COMEDI_RANGEINFO _IOR(CIO, 8, comedi_rangeinfo)
 303 #define COMEDI_CMD _IOR(CIO, 9, comedi_cmd)
 304 #define COMEDI_CMDTEST _IOR(CIO, 10, comedi_cmd)
 305 #define COMEDI_INSNLIST _IOR(CIO, 11, comedi_insnlist)
 306 #define COMEDI_INSN _IOR(CIO, 12, comedi_insn)
 307 #define COMEDI_BUFCONFIG _IOR(CIO, 13, comedi_bufconfig)
 308 #define COMEDI_BUFINFO _IOWR(CIO, 14, comedi_bufinfo)
 309 #define COMEDI_POLL _IO(CIO, 15)
 310
 311 /* structures */
 312
 313 typedef struct comedi_trig_struct comedi_trig;
 314 typedef struct comedi_cmd_struct comedi_cmd;
 315 typedef struct comedi_insn_struct comedi_insn;
 316 typedef struct comedi_insnlist_struct comedi_insnlist;
 317 typedef struct comedi_chaninfo_struct comedi_chaninfo;
 318 typedef struct comedi_subdinfo_struct comedi_subdinfo;
 319 typedef struct comedi_devinfo_struct comedi_devinfo;
 320 typedef struct comedi_devconfig_struct comedi_devconfig;
 321 typedef struct comedi_rangeinfo_struct comedi_rangeinfo;
 322 typedef struct comedi_krange_struct comedi_krange;
 323 typedef struct comedi_bufconfig_struct comedi_bufconfig;
 324 typedef struct comedi_bufinfo_struct comedi_bufinfo;
 325
 326 struct comedi_trig_struct {
 327         unsigned int subdev;    /* subdevice */
 328         unsigned int mode;      /* mode */
 329         unsigned int flags;
 330         unsigned int n_chan;    /* number of channels */
 331         unsigned int *chanlist; /* channel/range list */
 332         short *data;    /* data list, size depends on subd flags */
 333         unsigned int n; /* number of scans */
 334         unsigned int trigsrc;
 335         unsigned int trigvar;
 336         unsigned int trigvar1;
 337         unsigned int data_len;
 338         unsigned int unused[3];
 339 };
 340
 341 struct comedi_insn_struct {
 342         unsigned int insn;
 343         unsigned int n;
 344         unsigned int *data;
 345         unsigned int subdev;
 346         unsigned int chanspec;
 347         unsigned int unused[3];
 348 };
 349
 350 struct comedi_insnlist_struct {
 351         unsigned int n_insns;
 352         comedi_insn *insns;
 353 };
 354
 355 struct comedi_cmd_struct {
 356         unsigned int subdev;
 357         unsigned int flags;
 358
 359         unsigned int start_src;
 360         unsigned int start_arg;
 361
 362         unsigned int scan_begin_src;
 363         unsigned int scan_begin_arg;
 364
 365         unsigned int convert_src;
 366         unsigned int convert_arg;
 367
 368         unsigned int scan_end_src;
 369         unsigned int scan_end_arg;
 370
 371         unsigned int stop_src;
 372         unsigned int stop_arg;
 373
 374         unsigned int *chanlist; /* channel/range list */
 375         unsigned int chanlist_len;
 376
 377         short *data;    /* data list, size depends on subd flags */
 378         unsigned int data_len;
 379 };
 380
 381 struct comedi_chaninfo_struct {
 382         unsigned int subdev;
 383         unsigned int *maxdata_list;
 384         unsigned int *flaglist;
 385         unsigned int *rangelist;
 386         unsigned int unused[4];
 387 };
 388
 389 struct comedi_rangeinfo_struct {
 390         unsigned int range_type;
 391         void *range_ptr;
 392 };
 393
 394 struct comedi_krange_struct {
 395         int min;        /* fixed point, multiply by 1e-6 */
 396         int max;        /* fixed point, multiply by 1e-6 */
 397         unsigned int flags;
 398 };
 399
 400
 401 struct comedi_subdinfo_struct {
 402         unsigned int type;
 403         unsigned int n_chan;
 404         unsigned int subd_flags;
 405         unsigned int timer_type;
 406         unsigned int len_chanlist;
 407         unsigned int maxdata;
 408         unsigned int flags;     /* channel flags */
 409         unsigned int range_type;        /* lookup in kernel */
 410         unsigned int settling_time_0;
 411         unsigned insn_bits_support;     /* see support_level enum for values*/
 412         unsigned int unused[8];
 413 };
 414
 415 struct comedi_devinfo_struct {
 416         unsigned int version_code;
 417         unsigned int n_subdevs;
 418         char driver_name[COMEDI_NAMELEN];
 419         char board_name[COMEDI_NAMELEN];
 420         int read_subdevice;
 421         int write_subdevice;
 422         int unused[30];
 423 };
 424
 425 struct comedi_devconfig_struct {
 426         char board_name[COMEDI_NAMELEN];
 427         int options[COMEDI_NDEVCONFOPTS];
 428 };
 429
 430 struct comedi_bufconfig_struct {
 431         unsigned int subdevice;
 432         unsigned int flags;
 433
 434         unsigned int maximum_size;
 435         unsigned int size;
 436
 437         unsigned int unused[4];
 438 };
 439
 440 struct comedi_bufinfo_struct {
 441         unsigned int subdevice;
 442         unsigned int bytes_read;
 443
 444         unsigned int buf_write_ptr;
 445         unsigned int buf_read_ptr;
 446         unsigned int buf_write_count;
 447         unsigned int buf_read_count;
 448
 449         unsigned int bytes_written;
 450
 451         unsigned int unused[4];
 452 };
 453
 454 /* range stuff */
 455
 456 #define __RANGE(a, b)   ((((a)&0xffff)<<16)|((b)&0xffff))
 457
 458 #define RANGE_OFFSET(a)         (((a)>>16)&0xffff)
 459 #define RANGE_LENGTH(b)         ((b)&0xffff)
 460
 461 #define RF_UNIT(flags)          ((flags)&0xff)
 462 #define RF_EXTERNAL             (1<<8)
 463
 464 #define UNIT_volt               0
 465 #define UNIT_mA                 1
 466 #define UNIT_none               2
 467
 468 #define COMEDI_MIN_SPEED        ((unsigned int)0xffffffff)
 469
 470 /* callback stuff */
 471 /* only relevant to kernel modules. */
 472
 473 #define COMEDI_CB_EOS           1       /* end of scan */
 474 #define COMEDI_CB_EOA           2       /* end of acquisition */
 475 #define COMEDI_CB_BLOCK         4       /* DEPRECATED: convenient block size */
 476 #define COMEDI_CB_EOBUF         8       /* DEPRECATED: end of buffer */
 477 #define COMEDI_CB_ERROR         16      /* card error during acquisition */
 478 #define COMEDI_CB_OVERFLOW      32      /* buffer overflow/underflow */
 479
 480 /**********************************************************/
 481 /* everything after this line is ALPHA */
 482 /**********************************************************/
 483
 484 /*
 485   8254 specific configuration.
 486
 487   It supports two config commands:
 488
 489   0 ID: INSN_CONFIG_SET_COUNTER_MODE
 490   1 8254 Mode
 491     I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
 492     OR'ed with:
 493     I8254_BCD, I8254_BINARY
 494
 495   0 ID: INSN_CONFIG_8254_READ_STATUS
 496   1 <-- Status byte returned here.
 497     B7 = Output
 498     B6 = NULL Count
 499     B5 - B0 Current mode.
 500
 501 */
 502
 503 enum i8254_mode {
 504         I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
 505         I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
 506         I8254_MODE2 = (2 << 1), /* Rate generator */
 507         I8254_MODE3 = (3 << 1), /* Square wave mode */
 508         I8254_MODE4 = (4 << 1), /* Software triggered strobe */
 509         I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
 510         I8254_BCD = 1,  /* use binary-coded decimal instead of binary (pretty useless) */
 511         I8254_BINARY = 0
 512 };
 513
 514 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
 515 {
 516         if (pfi_channel < 10)
 517                 return 0x1 + pfi_channel;
 518         else
 519                 return 0xb + pfi_channel;
 520 }
 521 static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
 522 {
 523         if (rtsi_channel < 7)
 524                 return 0xb + rtsi_channel;
 525         else
 526                 return 0x1b;
 527 }
 528 /* mode bits for NI general-purpose counters, set with
 529  * INSN_CONFIG_SET_COUNTER_MODE */
 530 #define NI_GPCT_COUNTING_MODE_SHIFT 16
 531 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
 532 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
 533 enum ni_gpct_mode_bits {
 534         NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
 535         NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
 536         NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
 537         NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
 538         NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
 539         NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
 540         NI_GPCT_STOP_MODE_MASK = 0x60,
 541         NI_GPCT_STOP_ON_GATE_BITS = 0x00,
 542         NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
 543         NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
 544         NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
 545         NI_GPCT_OUTPUT_MODE_MASK = 0x300,
 546         NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
 547         NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
 548         NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
 549         NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
 550         NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
 551         NI_GPCT_DISARM_AT_TC_BITS = 0x400,
 552         NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
 553         NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
 554         NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
 555         NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
 556         NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
 557         NI_GPCT_COUNTING_MODE_NORMAL_BITS =
 558                 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
 559         NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
 560                 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
 561         NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
 562                 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
 563         NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
 564                 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
 565         NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
 566                 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
 567         NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
 568                 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
 569         NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 570         NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
 571                 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 572         NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
 573                 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 574         NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
 575                 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 576         NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
 577                 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 578         NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
 579         NI_GPCT_COUNTING_DIRECTION_MASK =
 580                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 581         NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
 582                 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 583         NI_GPCT_COUNTING_DIRECTION_UP_BITS =
 584                 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 585         NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
 586                 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 587         NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
 588                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 589         NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
 590         NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
 591         NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
 592         NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
 593         NI_GPCT_OR_GATE_BIT = 0x10000000,
 594         NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
 595 };
 596
 597 /* Bits for setting a clock source with
 598  * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
 599 enum ni_gpct_clock_source_bits {
 600         NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
 601         NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
 602         NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
 603         NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
 604         NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
 605         NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
 606         NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
 607         NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,      /* NI 660x-specific */
 608         NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
 609         NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
 610         NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
 611         NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
 612         NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
 613         NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */
 614         NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */
 615         NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
 616 };
 617 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
 618 {
 619         /* NI 660x-specific */
 620         return 0x10 + n;
 621 }
 622 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
 623 {
 624         return 0x18 + n;
 625 }
 626 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
 627 {
 628         /* no pfi on NI 660x */
 629         return 0x20 + n;
 630 }
 631
 632 /* Possibilities for setting a gate source with
 633 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
 634 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
 635 enum ni_gpct_gate_select {
 636         /* m-series gates */
 637         NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
 638         NI_GPCT_AI_START2_GATE_SELECT = 0x12,
 639         NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
 640         NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
 641         NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
 642         NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
 643         NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
 644         NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
 645         /* more gates for 660x */
 646         NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
 647         NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
 648         /* more gates for 660x "second gate" */
 649         NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
 650         NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
 651         /* m-series "second gate" sources are unknown,
 652            we should add them here with an offset of 0x300 when known. */
 653         NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
 654 };
 655 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
 656 {
 657         return 0x102 + n;
 658 }
 659 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
 660 {
 661         return NI_USUAL_RTSI_SELECT(n);
 662 }
 663 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
 664 {
 665         return NI_USUAL_PFI_SELECT(n);
 666 }
 667 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
 668 {
 669         return 0x202 + n;
 670 }
 671
 672 /* Possibilities for setting a source with
 673 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
 674 enum ni_gpct_other_index {
 675         NI_GPCT_SOURCE_ENCODER_A,
 676         NI_GPCT_SOURCE_ENCODER_B,
 677         NI_GPCT_SOURCE_ENCODER_Z
 678 };
 679 enum ni_gpct_other_select {
 680         /* m-series gates */
 681         /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
 682         NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
 683 };
 684 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
 685 {
 686         return NI_USUAL_PFI_SELECT(n);
 687 }
 688
 689 /* start sources for ni general-purpose counters for use with
 690 INSN_CONFIG_ARM */
 691 enum ni_gpct_arm_source {
 692         NI_GPCT_ARM_IMMEDIATE = 0x0,
 693         NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1,     /* Start both the counter and
 694                                                    the adjacent paired counter
 695                                                    simultaneously */
 696         /* NI doesn't document bits for selecting hardware arm triggers.  If
 697          * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
 698          * significant bits (3 bits for 660x or 5 bits for m-series) through to
 699          * the hardware.  This will at least allow someone to figure out what
 700          * the bits do later. */
 701         NI_GPCT_ARM_UNKNOWN = 0x1000,
 702 };
 703
 704 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
 705 enum ni_gpct_filter_select {
 706         NI_GPCT_FILTER_OFF = 0x0,
 707         NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
 708         NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
 709         NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
 710         NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
 711         NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
 712         NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
 713 };
 714
 715 /* PFI digital filtering options for ni m-series for use with
 716  * INSN_CONFIG_FILTER. */
 717 enum ni_pfi_filter_select {
 718         NI_PFI_FILTER_OFF = 0x0,
 719         NI_PFI_FILTER_125ns = 0x1,
 720         NI_PFI_FILTER_6425ns = 0x2,
 721         NI_PFI_FILTER_2550us = 0x3
 722 };
 723
 724 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
 725 enum ni_mio_clock_source {
 726         NI_MIO_INTERNAL_CLOCK = 0,
 727         NI_MIO_RTSI_CLOCK = 1,  /* doesn't work for m-series, use
 728                                    NI_MIO_PLL_RTSI_CLOCK() */
 729         /* the NI_MIO_PLL_* sources are m-series only */
 730         NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
 731         NI_MIO_PLL_PXI10_CLOCK = 3,
 732         NI_MIO_PLL_RTSI0_CLOCK = 4
 733 };
 734 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
 735 {
 736         return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
 737 }
 738
 739 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
 740  The numbers assigned are not arbitrary, they correspond to the bits required
 741  to program the board. */
 742 enum ni_rtsi_routing {
 743         NI_RTSI_OUTPUT_ADR_START1 = 0,
 744         NI_RTSI_OUTPUT_ADR_START2 = 1,
 745         NI_RTSI_OUTPUT_SCLKG = 2,
 746         NI_RTSI_OUTPUT_DACUPDN = 3,
 747         NI_RTSI_OUTPUT_DA_START1 = 4,
 748         NI_RTSI_OUTPUT_G_SRC0 = 5,
 749         NI_RTSI_OUTPUT_G_GATE0 = 6,
 750         NI_RTSI_OUTPUT_RGOUT0 = 7,
 751         NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
 752         NI_RTSI_OUTPUT_RTSI_OSC = 12    /* pre-m-series always have RTSI clock
 753                                            on line 7 */
 754 };
 755 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
 756 {
 757         return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
 758 }
 759
 760 /* Signals which can be routed to an NI PFI pin on an m-series board with
 761  * INSN_CONFIG_SET_ROUTING.  These numbers are also returned by
 762  * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
 763  * cannot be changed.  The numbers assigned are not arbitrary, they correspond
 764  * to the bits required to program the board. */
 765 enum ni_pfi_routing {
 766         NI_PFI_OUTPUT_PFI_DEFAULT = 0,
 767         NI_PFI_OUTPUT_AI_START1 = 1,
 768         NI_PFI_OUTPUT_AI_START2 = 2,
 769         NI_PFI_OUTPUT_AI_CONVERT = 3,
 770         NI_PFI_OUTPUT_G_SRC1 = 4,
 771         NI_PFI_OUTPUT_G_GATE1 = 5,
 772         NI_PFI_OUTPUT_AO_UPDATE_N = 6,
 773         NI_PFI_OUTPUT_AO_START1 = 7,
 774         NI_PFI_OUTPUT_AI_START_PULSE = 8,
 775         NI_PFI_OUTPUT_G_SRC0 = 9,
 776         NI_PFI_OUTPUT_G_GATE0 = 10,
 777         NI_PFI_OUTPUT_EXT_STROBE = 11,
 778         NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
 779         NI_PFI_OUTPUT_GOUT0 = 13,
 780         NI_PFI_OUTPUT_GOUT1 = 14,
 781         NI_PFI_OUTPUT_FREQ_OUT = 15,
 782         NI_PFI_OUTPUT_PFI_DO = 16,
 783         NI_PFI_OUTPUT_I_ATRIG = 17,
 784         NI_PFI_OUTPUT_RTSI0 = 18,
 785         NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
 786         NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
 787         NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
 788         NI_PFI_OUTPUT_CDI_SAMPLE = 29,
 789         NI_PFI_OUTPUT_CDO_UPDATE = 30
 790 };
 791 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
 792 {
 793         return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
 794 }
 795
 796 /* Signals which can be routed to output on a NI PFI pin on a 660x board
 797  with INSN_CONFIG_SET_ROUTING.  The numbers assigned are
 798  not arbitrary, they correspond to the bits required
 799  to program the board.  Lines 0 to 7 can only be set to
 800  NI_660X_PFI_OUTPUT_DIO.  Lines 32 to 39 can only be set to
 801  NI_660X_PFI_OUTPUT_COUNTER. */
 802 enum ni_660x_pfi_routing {
 803         NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
 804         NI_660X_PFI_OUTPUT_DIO = 2,     /* static digital output */
 805 };
 806
 807 /* NI External Trigger lines.  These values are not arbitrary, but are related
 808  * to the bits required to program the board (offset by 1 for historical
 809  * reasons). */
 810 static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
 811 {
 812         return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
 813 }
 814 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
 815 {
 816         return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
 817 }
 818
 819 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
 820 enum comedi_counter_status_flags {
 821         COMEDI_COUNTER_ARMED = 0x1,
 822         COMEDI_COUNTER_COUNTING = 0x2,
 823         COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
 824 };
 825
 826 /* Clock sources for CDIO subdevice on NI m-series boards.  Used as the
 827  * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
 828  * with CR_INVERT to change polarity. */
 829 enum ni_m_series_cdio_scan_begin_src {
 830         NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
 831         NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
 832         NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
 833         NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
 834         NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
 835         NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
 836         NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
 837         NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
 838         NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
 839         NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
 840 };
 841 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 842 {
 843         return NI_USUAL_PFI_SELECT(pfi_channel);
 844 }
 845 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 846 {
 847         return NI_USUAL_RTSI_SELECT(rtsi_channel);
 848 }
 849
 850 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
 851  * boards.  These scan begin sources can also be bitwise-or'd with CR_INVERT to
 852  * change polarity. */
 853 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 854 {
 855         return NI_USUAL_PFI_SELECT(pfi_channel);
 856 }
 857 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 858 {
 859         return NI_USUAL_RTSI_SELECT(rtsi_channel);
 860 }
 861
 862 /* Bits for setting a clock source with
 863  * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
 864 enum ni_freq_out_clock_source_bits {
 865         NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
 866         NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        /* 100 KHz */
 867 };
 868
 869 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 870  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 871         enum amplc_dio_clock_source {
 872                 AMPLC_DIO_CLK_CLKN,     /* per channel external clock
 873                                            input/output pin (pin is only an
 874                                            input when clock source set to this
 875                                            value, otherwise it is an output) */
 876                 AMPLC_DIO_CLK_10MHZ,    /* 10 MHz internal clock */
 877                 AMPLC_DIO_CLK_1MHZ,     /* 1 MHz internal clock */
 878                 AMPLC_DIO_CLK_100KHZ,   /* 100 kHz internal clock */
 879                 AMPLC_DIO_CLK_10KHZ,    /* 10 kHz internal clock */
 880                 AMPLC_DIO_CLK_1KHZ,     /* 1 kHz internal clock */
 881                 AMPLC_DIO_CLK_OUTNM1,   /* output of preceding counter channel
 882                                            (for channel 0, preceding counter
 883                                            channel is channel 2 on preceding
 884                                            counter subdevice, for first counter
 885                                            subdevice, preceding counter
 886                                            subdevice is the last counter
 887                                            subdevice) */
 888                 AMPLC_DIO_CLK_EXT       /* per chip external input pin */
 889         };
 890
 891 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
 892  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 893         enum amplc_dio_gate_source {
 894                 AMPLC_DIO_GAT_VCC,      /* internal high logic level */
 895                 AMPLC_DIO_GAT_GND,      /* internal low logic level */
 896                 AMPLC_DIO_GAT_GATN,     /* per channel external gate input */
 897                 AMPLC_DIO_GAT_NOUTNM2,  /* negated output of counter channel
 898                                            minus 2 (for channels 0 or 1,
 899                                            channel minus 2 is channel 1 or 2 on
 900                                            the preceding counter subdevice, for
 901                                            the first counter subdevice the
 902                                            preceding counter subdevice is the
 903                                            last counter subdevice) */
 904                 AMPLC_DIO_GAT_RESERVED4,
 905                 AMPLC_DIO_GAT_RESERVED5,
 906                 AMPLC_DIO_GAT_RESERVED6,
 907                 AMPLC_DIO_GAT_RESERVED7
 908         };
 909
 910 #ifdef __cplusplus
 911 }
 912 #endif
 913
 914 #endif /* _COMEDI_H */