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1251e074cb2bec57cd34901b2d733598980b55b2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / comedi.h
1 /*
2 include/comedi.h (installed as /usr/include/comedi.h)
3 header file for comedi
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU Lesser General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 */
23
24 #ifndef _COMEDI_H
25 #define _COMEDI_H
26
27 #define COMEDI_MAJORVERSION 0
28 #define COMEDI_MINORVERSION 7
29 #define COMEDI_MICROVERSION 76
30 #define VERSION "0.7.76"
31
32 /* comedi's major device number */
33 #define COMEDI_MAJOR 98
34
35 /*
36 maximum number of minor devices. This can be increased, although
37 kernel structures are currently statically allocated, thus you
38 don't want this to be much more than you actually use.
39 */
40 #define COMEDI_NDEVICES 16
41
42 /* number of config options in the config structure */
43 #define COMEDI_NDEVCONFOPTS 32
44 /*length of nth chunk of firmware data*/
45 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25
46 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26
47 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27
48 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28
49 #define COMEDI_DEVCONF_AUX_DATA_HI 29 /* most significant 32 bits of pointer address (if needed) */
50 #define COMEDI_DEVCONF_AUX_DATA_LO 30 /* least significant 32 bits of pointer address */
51 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */
52
53 /* max length of device and driver names */
54 #define COMEDI_NAMELEN 20
55
56 /* packs and unpacks a channel/range number */
57
58 #define CR_PACK(chan, rng, aref) ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
59 #define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
60
61 #define CR_CHAN(a) ((a)&0xffff)
62 #define CR_RANGE(a) (((a)>>16)&0xff)
63 #define CR_AREF(a) (((a)>>24)&0x03)
64
65 #define CR_FLAGS_MASK 0xfc000000
66 #define CR_ALT_FILTER (1<<26)
67 #define CR_DITHER CR_ALT_FILTER
68 #define CR_DEGLITCH CR_ALT_FILTER
69 #define CR_ALT_SOURCE (1<<27)
70 #define CR_EDGE (1<<30)
71 #define CR_INVERT (1<<31)
72
73 #define AREF_GROUND 0x00 /* analog ref = analog ground */
74 #define AREF_COMMON 0x01 /* analog ref = analog common */
75 #define AREF_DIFF 0x02 /* analog ref = differential */
76 #define AREF_OTHER 0x03 /* analog ref = other (undefined) */
77
78 /* counters -- these are arbitrary values */
79 #define GPCT_RESET 0x0001
80 #define GPCT_SET_SOURCE 0x0002
81 #define GPCT_SET_GATE 0x0004
82 #define GPCT_SET_DIRECTION 0x0008
83 #define GPCT_SET_OPERATION 0x0010
84 #define GPCT_ARM 0x0020
85 #define GPCT_DISARM 0x0040
86 #define GPCT_GET_INT_CLK_FRQ 0x0080
87
88 #define GPCT_INT_CLOCK 0x0001
89 #define GPCT_EXT_PIN 0x0002
90 #define GPCT_NO_GATE 0x0004
91 #define GPCT_UP 0x0008
92 #define GPCT_DOWN 0x0010
93 #define GPCT_HWUD 0x0020
94 #define GPCT_SIMPLE_EVENT 0x0040
95 #define GPCT_SINGLE_PERIOD 0x0080
96 #define GPCT_SINGLE_PW 0x0100
97 #define GPCT_CONT_PULSE_OUT 0x0200
98 #define GPCT_SINGLE_PULSE_OUT 0x0400
99
100 /* instructions */
101
102 #define INSN_MASK_WRITE 0x8000000
103 #define INSN_MASK_READ 0x4000000
104 #define INSN_MASK_SPECIAL 0x2000000
105
106 #define INSN_READ (0 | INSN_MASK_READ)
107 #define INSN_WRITE (1 | INSN_MASK_WRITE)
108 #define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE)
109 #define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE)
110 #define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
111 #define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
112 #define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
113
114 /* trigger flags */
115 /* These flags are used in comedi_trig structures */
116
117 #define TRIG_BOGUS 0x0001 /* do the motions */
118 #define TRIG_DITHER 0x0002 /* enable dithering */
119 #define TRIG_DEGLITCH 0x0004 /* enable deglitching */
120 /*#define TRIG_RT 0x0008 *//* perform op in real time */
121 #define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */
122 #define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */
123 /*#define TRIG_WRITE 0x0040*//* write to bidirectional devices */
124
125 /* command flags */
126 /* These flags are used in comedi_cmd structures */
127
128 #define CMDF_PRIORITY 0x00000008 /* try to use a real-time interrupt while performing command */
129
130 #define TRIG_RT CMDF_PRIORITY /* compatibility definition */
131
132 #define CMDF_WRITE 0x00000040
133 #define TRIG_WRITE CMDF_WRITE /* compatibility definition */
134
135 #define CMDF_RAWDATA 0x00000080
136
137 #define COMEDI_EV_START 0x00040000
138 #define COMEDI_EV_SCAN_BEGIN 0x00080000
139 #define COMEDI_EV_CONVERT 0x00100000
140 #define COMEDI_EV_SCAN_END 0x00200000
141 #define COMEDI_EV_STOP 0x00400000
142
143 #define TRIG_ROUND_MASK 0x00030000
144 #define TRIG_ROUND_NEAREST 0x00000000
145 #define TRIG_ROUND_DOWN 0x00010000
146 #define TRIG_ROUND_UP 0x00020000
147 #define TRIG_ROUND_UP_NEXT 0x00030000
148
149 /* trigger sources */
150
151 #define TRIG_ANY 0xffffffff
152 #define TRIG_INVALID 0x00000000
153
154 #define TRIG_NONE 0x00000001 /* never trigger */
155 #define TRIG_NOW 0x00000002 /* trigger now + N ns */
156 #define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */
157 #define TRIG_TIME 0x00000008 /* trigger at time N ns */
158 #define TRIG_TIMER 0x00000010 /* trigger at rate N ns */
159 #define TRIG_COUNT 0x00000020 /* trigger when count reaches N */
160 #define TRIG_EXT 0x00000040 /* trigger on external signal N */
161 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
162 #define TRIG_OTHER 0x00000100 /* driver defined */
163
164 /* subdevice flags */
165
166 #define SDF_BUSY 0x0001 /* device is busy */
167 #define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */
168 #define SDF_LOCKED 0x0004 /* subdevice is locked */
169 #define SDF_LOCK_OWNER 0x0008 /* you own lock */
170 #define SDF_MAXDATA 0x0010 /* maxdata depends on channel */
171 #define SDF_FLAGS 0x0020 /* flags depend on channel */
172 #define SDF_RANGETYPE 0x0040 /* range type depends on channel */
173 #define SDF_MODE0 0x0080 /* can do mode 0 */
174 #define SDF_MODE1 0x0100 /* can do mode 1 */
175 #define SDF_MODE2 0x0200 /* can do mode 2 */
176 #define SDF_MODE3 0x0400 /* can do mode 3 */
177 #define SDF_MODE4 0x0800 /* can do mode 4 */
178 #define SDF_CMD 0x1000 /* can do commands (deprecated) */
179 #define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */
180 #define SDF_CMD_WRITE 0x4000 /* can do output commands */
181 #define SDF_CMD_READ 0x8000 /* can do input commands */
182
183 #define SDF_READABLE 0x00010000 /* subdevice can be read (e.g. analog input) */
184 #define SDF_WRITABLE 0x00020000 /* subdevice can be written (e.g. analog output) */
185 #define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */
186 #define SDF_INTERNAL 0x00040000 /* subdevice does not have externally visible lines */
187 #define SDF_GROUND 0x00100000 /* can do aref=ground */
188 #define SDF_COMMON 0x00200000 /* can do aref=common */
189 #define SDF_DIFF 0x00400000 /* can do aref=diff */
190 #define SDF_OTHER 0x00800000 /* can do aref=other */
191 #define SDF_DITHER 0x01000000 /* can do dithering */
192 #define SDF_DEGLITCH 0x02000000 /* can do deglitching */
193 #define SDF_MMAP 0x04000000 /* can do mmap() */
194 #define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */
195 #define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */
196 #define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */
197 /* re recyle these flags for PWM */
198 #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */
199 #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */
200
201 /* subdevice types */
202
203 enum comedi_subdevice_type {
204 COMEDI_SUBD_UNUSED, /* unused by driver */
205 COMEDI_SUBD_AI, /* analog input */
206 COMEDI_SUBD_AO, /* analog output */
207 COMEDI_SUBD_DI, /* digital input */
208 COMEDI_SUBD_DO, /* digital output */
209 COMEDI_SUBD_DIO, /* digital input/output */
210 COMEDI_SUBD_COUNTER, /* counter */
211 COMEDI_SUBD_TIMER, /* timer */
212 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */
213 COMEDI_SUBD_CALIB, /* calibration DACs */
214 COMEDI_SUBD_PROC, /* processor, DSP */
215 COMEDI_SUBD_SERIAL, /* serial IO */
216 COMEDI_SUBD_PWM /* PWM */
217 };
218
219 /* configuration instructions */
220
221 enum configuration_ids {
222 INSN_CONFIG_DIO_INPUT = 0,
223 INSN_CONFIG_DIO_OUTPUT = 1,
224 INSN_CONFIG_DIO_OPENDRAIN = 2,
225 INSN_CONFIG_ANALOG_TRIG = 16,
226 /* INSN_CONFIG_WAVEFORM = 17, */
227 /* INSN_CONFIG_TRIG = 18, */
228 /* INSN_CONFIG_COUNTER = 19, */
229 INSN_CONFIG_ALT_SOURCE = 20,
230 INSN_CONFIG_DIGITAL_TRIG = 21,
231 INSN_CONFIG_BLOCK_SIZE = 22,
232 INSN_CONFIG_TIMER_1 = 23,
233 INSN_CONFIG_FILTER = 24,
234 INSN_CONFIG_CHANGE_NOTIFY = 25,
235
236 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
237 INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
238 INSN_CONFIG_DIO_QUERY = 28,
239 INSN_CONFIG_PWM_OUTPUT = 29,
240 INSN_CONFIG_GET_PWM_OUTPUT = 30,
241 INSN_CONFIG_ARM = 31,
242 INSN_CONFIG_DISARM = 32,
243 INSN_CONFIG_GET_COUNTER_STATUS = 33,
244 INSN_CONFIG_RESET = 34,
245 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, /* Use CTR as single pulsegenerator */
246 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002, /* Use CTR as pulsetraingenerator */
247 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003, /* Use the counter as encoder */
248 INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */
249 INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */
250 INSN_CONFIG_SET_CLOCK_SRC = 2003, /* Set master clock source */
251 INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */
252 INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */
253 /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */
254 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006, /* Get size in bytes of
255 subdevice's on-board
256 fifos used during
257 streaming
258 input/output */
259 INSN_CONFIG_SET_COUNTER_MODE = 4097,
260 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE, /* deprecated */
261 INSN_CONFIG_8254_READ_STATUS = 4098,
262 INSN_CONFIG_SET_ROUTING = 4099,
263 INSN_CONFIG_GET_ROUTING = 4109,
264 /* PWM */
265 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */
266 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */
267 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */
268 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay at the same time */
269 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004 /* gets H bridge data: duty cycle and the sign bit */
270 };
271
272 enum comedi_io_direction {
273 COMEDI_INPUT = 0,
274 COMEDI_OUTPUT = 1,
275 COMEDI_OPENDRAIN = 2
276 };
277
278 enum comedi_support_level {
279 COMEDI_UNKNOWN_SUPPORT = 0,
280 COMEDI_SUPPORTED,
281 COMEDI_UNSUPPORTED
282 };
283
284 /* ioctls */
285
286 #define CIO 'd'
287 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
288 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
289 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
290 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
291 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
292 #define COMEDI_LOCK _IO(CIO, 5)
293 #define COMEDI_UNLOCK _IO(CIO, 6)
294 #define COMEDI_CANCEL _IO(CIO, 7)
295 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
296 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
297 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
298 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
299 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
300 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
301 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
302 #define COMEDI_POLL _IO(CIO, 15)
303
304 /* structures */
305
306 struct comedi_trig {
307 unsigned int subdev; /* subdevice */
308 unsigned int mode; /* mode */
309 unsigned int flags;
310 unsigned int n_chan; /* number of channels */
311 unsigned int *chanlist; /* channel/range list */
312 short *data; /* data list, size depends on subd flags */
313 unsigned int n; /* number of scans */
314 unsigned int trigsrc;
315 unsigned int trigvar;
316 unsigned int trigvar1;
317 unsigned int data_len;
318 unsigned int unused[3];
319 };
320
321 struct comedi_insn {
322 unsigned int insn;
323 unsigned int n;
324 unsigned int *data;
325 unsigned int subdev;
326 unsigned int chanspec;
327 unsigned int unused[3];
328 };
329
330 struct comedi_insnlist {
331 unsigned int n_insns;
332 struct comedi_insn *insns;
333 };
334
335 struct comedi_cmd {
336 unsigned int subdev;
337 unsigned int flags;
338
339 unsigned int start_src;
340 unsigned int start_arg;
341
342 unsigned int scan_begin_src;
343 unsigned int scan_begin_arg;
344
345 unsigned int convert_src;
346 unsigned int convert_arg;
347
348 unsigned int scan_end_src;
349 unsigned int scan_end_arg;
350
351 unsigned int stop_src;
352 unsigned int stop_arg;
353
354 unsigned int *chanlist; /* channel/range list */
355 unsigned int chanlist_len;
356
357 short *data; /* data list, size depends on subd flags */
358 unsigned int data_len;
359 };
360
361 struct comedi_chaninfo {
362 unsigned int subdev;
363 unsigned int *maxdata_list;
364 unsigned int *flaglist;
365 unsigned int *rangelist;
366 unsigned int unused[4];
367 };
368
369 struct comedi_rangeinfo {
370 unsigned int range_type;
371 void *range_ptr;
372 };
373
374 struct comedi_krange {
375 int min; /* fixed point, multiply by 1e-6 */
376 int max; /* fixed point, multiply by 1e-6 */
377 unsigned int flags;
378 };
379
380 struct comedi_subdinfo {
381 unsigned int type;
382 unsigned int n_chan;
383 unsigned int subd_flags;
384 unsigned int timer_type;
385 unsigned int len_chanlist;
386 unsigned int maxdata;
387 unsigned int flags; /* channel flags */
388 unsigned int range_type; /* lookup in kernel */
389 unsigned int settling_time_0;
390 unsigned insn_bits_support; /* see support_level enum for values */
391 unsigned int unused[8];
392 };
393
394 struct comedi_devinfo {
395 unsigned int version_code;
396 unsigned int n_subdevs;
397 char driver_name[COMEDI_NAMELEN];
398 char board_name[COMEDI_NAMELEN];
399 int read_subdevice;
400 int write_subdevice;
401 int unused[30];
402 };
403
404 struct comedi_devconfig {
405 char board_name[COMEDI_NAMELEN];
406 int options[COMEDI_NDEVCONFOPTS];
407 };
408
409 struct comedi_bufconfig {
410 unsigned int subdevice;
411 unsigned int flags;
412
413 unsigned int maximum_size;
414 unsigned int size;
415
416 unsigned int unused[4];
417 };
418
419 struct comedi_bufinfo {
420 unsigned int subdevice;
421 unsigned int bytes_read;
422
423 unsigned int buf_write_ptr;
424 unsigned int buf_read_ptr;
425 unsigned int buf_write_count;
426 unsigned int buf_read_count;
427
428 unsigned int bytes_written;
429
430 unsigned int unused[4];
431 };
432
433 /* range stuff */
434
435 #define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff))
436
437 #define RANGE_OFFSET(a) (((a)>>16)&0xffff)
438 #define RANGE_LENGTH(b) ((b)&0xffff)
439
440 #define RF_UNIT(flags) ((flags)&0xff)
441 #define RF_EXTERNAL (1<<8)
442
443 #define UNIT_volt 0
444 #define UNIT_mA 1
445 #define UNIT_none 2
446
447 #define COMEDI_MIN_SPEED ((unsigned int)0xffffffff)
448
449 /* callback stuff */
450 /* only relevant to kernel modules. */
451
452 #define COMEDI_CB_EOS 1 /* end of scan */
453 #define COMEDI_CB_EOA 2 /* end of acquisition */
454 #define COMEDI_CB_BLOCK 4 /* data has arrived: wakes up read() / write() */
455 #define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */
456 #define COMEDI_CB_ERROR 16 /* card error during acquisition */
457 #define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */
458
459 /**********************************************************/
460 /* everything after this line is ALPHA */
461 /**********************************************************/
462
463 /*
464 8254 specific configuration.
465
466 It supports two config commands:
467
468 0 ID: INSN_CONFIG_SET_COUNTER_MODE
469 1 8254 Mode
470 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
471 OR'ed with:
472 I8254_BCD, I8254_BINARY
473
474 0 ID: INSN_CONFIG_8254_READ_STATUS
475 1 <-- Status byte returned here.
476 B7 = Output
477 B6 = NULL Count
478 B5 - B0 Current mode.
479
480 */
481
482 enum i8254_mode {
483 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
484 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
485 I8254_MODE2 = (2 << 1), /* Rate generator */
486 I8254_MODE3 = (3 << 1), /* Square wave mode */
487 I8254_MODE4 = (4 << 1), /* Software triggered strobe */
488 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
489 I8254_BCD = 1, /* use binary-coded decimal instead of binary (pretty useless) */
490 I8254_BINARY = 0
491 };
492
493 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
494 {
495 if (pfi_channel < 10)
496 return 0x1 + pfi_channel;
497 else
498 return 0xb + pfi_channel;
499 } static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) {
500 if (rtsi_channel < 7)
501 return 0xb + rtsi_channel;
502 else
503 return 0x1b;
504 }
505 /* mode bits for NI general-purpose counters, set with
506 * INSN_CONFIG_SET_COUNTER_MODE */
507 #define NI_GPCT_COUNTING_MODE_SHIFT 16
508 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
509 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
510 enum ni_gpct_mode_bits {
511 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
512 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
513 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
514 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
515 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
516 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
517 NI_GPCT_STOP_MODE_MASK = 0x60,
518 NI_GPCT_STOP_ON_GATE_BITS = 0x00,
519 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
520 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
521 NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
522 NI_GPCT_OUTPUT_MODE_MASK = 0x300,
523 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
524 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
525 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
526 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
527 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
528 NI_GPCT_DISARM_AT_TC_BITS = 0x400,
529 NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
530 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
531 NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
532 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
533 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
534 NI_GPCT_COUNTING_MODE_NORMAL_BITS =
535 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
536 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
537 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
538 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
539 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
540 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
541 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
542 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
543 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
544 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
545 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
546 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
547 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
548 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
549 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
550 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
551 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
552 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
553 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
554 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
555 NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
556 NI_GPCT_COUNTING_DIRECTION_MASK =
557 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
558 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
559 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
560 NI_GPCT_COUNTING_DIRECTION_UP_BITS =
561 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
562 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
563 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
564 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
565 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
566 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
567 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
568 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
569 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
570 NI_GPCT_OR_GATE_BIT = 0x10000000,
571 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
572 };
573
574 /* Bits for setting a clock source with
575 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
576 enum ni_gpct_clock_source_bits {
577 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
578 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
579 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
580 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
581 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
582 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
583 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
584 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6, /* NI 660x-specific */
585 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
586 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
587 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
588 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
589 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
590 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */
591 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */
592 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
593 };
594 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
595 {
596 /* NI 660x-specific */
597 return 0x10 + n;
598 }
599 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
600 {
601 return 0x18 + n;
602 }
603 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
604 {
605 /* no pfi on NI 660x */
606 return 0x20 + n;
607 }
608
609 /* Possibilities for setting a gate source with
610 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
611 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
612 enum ni_gpct_gate_select {
613 /* m-series gates */
614 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
615 NI_GPCT_AI_START2_GATE_SELECT = 0x12,
616 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
617 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
618 NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
619 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
620 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
621 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
622 /* more gates for 660x */
623 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
624 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
625 /* more gates for 660x "second gate" */
626 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
627 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
628 /* m-series "second gate" sources are unknown,
629 we should add them here with an offset of 0x300 when known. */
630 NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
631 };
632 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
633 {
634 return 0x102 + n;
635 }
636 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
637 {
638 return NI_USUAL_RTSI_SELECT(n);
639 }
640 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
641 {
642 return NI_USUAL_PFI_SELECT(n);
643 }
644 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
645 {
646 return 0x202 + n;
647 }
648
649 /* Possibilities for setting a source with
650 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
651 enum ni_gpct_other_index {
652 NI_GPCT_SOURCE_ENCODER_A,
653 NI_GPCT_SOURCE_ENCODER_B,
654 NI_GPCT_SOURCE_ENCODER_Z
655 };
656 enum ni_gpct_other_select {
657 /* m-series gates */
658 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
659 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
660 };
661 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
662 {
663 return NI_USUAL_PFI_SELECT(n);
664 }
665
666 /* start sources for ni general-purpose counters for use with
667 INSN_CONFIG_ARM */
668 enum ni_gpct_arm_source {
669 NI_GPCT_ARM_IMMEDIATE = 0x0,
670 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter and
671 the adjacent paired counter
672 simultaneously */
673 /* NI doesn't document bits for selecting hardware arm triggers. If
674 * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
675 * significant bits (3 bits for 660x or 5 bits for m-series) through to
676 * the hardware. This will at least allow someone to figure out what
677 * the bits do later. */
678 NI_GPCT_ARM_UNKNOWN = 0x1000,
679 };
680
681 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
682 enum ni_gpct_filter_select {
683 NI_GPCT_FILTER_OFF = 0x0,
684 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
685 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
686 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
687 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
688 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
689 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
690 };
691
692 /* PFI digital filtering options for ni m-series for use with
693 * INSN_CONFIG_FILTER. */
694 enum ni_pfi_filter_select {
695 NI_PFI_FILTER_OFF = 0x0,
696 NI_PFI_FILTER_125ns = 0x1,
697 NI_PFI_FILTER_6425ns = 0x2,
698 NI_PFI_FILTER_2550us = 0x3
699 };
700
701 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
702 enum ni_mio_clock_source {
703 NI_MIO_INTERNAL_CLOCK = 0,
704 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use
705 NI_MIO_PLL_RTSI_CLOCK() */
706 /* the NI_MIO_PLL_* sources are m-series only */
707 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
708 NI_MIO_PLL_PXI10_CLOCK = 3,
709 NI_MIO_PLL_RTSI0_CLOCK = 4
710 };
711 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
712 {
713 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
714 }
715
716 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
717 The numbers assigned are not arbitrary, they correspond to the bits required
718 to program the board. */
719 enum ni_rtsi_routing {
720 NI_RTSI_OUTPUT_ADR_START1 = 0,
721 NI_RTSI_OUTPUT_ADR_START2 = 1,
722 NI_RTSI_OUTPUT_SCLKG = 2,
723 NI_RTSI_OUTPUT_DACUPDN = 3,
724 NI_RTSI_OUTPUT_DA_START1 = 4,
725 NI_RTSI_OUTPUT_G_SRC0 = 5,
726 NI_RTSI_OUTPUT_G_GATE0 = 6,
727 NI_RTSI_OUTPUT_RGOUT0 = 7,
728 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
729 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI clock
730 on line 7 */
731 };
732 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
733 {
734 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
735 }
736
737 /* Signals which can be routed to an NI PFI pin on an m-series board with
738 * INSN_CONFIG_SET_ROUTING. These numbers are also returned by
739 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
740 * cannot be changed. The numbers assigned are not arbitrary, they correspond
741 * to the bits required to program the board. */
742 enum ni_pfi_routing {
743 NI_PFI_OUTPUT_PFI_DEFAULT = 0,
744 NI_PFI_OUTPUT_AI_START1 = 1,
745 NI_PFI_OUTPUT_AI_START2 = 2,
746 NI_PFI_OUTPUT_AI_CONVERT = 3,
747 NI_PFI_OUTPUT_G_SRC1 = 4,
748 NI_PFI_OUTPUT_G_GATE1 = 5,
749 NI_PFI_OUTPUT_AO_UPDATE_N = 6,
750 NI_PFI_OUTPUT_AO_START1 = 7,
751 NI_PFI_OUTPUT_AI_START_PULSE = 8,
752 NI_PFI_OUTPUT_G_SRC0 = 9,
753 NI_PFI_OUTPUT_G_GATE0 = 10,
754 NI_PFI_OUTPUT_EXT_STROBE = 11,
755 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
756 NI_PFI_OUTPUT_GOUT0 = 13,
757 NI_PFI_OUTPUT_GOUT1 = 14,
758 NI_PFI_OUTPUT_FREQ_OUT = 15,
759 NI_PFI_OUTPUT_PFI_DO = 16,
760 NI_PFI_OUTPUT_I_ATRIG = 17,
761 NI_PFI_OUTPUT_RTSI0 = 18,
762 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
763 NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
764 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
765 NI_PFI_OUTPUT_CDI_SAMPLE = 29,
766 NI_PFI_OUTPUT_CDO_UPDATE = 30
767 };
768 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
769 {
770 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
771 }
772
773 /* Signals which can be routed to output on a NI PFI pin on a 660x board
774 with INSN_CONFIG_SET_ROUTING. The numbers assigned are
775 not arbitrary, they correspond to the bits required
776 to program the board. Lines 0 to 7 can only be set to
777 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to
778 NI_660X_PFI_OUTPUT_COUNTER. */
779 enum ni_660x_pfi_routing {
780 NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
781 NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */
782 };
783
784 /* NI External Trigger lines. These values are not arbitrary, but are related
785 * to the bits required to program the board (offset by 1 for historical
786 * reasons). */
787 static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
788 {
789 return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
790 }
791 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
792 {
793 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
794 }
795
796 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
797 enum comedi_counter_status_flags {
798 COMEDI_COUNTER_ARMED = 0x1,
799 COMEDI_COUNTER_COUNTING = 0x2,
800 COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
801 };
802
803 /* Clock sources for CDIO subdevice on NI m-series boards. Used as the
804 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
805 * with CR_INVERT to change polarity. */
806 enum ni_m_series_cdio_scan_begin_src {
807 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
808 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
809 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
810 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
811 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
812 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
813 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
814 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
815 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
816 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
817 };
818 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
819 {
820 return NI_USUAL_PFI_SELECT(pfi_channel);
821 }
822 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
823 {
824 return NI_USUAL_RTSI_SELECT(rtsi_channel);
825 }
826
827 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
828 * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to
829 * change polarity. */
830 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
831 {
832 return NI_USUAL_PFI_SELECT(pfi_channel);
833 }
834 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
835 {
836 return NI_USUAL_RTSI_SELECT(rtsi_channel);
837 }
838
839 /* Bits for setting a clock source with
840 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
841 enum ni_freq_out_clock_source_bits {
842 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
843 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */
844 };
845
846 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
847 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
848 enum amplc_dio_clock_source {
849 AMPLC_DIO_CLK_CLKN, /* per channel external clock
850 input/output pin (pin is only an
851 input when clock source set to this
852 value, otherwise it is an output) */
853 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */
854 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */
855 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */
856 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */
857 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */
858 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel
859 (for channel 0, preceding counter
860 channel is channel 2 on preceding
861 counter subdevice, for first counter
862 subdevice, preceding counter
863 subdevice is the last counter
864 subdevice) */
865 AMPLC_DIO_CLK_EXT /* per chip external input pin */
866 };
867
868 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
869 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
870 enum amplc_dio_gate_source {
871 AMPLC_DIO_GAT_VCC, /* internal high logic level */
872 AMPLC_DIO_GAT_GND, /* internal low logic level */
873 AMPLC_DIO_GAT_GATN, /* per channel external gate input */
874 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel
875 minus 2 (for channels 0 or 1,
876 channel minus 2 is channel 1 or 2 on
877 the preceding counter subdevice, for
878 the first counter subdevice the
879 preceding counter subdevice is the
880 last counter subdevice) */
881 AMPLC_DIO_GAT_RESERVED4,
882 AMPLC_DIO_GAT_RESERVED5,
883 AMPLC_DIO_GAT_RESERVED6,
884 AMPLC_DIO_GAT_RESERVED7
885 };
886
887 #endif /* _COMEDI_H */
kernel source for telekom puls (alcatel/mediatek)