2 * Sonics Silicon Backplane
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "ssb_private.h"
13 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pci.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/slab.h>
25 #include <pcmcia/cistpl.h>
26 #include <pcmcia/ds.h>
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
33 /* Temporary list of yet-to-be-attached buses */
34 static LIST_HEAD(attach_queue
);
35 /* List if running buses */
36 static LIST_HEAD(buses
);
37 /* Software ID counter */
38 static unsigned int next_busnumber
;
39 /* buses_mutes locks the two buslists and the next_busnumber.
40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41 static DEFINE_MUTEX(buses_mutex
);
43 /* There are differences in the codeflow, if the bus is
44 * initialized from early boot, as various needed services
45 * are not available early. This is a mechanism to delay
46 * these initializations to after early boot has finished.
47 * It's also used to avoid mutex locking, as that's not
48 * available and needed early. */
49 static bool ssb_is_early_boot
= 1;
51 static void ssb_buses_lock(void);
52 static void ssb_buses_unlock(void);
55 #ifdef CONFIG_SSB_PCIHOST
56 struct ssb_bus
*ssb_pci_dev_to_bus(struct pci_dev
*pdev
)
61 list_for_each_entry(bus
, &buses
, list
) {
62 if (bus
->bustype
== SSB_BUSTYPE_PCI
&&
63 bus
->host_pci
== pdev
)
72 #endif /* CONFIG_SSB_PCIHOST */
74 #ifdef CONFIG_SSB_PCMCIAHOST
75 struct ssb_bus
*ssb_pcmcia_dev_to_bus(struct pcmcia_device
*pdev
)
80 list_for_each_entry(bus
, &buses
, list
) {
81 if (bus
->bustype
== SSB_BUSTYPE_PCMCIA
&&
82 bus
->host_pcmcia
== pdev
)
91 #endif /* CONFIG_SSB_PCMCIAHOST */
93 #ifdef CONFIG_SSB_SDIOHOST
94 struct ssb_bus
*ssb_sdio_func_to_bus(struct sdio_func
*func
)
99 list_for_each_entry(bus
, &buses
, list
) {
100 if (bus
->bustype
== SSB_BUSTYPE_SDIO
&&
101 bus
->host_sdio
== func
)
110 #endif /* CONFIG_SSB_SDIOHOST */
112 int ssb_for_each_bus_call(unsigned long data
,
113 int (*func
)(struct ssb_bus
*bus
, unsigned long data
))
119 list_for_each_entry(bus
, &buses
, list
) {
120 res
= func(bus
, data
);
131 static struct ssb_device
*ssb_device_get(struct ssb_device
*dev
)
134 get_device(dev
->dev
);
138 static void ssb_device_put(struct ssb_device
*dev
)
141 put_device(dev
->dev
);
144 static int ssb_device_resume(struct device
*dev
)
146 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
147 struct ssb_driver
*ssb_drv
;
151 ssb_drv
= drv_to_ssb_drv(dev
->driver
);
152 if (ssb_drv
&& ssb_drv
->resume
)
153 err
= ssb_drv
->resume(ssb_dev
);
161 static int ssb_device_suspend(struct device
*dev
, pm_message_t state
)
163 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
164 struct ssb_driver
*ssb_drv
;
168 ssb_drv
= drv_to_ssb_drv(dev
->driver
);
169 if (ssb_drv
&& ssb_drv
->suspend
)
170 err
= ssb_drv
->suspend(ssb_dev
, state
);
178 int ssb_bus_resume(struct ssb_bus
*bus
)
182 /* Reset HW state information in memory, so that HW is
183 * completely reinitialized. */
184 bus
->mapped_device
= NULL
;
185 #ifdef CONFIG_SSB_DRIVER_PCICORE
186 bus
->pcicore
.setup_done
= 0;
189 err
= ssb_bus_powerup(bus
, 0);
192 err
= ssb_pcmcia_hardware_setup(bus
);
194 ssb_bus_may_powerdown(bus
);
197 ssb_chipco_resume(&bus
->chipco
);
198 ssb_bus_may_powerdown(bus
);
202 EXPORT_SYMBOL(ssb_bus_resume
);
204 int ssb_bus_suspend(struct ssb_bus
*bus
)
206 ssb_chipco_suspend(&bus
->chipco
);
207 ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 0);
211 EXPORT_SYMBOL(ssb_bus_suspend
);
213 #ifdef CONFIG_SSB_SPROM
214 /** ssb_devices_freeze - Freeze all devices on the bus.
216 * After freezing no device driver will be handling a device
217 * on this bus anymore. ssb_devices_thaw() must be called after
218 * a successful freeze to reactivate the devices.
221 * @ctx: Context structure. Pass this to ssb_devices_thaw().
223 int ssb_devices_freeze(struct ssb_bus
*bus
, struct ssb_freeze_context
*ctx
)
225 struct ssb_device
*sdev
;
226 struct ssb_driver
*sdrv
;
229 memset(ctx
, 0, sizeof(*ctx
));
231 SSB_WARN_ON(bus
->nr_devices
> ARRAY_SIZE(ctx
->device_frozen
));
233 for (i
= 0; i
< bus
->nr_devices
; i
++) {
234 sdev
= ssb_device_get(&bus
->devices
[i
]);
236 if (!sdev
->dev
|| !sdev
->dev
->driver
||
237 !device_is_registered(sdev
->dev
)) {
238 ssb_device_put(sdev
);
241 sdrv
= drv_to_ssb_drv(sdev
->dev
->driver
);
242 if (SSB_WARN_ON(!sdrv
->remove
))
245 ctx
->device_frozen
[i
] = 1;
251 /** ssb_devices_thaw - Unfreeze all devices on the bus.
253 * This will re-attach the device drivers and re-init the devices.
255 * @ctx: The context structure from ssb_devices_freeze()
257 int ssb_devices_thaw(struct ssb_freeze_context
*ctx
)
259 struct ssb_bus
*bus
= ctx
->bus
;
260 struct ssb_device
*sdev
;
261 struct ssb_driver
*sdrv
;
265 for (i
= 0; i
< bus
->nr_devices
; i
++) {
266 if (!ctx
->device_frozen
[i
])
268 sdev
= &bus
->devices
[i
];
270 if (SSB_WARN_ON(!sdev
->dev
|| !sdev
->dev
->driver
))
272 sdrv
= drv_to_ssb_drv(sdev
->dev
->driver
);
273 if (SSB_WARN_ON(!sdrv
|| !sdrv
->probe
))
276 err
= sdrv
->probe(sdev
, &sdev
->id
);
278 ssb_printk(KERN_ERR PFX
"Failed to thaw device %s\n",
279 dev_name(sdev
->dev
));
282 ssb_device_put(sdev
);
287 #endif /* CONFIG_SSB_SPROM */
289 static void ssb_device_shutdown(struct device
*dev
)
291 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
292 struct ssb_driver
*ssb_drv
;
296 ssb_drv
= drv_to_ssb_drv(dev
->driver
);
297 if (ssb_drv
&& ssb_drv
->shutdown
)
298 ssb_drv
->shutdown(ssb_dev
);
301 static int ssb_device_remove(struct device
*dev
)
303 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
304 struct ssb_driver
*ssb_drv
= drv_to_ssb_drv(dev
->driver
);
306 if (ssb_drv
&& ssb_drv
->remove
)
307 ssb_drv
->remove(ssb_dev
);
308 ssb_device_put(ssb_dev
);
313 static int ssb_device_probe(struct device
*dev
)
315 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
316 struct ssb_driver
*ssb_drv
= drv_to_ssb_drv(dev
->driver
);
319 ssb_device_get(ssb_dev
);
320 if (ssb_drv
&& ssb_drv
->probe
)
321 err
= ssb_drv
->probe(ssb_dev
, &ssb_dev
->id
);
323 ssb_device_put(ssb_dev
);
328 static int ssb_match_devid(const struct ssb_device_id
*tabid
,
329 const struct ssb_device_id
*devid
)
331 if ((tabid
->vendor
!= devid
->vendor
) &&
332 tabid
->vendor
!= SSB_ANY_VENDOR
)
334 if ((tabid
->coreid
!= devid
->coreid
) &&
335 tabid
->coreid
!= SSB_ANY_ID
)
337 if ((tabid
->revision
!= devid
->revision
) &&
338 tabid
->revision
!= SSB_ANY_REV
)
343 static int ssb_bus_match(struct device
*dev
, struct device_driver
*drv
)
345 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
346 struct ssb_driver
*ssb_drv
= drv_to_ssb_drv(drv
);
347 const struct ssb_device_id
*id
;
349 for (id
= ssb_drv
->id_table
;
350 id
->vendor
|| id
->coreid
|| id
->revision
;
352 if (ssb_match_devid(id
, &ssb_dev
->id
))
353 return 1; /* found */
359 static int ssb_device_uevent(struct device
*dev
, struct kobj_uevent_env
*env
)
361 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
366 return add_uevent_var(env
,
367 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
368 ssb_dev
->id
.vendor
, ssb_dev
->id
.coreid
,
369 ssb_dev
->id
.revision
);
372 #define ssb_config_attr(attrib, field, format_string) \
374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
379 ssb_config_attr(core_num
, core_index
, "%u\n")
380 ssb_config_attr(coreid
, id
.coreid
, "0x%04x\n")
381 ssb_config_attr(vendor
, id
.vendor
, "0x%04x\n")
382 ssb_config_attr(revision
, id
.revision
, "%u\n")
383 ssb_config_attr(irq
, irq
, "%u\n")
385 name_show(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
387 return sprintf(buf
, "%s\n",
388 ssb_core_name(dev_to_ssb_dev(dev
)->id
.coreid
));
391 static struct device_attribute ssb_device_attrs
[] = {
401 static struct bus_type ssb_bustype
= {
403 .match
= ssb_bus_match
,
404 .probe
= ssb_device_probe
,
405 .remove
= ssb_device_remove
,
406 .shutdown
= ssb_device_shutdown
,
407 .suspend
= ssb_device_suspend
,
408 .resume
= ssb_device_resume
,
409 .uevent
= ssb_device_uevent
,
410 .dev_attrs
= ssb_device_attrs
,
413 static void ssb_buses_lock(void)
415 /* See the comment at the ssb_is_early_boot definition */
416 if (!ssb_is_early_boot
)
417 mutex_lock(&buses_mutex
);
420 static void ssb_buses_unlock(void)
422 /* See the comment at the ssb_is_early_boot definition */
423 if (!ssb_is_early_boot
)
424 mutex_unlock(&buses_mutex
);
427 static void ssb_devices_unregister(struct ssb_bus
*bus
)
429 struct ssb_device
*sdev
;
432 for (i
= bus
->nr_devices
- 1; i
>= 0; i
--) {
433 sdev
= &(bus
->devices
[i
]);
435 device_unregister(sdev
->dev
);
438 #ifdef CONFIG_SSB_EMBEDDED
439 if (bus
->bustype
== SSB_BUSTYPE_SSB
)
440 platform_device_unregister(bus
->watchdog
);
444 void ssb_bus_unregister(struct ssb_bus
*bus
)
447 ssb_devices_unregister(bus
);
448 list_del(&bus
->list
);
451 ssb_pcmcia_exit(bus
);
455 EXPORT_SYMBOL(ssb_bus_unregister
);
457 static void ssb_release_dev(struct device
*dev
)
459 struct __ssb_dev_wrapper
*devwrap
;
461 devwrap
= container_of(dev
, struct __ssb_dev_wrapper
, dev
);
465 static int ssb_devices_register(struct ssb_bus
*bus
)
467 struct ssb_device
*sdev
;
469 struct __ssb_dev_wrapper
*devwrap
;
473 for (i
= 0; i
< bus
->nr_devices
; i
++) {
474 sdev
= &(bus
->devices
[i
]);
476 /* We don't register SSB-system devices to the kernel,
477 * as the drivers for them are built into SSB. */
478 switch (sdev
->id
.coreid
) {
479 case SSB_DEV_CHIPCOMMON
:
484 case SSB_DEV_MIPS_3302
:
489 devwrap
= kzalloc(sizeof(*devwrap
), GFP_KERNEL
);
491 ssb_printk(KERN_ERR PFX
492 "Could not allocate device\n");
497 devwrap
->sdev
= sdev
;
499 dev
->release
= ssb_release_dev
;
500 dev
->bus
= &ssb_bustype
;
501 dev_set_name(dev
, "ssb%u:%d", bus
->busnumber
, dev_idx
);
503 switch (bus
->bustype
) {
504 case SSB_BUSTYPE_PCI
:
505 #ifdef CONFIG_SSB_PCIHOST
506 sdev
->irq
= bus
->host_pci
->irq
;
507 dev
->parent
= &bus
->host_pci
->dev
;
508 sdev
->dma_dev
= dev
->parent
;
511 case SSB_BUSTYPE_PCMCIA
:
512 #ifdef CONFIG_SSB_PCMCIAHOST
513 sdev
->irq
= bus
->host_pcmcia
->irq
;
514 dev
->parent
= &bus
->host_pcmcia
->dev
;
517 case SSB_BUSTYPE_SDIO
:
518 #ifdef CONFIG_SSB_SDIOHOST
519 dev
->parent
= &bus
->host_sdio
->dev
;
522 case SSB_BUSTYPE_SSB
:
523 dev
->dma_mask
= &dev
->coherent_dma_mask
;
529 err
= device_register(dev
);
531 ssb_printk(KERN_ERR PFX
532 "Could not register %s\n",
534 /* Set dev to NULL to not unregister
535 * dev on error unwinding. */
545 /* Unwind the already registered devices. */
546 ssb_devices_unregister(bus
);
550 /* Needs ssb_buses_lock() */
551 static int ssb_attach_queued_buses(void)
553 struct ssb_bus
*bus
, *n
;
555 int drop_them_all
= 0;
557 list_for_each_entry_safe(bus
, n
, &attach_queue
, list
) {
559 list_del(&bus
->list
);
562 /* Can't init the PCIcore in ssb_bus_register(), as that
563 * is too early in boot for embedded systems
564 * (no udelay() available). So do it here in attach stage.
566 err
= ssb_bus_powerup(bus
, 0);
569 ssb_pcicore_init(&bus
->pcicore
);
570 if (bus
->bustype
== SSB_BUSTYPE_SSB
)
571 ssb_watchdog_register(bus
);
572 ssb_bus_may_powerdown(bus
);
574 err
= ssb_devices_register(bus
);
578 list_del(&bus
->list
);
581 list_move_tail(&bus
->list
, &buses
);
587 static u8
ssb_ssb_read8(struct ssb_device
*dev
, u16 offset
)
589 struct ssb_bus
*bus
= dev
->bus
;
591 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
592 return readb(bus
->mmio
+ offset
);
595 static u16
ssb_ssb_read16(struct ssb_device
*dev
, u16 offset
)
597 struct ssb_bus
*bus
= dev
->bus
;
599 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
600 return readw(bus
->mmio
+ offset
);
603 static u32
ssb_ssb_read32(struct ssb_device
*dev
, u16 offset
)
605 struct ssb_bus
*bus
= dev
->bus
;
607 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
608 return readl(bus
->mmio
+ offset
);
611 #ifdef CONFIG_SSB_BLOCKIO
612 static void ssb_ssb_block_read(struct ssb_device
*dev
, void *buffer
,
613 size_t count
, u16 offset
, u8 reg_width
)
615 struct ssb_bus
*bus
= dev
->bus
;
618 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
619 addr
= bus
->mmio
+ offset
;
626 *buf
= __raw_readb(addr
);
633 __le16
*buf
= buffer
;
635 SSB_WARN_ON(count
& 1);
637 *buf
= (__force __le16
)__raw_readw(addr
);
644 __le32
*buf
= buffer
;
646 SSB_WARN_ON(count
& 3);
648 *buf
= (__force __le32
)__raw_readl(addr
);
658 #endif /* CONFIG_SSB_BLOCKIO */
660 static void ssb_ssb_write8(struct ssb_device
*dev
, u16 offset
, u8 value
)
662 struct ssb_bus
*bus
= dev
->bus
;
664 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
665 writeb(value
, bus
->mmio
+ offset
);
668 static void ssb_ssb_write16(struct ssb_device
*dev
, u16 offset
, u16 value
)
670 struct ssb_bus
*bus
= dev
->bus
;
672 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
673 writew(value
, bus
->mmio
+ offset
);
676 static void ssb_ssb_write32(struct ssb_device
*dev
, u16 offset
, u32 value
)
678 struct ssb_bus
*bus
= dev
->bus
;
680 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
681 writel(value
, bus
->mmio
+ offset
);
684 #ifdef CONFIG_SSB_BLOCKIO
685 static void ssb_ssb_block_write(struct ssb_device
*dev
, const void *buffer
,
686 size_t count
, u16 offset
, u8 reg_width
)
688 struct ssb_bus
*bus
= dev
->bus
;
691 offset
+= dev
->core_index
* SSB_CORE_SIZE
;
692 addr
= bus
->mmio
+ offset
;
696 const u8
*buf
= buffer
;
699 __raw_writeb(*buf
, addr
);
706 const __le16
*buf
= buffer
;
708 SSB_WARN_ON(count
& 1);
710 __raw_writew((__force u16
)(*buf
), addr
);
717 const __le32
*buf
= buffer
;
719 SSB_WARN_ON(count
& 3);
721 __raw_writel((__force u32
)(*buf
), addr
);
731 #endif /* CONFIG_SSB_BLOCKIO */
733 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
734 static const struct ssb_bus_ops ssb_ssb_ops
= {
735 .read8
= ssb_ssb_read8
,
736 .read16
= ssb_ssb_read16
,
737 .read32
= ssb_ssb_read32
,
738 .write8
= ssb_ssb_write8
,
739 .write16
= ssb_ssb_write16
,
740 .write32
= ssb_ssb_write32
,
741 #ifdef CONFIG_SSB_BLOCKIO
742 .block_read
= ssb_ssb_block_read
,
743 .block_write
= ssb_ssb_block_write
,
747 static int ssb_fetch_invariants(struct ssb_bus
*bus
,
748 ssb_invariants_func_t get_invariants
)
750 struct ssb_init_invariants iv
;
753 memset(&iv
, 0, sizeof(iv
));
754 err
= get_invariants(bus
, &iv
);
757 memcpy(&bus
->boardinfo
, &iv
.boardinfo
, sizeof(iv
.boardinfo
));
758 memcpy(&bus
->sprom
, &iv
.sprom
, sizeof(iv
.sprom
));
759 bus
->has_cardbus_slot
= iv
.has_cardbus_slot
;
764 static int ssb_bus_register(struct ssb_bus
*bus
,
765 ssb_invariants_func_t get_invariants
,
766 unsigned long baseaddr
)
770 spin_lock_init(&bus
->bar_lock
);
771 INIT_LIST_HEAD(&bus
->list
);
772 #ifdef CONFIG_SSB_EMBEDDED
773 spin_lock_init(&bus
->gpio_lock
);
776 /* Powerup the bus */
777 err
= ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 1);
781 /* Init SDIO-host device (if any), before the scan */
782 err
= ssb_sdio_init(bus
);
784 goto err_disable_xtal
;
787 bus
->busnumber
= next_busnumber
;
788 /* Scan for devices (cores) */
789 err
= ssb_bus_scan(bus
, baseaddr
);
793 /* Init PCI-host device (if any) */
794 err
= ssb_pci_init(bus
);
797 /* Init PCMCIA-host device (if any) */
798 err
= ssb_pcmcia_init(bus
);
802 /* Initialize basic system devices (if available) */
803 err
= ssb_bus_powerup(bus
, 0);
805 goto err_pcmcia_exit
;
806 ssb_chipcommon_init(&bus
->chipco
);
807 ssb_extif_init(&bus
->extif
);
808 ssb_mipscore_init(&bus
->mipscore
);
809 err
= ssb_gpio_init(bus
);
810 if (err
== -ENOTSUPP
)
811 ssb_dprintk(KERN_DEBUG PFX
"GPIO driver not activated\n");
813 ssb_dprintk(KERN_ERR PFX
814 "Error registering GPIO driver: %i\n", err
);
815 err
= ssb_fetch_invariants(bus
, get_invariants
);
817 ssb_bus_may_powerdown(bus
);
818 goto err_pcmcia_exit
;
820 ssb_bus_may_powerdown(bus
);
822 /* Queue it for attach.
823 * See the comment at the ssb_is_early_boot definition. */
824 list_add_tail(&bus
->list
, &attach_queue
);
825 if (!ssb_is_early_boot
) {
826 /* This is not early boot, so we must attach the bus now */
827 err
= ssb_attach_queued_buses();
838 list_del(&bus
->list
);
840 ssb_pcmcia_exit(bus
);
849 ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 0);
853 #ifdef CONFIG_SSB_PCIHOST
854 int ssb_bus_pcibus_register(struct ssb_bus
*bus
, struct pci_dev
*host_pci
)
858 bus
->bustype
= SSB_BUSTYPE_PCI
;
859 bus
->host_pci
= host_pci
;
860 bus
->ops
= &ssb_pci_ops
;
862 err
= ssb_bus_register(bus
, ssb_pci_get_invariants
, 0);
864 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found on "
865 "PCI device %s\n", dev_name(&host_pci
->dev
));
867 ssb_printk(KERN_ERR PFX
"Failed to register PCI version"
868 " of SSB with error %d\n", err
);
873 EXPORT_SYMBOL(ssb_bus_pcibus_register
);
874 #endif /* CONFIG_SSB_PCIHOST */
876 #ifdef CONFIG_SSB_PCMCIAHOST
877 int ssb_bus_pcmciabus_register(struct ssb_bus
*bus
,
878 struct pcmcia_device
*pcmcia_dev
,
879 unsigned long baseaddr
)
883 bus
->bustype
= SSB_BUSTYPE_PCMCIA
;
884 bus
->host_pcmcia
= pcmcia_dev
;
885 bus
->ops
= &ssb_pcmcia_ops
;
887 err
= ssb_bus_register(bus
, ssb_pcmcia_get_invariants
, baseaddr
);
889 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found on "
890 "PCMCIA device %s\n", pcmcia_dev
->devname
);
895 EXPORT_SYMBOL(ssb_bus_pcmciabus_register
);
896 #endif /* CONFIG_SSB_PCMCIAHOST */
898 #ifdef CONFIG_SSB_SDIOHOST
899 int ssb_bus_sdiobus_register(struct ssb_bus
*bus
, struct sdio_func
*func
,
904 bus
->bustype
= SSB_BUSTYPE_SDIO
;
905 bus
->host_sdio
= func
;
906 bus
->ops
= &ssb_sdio_ops
;
907 bus
->quirks
= quirks
;
909 err
= ssb_bus_register(bus
, ssb_sdio_get_invariants
, ~0);
911 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found on "
912 "SDIO device %s\n", sdio_func_id(func
));
917 EXPORT_SYMBOL(ssb_bus_sdiobus_register
);
918 #endif /* CONFIG_SSB_PCMCIAHOST */
920 int ssb_bus_ssbbus_register(struct ssb_bus
*bus
, unsigned long baseaddr
,
921 ssb_invariants_func_t get_invariants
)
925 bus
->bustype
= SSB_BUSTYPE_SSB
;
926 bus
->ops
= &ssb_ssb_ops
;
928 err
= ssb_bus_register(bus
, get_invariants
, baseaddr
);
930 ssb_printk(KERN_INFO PFX
"Sonics Silicon Backplane found at "
931 "address 0x%08lX\n", baseaddr
);
937 int __ssb_driver_register(struct ssb_driver
*drv
, struct module
*owner
)
939 drv
->drv
.name
= drv
->name
;
940 drv
->drv
.bus
= &ssb_bustype
;
941 drv
->drv
.owner
= owner
;
943 return driver_register(&drv
->drv
);
945 EXPORT_SYMBOL(__ssb_driver_register
);
947 void ssb_driver_unregister(struct ssb_driver
*drv
)
949 driver_unregister(&drv
->drv
);
951 EXPORT_SYMBOL(ssb_driver_unregister
);
953 void ssb_set_devtypedata(struct ssb_device
*dev
, void *data
)
955 struct ssb_bus
*bus
= dev
->bus
;
956 struct ssb_device
*ent
;
959 for (i
= 0; i
< bus
->nr_devices
; i
++) {
960 ent
= &(bus
->devices
[i
]);
961 if (ent
->id
.vendor
!= dev
->id
.vendor
)
963 if (ent
->id
.coreid
!= dev
->id
.coreid
)
966 ent
->devtypedata
= data
;
969 EXPORT_SYMBOL(ssb_set_devtypedata
);
971 static u32
clkfactor_f6_resolve(u32 v
)
973 /* map the magic values */
975 case SSB_CHIPCO_CLK_F6_2
:
977 case SSB_CHIPCO_CLK_F6_3
:
979 case SSB_CHIPCO_CLK_F6_4
:
981 case SSB_CHIPCO_CLK_F6_5
:
983 case SSB_CHIPCO_CLK_F6_6
:
985 case SSB_CHIPCO_CLK_F6_7
:
991 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
992 u32
ssb_calc_clock_rate(u32 plltype
, u32 n
, u32 m
)
994 u32 n1
, n2
, clock
, m1
, m2
, m3
, mc
;
996 n1
= (n
& SSB_CHIPCO_CLK_N1
);
997 n2
= ((n
& SSB_CHIPCO_CLK_N2
) >> SSB_CHIPCO_CLK_N2_SHIFT
);
1000 case SSB_PLLTYPE_6
: /* 100/200 or 120/240 only */
1001 if (m
& SSB_CHIPCO_CLK_T6_MMASK
)
1002 return SSB_CHIPCO_CLK_T6_M1
;
1003 return SSB_CHIPCO_CLK_T6_M0
;
1004 case SSB_PLLTYPE_1
: /* 48Mhz base, 3 dividers */
1005 case SSB_PLLTYPE_3
: /* 25Mhz, 2 dividers */
1006 case SSB_PLLTYPE_4
: /* 48Mhz, 4 dividers */
1007 case SSB_PLLTYPE_7
: /* 25Mhz, 4 dividers */
1008 n1
= clkfactor_f6_resolve(n1
);
1009 n2
+= SSB_CHIPCO_CLK_F5_BIAS
;
1011 case SSB_PLLTYPE_2
: /* 48Mhz, 4 dividers */
1012 n1
+= SSB_CHIPCO_CLK_T2_BIAS
;
1013 n2
+= SSB_CHIPCO_CLK_T2_BIAS
;
1014 SSB_WARN_ON(!((n1
>= 2) && (n1
<= 7)));
1015 SSB_WARN_ON(!((n2
>= 5) && (n2
<= 23)));
1017 case SSB_PLLTYPE_5
: /* 25Mhz, 4 dividers */
1024 case SSB_PLLTYPE_3
: /* 25Mhz, 2 dividers */
1025 case SSB_PLLTYPE_7
: /* 25Mhz, 4 dividers */
1026 clock
= SSB_CHIPCO_CLK_BASE2
* n1
* n2
;
1029 clock
= SSB_CHIPCO_CLK_BASE1
* n1
* n2
;
1034 m1
= (m
& SSB_CHIPCO_CLK_M1
);
1035 m2
= ((m
& SSB_CHIPCO_CLK_M2
) >> SSB_CHIPCO_CLK_M2_SHIFT
);
1036 m3
= ((m
& SSB_CHIPCO_CLK_M3
) >> SSB_CHIPCO_CLK_M3_SHIFT
);
1037 mc
= ((m
& SSB_CHIPCO_CLK_MC
) >> SSB_CHIPCO_CLK_MC_SHIFT
);
1040 case SSB_PLLTYPE_1
: /* 48Mhz base, 3 dividers */
1041 case SSB_PLLTYPE_3
: /* 25Mhz, 2 dividers */
1042 case SSB_PLLTYPE_4
: /* 48Mhz, 4 dividers */
1043 case SSB_PLLTYPE_7
: /* 25Mhz, 4 dividers */
1044 m1
= clkfactor_f6_resolve(m1
);
1045 if ((plltype
== SSB_PLLTYPE_1
) ||
1046 (plltype
== SSB_PLLTYPE_3
))
1047 m2
+= SSB_CHIPCO_CLK_F5_BIAS
;
1049 m2
= clkfactor_f6_resolve(m2
);
1050 m3
= clkfactor_f6_resolve(m3
);
1053 case SSB_CHIPCO_CLK_MC_BYPASS
:
1055 case SSB_CHIPCO_CLK_MC_M1
:
1056 return (clock
/ m1
);
1057 case SSB_CHIPCO_CLK_MC_M1M2
:
1058 return (clock
/ (m1
* m2
));
1059 case SSB_CHIPCO_CLK_MC_M1M2M3
:
1060 return (clock
/ (m1
* m2
* m3
));
1061 case SSB_CHIPCO_CLK_MC_M1M3
:
1062 return (clock
/ (m1
* m3
));
1066 m1
+= SSB_CHIPCO_CLK_T2_BIAS
;
1067 m2
+= SSB_CHIPCO_CLK_T2M2_BIAS
;
1068 m3
+= SSB_CHIPCO_CLK_T2_BIAS
;
1069 SSB_WARN_ON(!((m1
>= 2) && (m1
<= 7)));
1070 SSB_WARN_ON(!((m2
>= 3) && (m2
<= 10)));
1071 SSB_WARN_ON(!((m3
>= 2) && (m3
<= 7)));
1073 if (!(mc
& SSB_CHIPCO_CLK_T2MC_M1BYP
))
1075 if (!(mc
& SSB_CHIPCO_CLK_T2MC_M2BYP
))
1077 if (!(mc
& SSB_CHIPCO_CLK_T2MC_M3BYP
))
1086 /* Get the current speed the backplane is running at */
1087 u32
ssb_clockspeed(struct ssb_bus
*bus
)
1091 u32 clkctl_n
, clkctl_m
;
1093 if (bus
->chipco
.capabilities
& SSB_CHIPCO_CAP_PMU
)
1094 return ssb_pmu_get_controlclock(&bus
->chipco
);
1096 if (ssb_extif_available(&bus
->extif
))
1097 ssb_extif_get_clockcontrol(&bus
->extif
, &plltype
,
1098 &clkctl_n
, &clkctl_m
);
1099 else if (bus
->chipco
.dev
)
1100 ssb_chipco_get_clockcontrol(&bus
->chipco
, &plltype
,
1101 &clkctl_n
, &clkctl_m
);
1105 if (bus
->chip_id
== 0x5365) {
1108 rate
= ssb_calc_clock_rate(plltype
, clkctl_n
, clkctl_m
);
1109 if (plltype
== SSB_PLLTYPE_3
) /* 25Mhz, 2 dividers */
1115 EXPORT_SYMBOL(ssb_clockspeed
);
1117 static u32
ssb_tmslow_reject_bitmask(struct ssb_device
*dev
)
1119 u32 rev
= ssb_read32(dev
, SSB_IDLOW
) & SSB_IDLOW_SSBREV
;
1121 /* The REJECT bit seems to be different for Backplane rev 2.3 */
1123 case SSB_IDLOW_SSBREV_22
:
1124 case SSB_IDLOW_SSBREV_24
:
1125 case SSB_IDLOW_SSBREV_26
:
1126 return SSB_TMSLOW_REJECT
;
1127 case SSB_IDLOW_SSBREV_23
:
1128 return SSB_TMSLOW_REJECT_23
;
1129 case SSB_IDLOW_SSBREV_25
: /* TODO - find the proper REJECT bit */
1130 case SSB_IDLOW_SSBREV_27
: /* same here */
1131 return SSB_TMSLOW_REJECT
; /* this is a guess */
1133 WARN(1, KERN_INFO
"ssb: Backplane Revision 0x%.8X\n", rev
);
1135 return (SSB_TMSLOW_REJECT
| SSB_TMSLOW_REJECT_23
);
1138 int ssb_device_is_enabled(struct ssb_device
*dev
)
1143 reject
= ssb_tmslow_reject_bitmask(dev
);
1144 val
= ssb_read32(dev
, SSB_TMSLOW
);
1145 val
&= SSB_TMSLOW_CLOCK
| SSB_TMSLOW_RESET
| reject
;
1147 return (val
== SSB_TMSLOW_CLOCK
);
1149 EXPORT_SYMBOL(ssb_device_is_enabled
);
1151 static void ssb_flush_tmslow(struct ssb_device
*dev
)
1153 /* Make _really_ sure the device has finished the TMSLOW
1154 * register write transaction, as we risk running into
1155 * a machine check exception otherwise.
1156 * Do this by reading the register back to commit the
1157 * PCI write and delay an additional usec for the device
1158 * to react to the change. */
1159 ssb_read32(dev
, SSB_TMSLOW
);
1163 void ssb_device_enable(struct ssb_device
*dev
, u32 core_specific_flags
)
1167 ssb_device_disable(dev
, core_specific_flags
);
1168 ssb_write32(dev
, SSB_TMSLOW
,
1169 SSB_TMSLOW_RESET
| SSB_TMSLOW_CLOCK
|
1170 SSB_TMSLOW_FGC
| core_specific_flags
);
1171 ssb_flush_tmslow(dev
);
1173 /* Clear SERR if set. This is a hw bug workaround. */
1174 if (ssb_read32(dev
, SSB_TMSHIGH
) & SSB_TMSHIGH_SERR
)
1175 ssb_write32(dev
, SSB_TMSHIGH
, 0);
1177 val
= ssb_read32(dev
, SSB_IMSTATE
);
1178 if (val
& (SSB_IMSTATE_IBE
| SSB_IMSTATE_TO
)) {
1179 val
&= ~(SSB_IMSTATE_IBE
| SSB_IMSTATE_TO
);
1180 ssb_write32(dev
, SSB_IMSTATE
, val
);
1183 ssb_write32(dev
, SSB_TMSLOW
,
1184 SSB_TMSLOW_CLOCK
| SSB_TMSLOW_FGC
|
1185 core_specific_flags
);
1186 ssb_flush_tmslow(dev
);
1188 ssb_write32(dev
, SSB_TMSLOW
, SSB_TMSLOW_CLOCK
|
1189 core_specific_flags
);
1190 ssb_flush_tmslow(dev
);
1192 EXPORT_SYMBOL(ssb_device_enable
);
1194 /* Wait for bitmask in a register to get set or cleared.
1195 * timeout is in units of ten-microseconds */
1196 static int ssb_wait_bits(struct ssb_device
*dev
, u16 reg
, u32 bitmask
,
1197 int timeout
, int set
)
1202 for (i
= 0; i
< timeout
; i
++) {
1203 val
= ssb_read32(dev
, reg
);
1205 if ((val
& bitmask
) == bitmask
)
1208 if (!(val
& bitmask
))
1213 printk(KERN_ERR PFX
"Timeout waiting for bitmask %08X on "
1214 "register %04X to %s.\n",
1215 bitmask
, reg
, (set
? "set" : "clear"));
1220 void ssb_device_disable(struct ssb_device
*dev
, u32 core_specific_flags
)
1224 if (ssb_read32(dev
, SSB_TMSLOW
) & SSB_TMSLOW_RESET
)
1227 reject
= ssb_tmslow_reject_bitmask(dev
);
1229 if (ssb_read32(dev
, SSB_TMSLOW
) & SSB_TMSLOW_CLOCK
) {
1230 ssb_write32(dev
, SSB_TMSLOW
, reject
| SSB_TMSLOW_CLOCK
);
1231 ssb_wait_bits(dev
, SSB_TMSLOW
, reject
, 1000, 1);
1232 ssb_wait_bits(dev
, SSB_TMSHIGH
, SSB_TMSHIGH_BUSY
, 1000, 0);
1234 if (ssb_read32(dev
, SSB_IDLOW
) & SSB_IDLOW_INITIATOR
) {
1235 val
= ssb_read32(dev
, SSB_IMSTATE
);
1236 val
|= SSB_IMSTATE_REJECT
;
1237 ssb_write32(dev
, SSB_IMSTATE
, val
);
1238 ssb_wait_bits(dev
, SSB_IMSTATE
, SSB_IMSTATE_BUSY
, 1000,
1242 ssb_write32(dev
, SSB_TMSLOW
,
1243 SSB_TMSLOW_FGC
| SSB_TMSLOW_CLOCK
|
1244 reject
| SSB_TMSLOW_RESET
|
1245 core_specific_flags
);
1246 ssb_flush_tmslow(dev
);
1248 if (ssb_read32(dev
, SSB_IDLOW
) & SSB_IDLOW_INITIATOR
) {
1249 val
= ssb_read32(dev
, SSB_IMSTATE
);
1250 val
&= ~SSB_IMSTATE_REJECT
;
1251 ssb_write32(dev
, SSB_IMSTATE
, val
);
1255 ssb_write32(dev
, SSB_TMSLOW
,
1256 reject
| SSB_TMSLOW_RESET
|
1257 core_specific_flags
);
1258 ssb_flush_tmslow(dev
);
1260 EXPORT_SYMBOL(ssb_device_disable
);
1262 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1263 static bool ssb_dma_translation_special_bit(struct ssb_device
*dev
)
1265 u16 chip_id
= dev
->bus
->chip_id
;
1267 if (dev
->id
.coreid
== SSB_DEV_80211
) {
1268 return (chip_id
== 0x4322 || chip_id
== 43221 ||
1269 chip_id
== 43231 || chip_id
== 43222);
1275 u32
ssb_dma_translation(struct ssb_device
*dev
)
1277 switch (dev
->bus
->bustype
) {
1278 case SSB_BUSTYPE_SSB
:
1280 case SSB_BUSTYPE_PCI
:
1281 if (pci_is_pcie(dev
->bus
->host_pci
) &&
1282 ssb_read32(dev
, SSB_TMSHIGH
) & SSB_TMSHIGH_DMA64
) {
1283 return SSB_PCIE_DMA_H32
;
1285 if (ssb_dma_translation_special_bit(dev
))
1286 return SSB_PCIE_DMA_H32
;
1291 __ssb_dma_not_implemented(dev
);
1295 EXPORT_SYMBOL(ssb_dma_translation
);
1297 int ssb_bus_may_powerdown(struct ssb_bus
*bus
)
1299 struct ssb_chipcommon
*cc
;
1302 /* On buses where more than one core may be working
1303 * at a time, we must not powerdown stuff if there are
1304 * still cores that may want to run. */
1305 if (bus
->bustype
== SSB_BUSTYPE_SSB
)
1312 if (cc
->dev
->id
.revision
< 5)
1315 ssb_chipco_set_clockmode(cc
, SSB_CLKMODE_SLOW
);
1316 err
= ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 0);
1320 #ifdef CONFIG_SSB_DEBUG
1321 bus
->powered_up
= 0;
1325 ssb_printk(KERN_ERR PFX
"Bus powerdown failed\n");
1328 EXPORT_SYMBOL(ssb_bus_may_powerdown
);
1330 int ssb_bus_powerup(struct ssb_bus
*bus
, bool dynamic_pctl
)
1333 enum ssb_clkmode mode
;
1335 err
= ssb_pci_xtal(bus
, SSB_GPIO_XTAL
| SSB_GPIO_PLL
, 1);
1339 #ifdef CONFIG_SSB_DEBUG
1340 bus
->powered_up
= 1;
1343 mode
= dynamic_pctl
? SSB_CLKMODE_DYNAMIC
: SSB_CLKMODE_FAST
;
1344 ssb_chipco_set_clockmode(&bus
->chipco
, mode
);
1348 ssb_printk(KERN_ERR PFX
"Bus powerup failed\n");
1351 EXPORT_SYMBOL(ssb_bus_powerup
);
1353 static void ssb_broadcast_value(struct ssb_device
*dev
,
1354 u32 address
, u32 data
)
1356 #ifdef CONFIG_SSB_DRIVER_PCICORE
1357 /* This is used for both, PCI and ChipCommon core, so be careful. */
1358 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR
!= SSB_CHIPCO_BCAST_ADDR
);
1359 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA
!= SSB_CHIPCO_BCAST_DATA
);
1362 ssb_write32(dev
, SSB_CHIPCO_BCAST_ADDR
, address
);
1363 ssb_read32(dev
, SSB_CHIPCO_BCAST_ADDR
); /* flush */
1364 ssb_write32(dev
, SSB_CHIPCO_BCAST_DATA
, data
);
1365 ssb_read32(dev
, SSB_CHIPCO_BCAST_DATA
); /* flush */
1368 void ssb_commit_settings(struct ssb_bus
*bus
)
1370 struct ssb_device
*dev
;
1372 #ifdef CONFIG_SSB_DRIVER_PCICORE
1373 dev
= bus
->chipco
.dev
? bus
->chipco
.dev
: bus
->pcicore
.dev
;
1375 dev
= bus
->chipco
.dev
;
1379 /* This forces an update of the cached registers. */
1380 ssb_broadcast_value(dev
, 0xFD8, 0);
1382 EXPORT_SYMBOL(ssb_commit_settings
);
1384 u32
ssb_admatch_base(u32 adm
)
1388 switch (adm
& SSB_ADM_TYPE
) {
1390 base
= (adm
& SSB_ADM_BASE0
);
1393 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1394 base
= (adm
& SSB_ADM_BASE1
);
1397 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1398 base
= (adm
& SSB_ADM_BASE2
);
1406 EXPORT_SYMBOL(ssb_admatch_base
);
1408 u32
ssb_admatch_size(u32 adm
)
1412 switch (adm
& SSB_ADM_TYPE
) {
1414 size
= ((adm
& SSB_ADM_SZ0
) >> SSB_ADM_SZ0_SHIFT
);
1417 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1418 size
= ((adm
& SSB_ADM_SZ1
) >> SSB_ADM_SZ1_SHIFT
);
1421 SSB_WARN_ON(adm
& SSB_ADM_NEG
); /* unsupported */
1422 size
= ((adm
& SSB_ADM_SZ2
) >> SSB_ADM_SZ2_SHIFT
);
1427 size
= (1 << (size
+ 1));
1431 EXPORT_SYMBOL(ssb_admatch_size
);
1433 static int __init
ssb_modinit(void)
1437 /* See the comment at the ssb_is_early_boot definition */
1438 ssb_is_early_boot
= 0;
1439 err
= bus_register(&ssb_bustype
);
1443 /* Maybe we already registered some buses at early boot.
1444 * Check for this and attach them
1447 err
= ssb_attach_queued_buses();
1450 bus_unregister(&ssb_bustype
);
1454 err
= b43_pci_ssb_bridge_init();
1456 ssb_printk(KERN_ERR
"Broadcom 43xx PCI-SSB-bridge "
1457 "initialization failed\n");
1458 /* don't fail SSB init because of this */
1461 err
= ssb_gige_init();
1463 ssb_printk(KERN_ERR
"SSB Broadcom Gigabit Ethernet "
1464 "driver initialization failed\n");
1465 /* don't fail SSB init because of this */
1471 /* ssb must be initialized after PCI but before the ssb drivers.
1472 * That means we must use some initcall between subsys_initcall
1473 * and device_initcall. */
1474 fs_initcall(ssb_modinit
);
1476 static void __exit
ssb_modexit(void)
1479 b43_pci_ssb_bridge_exit();
1480 bus_unregister(&ssb_bustype
);
1482 module_exit(ssb_modexit
)