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Merge branch 'slab/next' into slab/for-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ssb / main.c
1 /*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include "ssb_private.h"
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pci.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/slab.h>
24
25 #include <pcmcia/cistpl.h>
26 #include <pcmcia/ds.h>
27
28
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
31
32
33 /* Temporary list of yet-to-be-attached buses */
34 static LIST_HEAD(attach_queue);
35 /* List if running buses */
36 static LIST_HEAD(buses);
37 /* Software ID counter */
38 static unsigned int next_busnumber;
39 /* buses_mutes locks the two buslists and the next_busnumber.
40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41 static DEFINE_MUTEX(buses_mutex);
42
43 /* There are differences in the codeflow, if the bus is
44 * initialized from early boot, as various needed services
45 * are not available early. This is a mechanism to delay
46 * these initializations to after early boot has finished.
47 * It's also used to avoid mutex locking, as that's not
48 * available and needed early. */
49 static bool ssb_is_early_boot = 1;
50
51 static void ssb_buses_lock(void);
52 static void ssb_buses_unlock(void);
53
54
55 #ifdef CONFIG_SSB_PCIHOST
56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
57 {
58 struct ssb_bus *bus;
59
60 ssb_buses_lock();
61 list_for_each_entry(bus, &buses, list) {
62 if (bus->bustype == SSB_BUSTYPE_PCI &&
63 bus->host_pci == pdev)
64 goto found;
65 }
66 bus = NULL;
67 found:
68 ssb_buses_unlock();
69
70 return bus;
71 }
72 #endif /* CONFIG_SSB_PCIHOST */
73
74 #ifdef CONFIG_SSB_PCMCIAHOST
75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
76 {
77 struct ssb_bus *bus;
78
79 ssb_buses_lock();
80 list_for_each_entry(bus, &buses, list) {
81 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
82 bus->host_pcmcia == pdev)
83 goto found;
84 }
85 bus = NULL;
86 found:
87 ssb_buses_unlock();
88
89 return bus;
90 }
91 #endif /* CONFIG_SSB_PCMCIAHOST */
92
93 #ifdef CONFIG_SSB_SDIOHOST
94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
95 {
96 struct ssb_bus *bus;
97
98 ssb_buses_lock();
99 list_for_each_entry(bus, &buses, list) {
100 if (bus->bustype == SSB_BUSTYPE_SDIO &&
101 bus->host_sdio == func)
102 goto found;
103 }
104 bus = NULL;
105 found:
106 ssb_buses_unlock();
107
108 return bus;
109 }
110 #endif /* CONFIG_SSB_SDIOHOST */
111
112 int ssb_for_each_bus_call(unsigned long data,
113 int (*func)(struct ssb_bus *bus, unsigned long data))
114 {
115 struct ssb_bus *bus;
116 int res;
117
118 ssb_buses_lock();
119 list_for_each_entry(bus, &buses, list) {
120 res = func(bus, data);
121 if (res >= 0) {
122 ssb_buses_unlock();
123 return res;
124 }
125 }
126 ssb_buses_unlock();
127
128 return -ENODEV;
129 }
130
131 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
132 {
133 if (dev)
134 get_device(dev->dev);
135 return dev;
136 }
137
138 static void ssb_device_put(struct ssb_device *dev)
139 {
140 if (dev)
141 put_device(dev->dev);
142 }
143
144 static int ssb_device_resume(struct device *dev)
145 {
146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
147 struct ssb_driver *ssb_drv;
148 int err = 0;
149
150 if (dev->driver) {
151 ssb_drv = drv_to_ssb_drv(dev->driver);
152 if (ssb_drv && ssb_drv->resume)
153 err = ssb_drv->resume(ssb_dev);
154 if (err)
155 goto out;
156 }
157 out:
158 return err;
159 }
160
161 static int ssb_device_suspend(struct device *dev, pm_message_t state)
162 {
163 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
164 struct ssb_driver *ssb_drv;
165 int err = 0;
166
167 if (dev->driver) {
168 ssb_drv = drv_to_ssb_drv(dev->driver);
169 if (ssb_drv && ssb_drv->suspend)
170 err = ssb_drv->suspend(ssb_dev, state);
171 if (err)
172 goto out;
173 }
174 out:
175 return err;
176 }
177
178 int ssb_bus_resume(struct ssb_bus *bus)
179 {
180 int err;
181
182 /* Reset HW state information in memory, so that HW is
183 * completely reinitialized. */
184 bus->mapped_device = NULL;
185 #ifdef CONFIG_SSB_DRIVER_PCICORE
186 bus->pcicore.setup_done = 0;
187 #endif
188
189 err = ssb_bus_powerup(bus, 0);
190 if (err)
191 return err;
192 err = ssb_pcmcia_hardware_setup(bus);
193 if (err) {
194 ssb_bus_may_powerdown(bus);
195 return err;
196 }
197 ssb_chipco_resume(&bus->chipco);
198 ssb_bus_may_powerdown(bus);
199
200 return 0;
201 }
202 EXPORT_SYMBOL(ssb_bus_resume);
203
204 int ssb_bus_suspend(struct ssb_bus *bus)
205 {
206 ssb_chipco_suspend(&bus->chipco);
207 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
208
209 return 0;
210 }
211 EXPORT_SYMBOL(ssb_bus_suspend);
212
213 #ifdef CONFIG_SSB_SPROM
214 /** ssb_devices_freeze - Freeze all devices on the bus.
215 *
216 * After freezing no device driver will be handling a device
217 * on this bus anymore. ssb_devices_thaw() must be called after
218 * a successful freeze to reactivate the devices.
219 *
220 * @bus: The bus.
221 * @ctx: Context structure. Pass this to ssb_devices_thaw().
222 */
223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
224 {
225 struct ssb_device *sdev;
226 struct ssb_driver *sdrv;
227 unsigned int i;
228
229 memset(ctx, 0, sizeof(*ctx));
230 ctx->bus = bus;
231 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
232
233 for (i = 0; i < bus->nr_devices; i++) {
234 sdev = ssb_device_get(&bus->devices[i]);
235
236 if (!sdev->dev || !sdev->dev->driver ||
237 !device_is_registered(sdev->dev)) {
238 ssb_device_put(sdev);
239 continue;
240 }
241 sdrv = drv_to_ssb_drv(sdev->dev->driver);
242 if (SSB_WARN_ON(!sdrv->remove))
243 continue;
244 sdrv->remove(sdev);
245 ctx->device_frozen[i] = 1;
246 }
247
248 return 0;
249 }
250
251 /** ssb_devices_thaw - Unfreeze all devices on the bus.
252 *
253 * This will re-attach the device drivers and re-init the devices.
254 *
255 * @ctx: The context structure from ssb_devices_freeze()
256 */
257 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
258 {
259 struct ssb_bus *bus = ctx->bus;
260 struct ssb_device *sdev;
261 struct ssb_driver *sdrv;
262 unsigned int i;
263 int err, result = 0;
264
265 for (i = 0; i < bus->nr_devices; i++) {
266 if (!ctx->device_frozen[i])
267 continue;
268 sdev = &bus->devices[i];
269
270 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
271 continue;
272 sdrv = drv_to_ssb_drv(sdev->dev->driver);
273 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
274 continue;
275
276 err = sdrv->probe(sdev, &sdev->id);
277 if (err) {
278 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
279 dev_name(sdev->dev));
280 result = err;
281 }
282 ssb_device_put(sdev);
283 }
284
285 return result;
286 }
287 #endif /* CONFIG_SSB_SPROM */
288
289 static void ssb_device_shutdown(struct device *dev)
290 {
291 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
292 struct ssb_driver *ssb_drv;
293
294 if (!dev->driver)
295 return;
296 ssb_drv = drv_to_ssb_drv(dev->driver);
297 if (ssb_drv && ssb_drv->shutdown)
298 ssb_drv->shutdown(ssb_dev);
299 }
300
301 static int ssb_device_remove(struct device *dev)
302 {
303 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
304 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
305
306 if (ssb_drv && ssb_drv->remove)
307 ssb_drv->remove(ssb_dev);
308 ssb_device_put(ssb_dev);
309
310 return 0;
311 }
312
313 static int ssb_device_probe(struct device *dev)
314 {
315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
316 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
317 int err = 0;
318
319 ssb_device_get(ssb_dev);
320 if (ssb_drv && ssb_drv->probe)
321 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
322 if (err)
323 ssb_device_put(ssb_dev);
324
325 return err;
326 }
327
328 static int ssb_match_devid(const struct ssb_device_id *tabid,
329 const struct ssb_device_id *devid)
330 {
331 if ((tabid->vendor != devid->vendor) &&
332 tabid->vendor != SSB_ANY_VENDOR)
333 return 0;
334 if ((tabid->coreid != devid->coreid) &&
335 tabid->coreid != SSB_ANY_ID)
336 return 0;
337 if ((tabid->revision != devid->revision) &&
338 tabid->revision != SSB_ANY_REV)
339 return 0;
340 return 1;
341 }
342
343 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
344 {
345 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
346 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
347 const struct ssb_device_id *id;
348
349 for (id = ssb_drv->id_table;
350 id->vendor || id->coreid || id->revision;
351 id++) {
352 if (ssb_match_devid(id, &ssb_dev->id))
353 return 1; /* found */
354 }
355
356 return 0;
357 }
358
359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
360 {
361 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
362
363 if (!dev)
364 return -ENODEV;
365
366 return add_uevent_var(env,
367 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
368 ssb_dev->id.vendor, ssb_dev->id.coreid,
369 ssb_dev->id.revision);
370 }
371
372 #define ssb_config_attr(attrib, field, format_string) \
373 static ssize_t \
374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
375 { \
376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
377 }
378
379 ssb_config_attr(core_num, core_index, "%u\n")
380 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
381 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
382 ssb_config_attr(revision, id.revision, "%u\n")
383 ssb_config_attr(irq, irq, "%u\n")
384 static ssize_t
385 name_show(struct device *dev, struct device_attribute *attr, char *buf)
386 {
387 return sprintf(buf, "%s\n",
388 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
389 }
390
391 static struct device_attribute ssb_device_attrs[] = {
392 __ATTR_RO(name),
393 __ATTR_RO(core_num),
394 __ATTR_RO(coreid),
395 __ATTR_RO(vendor),
396 __ATTR_RO(revision),
397 __ATTR_RO(irq),
398 __ATTR_NULL,
399 };
400
401 static struct bus_type ssb_bustype = {
402 .name = "ssb",
403 .match = ssb_bus_match,
404 .probe = ssb_device_probe,
405 .remove = ssb_device_remove,
406 .shutdown = ssb_device_shutdown,
407 .suspend = ssb_device_suspend,
408 .resume = ssb_device_resume,
409 .uevent = ssb_device_uevent,
410 .dev_attrs = ssb_device_attrs,
411 };
412
413 static void ssb_buses_lock(void)
414 {
415 /* See the comment at the ssb_is_early_boot definition */
416 if (!ssb_is_early_boot)
417 mutex_lock(&buses_mutex);
418 }
419
420 static void ssb_buses_unlock(void)
421 {
422 /* See the comment at the ssb_is_early_boot definition */
423 if (!ssb_is_early_boot)
424 mutex_unlock(&buses_mutex);
425 }
426
427 static void ssb_devices_unregister(struct ssb_bus *bus)
428 {
429 struct ssb_device *sdev;
430 int i;
431
432 for (i = bus->nr_devices - 1; i >= 0; i--) {
433 sdev = &(bus->devices[i]);
434 if (sdev->dev)
435 device_unregister(sdev->dev);
436 }
437
438 #ifdef CONFIG_SSB_EMBEDDED
439 if (bus->bustype == SSB_BUSTYPE_SSB)
440 platform_device_unregister(bus->watchdog);
441 #endif
442 }
443
444 void ssb_bus_unregister(struct ssb_bus *bus)
445 {
446 int err;
447
448 err = ssb_gpio_unregister(bus);
449 if (err == -EBUSY)
450 ssb_dprintk(KERN_ERR PFX "Some GPIOs are still in use.\n");
451 else if (err)
452 ssb_dprintk(KERN_ERR PFX
453 "Can not unregister GPIO driver: %i\n", err);
454
455 ssb_buses_lock();
456 ssb_devices_unregister(bus);
457 list_del(&bus->list);
458 ssb_buses_unlock();
459
460 ssb_pcmcia_exit(bus);
461 ssb_pci_exit(bus);
462 ssb_iounmap(bus);
463 }
464 EXPORT_SYMBOL(ssb_bus_unregister);
465
466 static void ssb_release_dev(struct device *dev)
467 {
468 struct __ssb_dev_wrapper *devwrap;
469
470 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
471 kfree(devwrap);
472 }
473
474 static int ssb_devices_register(struct ssb_bus *bus)
475 {
476 struct ssb_device *sdev;
477 struct device *dev;
478 struct __ssb_dev_wrapper *devwrap;
479 int i, err = 0;
480 int dev_idx = 0;
481
482 for (i = 0; i < bus->nr_devices; i++) {
483 sdev = &(bus->devices[i]);
484
485 /* We don't register SSB-system devices to the kernel,
486 * as the drivers for them are built into SSB. */
487 switch (sdev->id.coreid) {
488 case SSB_DEV_CHIPCOMMON:
489 case SSB_DEV_PCI:
490 case SSB_DEV_PCIE:
491 case SSB_DEV_PCMCIA:
492 case SSB_DEV_MIPS:
493 case SSB_DEV_MIPS_3302:
494 case SSB_DEV_EXTIF:
495 continue;
496 }
497
498 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
499 if (!devwrap) {
500 ssb_printk(KERN_ERR PFX
501 "Could not allocate device\n");
502 err = -ENOMEM;
503 goto error;
504 }
505 dev = &devwrap->dev;
506 devwrap->sdev = sdev;
507
508 dev->release = ssb_release_dev;
509 dev->bus = &ssb_bustype;
510 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
511
512 switch (bus->bustype) {
513 case SSB_BUSTYPE_PCI:
514 #ifdef CONFIG_SSB_PCIHOST
515 sdev->irq = bus->host_pci->irq;
516 dev->parent = &bus->host_pci->dev;
517 sdev->dma_dev = dev->parent;
518 #endif
519 break;
520 case SSB_BUSTYPE_PCMCIA:
521 #ifdef CONFIG_SSB_PCMCIAHOST
522 sdev->irq = bus->host_pcmcia->irq;
523 dev->parent = &bus->host_pcmcia->dev;
524 #endif
525 break;
526 case SSB_BUSTYPE_SDIO:
527 #ifdef CONFIG_SSB_SDIOHOST
528 dev->parent = &bus->host_sdio->dev;
529 #endif
530 break;
531 case SSB_BUSTYPE_SSB:
532 dev->dma_mask = &dev->coherent_dma_mask;
533 sdev->dma_dev = dev;
534 break;
535 }
536
537 sdev->dev = dev;
538 err = device_register(dev);
539 if (err) {
540 ssb_printk(KERN_ERR PFX
541 "Could not register %s\n",
542 dev_name(dev));
543 /* Set dev to NULL to not unregister
544 * dev on error unwinding. */
545 sdev->dev = NULL;
546 kfree(devwrap);
547 goto error;
548 }
549 dev_idx++;
550 }
551
552 #ifdef CONFIG_SSB_DRIVER_MIPS
553 if (bus->mipscore.pflash.present) {
554 err = platform_device_register(&ssb_pflash_dev);
555 if (err)
556 pr_err("Error registering parallel flash\n");
557 }
558 #endif
559
560 return 0;
561 error:
562 /* Unwind the already registered devices. */
563 ssb_devices_unregister(bus);
564 return err;
565 }
566
567 /* Needs ssb_buses_lock() */
568 static int ssb_attach_queued_buses(void)
569 {
570 struct ssb_bus *bus, *n;
571 int err = 0;
572 int drop_them_all = 0;
573
574 list_for_each_entry_safe(bus, n, &attach_queue, list) {
575 if (drop_them_all) {
576 list_del(&bus->list);
577 continue;
578 }
579 /* Can't init the PCIcore in ssb_bus_register(), as that
580 * is too early in boot for embedded systems
581 * (no udelay() available). So do it here in attach stage.
582 */
583 err = ssb_bus_powerup(bus, 0);
584 if (err)
585 goto error;
586 ssb_pcicore_init(&bus->pcicore);
587 if (bus->bustype == SSB_BUSTYPE_SSB)
588 ssb_watchdog_register(bus);
589 ssb_bus_may_powerdown(bus);
590
591 err = ssb_devices_register(bus);
592 error:
593 if (err) {
594 drop_them_all = 1;
595 list_del(&bus->list);
596 continue;
597 }
598 list_move_tail(&bus->list, &buses);
599 }
600
601 return err;
602 }
603
604 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
605 {
606 struct ssb_bus *bus = dev->bus;
607
608 offset += dev->core_index * SSB_CORE_SIZE;
609 return readb(bus->mmio + offset);
610 }
611
612 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
613 {
614 struct ssb_bus *bus = dev->bus;
615
616 offset += dev->core_index * SSB_CORE_SIZE;
617 return readw(bus->mmio + offset);
618 }
619
620 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
621 {
622 struct ssb_bus *bus = dev->bus;
623
624 offset += dev->core_index * SSB_CORE_SIZE;
625 return readl(bus->mmio + offset);
626 }
627
628 #ifdef CONFIG_SSB_BLOCKIO
629 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
630 size_t count, u16 offset, u8 reg_width)
631 {
632 struct ssb_bus *bus = dev->bus;
633 void __iomem *addr;
634
635 offset += dev->core_index * SSB_CORE_SIZE;
636 addr = bus->mmio + offset;
637
638 switch (reg_width) {
639 case sizeof(u8): {
640 u8 *buf = buffer;
641
642 while (count) {
643 *buf = __raw_readb(addr);
644 buf++;
645 count--;
646 }
647 break;
648 }
649 case sizeof(u16): {
650 __le16 *buf = buffer;
651
652 SSB_WARN_ON(count & 1);
653 while (count) {
654 *buf = (__force __le16)__raw_readw(addr);
655 buf++;
656 count -= 2;
657 }
658 break;
659 }
660 case sizeof(u32): {
661 __le32 *buf = buffer;
662
663 SSB_WARN_ON(count & 3);
664 while (count) {
665 *buf = (__force __le32)__raw_readl(addr);
666 buf++;
667 count -= 4;
668 }
669 break;
670 }
671 default:
672 SSB_WARN_ON(1);
673 }
674 }
675 #endif /* CONFIG_SSB_BLOCKIO */
676
677 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
678 {
679 struct ssb_bus *bus = dev->bus;
680
681 offset += dev->core_index * SSB_CORE_SIZE;
682 writeb(value, bus->mmio + offset);
683 }
684
685 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
686 {
687 struct ssb_bus *bus = dev->bus;
688
689 offset += dev->core_index * SSB_CORE_SIZE;
690 writew(value, bus->mmio + offset);
691 }
692
693 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
694 {
695 struct ssb_bus *bus = dev->bus;
696
697 offset += dev->core_index * SSB_CORE_SIZE;
698 writel(value, bus->mmio + offset);
699 }
700
701 #ifdef CONFIG_SSB_BLOCKIO
702 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
703 size_t count, u16 offset, u8 reg_width)
704 {
705 struct ssb_bus *bus = dev->bus;
706 void __iomem *addr;
707
708 offset += dev->core_index * SSB_CORE_SIZE;
709 addr = bus->mmio + offset;
710
711 switch (reg_width) {
712 case sizeof(u8): {
713 const u8 *buf = buffer;
714
715 while (count) {
716 __raw_writeb(*buf, addr);
717 buf++;
718 count--;
719 }
720 break;
721 }
722 case sizeof(u16): {
723 const __le16 *buf = buffer;
724
725 SSB_WARN_ON(count & 1);
726 while (count) {
727 __raw_writew((__force u16)(*buf), addr);
728 buf++;
729 count -= 2;
730 }
731 break;
732 }
733 case sizeof(u32): {
734 const __le32 *buf = buffer;
735
736 SSB_WARN_ON(count & 3);
737 while (count) {
738 __raw_writel((__force u32)(*buf), addr);
739 buf++;
740 count -= 4;
741 }
742 break;
743 }
744 default:
745 SSB_WARN_ON(1);
746 }
747 }
748 #endif /* CONFIG_SSB_BLOCKIO */
749
750 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
751 static const struct ssb_bus_ops ssb_ssb_ops = {
752 .read8 = ssb_ssb_read8,
753 .read16 = ssb_ssb_read16,
754 .read32 = ssb_ssb_read32,
755 .write8 = ssb_ssb_write8,
756 .write16 = ssb_ssb_write16,
757 .write32 = ssb_ssb_write32,
758 #ifdef CONFIG_SSB_BLOCKIO
759 .block_read = ssb_ssb_block_read,
760 .block_write = ssb_ssb_block_write,
761 #endif
762 };
763
764 static int ssb_fetch_invariants(struct ssb_bus *bus,
765 ssb_invariants_func_t get_invariants)
766 {
767 struct ssb_init_invariants iv;
768 int err;
769
770 memset(&iv, 0, sizeof(iv));
771 err = get_invariants(bus, &iv);
772 if (err)
773 goto out;
774 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
775 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
776 bus->has_cardbus_slot = iv.has_cardbus_slot;
777 out:
778 return err;
779 }
780
781 static int ssb_bus_register(struct ssb_bus *bus,
782 ssb_invariants_func_t get_invariants,
783 unsigned long baseaddr)
784 {
785 int err;
786
787 spin_lock_init(&bus->bar_lock);
788 INIT_LIST_HEAD(&bus->list);
789 #ifdef CONFIG_SSB_EMBEDDED
790 spin_lock_init(&bus->gpio_lock);
791 #endif
792
793 /* Powerup the bus */
794 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
795 if (err)
796 goto out;
797
798 /* Init SDIO-host device (if any), before the scan */
799 err = ssb_sdio_init(bus);
800 if (err)
801 goto err_disable_xtal;
802
803 ssb_buses_lock();
804 bus->busnumber = next_busnumber;
805 /* Scan for devices (cores) */
806 err = ssb_bus_scan(bus, baseaddr);
807 if (err)
808 goto err_sdio_exit;
809
810 /* Init PCI-host device (if any) */
811 err = ssb_pci_init(bus);
812 if (err)
813 goto err_unmap;
814 /* Init PCMCIA-host device (if any) */
815 err = ssb_pcmcia_init(bus);
816 if (err)
817 goto err_pci_exit;
818
819 /* Initialize basic system devices (if available) */
820 err = ssb_bus_powerup(bus, 0);
821 if (err)
822 goto err_pcmcia_exit;
823 ssb_chipcommon_init(&bus->chipco);
824 ssb_extif_init(&bus->extif);
825 ssb_mipscore_init(&bus->mipscore);
826 err = ssb_gpio_init(bus);
827 if (err == -ENOTSUPP)
828 ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
829 else if (err)
830 ssb_dprintk(KERN_ERR PFX
831 "Error registering GPIO driver: %i\n", err);
832 err = ssb_fetch_invariants(bus, get_invariants);
833 if (err) {
834 ssb_bus_may_powerdown(bus);
835 goto err_pcmcia_exit;
836 }
837 ssb_bus_may_powerdown(bus);
838
839 /* Queue it for attach.
840 * See the comment at the ssb_is_early_boot definition. */
841 list_add_tail(&bus->list, &attach_queue);
842 if (!ssb_is_early_boot) {
843 /* This is not early boot, so we must attach the bus now */
844 err = ssb_attach_queued_buses();
845 if (err)
846 goto err_dequeue;
847 }
848 next_busnumber++;
849 ssb_buses_unlock();
850
851 out:
852 return err;
853
854 err_dequeue:
855 list_del(&bus->list);
856 err_pcmcia_exit:
857 ssb_pcmcia_exit(bus);
858 err_pci_exit:
859 ssb_pci_exit(bus);
860 err_unmap:
861 ssb_iounmap(bus);
862 err_sdio_exit:
863 ssb_sdio_exit(bus);
864 err_disable_xtal:
865 ssb_buses_unlock();
866 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
867 return err;
868 }
869
870 #ifdef CONFIG_SSB_PCIHOST
871 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci)
872 {
873 int err;
874
875 bus->bustype = SSB_BUSTYPE_PCI;
876 bus->host_pci = host_pci;
877 bus->ops = &ssb_pci_ops;
878
879 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
880 if (!err) {
881 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
882 "PCI device %s\n", dev_name(&host_pci->dev));
883 } else {
884 ssb_printk(KERN_ERR PFX "Failed to register PCI version"
885 " of SSB with error %d\n", err);
886 }
887
888 return err;
889 }
890 EXPORT_SYMBOL(ssb_bus_pcibus_register);
891 #endif /* CONFIG_SSB_PCIHOST */
892
893 #ifdef CONFIG_SSB_PCMCIAHOST
894 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
895 struct pcmcia_device *pcmcia_dev,
896 unsigned long baseaddr)
897 {
898 int err;
899
900 bus->bustype = SSB_BUSTYPE_PCMCIA;
901 bus->host_pcmcia = pcmcia_dev;
902 bus->ops = &ssb_pcmcia_ops;
903
904 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
905 if (!err) {
906 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
907 "PCMCIA device %s\n", pcmcia_dev->devname);
908 }
909
910 return err;
911 }
912 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
913 #endif /* CONFIG_SSB_PCMCIAHOST */
914
915 #ifdef CONFIG_SSB_SDIOHOST
916 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
917 unsigned int quirks)
918 {
919 int err;
920
921 bus->bustype = SSB_BUSTYPE_SDIO;
922 bus->host_sdio = func;
923 bus->ops = &ssb_sdio_ops;
924 bus->quirks = quirks;
925
926 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
927 if (!err) {
928 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
929 "SDIO device %s\n", sdio_func_id(func));
930 }
931
932 return err;
933 }
934 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
935 #endif /* CONFIG_SSB_PCMCIAHOST */
936
937 int ssb_bus_ssbbus_register(struct ssb_bus *bus, unsigned long baseaddr,
938 ssb_invariants_func_t get_invariants)
939 {
940 int err;
941
942 bus->bustype = SSB_BUSTYPE_SSB;
943 bus->ops = &ssb_ssb_ops;
944
945 err = ssb_bus_register(bus, get_invariants, baseaddr);
946 if (!err) {
947 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
948 "address 0x%08lX\n", baseaddr);
949 }
950
951 return err;
952 }
953
954 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
955 {
956 drv->drv.name = drv->name;
957 drv->drv.bus = &ssb_bustype;
958 drv->drv.owner = owner;
959
960 return driver_register(&drv->drv);
961 }
962 EXPORT_SYMBOL(__ssb_driver_register);
963
964 void ssb_driver_unregister(struct ssb_driver *drv)
965 {
966 driver_unregister(&drv->drv);
967 }
968 EXPORT_SYMBOL(ssb_driver_unregister);
969
970 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
971 {
972 struct ssb_bus *bus = dev->bus;
973 struct ssb_device *ent;
974 int i;
975
976 for (i = 0; i < bus->nr_devices; i++) {
977 ent = &(bus->devices[i]);
978 if (ent->id.vendor != dev->id.vendor)
979 continue;
980 if (ent->id.coreid != dev->id.coreid)
981 continue;
982
983 ent->devtypedata = data;
984 }
985 }
986 EXPORT_SYMBOL(ssb_set_devtypedata);
987
988 static u32 clkfactor_f6_resolve(u32 v)
989 {
990 /* map the magic values */
991 switch (v) {
992 case SSB_CHIPCO_CLK_F6_2:
993 return 2;
994 case SSB_CHIPCO_CLK_F6_3:
995 return 3;
996 case SSB_CHIPCO_CLK_F6_4:
997 return 4;
998 case SSB_CHIPCO_CLK_F6_5:
999 return 5;
1000 case SSB_CHIPCO_CLK_F6_6:
1001 return 6;
1002 case SSB_CHIPCO_CLK_F6_7:
1003 return 7;
1004 }
1005 return 0;
1006 }
1007
1008 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
1009 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
1010 {
1011 u32 n1, n2, clock, m1, m2, m3, mc;
1012
1013 n1 = (n & SSB_CHIPCO_CLK_N1);
1014 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
1015
1016 switch (plltype) {
1017 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1018 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1019 return SSB_CHIPCO_CLK_T6_M1;
1020 return SSB_CHIPCO_CLK_T6_M0;
1021 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1022 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1023 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1024 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1025 n1 = clkfactor_f6_resolve(n1);
1026 n2 += SSB_CHIPCO_CLK_F5_BIAS;
1027 break;
1028 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
1029 n1 += SSB_CHIPCO_CLK_T2_BIAS;
1030 n2 += SSB_CHIPCO_CLK_T2_BIAS;
1031 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
1032 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
1033 break;
1034 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
1035 return 100000000;
1036 default:
1037 SSB_WARN_ON(1);
1038 }
1039
1040 switch (plltype) {
1041 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1042 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1043 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
1044 break;
1045 default:
1046 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1047 }
1048 if (!clock)
1049 return 0;
1050
1051 m1 = (m & SSB_CHIPCO_CLK_M1);
1052 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1053 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1054 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1055
1056 switch (plltype) {
1057 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1058 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1059 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1060 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1061 m1 = clkfactor_f6_resolve(m1);
1062 if ((plltype == SSB_PLLTYPE_1) ||
1063 (plltype == SSB_PLLTYPE_3))
1064 m2 += SSB_CHIPCO_CLK_F5_BIAS;
1065 else
1066 m2 = clkfactor_f6_resolve(m2);
1067 m3 = clkfactor_f6_resolve(m3);
1068
1069 switch (mc) {
1070 case SSB_CHIPCO_CLK_MC_BYPASS:
1071 return clock;
1072 case SSB_CHIPCO_CLK_MC_M1:
1073 return (clock / m1);
1074 case SSB_CHIPCO_CLK_MC_M1M2:
1075 return (clock / (m1 * m2));
1076 case SSB_CHIPCO_CLK_MC_M1M2M3:
1077 return (clock / (m1 * m2 * m3));
1078 case SSB_CHIPCO_CLK_MC_M1M3:
1079 return (clock / (m1 * m3));
1080 }
1081 return 0;
1082 case SSB_PLLTYPE_2:
1083 m1 += SSB_CHIPCO_CLK_T2_BIAS;
1084 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1085 m3 += SSB_CHIPCO_CLK_T2_BIAS;
1086 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1087 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1088 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1089
1090 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1091 clock /= m1;
1092 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1093 clock /= m2;
1094 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1095 clock /= m3;
1096 return clock;
1097 default:
1098 SSB_WARN_ON(1);
1099 }
1100 return 0;
1101 }
1102
1103 /* Get the current speed the backplane is running at */
1104 u32 ssb_clockspeed(struct ssb_bus *bus)
1105 {
1106 u32 rate;
1107 u32 plltype;
1108 u32 clkctl_n, clkctl_m;
1109
1110 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1111 return ssb_pmu_get_controlclock(&bus->chipco);
1112
1113 if (ssb_extif_available(&bus->extif))
1114 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1115 &clkctl_n, &clkctl_m);
1116 else if (bus->chipco.dev)
1117 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1118 &clkctl_n, &clkctl_m);
1119 else
1120 return 0;
1121
1122 if (bus->chip_id == 0x5365) {
1123 rate = 100000000;
1124 } else {
1125 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1126 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1127 rate /= 2;
1128 }
1129
1130 return rate;
1131 }
1132 EXPORT_SYMBOL(ssb_clockspeed);
1133
1134 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1135 {
1136 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1137
1138 /* The REJECT bit seems to be different for Backplane rev 2.3 */
1139 switch (rev) {
1140 case SSB_IDLOW_SSBREV_22:
1141 case SSB_IDLOW_SSBREV_24:
1142 case SSB_IDLOW_SSBREV_26:
1143 return SSB_TMSLOW_REJECT;
1144 case SSB_IDLOW_SSBREV_23:
1145 return SSB_TMSLOW_REJECT_23;
1146 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1147 case SSB_IDLOW_SSBREV_27: /* same here */
1148 return SSB_TMSLOW_REJECT; /* this is a guess */
1149 default:
1150 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1151 }
1152 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1153 }
1154
1155 int ssb_device_is_enabled(struct ssb_device *dev)
1156 {
1157 u32 val;
1158 u32 reject;
1159
1160 reject = ssb_tmslow_reject_bitmask(dev);
1161 val = ssb_read32(dev, SSB_TMSLOW);
1162 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1163
1164 return (val == SSB_TMSLOW_CLOCK);
1165 }
1166 EXPORT_SYMBOL(ssb_device_is_enabled);
1167
1168 static void ssb_flush_tmslow(struct ssb_device *dev)
1169 {
1170 /* Make _really_ sure the device has finished the TMSLOW
1171 * register write transaction, as we risk running into
1172 * a machine check exception otherwise.
1173 * Do this by reading the register back to commit the
1174 * PCI write and delay an additional usec for the device
1175 * to react to the change. */
1176 ssb_read32(dev, SSB_TMSLOW);
1177 udelay(1);
1178 }
1179
1180 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1181 {
1182 u32 val;
1183
1184 ssb_device_disable(dev, core_specific_flags);
1185 ssb_write32(dev, SSB_TMSLOW,
1186 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1187 SSB_TMSLOW_FGC | core_specific_flags);
1188 ssb_flush_tmslow(dev);
1189
1190 /* Clear SERR if set. This is a hw bug workaround. */
1191 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1192 ssb_write32(dev, SSB_TMSHIGH, 0);
1193
1194 val = ssb_read32(dev, SSB_IMSTATE);
1195 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1196 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1197 ssb_write32(dev, SSB_IMSTATE, val);
1198 }
1199
1200 ssb_write32(dev, SSB_TMSLOW,
1201 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1202 core_specific_flags);
1203 ssb_flush_tmslow(dev);
1204
1205 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1206 core_specific_flags);
1207 ssb_flush_tmslow(dev);
1208 }
1209 EXPORT_SYMBOL(ssb_device_enable);
1210
1211 /* Wait for bitmask in a register to get set or cleared.
1212 * timeout is in units of ten-microseconds */
1213 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1214 int timeout, int set)
1215 {
1216 int i;
1217 u32 val;
1218
1219 for (i = 0; i < timeout; i++) {
1220 val = ssb_read32(dev, reg);
1221 if (set) {
1222 if ((val & bitmask) == bitmask)
1223 return 0;
1224 } else {
1225 if (!(val & bitmask))
1226 return 0;
1227 }
1228 udelay(10);
1229 }
1230 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1231 "register %04X to %s.\n",
1232 bitmask, reg, (set ? "set" : "clear"));
1233
1234 return -ETIMEDOUT;
1235 }
1236
1237 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1238 {
1239 u32 reject, val;
1240
1241 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1242 return;
1243
1244 reject = ssb_tmslow_reject_bitmask(dev);
1245
1246 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1247 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1248 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1249 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1250
1251 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1252 val = ssb_read32(dev, SSB_IMSTATE);
1253 val |= SSB_IMSTATE_REJECT;
1254 ssb_write32(dev, SSB_IMSTATE, val);
1255 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1256 0);
1257 }
1258
1259 ssb_write32(dev, SSB_TMSLOW,
1260 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1261 reject | SSB_TMSLOW_RESET |
1262 core_specific_flags);
1263 ssb_flush_tmslow(dev);
1264
1265 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1266 val = ssb_read32(dev, SSB_IMSTATE);
1267 val &= ~SSB_IMSTATE_REJECT;
1268 ssb_write32(dev, SSB_IMSTATE, val);
1269 }
1270 }
1271
1272 ssb_write32(dev, SSB_TMSLOW,
1273 reject | SSB_TMSLOW_RESET |
1274 core_specific_flags);
1275 ssb_flush_tmslow(dev);
1276 }
1277 EXPORT_SYMBOL(ssb_device_disable);
1278
1279 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1280 static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1281 {
1282 u16 chip_id = dev->bus->chip_id;
1283
1284 if (dev->id.coreid == SSB_DEV_80211) {
1285 return (chip_id == 0x4322 || chip_id == 43221 ||
1286 chip_id == 43231 || chip_id == 43222);
1287 }
1288
1289 return 0;
1290 }
1291
1292 u32 ssb_dma_translation(struct ssb_device *dev)
1293 {
1294 switch (dev->bus->bustype) {
1295 case SSB_BUSTYPE_SSB:
1296 return 0;
1297 case SSB_BUSTYPE_PCI:
1298 if (pci_is_pcie(dev->bus->host_pci) &&
1299 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1300 return SSB_PCIE_DMA_H32;
1301 } else {
1302 if (ssb_dma_translation_special_bit(dev))
1303 return SSB_PCIE_DMA_H32;
1304 else
1305 return SSB_PCI_DMA;
1306 }
1307 default:
1308 __ssb_dma_not_implemented(dev);
1309 }
1310 return 0;
1311 }
1312 EXPORT_SYMBOL(ssb_dma_translation);
1313
1314 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1315 {
1316 struct ssb_chipcommon *cc;
1317 int err = 0;
1318
1319 /* On buses where more than one core may be working
1320 * at a time, we must not powerdown stuff if there are
1321 * still cores that may want to run. */
1322 if (bus->bustype == SSB_BUSTYPE_SSB)
1323 goto out;
1324
1325 cc = &bus->chipco;
1326
1327 if (!cc->dev)
1328 goto out;
1329 if (cc->dev->id.revision < 5)
1330 goto out;
1331
1332 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1333 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1334 if (err)
1335 goto error;
1336 out:
1337 #ifdef CONFIG_SSB_DEBUG
1338 bus->powered_up = 0;
1339 #endif
1340 return err;
1341 error:
1342 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1343 goto out;
1344 }
1345 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1346
1347 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1348 {
1349 int err;
1350 enum ssb_clkmode mode;
1351
1352 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1353 if (err)
1354 goto error;
1355
1356 #ifdef CONFIG_SSB_DEBUG
1357 bus->powered_up = 1;
1358 #endif
1359
1360 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1361 ssb_chipco_set_clockmode(&bus->chipco, mode);
1362
1363 return 0;
1364 error:
1365 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1366 return err;
1367 }
1368 EXPORT_SYMBOL(ssb_bus_powerup);
1369
1370 static void ssb_broadcast_value(struct ssb_device *dev,
1371 u32 address, u32 data)
1372 {
1373 #ifdef CONFIG_SSB_DRIVER_PCICORE
1374 /* This is used for both, PCI and ChipCommon core, so be careful. */
1375 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1376 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1377 #endif
1378
1379 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1380 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1381 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1382 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1383 }
1384
1385 void ssb_commit_settings(struct ssb_bus *bus)
1386 {
1387 struct ssb_device *dev;
1388
1389 #ifdef CONFIG_SSB_DRIVER_PCICORE
1390 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1391 #else
1392 dev = bus->chipco.dev;
1393 #endif
1394 if (WARN_ON(!dev))
1395 return;
1396 /* This forces an update of the cached registers. */
1397 ssb_broadcast_value(dev, 0xFD8, 0);
1398 }
1399 EXPORT_SYMBOL(ssb_commit_settings);
1400
1401 u32 ssb_admatch_base(u32 adm)
1402 {
1403 u32 base = 0;
1404
1405 switch (adm & SSB_ADM_TYPE) {
1406 case SSB_ADM_TYPE0:
1407 base = (adm & SSB_ADM_BASE0);
1408 break;
1409 case SSB_ADM_TYPE1:
1410 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1411 base = (adm & SSB_ADM_BASE1);
1412 break;
1413 case SSB_ADM_TYPE2:
1414 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1415 base = (adm & SSB_ADM_BASE2);
1416 break;
1417 default:
1418 SSB_WARN_ON(1);
1419 }
1420
1421 return base;
1422 }
1423 EXPORT_SYMBOL(ssb_admatch_base);
1424
1425 u32 ssb_admatch_size(u32 adm)
1426 {
1427 u32 size = 0;
1428
1429 switch (adm & SSB_ADM_TYPE) {
1430 case SSB_ADM_TYPE0:
1431 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1432 break;
1433 case SSB_ADM_TYPE1:
1434 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1435 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1436 break;
1437 case SSB_ADM_TYPE2:
1438 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1439 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1440 break;
1441 default:
1442 SSB_WARN_ON(1);
1443 }
1444 size = (1 << (size + 1));
1445
1446 return size;
1447 }
1448 EXPORT_SYMBOL(ssb_admatch_size);
1449
1450 static int __init ssb_modinit(void)
1451 {
1452 int err;
1453
1454 /* See the comment at the ssb_is_early_boot definition */
1455 ssb_is_early_boot = 0;
1456 err = bus_register(&ssb_bustype);
1457 if (err)
1458 return err;
1459
1460 /* Maybe we already registered some buses at early boot.
1461 * Check for this and attach them
1462 */
1463 ssb_buses_lock();
1464 err = ssb_attach_queued_buses();
1465 ssb_buses_unlock();
1466 if (err) {
1467 bus_unregister(&ssb_bustype);
1468 goto out;
1469 }
1470
1471 err = b43_pci_ssb_bridge_init();
1472 if (err) {
1473 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1474 "initialization failed\n");
1475 /* don't fail SSB init because of this */
1476 err = 0;
1477 }
1478 err = ssb_gige_init();
1479 if (err) {
1480 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1481 "driver initialization failed\n");
1482 /* don't fail SSB init because of this */
1483 err = 0;
1484 }
1485 out:
1486 return err;
1487 }
1488 /* ssb must be initialized after PCI but before the ssb drivers.
1489 * That means we must use some initcall between subsys_initcall
1490 * and device_initcall. */
1491 fs_initcall(ssb_modinit);
1492
1493 static void __exit ssb_modexit(void)
1494 {
1495 ssb_gige_exit();
1496 b43_pci_ssb_bridge_exit();
1497 bus_unregister(&ssb_bustype);
1498 }
1499 module_exit(ssb_modexit)
kernel source for telekom puls (alcatel/mediatek)