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ssb: set the PMU watchdog if available
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ssb / driver_chipcommon.c
1 /*
2 * Sonics Silicon Backplane
3 * Broadcom ChipCommon core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/export.h>
14 #include <linux/pci.h>
15
16 #include "ssb_private.h"
17
18
19 /* Clock sources */
20 enum ssb_clksrc {
21 /* PCI clock */
22 SSB_CHIPCO_CLKSRC_PCI,
23 /* Crystal slow clock oscillator */
24 SSB_CHIPCO_CLKSRC_XTALOS,
25 /* Low power oscillator */
26 SSB_CHIPCO_CLKSRC_LOPWROS,
27 };
28
29
30 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
31 u32 mask, u32 value)
32 {
33 value &= mask;
34 value |= chipco_read32(cc, offset) & ~mask;
35 chipco_write32(cc, offset, value);
36
37 return value;
38 }
39
40 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
41 enum ssb_clkmode mode)
42 {
43 struct ssb_device *ccdev = cc->dev;
44 struct ssb_bus *bus;
45 u32 tmp;
46
47 if (!ccdev)
48 return;
49 bus = ccdev->bus;
50
51 /* We support SLOW only on 6..9 */
52 if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
53 mode = SSB_CLKMODE_DYNAMIC;
54
55 if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
56 return; /* PMU controls clockmode, separated function needed */
57 SSB_WARN_ON(ccdev->id.revision >= 20);
58
59 /* chipcommon cores prior to rev6 don't support dynamic clock control */
60 if (ccdev->id.revision < 6)
61 return;
62
63 /* ChipCommon cores rev10+ need testing */
64 if (ccdev->id.revision >= 10)
65 return;
66
67 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
68 return;
69
70 switch (mode) {
71 case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
72 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
73 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
74 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
75 break;
76 case SSB_CLKMODE_FAST:
77 if (ccdev->id.revision < 10) {
78 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
79 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
80 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
81 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
82 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
83 } else {
84 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
85 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
86 SSB_CHIPCO_SYSCLKCTL_FORCEHT));
87 /* udelay(150); TODO: not available in early init */
88 }
89 break;
90 case SSB_CLKMODE_DYNAMIC:
91 if (ccdev->id.revision < 10) {
92 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
93 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
94 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
95 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
96 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
97 SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
98 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
99 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
100
101 /* For dynamic control, we have to release our xtal_pu
102 * "force on" */
103 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
104 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
105 } else {
106 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
107 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
108 ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
109 }
110 break;
111 default:
112 SSB_WARN_ON(1);
113 }
114 }
115
116 /* Get the Slow Clock Source */
117 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
118 {
119 struct ssb_bus *bus = cc->dev->bus;
120 u32 uninitialized_var(tmp);
121
122 if (cc->dev->id.revision < 6) {
123 if (bus->bustype == SSB_BUSTYPE_SSB ||
124 bus->bustype == SSB_BUSTYPE_PCMCIA)
125 return SSB_CHIPCO_CLKSRC_XTALOS;
126 if (bus->bustype == SSB_BUSTYPE_PCI) {
127 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
128 if (tmp & 0x10)
129 return SSB_CHIPCO_CLKSRC_PCI;
130 return SSB_CHIPCO_CLKSRC_XTALOS;
131 }
132 }
133 if (cc->dev->id.revision < 10) {
134 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
135 tmp &= 0x7;
136 if (tmp == 0)
137 return SSB_CHIPCO_CLKSRC_LOPWROS;
138 if (tmp == 1)
139 return SSB_CHIPCO_CLKSRC_XTALOS;
140 if (tmp == 2)
141 return SSB_CHIPCO_CLKSRC_PCI;
142 }
143
144 return SSB_CHIPCO_CLKSRC_XTALOS;
145 }
146
147 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
148 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
149 {
150 int uninitialized_var(limit);
151 enum ssb_clksrc clocksrc;
152 int divisor = 1;
153 u32 tmp;
154
155 clocksrc = chipco_pctl_get_slowclksrc(cc);
156 if (cc->dev->id.revision < 6) {
157 switch (clocksrc) {
158 case SSB_CHIPCO_CLKSRC_PCI:
159 divisor = 64;
160 break;
161 case SSB_CHIPCO_CLKSRC_XTALOS:
162 divisor = 32;
163 break;
164 default:
165 SSB_WARN_ON(1);
166 }
167 } else if (cc->dev->id.revision < 10) {
168 switch (clocksrc) {
169 case SSB_CHIPCO_CLKSRC_LOPWROS:
170 break;
171 case SSB_CHIPCO_CLKSRC_XTALOS:
172 case SSB_CHIPCO_CLKSRC_PCI:
173 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
174 divisor = (tmp >> 16) + 1;
175 divisor *= 4;
176 break;
177 }
178 } else {
179 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
180 divisor = (tmp >> 16) + 1;
181 divisor *= 4;
182 }
183
184 switch (clocksrc) {
185 case SSB_CHIPCO_CLKSRC_LOPWROS:
186 if (get_max)
187 limit = 43000;
188 else
189 limit = 25000;
190 break;
191 case SSB_CHIPCO_CLKSRC_XTALOS:
192 if (get_max)
193 limit = 20200000;
194 else
195 limit = 19800000;
196 break;
197 case SSB_CHIPCO_CLKSRC_PCI:
198 if (get_max)
199 limit = 34000000;
200 else
201 limit = 25000000;
202 break;
203 }
204 limit /= divisor;
205
206 return limit;
207 }
208
209 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
210 {
211 struct ssb_bus *bus = cc->dev->bus;
212
213 if (bus->chip_id == 0x4321) {
214 if (bus->chip_rev == 0)
215 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
216 else if (bus->chip_rev == 1)
217 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
218 }
219
220 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
221 return;
222
223 if (cc->dev->id.revision >= 10) {
224 /* Set Idle Power clock rate to 1Mhz */
225 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
226 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
227 0x0000FFFF) | 0x00040000);
228 } else {
229 int maxfreq;
230
231 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
232 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
233 (maxfreq * 150 + 999999) / 1000000);
234 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
235 (maxfreq * 15 + 999999) / 1000000);
236 }
237 }
238
239 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
240 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
241 {
242 struct ssb_bus *bus = cc->dev->bus;
243
244 switch (bus->chip_id) {
245 case 0x4312:
246 case 0x4322:
247 case 0x4328:
248 return 7000;
249 case 0x4325:
250 /* TODO: */
251 default:
252 return 15000;
253 }
254 }
255
256 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
257 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
258 {
259 struct ssb_bus *bus = cc->dev->bus;
260 int minfreq;
261 unsigned int tmp;
262 u32 pll_on_delay;
263
264 if (bus->bustype != SSB_BUSTYPE_PCI)
265 return;
266
267 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
268 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
269 return;
270 }
271
272 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
273 return;
274
275 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
276 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
277 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
278 SSB_WARN_ON(tmp & ~0xFFFF);
279
280 cc->fast_pwrup_delay = tmp;
281 }
282
283 static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
284 {
285 if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
286 return ssb_pmu_get_alp_clock(cc);
287
288 return 20000000;
289 }
290
291 static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
292 {
293 u32 nb;
294
295 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
296 if (cc->dev->id.revision < 26)
297 nb = 16;
298 else
299 nb = (cc->dev->id.revision >= 37) ? 32 : 24;
300 } else {
301 nb = 28;
302 }
303 if (nb == 32)
304 return 0xffffffff;
305 else
306 return (1 << nb) - 1;
307 }
308
309 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
310 {
311 if (!cc->dev)
312 return; /* We don't have a ChipCommon */
313 if (cc->dev->id.revision >= 11)
314 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
315 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
316
317 if (cc->dev->id.revision >= 20) {
318 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
319 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
320 }
321
322 ssb_pmu_init(cc);
323 chipco_powercontrol_init(cc);
324 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
325 calc_fast_powerup_delay(cc);
326 }
327
328 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
329 {
330 if (!cc->dev)
331 return;
332 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
333 }
334
335 void ssb_chipco_resume(struct ssb_chipcommon *cc)
336 {
337 if (!cc->dev)
338 return;
339 chipco_powercontrol_init(cc);
340 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
341 }
342
343 /* Get the processor clock */
344 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
345 u32 *plltype, u32 *n, u32 *m)
346 {
347 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
348 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
349 switch (*plltype) {
350 case SSB_PLLTYPE_2:
351 case SSB_PLLTYPE_4:
352 case SSB_PLLTYPE_6:
353 case SSB_PLLTYPE_7:
354 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
355 break;
356 case SSB_PLLTYPE_3:
357 /* 5350 uses m2 to control mips */
358 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
359 break;
360 default:
361 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
362 break;
363 }
364 }
365
366 /* Get the bus clock */
367 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
368 u32 *plltype, u32 *n, u32 *m)
369 {
370 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
371 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
372 switch (*plltype) {
373 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
374 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
375 break;
376 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
377 if (cc->dev->bus->chip_id != 0x5365) {
378 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
379 break;
380 }
381 /* Fallthough */
382 default:
383 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
384 }
385 }
386
387 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
388 unsigned long ns)
389 {
390 struct ssb_device *dev = cc->dev;
391 struct ssb_bus *bus = dev->bus;
392 u32 tmp;
393
394 /* set register for external IO to control LED. */
395 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
396 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
397 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
398 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
399 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
400
401 /* Set timing for the flash */
402 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
403 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
404 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
405 if ((bus->chip_id == 0x5365) ||
406 (dev->id.revision < 9))
407 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
408 if ((bus->chip_id == 0x5365) ||
409 (dev->id.revision < 9) ||
410 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
411 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
412
413 if (bus->chip_id == 0x5350) {
414 /* Enable EXTIF */
415 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
416 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
417 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
418 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
419 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
420 }
421 }
422
423 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
424 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
425 {
426 u32 maxt;
427 enum ssb_clkmode clkmode;
428
429 maxt = ssb_chipco_watchdog_get_max_timer(cc);
430 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
431 if (ticks == 1)
432 ticks = 2;
433 else if (ticks > maxt)
434 ticks = maxt;
435 chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
436 } else {
437 clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
438 ssb_chipco_set_clockmode(cc, clkmode);
439 if (ticks > maxt)
440 ticks = maxt;
441 /* instant NMI */
442 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
443 }
444 }
445
446 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
447 {
448 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
449 }
450
451 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
452 {
453 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
454 }
455
456 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
457 {
458 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
459 }
460
461 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
462 {
463 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
464 }
465
466 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
467 {
468 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
469 }
470
471 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
472 {
473 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
474 }
475 EXPORT_SYMBOL(ssb_chipco_gpio_control);
476
477 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
478 {
479 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
480 }
481
482 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
483 {
484 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
485 }
486
487 #ifdef CONFIG_SSB_SERIAL
488 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
489 struct ssb_serial_port *ports)
490 {
491 struct ssb_bus *bus = cc->dev->bus;
492 int nr_ports = 0;
493 u32 plltype;
494 unsigned int irq;
495 u32 baud_base, div;
496 u32 i, n;
497 unsigned int ccrev = cc->dev->id.revision;
498
499 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
500 irq = ssb_mips_irq(cc->dev);
501
502 if (plltype == SSB_PLLTYPE_1) {
503 /* PLL clock */
504 baud_base = ssb_calc_clock_rate(plltype,
505 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
506 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
507 div = 1;
508 } else {
509 if (ccrev == 20) {
510 /* BCM5354 uses constant 25MHz clock */
511 baud_base = 25000000;
512 div = 48;
513 /* Set the override bit so we don't divide it */
514 chipco_write32(cc, SSB_CHIPCO_CORECTL,
515 chipco_read32(cc, SSB_CHIPCO_CORECTL)
516 | SSB_CHIPCO_CORECTL_UARTCLK0);
517 } else if ((ccrev >= 11) && (ccrev != 15)) {
518 baud_base = ssb_chipco_alp_clock(cc);
519 div = 1;
520 if (ccrev >= 21) {
521 /* Turn off UART clock before switching clocksource. */
522 chipco_write32(cc, SSB_CHIPCO_CORECTL,
523 chipco_read32(cc, SSB_CHIPCO_CORECTL)
524 & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
525 }
526 /* Set the override bit so we don't divide it */
527 chipco_write32(cc, SSB_CHIPCO_CORECTL,
528 chipco_read32(cc, SSB_CHIPCO_CORECTL)
529 | SSB_CHIPCO_CORECTL_UARTCLK0);
530 if (ccrev >= 21) {
531 /* Re-enable the UART clock. */
532 chipco_write32(cc, SSB_CHIPCO_CORECTL,
533 chipco_read32(cc, SSB_CHIPCO_CORECTL)
534 | SSB_CHIPCO_CORECTL_UARTCLKEN);
535 }
536 } else if (ccrev >= 3) {
537 /* Internal backplane clock */
538 baud_base = ssb_clockspeed(bus);
539 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
540 & SSB_CHIPCO_CLKDIV_UART;
541 } else {
542 /* Fixed internal backplane clock */
543 baud_base = 88000000;
544 div = 48;
545 }
546
547 /* Clock source depends on strapping if UartClkOverride is unset */
548 if ((ccrev > 0) &&
549 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
550 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
551 SSB_CHIPCO_CAP_UARTCLK_INT) {
552 /* Internal divided backplane clock */
553 baud_base /= div;
554 } else {
555 /* Assume external clock of 1.8432 MHz */
556 baud_base = 1843200;
557 }
558 }
559 }
560
561 /* Determine the registers of the UARTs */
562 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
563 for (i = 0; i < n; i++) {
564 void __iomem *cc_mmio;
565 void __iomem *uart_regs;
566
567 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
568 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
569 /* Offset changed at after rev 0 */
570 if (ccrev == 0)
571 uart_regs += (i * 8);
572 else
573 uart_regs += (i * 256);
574
575 nr_ports++;
576 ports[i].regs = uart_regs;
577 ports[i].irq = irq;
578 ports[i].baud_base = baud_base;
579 ports[i].reg_shift = 0;
580 }
581
582 return nr_ports;
583 }
584 #endif /* CONFIG_SSB_SERIAL */
kernel source for telekom puls (alcatel/mediatek)