drivers/spi/spi_mpc83xx.c

   1 /*
   2  * MPC83xx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/completion.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/delay.h>
  20 #include <linux/irq.h>
  21 #include <linux/device.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/spi_bitbang.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/fsl_devices.h>
  26
  27 #include <asm/irq.h>
  28 #include <asm/io.h>
  29
  30 /* SPI Controller registers */
  31 struct mpc83xx_spi_reg {
  32         u8 res1[0x20];
  33         __be32 mode;
  34         __be32 event;
  35         __be32 mask;
  36         __be32 command;
  37         __be32 transmit;
  38         __be32 receive;
  39 };
  40
  41 /* SPI Controller mode register definitions */
  42 #define SPMODE_LOOP             (1 << 30)
  43 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  44 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  45 #define SPMODE_DIV16            (1 << 27)
  46 #define SPMODE_REV              (1 << 26)
  47 #define SPMODE_MS               (1 << 25)
  48 #define SPMODE_ENABLE           (1 << 24)
  49 #define SPMODE_LEN(x)           ((x) << 20)
  50 #define SPMODE_PM(x)            ((x) << 16)
  51 #define SPMODE_OP               (1 << 14)
  52
  53 /*
  54  * Default for SPI Mode:
  55  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  56  */
  57 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  58                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  59
  60 /* SPIE register values */
  61 #define SPIE_NE         0x00000200      /* Not empty */
  62 #define SPIE_NF         0x00000100      /* Not full */
  63
  64 /* SPIM register values */
  65 #define SPIM_NE         0x00000200      /* Not empty */
  66 #define SPIM_NF         0x00000100      /* Not full */
  67
  68 /* SPI Controller driver's private data. */
  69 struct mpc83xx_spi {
  70         /* bitbang has to be first */
  71         struct spi_bitbang bitbang;
  72         struct completion done;
  73
  74         struct mpc83xx_spi_reg __iomem *base;
  75
  76         /* rx & tx bufs from the spi_transfer */
  77         const void *tx;
  78         void *rx;
  79
  80         /* functions to deal with different sized buffers */
  81         void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
  82         u32(*get_tx) (struct mpc83xx_spi *);
  83
  84         unsigned int count;
  85         u32 irq;
  86
  87         unsigned nsecs;         /* (clock cycle time)/2 */
  88
  89         u32 spibrg;             /* SPIBRG input clock */
  90         u32 rx_shift;           /* RX data reg shift when in qe mode */
  91         u32 tx_shift;           /* TX data reg shift when in qe mode */
  92
  93         bool qe_mode;
  94
  95         void (*activate_cs) (u8 cs, u8 polarity);
  96         void (*deactivate_cs) (u8 cs, u8 polarity);
  97 };
  98
  99 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
 100 {
 101         out_be32(reg, val);
 102 }
 103
 104 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
 105 {
 106         return in_be32(reg);
 107 }
 108
 109 #define MPC83XX_SPI_RX_BUF(type)                                          \
 110 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 111 {                                                                         \
 112         type * rx = mpc83xx_spi->rx;                                      \
 113         *rx++ = (type)(data >> mpc83xx_spi->rx_shift);                    \
 114         mpc83xx_spi->rx = rx;                                             \
 115 }
 116
 117 #define MPC83XX_SPI_TX_BUF(type)                                \
 118 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)  \
 119 {                                                               \
 120         u32 data;                                               \
 121         const type * tx = mpc83xx_spi->tx;                      \
 122         if (!tx)                                                \
 123                 return 0;                                       \
 124         data = *tx++ << mpc83xx_spi->tx_shift;                  \
 125         mpc83xx_spi->tx = tx;                                   \
 126         return data;                                            \
 127 }
 128
 129 MPC83XX_SPI_RX_BUF(u8)
 130 MPC83XX_SPI_RX_BUF(u16)
 131 MPC83XX_SPI_RX_BUF(u32)
 132 MPC83XX_SPI_TX_BUF(u8)
 133 MPC83XX_SPI_TX_BUF(u16)
 134 MPC83XX_SPI_TX_BUF(u32)
 135
 136 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 137 {
 138         struct mpc83xx_spi *mpc83xx_spi;
 139         u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 140
 141         mpc83xx_spi = spi_master_get_devdata(spi->master);
 142
 143         if (value == BITBANG_CS_INACTIVE) {
 144                 if (mpc83xx_spi->deactivate_cs)
 145                         mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
 146         }
 147
 148         if (value == BITBANG_CS_ACTIVE) {
 149                 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 150                 u32 len = spi->bits_per_word;
 151                 u8 pm;
 152
 153                 if (len == 32)
 154                         len = 0;
 155                 else
 156                         len = len - 1;
 157
 158                 /* mask out bits we are going to set */
 159                 regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 160                                 | SPMODE_LEN(0xF) | SPMODE_DIV16
 161                                 | SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP);
 162
 163                 if (spi->mode & SPI_CPHA)
 164                         regval |= SPMODE_CP_BEGIN_EDGECLK;
 165                 if (spi->mode & SPI_CPOL)
 166                         regval |= SPMODE_CI_INACTIVEHIGH;
 167                 if (!(spi->mode & SPI_LSB_FIRST))
 168                         regval |= SPMODE_REV;
 169                 if (spi->mode & SPI_LOOP)
 170                         regval |= SPMODE_LOOP;
 171
 172                 regval |= SPMODE_LEN(len);
 173
 174                 if ((mpc83xx_spi->spibrg / spi->max_speed_hz) >= 64) {
 175                         pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 64) - 1;
 176                         if (pm > 0x0f) {
 177                                 dev_err(&spi->dev, "Requested speed is too "
 178                                         "low: %d Hz. Will use %d Hz instead.\n",
 179                                         spi->max_speed_hz,
 180                                         mpc83xx_spi->spibrg / 1024);
 181                                 pm = 0x0f;
 182                         }
 183                         regval |= SPMODE_PM(pm) | SPMODE_DIV16;
 184                 } else {
 185                         pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 4);
 186                         if (pm)
 187                                 pm--;
 188                         regval |= SPMODE_PM(pm);
 189                 }
 190
 191                 /* Turn off SPI unit prior changing mode */
 192                 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 193                 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 194                 if (mpc83xx_spi->activate_cs)
 195                         mpc83xx_spi->activate_cs(spi->chip_select, pol);
 196         }
 197 }
 198
 199 static
 200 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 201 {
 202         struct mpc83xx_spi *mpc83xx_spi;
 203         u32 regval;
 204         u8 bits_per_word;
 205         u32 hz;
 206
 207         mpc83xx_spi = spi_master_get_devdata(spi->master);
 208
 209         if (t) {
 210                 bits_per_word = t->bits_per_word;
 211                 hz = t->speed_hz;
 212         } else {
 213                 bits_per_word = 0;
 214                 hz = 0;
 215         }
 216
 217         /* spi_transfer level calls that work per-word */
 218         if (!bits_per_word)
 219                 bits_per_word = spi->bits_per_word;
 220
 221         /* Make sure its a bit width we support [4..16, 32] */
 222         if ((bits_per_word < 4)
 223             || ((bits_per_word > 16) && (bits_per_word != 32)))
 224                 return -EINVAL;
 225
 226         mpc83xx_spi->rx_shift = 0;
 227         mpc83xx_spi->tx_shift = 0;
 228         if (bits_per_word <= 8) {
 229                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 230                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 231                 if (mpc83xx_spi->qe_mode) {
 232                         mpc83xx_spi->rx_shift = 16;
 233                         mpc83xx_spi->tx_shift = 24;
 234                 }
 235         } else if (bits_per_word <= 16) {
 236                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
 237                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
 238                 if (mpc83xx_spi->qe_mode) {
 239                         mpc83xx_spi->rx_shift = 16;
 240                         mpc83xx_spi->tx_shift = 16;
 241                 }
 242         } else if (bits_per_word <= 32) {
 243                 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
 244                 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
 245         } else
 246                 return -EINVAL;
 247
 248         if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
 249                 mpc83xx_spi->tx_shift = 0;
 250                 if (bits_per_word <= 8)
 251                         mpc83xx_spi->rx_shift = 8;
 252                 else
 253                         mpc83xx_spi->rx_shift = 0;
 254         }
 255
 256         /* nsecs = (clock period)/2 */
 257         if (!hz)
 258                 hz = spi->max_speed_hz;
 259         mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
 260         if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
 261                 return -EINVAL;
 262
 263         if (bits_per_word == 32)
 264                 bits_per_word = 0;
 265         else
 266                 bits_per_word = bits_per_word - 1;
 267
 268         regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 269
 270         /* mask out bits we are going to set */
 271         regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
 272         regval |= SPMODE_LEN(bits_per_word);
 273         if (!(spi->mode & SPI_LSB_FIRST))
 274                 regval |= SPMODE_REV;
 275
 276         /* Turn off SPI unit prior changing mode */
 277         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 278         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 279
 280         return 0;
 281 }
 282
 283 /* the spi->mode bits understood by this driver: */
 284 #define MODEBITS        (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
 285                         | SPI_LSB_FIRST | SPI_LOOP)
 286
 287 static int mpc83xx_spi_setup(struct spi_device *spi)
 288 {
 289         struct spi_bitbang *bitbang;
 290         struct mpc83xx_spi *mpc83xx_spi;
 291         int retval;
 292
 293         if (spi->mode & ~MODEBITS) {
 294                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 295                         spi->mode & ~MODEBITS);
 296                 return -EINVAL;
 297         }
 298
 299         if (!spi->max_speed_hz)
 300                 return -EINVAL;
 301
 302         bitbang = spi_master_get_devdata(spi->master);
 303         mpc83xx_spi = spi_master_get_devdata(spi->master);
 304
 305         if (!spi->bits_per_word)
 306                 spi->bits_per_word = 8;
 307
 308         retval = mpc83xx_spi_setup_transfer(spi, NULL);
 309         if (retval < 0)
 310                 return retval;
 311
 312         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
 313                 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
 314                 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
 315
 316         /* NOTE we _need_ to call chipselect() early, ideally with adapter
 317          * setup, unless the hardware defaults cooperate to avoid confusion
 318          * between normal (active low) and inverted chipselects.
 319          */
 320
 321         /* deselect chip (low or high) */
 322         spin_lock(&bitbang->lock);
 323         if (!bitbang->busy) {
 324                 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
 325                 ndelay(mpc83xx_spi->nsecs);
 326         }
 327         spin_unlock(&bitbang->lock);
 328
 329         return 0;
 330 }
 331
 332 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 333 {
 334         struct mpc83xx_spi *mpc83xx_spi;
 335         u32 word;
 336
 337         mpc83xx_spi = spi_master_get_devdata(spi->master);
 338
 339         mpc83xx_spi->tx = t->tx_buf;
 340         mpc83xx_spi->rx = t->rx_buf;
 341         mpc83xx_spi->count = t->len;
 342         INIT_COMPLETION(mpc83xx_spi->done);
 343
 344         /* enable rx ints */
 345         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
 346
 347         /* transmit word */
 348         word = mpc83xx_spi->get_tx(mpc83xx_spi);
 349         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 350
 351         wait_for_completion(&mpc83xx_spi->done);
 352
 353         /* disable rx ints */
 354         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 355
 356         return t->len - mpc83xx_spi->count;
 357 }
 358
 359 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
 360 {
 361         struct mpc83xx_spi *mpc83xx_spi = context_data;
 362         u32 event;
 363         irqreturn_t ret = IRQ_NONE;
 364
 365         /* Get interrupt events(tx/rx) */
 366         event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
 367
 368         /* We need handle RX first */
 369         if (event & SPIE_NE) {
 370                 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
 371
 372                 if (mpc83xx_spi->rx)
 373                         mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
 374
 375                 ret = IRQ_HANDLED;
 376         }
 377
 378         if ((event & SPIE_NF) == 0)
 379                 /* spin until TX is done */
 380                 while (((event =
 381                          mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
 382                                                 SPIE_NF) == 0)
 383                          cpu_relax();
 384
 385         mpc83xx_spi->count -= 1;
 386         if (mpc83xx_spi->count) {
 387                 if (mpc83xx_spi->tx) {
 388                         u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
 389                         mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
 390                                               word);
 391                 }
 392         } else {
 393                 complete(&mpc83xx_spi->done);
 394         }
 395
 396         /* Clear the events */
 397         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
 398
 399         return ret;
 400 }
 401
 402 static int __init mpc83xx_spi_probe(struct platform_device *dev)
 403 {
 404         struct spi_master *master;
 405         struct mpc83xx_spi *mpc83xx_spi;
 406         struct fsl_spi_platform_data *pdata;
 407         struct resource *r;
 408         u32 regval;
 409         int ret = 0;
 410
 411         /* Get resources(memory, IRQ) associated with the device */
 412         master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
 413
 414         if (master == NULL) {
 415                 ret = -ENOMEM;
 416                 goto err;
 417         }
 418
 419         platform_set_drvdata(dev, master);
 420         pdata = dev->dev.platform_data;
 421
 422         if (pdata == NULL) {
 423                 ret = -ENODEV;
 424                 goto free_master;
 425         }
 426
 427         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
 428         if (r == NULL) {
 429                 ret = -ENODEV;
 430                 goto free_master;
 431         }
 432         mpc83xx_spi = spi_master_get_devdata(master);
 433         mpc83xx_spi->bitbang.master = spi_master_get(master);
 434         mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
 435         mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
 436         mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
 437         mpc83xx_spi->activate_cs = pdata->activate_cs;
 438         mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
 439         mpc83xx_spi->qe_mode = pdata->qe_mode;
 440         mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 441         mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 442
 443         if (mpc83xx_spi->qe_mode)
 444                 mpc83xx_spi->spibrg = pdata->sysclk / 2;
 445         else
 446                 mpc83xx_spi->spibrg = pdata->sysclk;
 447
 448         mpc83xx_spi->rx_shift = 0;
 449         mpc83xx_spi->tx_shift = 0;
 450         if (mpc83xx_spi->qe_mode) {
 451                 mpc83xx_spi->rx_shift = 16;
 452                 mpc83xx_spi->tx_shift = 24;
 453         }
 454
 455         mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
 456         init_completion(&mpc83xx_spi->done);
 457
 458         mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
 459         if (mpc83xx_spi->base == NULL) {
 460                 ret = -ENOMEM;
 461                 goto put_master;
 462         }
 463
 464         mpc83xx_spi->irq = platform_get_irq(dev, 0);
 465
 466         if (mpc83xx_spi->irq < 0) {
 467                 ret = -ENXIO;
 468                 goto unmap_io;
 469         }
 470
 471         /* Register for SPI Interrupt */
 472         ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
 473                           0, "mpc83xx_spi", mpc83xx_spi);
 474
 475         if (ret != 0)
 476                 goto unmap_io;
 477
 478         master->bus_num = pdata->bus_num;
 479         master->num_chipselect = pdata->max_chipselect;
 480
 481         /* SPI controller initializations */
 482         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 483         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 484         mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
 485         mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
 486
 487         /* Enable SPI interface */
 488         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 489         if (pdata->qe_mode)
 490                 regval |= SPMODE_OP;
 491
 492         mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 493
 494         ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
 495
 496         if (ret != 0)
 497                 goto free_irq;
 498
 499         printk(KERN_INFO
 500                "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
 501                dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
 502
 503         return ret;
 504
 505 free_irq:
 506         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 507 unmap_io:
 508         iounmap(mpc83xx_spi->base);
 509 put_master:
 510         spi_master_put(master);
 511 free_master:
 512         kfree(master);
 513 err:
 514         return ret;
 515 }
 516
 517 static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
 518 {
 519         struct mpc83xx_spi *mpc83xx_spi;
 520         struct spi_master *master;
 521
 522         master = platform_get_drvdata(dev);
 523         mpc83xx_spi = spi_master_get_devdata(master);
 524
 525         spi_bitbang_stop(&mpc83xx_spi->bitbang);
 526         free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 527         iounmap(mpc83xx_spi->base);
 528         spi_master_put(mpc83xx_spi->bitbang.master);
 529
 530         return 0;
 531 }
 532
 533 static struct platform_driver mpc83xx_spi_driver = {
 534         .probe = mpc83xx_spi_probe,
 535         .remove = __devexit_p(mpc83xx_spi_remove),
 536         .driver = {
 537                    .name = "mpc83xx_spi",
 538         },
 539 };
 540
 541 static int __init mpc83xx_spi_init(void)
 542 {
 543         return platform_driver_register(&mpc83xx_spi_driver);
 544 }
 545
 546 static void __exit mpc83xx_spi_exit(void)
 547 {
 548         platform_driver_unregister(&mpc83xx_spi_driver);
 549 }
 550
 551 module_init(mpc83xx_spi_init);
 552 module_exit(mpc83xx_spi_exit);
 553
 554 MODULE_AUTHOR("Kumar Gala");
 555 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
 556 MODULE_LICENSE("GPL");