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Blackfin SPI Driver: tweak magic spi dma sequence to get it working on BF54x
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_bfin5xx.c
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/dma.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/cacheflush.h>
29
30 #define DRV_NAME "bfin-spi"
31 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
32 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
33 #define DRV_VERSION "1.0"
34
35 MODULE_AUTHOR(DRV_AUTHOR);
36 MODULE_DESCRIPTION(DRV_DESC);
37 MODULE_LICENSE("GPL");
38
39 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
40
41 #define START_STATE ((void *)0)
42 #define RUNNING_STATE ((void *)1)
43 #define DONE_STATE ((void *)2)
44 #define ERROR_STATE ((void *)-1)
45 #define QUEUE_RUNNING 0
46 #define QUEUE_STOPPED 1
47
48 struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
55 /* Regs base of SPI controller */
56 void __iomem *regs_base;
57
58 /* Pin request list */
59 u16 *pin_req;
60
61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
85
86 /* DMA stuffs */
87 int dma_channel;
88 int dma_mapped;
89 int dma_requested;
90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
92
93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
96 int cs_change;
97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100 };
101
102 struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
109 u8 width; /* 0 or 1 */
110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117 };
118
119 #define DEFINE_SPI_REG(reg, off) \
120 static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125 DEFINE_SPI_REG(CTRL, 0x00)
126 DEFINE_SPI_REG(FLAG, 0x04)
127 DEFINE_SPI_REG(STAT, 0x08)
128 DEFINE_SPI_REG(TDBR, 0x0C)
129 DEFINE_SPI_REG(RDBR, 0x10)
130 DEFINE_SPI_REG(BAUD, 0x14)
131 DEFINE_SPI_REG(SHAW, 0x18)
132
133 static void bfin_spi_enable(struct driver_data *drv_data)
134 {
135 u16 cr;
136
137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
139 }
140
141 static void bfin_spi_disable(struct driver_data *drv_data)
142 {
143 u16 cr;
144
145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
147 }
148
149 /* Caculate the SPI_BAUD register value based on input HZ */
150 static u16 hz_to_spi_baud(u32 speed_hz)
151 {
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
161 return spi_baud;
162 }
163
164 static int flush(struct driver_data *drv_data)
165 {
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
170 cpu_relax();
171
172 write_STAT(drv_data, BIT_STAT_CLR);
173
174 return limit;
175 }
176
177 /* Chip select operation functions for cs_change flag */
178 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
179 {
180 u16 flag = read_FLAG(drv_data);
181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
185 write_FLAG(drv_data, flag);
186 }
187
188 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
189 {
190 u16 flag = read_FLAG(drv_data);
191
192 flag |= (chip->flag << 8);
193
194 write_FLAG(drv_data, flag);
195
196 /* Move delay here for consistency */
197 if (chip->cs_chg_udelay)
198 udelay(chip->cs_chg_udelay);
199 }
200
201 /* stop controller and re-config current chip*/
202 static void restore_state(struct driver_data *drv_data)
203 {
204 struct chip_data *chip = drv_data->cur_chip;
205
206 /* Clear status and disable clock */
207 write_STAT(drv_data, BIT_STAT_CLR);
208 bfin_spi_disable(drv_data);
209 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
210
211 /* Load the registers */
212 write_CTRL(drv_data, chip->ctl_reg);
213 write_BAUD(drv_data, chip->baud);
214
215 bfin_spi_enable(drv_data);
216 cs_active(drv_data, chip);
217 }
218
219 /* used to kick off transfer in rx mode */
220 static unsigned short dummy_read(struct driver_data *drv_data)
221 {
222 unsigned short tmp;
223 tmp = read_RDBR(drv_data);
224 return tmp;
225 }
226
227 static void null_writer(struct driver_data *drv_data)
228 {
229 u8 n_bytes = drv_data->n_bytes;
230
231 while (drv_data->tx < drv_data->tx_end) {
232 write_TDBR(drv_data, 0);
233 while ((read_STAT(drv_data) & BIT_STAT_TXS))
234 cpu_relax();
235 drv_data->tx += n_bytes;
236 }
237 }
238
239 static void null_reader(struct driver_data *drv_data)
240 {
241 u8 n_bytes = drv_data->n_bytes;
242 dummy_read(drv_data);
243
244 while (drv_data->rx < drv_data->rx_end) {
245 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
246 cpu_relax();
247 dummy_read(drv_data);
248 drv_data->rx += n_bytes;
249 }
250 }
251
252 static void u8_writer(struct driver_data *drv_data)
253 {
254 dev_dbg(&drv_data->pdev->dev,
255 "cr8-s is 0x%x\n", read_STAT(drv_data));
256
257 while (drv_data->tx < drv_data->tx_end) {
258 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
259 while (read_STAT(drv_data) & BIT_STAT_TXS)
260 cpu_relax();
261 ++drv_data->tx;
262 }
263
264 /* poll for SPI completion before return */
265 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
266 cpu_relax();
267 }
268
269 static void u8_cs_chg_writer(struct driver_data *drv_data)
270 {
271 struct chip_data *chip = drv_data->cur_chip;
272
273 while (drv_data->tx < drv_data->tx_end) {
274 cs_active(drv_data, chip);
275
276 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
277 while (read_STAT(drv_data) & BIT_STAT_TXS)
278 cpu_relax();
279 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
280 cpu_relax();
281
282 cs_deactive(drv_data, chip);
283
284 ++drv_data->tx;
285 }
286 }
287
288 static void u8_reader(struct driver_data *drv_data)
289 {
290 dev_dbg(&drv_data->pdev->dev,
291 "cr-8 is 0x%x\n", read_STAT(drv_data));
292
293 /* poll for SPI completion before start */
294 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
295 cpu_relax();
296
297 /* clear TDBR buffer before read(else it will be shifted out) */
298 write_TDBR(drv_data, 0xFFFF);
299
300 dummy_read(drv_data);
301
302 while (drv_data->rx < drv_data->rx_end - 1) {
303 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
304 cpu_relax();
305 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
306 ++drv_data->rx;
307 }
308
309 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
310 cpu_relax();
311 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
312 ++drv_data->rx;
313 }
314
315 static void u8_cs_chg_reader(struct driver_data *drv_data)
316 {
317 struct chip_data *chip = drv_data->cur_chip;
318
319 while (drv_data->rx < drv_data->rx_end) {
320 cs_active(drv_data, chip);
321 read_RDBR(drv_data); /* kick off */
322
323 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
324 cpu_relax();
325 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
326 cpu_relax();
327
328 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
329 cs_deactive(drv_data, chip);
330
331 ++drv_data->rx;
332 }
333 }
334
335 static void u8_duplex(struct driver_data *drv_data)
336 {
337 /* in duplex mode, clk is triggered by writing of TDBR */
338 while (drv_data->rx < drv_data->rx_end) {
339 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
340 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
341 cpu_relax();
342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
343 cpu_relax();
344 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
345 ++drv_data->rx;
346 ++drv_data->tx;
347 }
348 }
349
350 static void u8_cs_chg_duplex(struct driver_data *drv_data)
351 {
352 struct chip_data *chip = drv_data->cur_chip;
353
354 while (drv_data->rx < drv_data->rx_end) {
355 cs_active(drv_data, chip);
356
357 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
358
359 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
360 cpu_relax();
361 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
362 cpu_relax();
363 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
364
365 cs_deactive(drv_data, chip);
366
367 ++drv_data->rx;
368 ++drv_data->tx;
369 }
370 }
371
372 static void u16_writer(struct driver_data *drv_data)
373 {
374 dev_dbg(&drv_data->pdev->dev,
375 "cr16 is 0x%x\n", read_STAT(drv_data));
376
377 while (drv_data->tx < drv_data->tx_end) {
378 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
379 while ((read_STAT(drv_data) & BIT_STAT_TXS))
380 cpu_relax();
381 drv_data->tx += 2;
382 }
383
384 /* poll for SPI completion before return */
385 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
386 cpu_relax();
387 }
388
389 static void u16_cs_chg_writer(struct driver_data *drv_data)
390 {
391 struct chip_data *chip = drv_data->cur_chip;
392
393 while (drv_data->tx < drv_data->tx_end) {
394 cs_active(drv_data, chip);
395
396 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
397 while ((read_STAT(drv_data) & BIT_STAT_TXS))
398 cpu_relax();
399 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
400 cpu_relax();
401
402 cs_deactive(drv_data, chip);
403
404 drv_data->tx += 2;
405 }
406 }
407
408 static void u16_reader(struct driver_data *drv_data)
409 {
410 dev_dbg(&drv_data->pdev->dev,
411 "cr-16 is 0x%x\n", read_STAT(drv_data));
412
413 /* poll for SPI completion before start */
414 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
415 cpu_relax();
416
417 /* clear TDBR buffer before read(else it will be shifted out) */
418 write_TDBR(drv_data, 0xFFFF);
419
420 dummy_read(drv_data);
421
422 while (drv_data->rx < (drv_data->rx_end - 2)) {
423 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
424 cpu_relax();
425 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
426 drv_data->rx += 2;
427 }
428
429 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
430 cpu_relax();
431 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
432 drv_data->rx += 2;
433 }
434
435 static void u16_cs_chg_reader(struct driver_data *drv_data)
436 {
437 struct chip_data *chip = drv_data->cur_chip;
438
439 /* poll for SPI completion before start */
440 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
441 cpu_relax();
442
443 /* clear TDBR buffer before read(else it will be shifted out) */
444 write_TDBR(drv_data, 0xFFFF);
445
446 cs_active(drv_data, chip);
447 dummy_read(drv_data);
448
449 while (drv_data->rx < drv_data->rx_end - 2) {
450 cs_deactive(drv_data, chip);
451
452 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
453 cpu_relax();
454 cs_active(drv_data, chip);
455 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
456 drv_data->rx += 2;
457 }
458 cs_deactive(drv_data, chip);
459
460 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
461 cpu_relax();
462 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
463 drv_data->rx += 2;
464 }
465
466 static void u16_duplex(struct driver_data *drv_data)
467 {
468 /* in duplex mode, clk is triggered by writing of TDBR */
469 while (drv_data->tx < drv_data->tx_end) {
470 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
471 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
472 cpu_relax();
473 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
474 cpu_relax();
475 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
476 drv_data->rx += 2;
477 drv_data->tx += 2;
478 }
479 }
480
481 static void u16_cs_chg_duplex(struct driver_data *drv_data)
482 {
483 struct chip_data *chip = drv_data->cur_chip;
484
485 while (drv_data->tx < drv_data->tx_end) {
486 cs_active(drv_data, chip);
487
488 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
489 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
490 cpu_relax();
491 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
492 cpu_relax();
493 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
494
495 cs_deactive(drv_data, chip);
496
497 drv_data->rx += 2;
498 drv_data->tx += 2;
499 }
500 }
501
502 /* test if ther is more transfer to be done */
503 static void *next_transfer(struct driver_data *drv_data)
504 {
505 struct spi_message *msg = drv_data->cur_msg;
506 struct spi_transfer *trans = drv_data->cur_transfer;
507
508 /* Move to next transfer */
509 if (trans->transfer_list.next != &msg->transfers) {
510 drv_data->cur_transfer =
511 list_entry(trans->transfer_list.next,
512 struct spi_transfer, transfer_list);
513 return RUNNING_STATE;
514 } else
515 return DONE_STATE;
516 }
517
518 /*
519 * caller already set message->status;
520 * dma and pio irqs are blocked give finished message back
521 */
522 static void giveback(struct driver_data *drv_data)
523 {
524 struct chip_data *chip = drv_data->cur_chip;
525 struct spi_transfer *last_transfer;
526 unsigned long flags;
527 struct spi_message *msg;
528
529 spin_lock_irqsave(&drv_data->lock, flags);
530 msg = drv_data->cur_msg;
531 drv_data->cur_msg = NULL;
532 drv_data->cur_transfer = NULL;
533 drv_data->cur_chip = NULL;
534 queue_work(drv_data->workqueue, &drv_data->pump_messages);
535 spin_unlock_irqrestore(&drv_data->lock, flags);
536
537 last_transfer = list_entry(msg->transfers.prev,
538 struct spi_transfer, transfer_list);
539
540 msg->state = NULL;
541
542 /* disable chip select signal. And not stop spi in autobuffer mode */
543 if (drv_data->tx_dma != 0xFFFF) {
544 cs_deactive(drv_data, chip);
545 bfin_spi_disable(drv_data);
546 }
547
548 if (!drv_data->cs_change)
549 cs_deactive(drv_data, chip);
550
551 if (msg->complete)
552 msg->complete(msg->context);
553 }
554
555 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
556 {
557 struct driver_data *drv_data = dev_id;
558 struct chip_data *chip = drv_data->cur_chip;
559 struct spi_message *msg = drv_data->cur_msg;
560 unsigned long timeout;
561 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
562 u16 spistat = read_STAT(drv_data);
563
564 dev_dbg(&drv_data->pdev->dev,
565 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
566 dmastat, spistat);
567
568 clear_dma_irqstat(drv_data->dma_channel);
569
570 /* Wait for DMA to complete */
571 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
572 cpu_relax();
573
574 /*
575 * wait for the last transaction shifted out. HRM states:
576 * at this point there may still be data in the SPI DMA FIFO waiting
577 * to be transmitted ... software needs to poll TXS in the SPI_STAT
578 * register until it goes low for 2 successive reads
579 */
580 if (drv_data->tx != NULL) {
581 while ((read_STAT(drv_data) & TXS) ||
582 (read_STAT(drv_data) & TXS))
583 cpu_relax();
584 }
585
586 dev_dbg(&drv_data->pdev->dev,
587 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
588 dmastat, read_STAT(drv_data));
589
590 timeout = jiffies + HZ;
591 while (!(read_STAT(drv_data) & SPIF))
592 if (!time_before(jiffies, timeout)) {
593 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
594 break;
595 } else
596 cpu_relax();
597
598 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
599 msg->state = ERROR_STATE;
600 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
601 } else {
602 msg->actual_length += drv_data->len_in_bytes;
603
604 if (drv_data->cs_change)
605 cs_deactive(drv_data, chip);
606
607 /* Move to next transfer */
608 msg->state = next_transfer(drv_data);
609 }
610
611 /* Schedule transfer tasklet */
612 tasklet_schedule(&drv_data->pump_transfers);
613
614 /* free the irq handler before next transfer */
615 dev_dbg(&drv_data->pdev->dev,
616 "disable dma channel irq%d\n",
617 drv_data->dma_channel);
618 dma_disable_irq(drv_data->dma_channel);
619
620 return IRQ_HANDLED;
621 }
622
623 static void pump_transfers(unsigned long data)
624 {
625 struct driver_data *drv_data = (struct driver_data *)data;
626 struct spi_message *message = NULL;
627 struct spi_transfer *transfer = NULL;
628 struct spi_transfer *previous = NULL;
629 struct chip_data *chip = NULL;
630 u8 width;
631 u16 cr, dma_width, dma_config;
632 u32 tranf_success = 1;
633 u8 full_duplex = 0;
634
635 /* Get current state information */
636 message = drv_data->cur_msg;
637 transfer = drv_data->cur_transfer;
638 chip = drv_data->cur_chip;
639
640 /*
641 * if msg is error or done, report it back using complete() callback
642 */
643
644 /* Handle for abort */
645 if (message->state == ERROR_STATE) {
646 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
647 message->status = -EIO;
648 giveback(drv_data);
649 return;
650 }
651
652 /* Handle end of message */
653 if (message->state == DONE_STATE) {
654 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
655 message->status = 0;
656 giveback(drv_data);
657 return;
658 }
659
660 /* Delay if requested at end of transfer */
661 if (message->state == RUNNING_STATE) {
662 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
663 previous = list_entry(transfer->transfer_list.prev,
664 struct spi_transfer, transfer_list);
665 if (previous->delay_usecs)
666 udelay(previous->delay_usecs);
667 }
668
669 /* Setup the transfer state based on the type of transfer */
670 if (flush(drv_data) == 0) {
671 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
672 message->status = -EIO;
673 giveback(drv_data);
674 return;
675 }
676
677 if (transfer->tx_buf != NULL) {
678 drv_data->tx = (void *)transfer->tx_buf;
679 drv_data->tx_end = drv_data->tx + transfer->len;
680 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
681 transfer->tx_buf, drv_data->tx_end);
682 } else {
683 drv_data->tx = NULL;
684 }
685
686 if (transfer->rx_buf != NULL) {
687 full_duplex = transfer->tx_buf != NULL;
688 drv_data->rx = transfer->rx_buf;
689 drv_data->rx_end = drv_data->rx + transfer->len;
690 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
691 transfer->rx_buf, drv_data->rx_end);
692 } else {
693 drv_data->rx = NULL;
694 }
695
696 drv_data->rx_dma = transfer->rx_dma;
697 drv_data->tx_dma = transfer->tx_dma;
698 drv_data->len_in_bytes = transfer->len;
699 drv_data->cs_change = transfer->cs_change;
700
701 /* Bits per word setup */
702 switch (transfer->bits_per_word) {
703 case 8:
704 drv_data->n_bytes = 1;
705 width = CFG_SPI_WORDSIZE8;
706 drv_data->read = chip->cs_change_per_word ?
707 u8_cs_chg_reader : u8_reader;
708 drv_data->write = chip->cs_change_per_word ?
709 u8_cs_chg_writer : u8_writer;
710 drv_data->duplex = chip->cs_change_per_word ?
711 u8_cs_chg_duplex : u8_duplex;
712 break;
713
714 case 16:
715 drv_data->n_bytes = 2;
716 width = CFG_SPI_WORDSIZE16;
717 drv_data->read = chip->cs_change_per_word ?
718 u16_cs_chg_reader : u16_reader;
719 drv_data->write = chip->cs_change_per_word ?
720 u16_cs_chg_writer : u16_writer;
721 drv_data->duplex = chip->cs_change_per_word ?
722 u16_cs_chg_duplex : u16_duplex;
723 break;
724
725 default:
726 /* No change, the same as default setting */
727 drv_data->n_bytes = chip->n_bytes;
728 width = chip->width;
729 drv_data->write = drv_data->tx ? chip->write : null_writer;
730 drv_data->read = drv_data->rx ? chip->read : null_reader;
731 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
732 break;
733 }
734 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
735 cr |= (width << 8);
736 write_CTRL(drv_data, cr);
737
738 if (width == CFG_SPI_WORDSIZE16) {
739 drv_data->len = (transfer->len) >> 1;
740 } else {
741 drv_data->len = transfer->len;
742 }
743 dev_dbg(&drv_data->pdev->dev,
744 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
745 drv_data->write, chip->write, null_writer);
746
747 /* speed and width has been set on per message */
748 message->state = RUNNING_STATE;
749 dma_config = 0;
750
751 /* Speed setup (surely valid because already checked) */
752 if (transfer->speed_hz)
753 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
754 else
755 write_BAUD(drv_data, chip->baud);
756
757 write_STAT(drv_data, BIT_STAT_CLR);
758 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
759 cs_active(drv_data, chip);
760
761 dev_dbg(&drv_data->pdev->dev,
762 "now pumping a transfer: width is %d, len is %d\n",
763 width, transfer->len);
764
765 /*
766 * Try to map dma buffer and do a dma transfer. If successful use,
767 * different way to r/w according to the enable_dma settings and if
768 * we are not doing a full duplex transfer (since the hardware does
769 * not support full duplex DMA transfers).
770 */
771 if (!full_duplex && drv_data->cur_chip->enable_dma
772 && drv_data->len > 6) {
773
774 unsigned long dma_start_addr, flags;
775
776 disable_dma(drv_data->dma_channel);
777 clear_dma_irqstat(drv_data->dma_channel);
778
779 /* config dma channel */
780 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
781 set_dma_x_count(drv_data->dma_channel, drv_data->len);
782 if (width == CFG_SPI_WORDSIZE16) {
783 set_dma_x_modify(drv_data->dma_channel, 2);
784 dma_width = WDSIZE_16;
785 } else {
786 set_dma_x_modify(drv_data->dma_channel, 1);
787 dma_width = WDSIZE_8;
788 }
789
790 /* poll for SPI completion before start */
791 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
792 cpu_relax();
793
794 /* dirty hack for autobuffer DMA mode */
795 if (drv_data->tx_dma == 0xFFFF) {
796 dev_dbg(&drv_data->pdev->dev,
797 "doing autobuffer DMA out.\n");
798
799 /* no irq in autobuffer mode */
800 dma_config =
801 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
802 set_dma_config(drv_data->dma_channel, dma_config);
803 set_dma_start_addr(drv_data->dma_channel,
804 (unsigned long)drv_data->tx);
805 enable_dma(drv_data->dma_channel);
806
807 /* start SPI transfer */
808 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
809
810 /* just return here, there can only be one transfer
811 * in this mode
812 */
813 message->status = 0;
814 giveback(drv_data);
815 return;
816 }
817
818 /* In dma mode, rx or tx must be NULL in one transfer */
819 dma_config = (RESTART | dma_width | DI_EN);
820 if (drv_data->rx != NULL) {
821 /* set transfer mode, and enable SPI */
822 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
823 drv_data->rx, drv_data->len_in_bytes);
824
825 /* invalidate caches, if needed */
826 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
827 invalidate_dcache_range((unsigned long) drv_data->rx,
828 (unsigned long) (drv_data->rx +
829 drv_data->len_in_bytes));
830
831 /* clear tx reg soformer data is not shifted out */
832 write_TDBR(drv_data, 0xFFFF);
833
834 dma_config |= WNR;
835 dma_start_addr = (unsigned long)drv_data->rx;
836 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
837
838 } else if (drv_data->tx != NULL) {
839 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
840
841 /* flush caches, if needed */
842 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
843 flush_dcache_range((unsigned long) drv_data->tx,
844 (unsigned long) (drv_data->tx +
845 drv_data->len_in_bytes));
846
847 dma_start_addr = (unsigned long)drv_data->tx;
848 cr |= BIT_CTL_TIMOD_DMA_TX;
849
850 } else
851 BUG();
852
853 /* oh man, here there be monsters ... and i dont mean the
854 * fluffy cute ones from pixar, i mean the kind that'll eat
855 * your data, kick your dog, and love it all. do *not* try
856 * and change these lines unless you (1) heavily test DMA
857 * with SPI flashes on a loaded system (e.g. ping floods),
858 * (2) know just how broken the DMA engine interaction with
859 * the SPI peripheral is, and (3) have someone else to blame
860 * when you screw it all up anyways.
861 */
862 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
863 set_dma_config(drv_data->dma_channel, dma_config);
864 local_irq_save(flags);
865 SSYNC();
866 write_CTRL(drv_data, cr);
867 enable_dma(drv_data->dma_channel);
868 dma_enable_irq(drv_data->dma_channel);
869 local_irq_restore(flags);
870
871 } else {
872 /* IO mode write then read */
873 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
874
875 if (full_duplex) {
876 /* full duplex mode */
877 BUG_ON((drv_data->tx_end - drv_data->tx) !=
878 (drv_data->rx_end - drv_data->rx));
879 dev_dbg(&drv_data->pdev->dev,
880 "IO duplex: cr is 0x%x\n", cr);
881
882 /* set SPI transfer mode */
883 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
884
885 drv_data->duplex(drv_data);
886
887 if (drv_data->tx != drv_data->tx_end)
888 tranf_success = 0;
889 } else if (drv_data->tx != NULL) {
890 /* write only half duplex */
891 dev_dbg(&drv_data->pdev->dev,
892 "IO write: cr is 0x%x\n", cr);
893
894 /* set SPI transfer mode */
895 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
896
897 drv_data->write(drv_data);
898
899 if (drv_data->tx != drv_data->tx_end)
900 tranf_success = 0;
901 } else if (drv_data->rx != NULL) {
902 /* read only half duplex */
903 dev_dbg(&drv_data->pdev->dev,
904 "IO read: cr is 0x%x\n", cr);
905
906 /* set SPI transfer mode */
907 write_CTRL(drv_data, (cr | CFG_SPI_READ));
908
909 drv_data->read(drv_data);
910 if (drv_data->rx != drv_data->rx_end)
911 tranf_success = 0;
912 }
913
914 if (!tranf_success) {
915 dev_dbg(&drv_data->pdev->dev,
916 "IO write error!\n");
917 message->state = ERROR_STATE;
918 } else {
919 /* Update total byte transfered */
920 message->actual_length += drv_data->len_in_bytes;
921
922 /* Move to next transfer of this msg */
923 message->state = next_transfer(drv_data);
924 }
925
926 /* Schedule next transfer tasklet */
927 tasklet_schedule(&drv_data->pump_transfers);
928
929 }
930 }
931
932 /* pop a msg from queue and kick off real transfer */
933 static void pump_messages(struct work_struct *work)
934 {
935 struct driver_data *drv_data;
936 unsigned long flags;
937
938 drv_data = container_of(work, struct driver_data, pump_messages);
939
940 /* Lock queue and check for queue work */
941 spin_lock_irqsave(&drv_data->lock, flags);
942 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
943 /* pumper kicked off but no work to do */
944 drv_data->busy = 0;
945 spin_unlock_irqrestore(&drv_data->lock, flags);
946 return;
947 }
948
949 /* Make sure we are not already running a message */
950 if (drv_data->cur_msg) {
951 spin_unlock_irqrestore(&drv_data->lock, flags);
952 return;
953 }
954
955 /* Extract head of queue */
956 drv_data->cur_msg = list_entry(drv_data->queue.next,
957 struct spi_message, queue);
958
959 /* Setup the SSP using the per chip configuration */
960 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
961 restore_state(drv_data);
962
963 list_del_init(&drv_data->cur_msg->queue);
964
965 /* Initial message state */
966 drv_data->cur_msg->state = START_STATE;
967 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
968 struct spi_transfer, transfer_list);
969
970 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
971 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
972 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
973 drv_data->cur_chip->ctl_reg);
974
975 dev_dbg(&drv_data->pdev->dev,
976 "the first transfer len is %d\n",
977 drv_data->cur_transfer->len);
978
979 /* Mark as busy and launch transfers */
980 tasklet_schedule(&drv_data->pump_transfers);
981
982 drv_data->busy = 1;
983 spin_unlock_irqrestore(&drv_data->lock, flags);
984 }
985
986 /*
987 * got a msg to transfer, queue it in drv_data->queue.
988 * And kick off message pumper
989 */
990 static int transfer(struct spi_device *spi, struct spi_message *msg)
991 {
992 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
993 unsigned long flags;
994
995 spin_lock_irqsave(&drv_data->lock, flags);
996
997 if (drv_data->run == QUEUE_STOPPED) {
998 spin_unlock_irqrestore(&drv_data->lock, flags);
999 return -ESHUTDOWN;
1000 }
1001
1002 msg->actual_length = 0;
1003 msg->status = -EINPROGRESS;
1004 msg->state = START_STATE;
1005
1006 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
1007 list_add_tail(&msg->queue, &drv_data->queue);
1008
1009 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1010 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1011
1012 spin_unlock_irqrestore(&drv_data->lock, flags);
1013
1014 return 0;
1015 }
1016
1017 #define MAX_SPI_SSEL 7
1018
1019 static u16 ssel[][MAX_SPI_SSEL] = {
1020 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1021 P_SPI0_SSEL4, P_SPI0_SSEL5,
1022 P_SPI0_SSEL6, P_SPI0_SSEL7},
1023
1024 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1025 P_SPI1_SSEL4, P_SPI1_SSEL5,
1026 P_SPI1_SSEL6, P_SPI1_SSEL7},
1027
1028 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1029 P_SPI2_SSEL4, P_SPI2_SSEL5,
1030 P_SPI2_SSEL6, P_SPI2_SSEL7},
1031 };
1032
1033 /* first setup for new devices */
1034 static int setup(struct spi_device *spi)
1035 {
1036 struct bfin5xx_spi_chip *chip_info = NULL;
1037 struct chip_data *chip;
1038 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1039 u8 spi_flg;
1040
1041 /* Abort device setup if requested features are not supported */
1042 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1043 dev_err(&spi->dev, "requested mode not fully supported\n");
1044 return -EINVAL;
1045 }
1046
1047 /* Zero (the default) here means 8 bits */
1048 if (!spi->bits_per_word)
1049 spi->bits_per_word = 8;
1050
1051 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1052 return -EINVAL;
1053
1054 /* Only alloc (or use chip_info) on first setup */
1055 chip = spi_get_ctldata(spi);
1056 if (chip == NULL) {
1057 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1058 if (!chip)
1059 return -ENOMEM;
1060
1061 chip->enable_dma = 0;
1062 chip_info = spi->controller_data;
1063 }
1064
1065 /* chip_info isn't always needed */
1066 if (chip_info) {
1067 /* Make sure people stop trying to set fields via ctl_reg
1068 * when they should actually be using common SPI framework.
1069 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1070 * Not sure if a user actually needs/uses any of these,
1071 * but let's assume (for now) they do.
1072 */
1073 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1074 dev_err(&spi->dev, "do not set bits in ctl_reg "
1075 "that the SPI framework manages\n");
1076 return -EINVAL;
1077 }
1078
1079 chip->enable_dma = chip_info->enable_dma != 0
1080 && drv_data->master_info->enable_dma;
1081 chip->ctl_reg = chip_info->ctl_reg;
1082 chip->bits_per_word = chip_info->bits_per_word;
1083 chip->cs_change_per_word = chip_info->cs_change_per_word;
1084 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1085 }
1086
1087 /* translate common spi framework into our register */
1088 if (spi->mode & SPI_CPOL)
1089 chip->ctl_reg |= CPOL;
1090 if (spi->mode & SPI_CPHA)
1091 chip->ctl_reg |= CPHA;
1092 if (spi->mode & SPI_LSB_FIRST)
1093 chip->ctl_reg |= LSBF;
1094 /* we dont support running in slave mode (yet?) */
1095 chip->ctl_reg |= MSTR;
1096
1097 /*
1098 * if any one SPI chip is registered and wants DMA, request the
1099 * DMA channel for it
1100 */
1101 if (chip->enable_dma && !drv_data->dma_requested) {
1102 /* register dma irq handler */
1103 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1104 dev_dbg(&spi->dev,
1105 "Unable to request BlackFin SPI DMA channel\n");
1106 return -ENODEV;
1107 }
1108 if (set_dma_callback(drv_data->dma_channel,
1109 dma_irq_handler, drv_data) < 0) {
1110 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1111 return -EPERM;
1112 }
1113 dma_disable_irq(drv_data->dma_channel);
1114 drv_data->dma_requested = 1;
1115 }
1116
1117 /*
1118 * Notice: for blackfin, the speed_hz is the value of register
1119 * SPI_BAUD, not the real baudrate
1120 */
1121 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1122 spi_flg = ~(1 << (spi->chip_select));
1123 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1124 chip->chip_select_num = spi->chip_select;
1125
1126 switch (chip->bits_per_word) {
1127 case 8:
1128 chip->n_bytes = 1;
1129 chip->width = CFG_SPI_WORDSIZE8;
1130 chip->read = chip->cs_change_per_word ?
1131 u8_cs_chg_reader : u8_reader;
1132 chip->write = chip->cs_change_per_word ?
1133 u8_cs_chg_writer : u8_writer;
1134 chip->duplex = chip->cs_change_per_word ?
1135 u8_cs_chg_duplex : u8_duplex;
1136 break;
1137
1138 case 16:
1139 chip->n_bytes = 2;
1140 chip->width = CFG_SPI_WORDSIZE16;
1141 chip->read = chip->cs_change_per_word ?
1142 u16_cs_chg_reader : u16_reader;
1143 chip->write = chip->cs_change_per_word ?
1144 u16_cs_chg_writer : u16_writer;
1145 chip->duplex = chip->cs_change_per_word ?
1146 u16_cs_chg_duplex : u16_duplex;
1147 break;
1148
1149 default:
1150 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1151 chip->bits_per_word);
1152 kfree(chip);
1153 return -ENODEV;
1154 }
1155
1156 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1157 spi->modalias, chip->width, chip->enable_dma);
1158 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1159 chip->ctl_reg, chip->flag);
1160
1161 spi_set_ctldata(spi, chip);
1162
1163 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1164 if ((chip->chip_select_num > 0)
1165 && (chip->chip_select_num <= spi->master->num_chipselect))
1166 peripheral_request(ssel[spi->master->bus_num]
1167 [chip->chip_select_num-1], spi->modalias);
1168
1169 cs_deactive(drv_data, chip);
1170
1171 return 0;
1172 }
1173
1174 /*
1175 * callback for spi framework.
1176 * clean driver specific data
1177 */
1178 static void cleanup(struct spi_device *spi)
1179 {
1180 struct chip_data *chip = spi_get_ctldata(spi);
1181
1182 if ((chip->chip_select_num > 0)
1183 && (chip->chip_select_num <= spi->master->num_chipselect))
1184 peripheral_free(ssel[spi->master->bus_num]
1185 [chip->chip_select_num-1]);
1186
1187 kfree(chip);
1188 }
1189
1190 static inline int init_queue(struct driver_data *drv_data)
1191 {
1192 INIT_LIST_HEAD(&drv_data->queue);
1193 spin_lock_init(&drv_data->lock);
1194
1195 drv_data->run = QUEUE_STOPPED;
1196 drv_data->busy = 0;
1197
1198 /* init transfer tasklet */
1199 tasklet_init(&drv_data->pump_transfers,
1200 pump_transfers, (unsigned long)drv_data);
1201
1202 /* init messages workqueue */
1203 INIT_WORK(&drv_data->pump_messages, pump_messages);
1204 drv_data->workqueue = create_singlethread_workqueue(
1205 dev_name(drv_data->master->dev.parent));
1206 if (drv_data->workqueue == NULL)
1207 return -EBUSY;
1208
1209 return 0;
1210 }
1211
1212 static inline int start_queue(struct driver_data *drv_data)
1213 {
1214 unsigned long flags;
1215
1216 spin_lock_irqsave(&drv_data->lock, flags);
1217
1218 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1219 spin_unlock_irqrestore(&drv_data->lock, flags);
1220 return -EBUSY;
1221 }
1222
1223 drv_data->run = QUEUE_RUNNING;
1224 drv_data->cur_msg = NULL;
1225 drv_data->cur_transfer = NULL;
1226 drv_data->cur_chip = NULL;
1227 spin_unlock_irqrestore(&drv_data->lock, flags);
1228
1229 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1230
1231 return 0;
1232 }
1233
1234 static inline int stop_queue(struct driver_data *drv_data)
1235 {
1236 unsigned long flags;
1237 unsigned limit = 500;
1238 int status = 0;
1239
1240 spin_lock_irqsave(&drv_data->lock, flags);
1241
1242 /*
1243 * This is a bit lame, but is optimized for the common execution path.
1244 * A wait_queue on the drv_data->busy could be used, but then the common
1245 * execution path (pump_messages) would be required to call wake_up or
1246 * friends on every SPI message. Do this instead
1247 */
1248 drv_data->run = QUEUE_STOPPED;
1249 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1250 spin_unlock_irqrestore(&drv_data->lock, flags);
1251 msleep(10);
1252 spin_lock_irqsave(&drv_data->lock, flags);
1253 }
1254
1255 if (!list_empty(&drv_data->queue) || drv_data->busy)
1256 status = -EBUSY;
1257
1258 spin_unlock_irqrestore(&drv_data->lock, flags);
1259
1260 return status;
1261 }
1262
1263 static inline int destroy_queue(struct driver_data *drv_data)
1264 {
1265 int status;
1266
1267 status = stop_queue(drv_data);
1268 if (status != 0)
1269 return status;
1270
1271 destroy_workqueue(drv_data->workqueue);
1272
1273 return 0;
1274 }
1275
1276 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1277 {
1278 struct device *dev = &pdev->dev;
1279 struct bfin5xx_spi_master *platform_info;
1280 struct spi_master *master;
1281 struct driver_data *drv_data = 0;
1282 struct resource *res;
1283 int status = 0;
1284
1285 platform_info = dev->platform_data;
1286
1287 /* Allocate master with space for drv_data */
1288 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1289 if (!master) {
1290 dev_err(&pdev->dev, "can not alloc spi_master\n");
1291 return -ENOMEM;
1292 }
1293
1294 drv_data = spi_master_get_devdata(master);
1295 drv_data->master = master;
1296 drv_data->master_info = platform_info;
1297 drv_data->pdev = pdev;
1298 drv_data->pin_req = platform_info->pin_req;
1299
1300 master->bus_num = pdev->id;
1301 master->num_chipselect = platform_info->num_chipselect;
1302 master->cleanup = cleanup;
1303 master->setup = setup;
1304 master->transfer = transfer;
1305
1306 /* Find and map our resources */
1307 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1308 if (res == NULL) {
1309 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1310 status = -ENOENT;
1311 goto out_error_get_res;
1312 }
1313
1314 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1315 if (drv_data->regs_base == NULL) {
1316 dev_err(dev, "Cannot map IO\n");
1317 status = -ENXIO;
1318 goto out_error_ioremap;
1319 }
1320
1321 drv_data->dma_channel = platform_get_irq(pdev, 0);
1322 if (drv_data->dma_channel < 0) {
1323 dev_err(dev, "No DMA channel specified\n");
1324 status = -ENOENT;
1325 goto out_error_no_dma_ch;
1326 }
1327
1328 /* Initial and start queue */
1329 status = init_queue(drv_data);
1330 if (status != 0) {
1331 dev_err(dev, "problem initializing queue\n");
1332 goto out_error_queue_alloc;
1333 }
1334
1335 status = start_queue(drv_data);
1336 if (status != 0) {
1337 dev_err(dev, "problem starting queue\n");
1338 goto out_error_queue_alloc;
1339 }
1340
1341 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1342 if (status != 0) {
1343 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1344 goto out_error_queue_alloc;
1345 }
1346
1347 /* Register with the SPI framework */
1348 platform_set_drvdata(pdev, drv_data);
1349 status = spi_register_master(master);
1350 if (status != 0) {
1351 dev_err(dev, "problem registering spi master\n");
1352 goto out_error_queue_alloc;
1353 }
1354
1355 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1356 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1357 drv_data->dma_channel);
1358 return status;
1359
1360 out_error_queue_alloc:
1361 destroy_queue(drv_data);
1362 out_error_no_dma_ch:
1363 iounmap((void *) drv_data->regs_base);
1364 out_error_ioremap:
1365 out_error_get_res:
1366 spi_master_put(master);
1367
1368 return status;
1369 }
1370
1371 /* stop hardware and remove the driver */
1372 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1373 {
1374 struct driver_data *drv_data = platform_get_drvdata(pdev);
1375 int status = 0;
1376
1377 if (!drv_data)
1378 return 0;
1379
1380 /* Remove the queue */
1381 status = destroy_queue(drv_data);
1382 if (status != 0)
1383 return status;
1384
1385 /* Disable the SSP at the peripheral and SOC level */
1386 bfin_spi_disable(drv_data);
1387
1388 /* Release DMA */
1389 if (drv_data->master_info->enable_dma) {
1390 if (dma_channel_active(drv_data->dma_channel))
1391 free_dma(drv_data->dma_channel);
1392 }
1393
1394 /* Disconnect from the SPI framework */
1395 spi_unregister_master(drv_data->master);
1396
1397 peripheral_free_list(drv_data->pin_req);
1398
1399 /* Prevent double remove */
1400 platform_set_drvdata(pdev, NULL);
1401
1402 return 0;
1403 }
1404
1405 #ifdef CONFIG_PM
1406 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1407 {
1408 struct driver_data *drv_data = platform_get_drvdata(pdev);
1409 int status = 0;
1410
1411 status = stop_queue(drv_data);
1412 if (status != 0)
1413 return status;
1414
1415 /* stop hardware */
1416 bfin_spi_disable(drv_data);
1417
1418 return 0;
1419 }
1420
1421 static int bfin5xx_spi_resume(struct platform_device *pdev)
1422 {
1423 struct driver_data *drv_data = platform_get_drvdata(pdev);
1424 int status = 0;
1425
1426 /* Enable the SPI interface */
1427 bfin_spi_enable(drv_data);
1428
1429 /* Start the queue running */
1430 status = start_queue(drv_data);
1431 if (status != 0) {
1432 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1433 return status;
1434 }
1435
1436 return 0;
1437 }
1438 #else
1439 #define bfin5xx_spi_suspend NULL
1440 #define bfin5xx_spi_resume NULL
1441 #endif /* CONFIG_PM */
1442
1443 MODULE_ALIAS("platform:bfin-spi");
1444 static struct platform_driver bfin5xx_spi_driver = {
1445 .driver = {
1446 .name = DRV_NAME,
1447 .owner = THIS_MODULE,
1448 },
1449 .suspend = bfin5xx_spi_suspend,
1450 .resume = bfin5xx_spi_resume,
1451 .remove = __devexit_p(bfin5xx_spi_remove),
1452 };
1453
1454 static int __init bfin5xx_spi_init(void)
1455 {
1456 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1457 }
1458 module_init(bfin5xx_spi_init);
1459
1460 static void __exit bfin5xx_spi_exit(void)
1461 {
1462 platform_driver_unregister(&bfin5xx_spi_driver);
1463 }
1464 module_exit(bfin5xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)