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Blackfin SPI Driver: Fix erroneous SPI Clock divisor calculation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi_bfin5xx.c
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/dma.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28
29 /* reserved_mem_dcache_on and cache friends */
30 #include <asm/cplbinit.h>
31 #include <asm/cacheflush.h>
32
33 #define DRV_NAME "bfin-spi"
34 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
35 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
36 #define DRV_VERSION "1.0"
37
38 MODULE_AUTHOR(DRV_AUTHOR);
39 MODULE_DESCRIPTION(DRV_DESC);
40 MODULE_LICENSE("GPL");
41
42 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
43
44 #define START_STATE ((void *)0)
45 #define RUNNING_STATE ((void *)1)
46 #define DONE_STATE ((void *)2)
47 #define ERROR_STATE ((void *)-1)
48 #define QUEUE_RUNNING 0
49 #define QUEUE_STOPPED 1
50
51 struct driver_data {
52 /* Driver model hookup */
53 struct platform_device *pdev;
54
55 /* SPI framework hookup */
56 struct spi_master *master;
57
58 /* Regs base of SPI controller */
59 void __iomem *regs_base;
60
61 /* Pin request list */
62 u16 *pin_req;
63
64 /* BFIN hookup */
65 struct bfin5xx_spi_master *master_info;
66
67 /* Driver message queue */
68 struct workqueue_struct *workqueue;
69 struct work_struct pump_messages;
70 spinlock_t lock;
71 struct list_head queue;
72 int busy;
73 int run;
74
75 /* Message Transfer pump */
76 struct tasklet_struct pump_transfers;
77
78 /* Current message transfer state info */
79 struct spi_message *cur_msg;
80 struct spi_transfer *cur_transfer;
81 struct chip_data *cur_chip;
82 size_t len_in_bytes;
83 size_t len;
84 void *tx;
85 void *tx_end;
86 void *rx;
87 void *rx_end;
88
89 /* DMA stuffs */
90 int dma_channel;
91 int dma_mapped;
92 int dma_requested;
93 dma_addr_t rx_dma;
94 dma_addr_t tx_dma;
95
96 size_t rx_map_len;
97 size_t tx_map_len;
98 u8 n_bytes;
99 int cs_change;
100 void (*write) (struct driver_data *);
101 void (*read) (struct driver_data *);
102 void (*duplex) (struct driver_data *);
103 };
104
105 struct chip_data {
106 u16 ctl_reg;
107 u16 baud;
108 u16 flag;
109
110 u8 chip_select_num;
111 u8 n_bytes;
112 u8 width; /* 0 or 1 */
113 u8 enable_dma;
114 u8 bits_per_word; /* 8 or 16 */
115 u8 cs_change_per_word;
116 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
117 void (*write) (struct driver_data *);
118 void (*read) (struct driver_data *);
119 void (*duplex) (struct driver_data *);
120 };
121
122 #define DEFINE_SPI_REG(reg, off) \
123 static inline u16 read_##reg(struct driver_data *drv_data) \
124 { return bfin_read16(drv_data->regs_base + off); } \
125 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
126 { bfin_write16(drv_data->regs_base + off, v); }
127
128 DEFINE_SPI_REG(CTRL, 0x00)
129 DEFINE_SPI_REG(FLAG, 0x04)
130 DEFINE_SPI_REG(STAT, 0x08)
131 DEFINE_SPI_REG(TDBR, 0x0C)
132 DEFINE_SPI_REG(RDBR, 0x10)
133 DEFINE_SPI_REG(BAUD, 0x14)
134 DEFINE_SPI_REG(SHAW, 0x18)
135
136 static void bfin_spi_enable(struct driver_data *drv_data)
137 {
138 u16 cr;
139
140 cr = read_CTRL(drv_data);
141 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
142 }
143
144 static void bfin_spi_disable(struct driver_data *drv_data)
145 {
146 u16 cr;
147
148 cr = read_CTRL(drv_data);
149 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
150 }
151
152 /* Caculate the SPI_BAUD register value based on input HZ */
153 static u16 hz_to_spi_baud(u32 speed_hz)
154 {
155 u_long sclk = get_sclk();
156 u16 spi_baud = (sclk / (2 * speed_hz));
157
158 if ((sclk % (2 * speed_hz)) > 0)
159 spi_baud++;
160
161 if (spi_baud < MIN_SPI_BAUD_VAL)
162 spi_baud = MIN_SPI_BAUD_VAL;
163
164 return spi_baud;
165 }
166
167 static int flush(struct driver_data *drv_data)
168 {
169 unsigned long limit = loops_per_jiffy << 1;
170
171 /* wait for stop and clear stat */
172 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
173 cpu_relax();
174
175 write_STAT(drv_data, BIT_STAT_CLR);
176
177 return limit;
178 }
179
180 /* Chip select operation functions for cs_change flag */
181 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
182 {
183 u16 flag = read_FLAG(drv_data);
184
185 flag |= chip->flag;
186 flag &= ~(chip->flag << 8);
187
188 write_FLAG(drv_data, flag);
189 }
190
191 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
192 {
193 u16 flag = read_FLAG(drv_data);
194
195 flag |= (chip->flag << 8);
196
197 write_FLAG(drv_data, flag);
198
199 /* Move delay here for consistency */
200 if (chip->cs_chg_udelay)
201 udelay(chip->cs_chg_udelay);
202 }
203
204 #define MAX_SPI_SSEL 7
205
206 /* stop controller and re-config current chip*/
207 static void restore_state(struct driver_data *drv_data)
208 {
209 struct chip_data *chip = drv_data->cur_chip;
210
211 /* Clear status and disable clock */
212 write_STAT(drv_data, BIT_STAT_CLR);
213 bfin_spi_disable(drv_data);
214 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
215
216 /* Load the registers */
217 write_CTRL(drv_data, chip->ctl_reg);
218 write_BAUD(drv_data, chip->baud);
219
220 bfin_spi_enable(drv_data);
221 cs_active(drv_data, chip);
222 }
223
224 /* used to kick off transfer in rx mode */
225 static unsigned short dummy_read(struct driver_data *drv_data)
226 {
227 unsigned short tmp;
228 tmp = read_RDBR(drv_data);
229 return tmp;
230 }
231
232 static void null_writer(struct driver_data *drv_data)
233 {
234 u8 n_bytes = drv_data->n_bytes;
235
236 while (drv_data->tx < drv_data->tx_end) {
237 write_TDBR(drv_data, 0);
238 while ((read_STAT(drv_data) & BIT_STAT_TXS))
239 cpu_relax();
240 drv_data->tx += n_bytes;
241 }
242 }
243
244 static void null_reader(struct driver_data *drv_data)
245 {
246 u8 n_bytes = drv_data->n_bytes;
247 dummy_read(drv_data);
248
249 while (drv_data->rx < drv_data->rx_end) {
250 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
251 cpu_relax();
252 dummy_read(drv_data);
253 drv_data->rx += n_bytes;
254 }
255 }
256
257 static void u8_writer(struct driver_data *drv_data)
258 {
259 dev_dbg(&drv_data->pdev->dev,
260 "cr8-s is 0x%x\n", read_STAT(drv_data));
261
262 while (drv_data->tx < drv_data->tx_end) {
263 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
264 while (read_STAT(drv_data) & BIT_STAT_TXS)
265 cpu_relax();
266 ++drv_data->tx;
267 }
268
269 /* poll for SPI completion before return */
270 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
271 cpu_relax();
272 }
273
274 static void u8_cs_chg_writer(struct driver_data *drv_data)
275 {
276 struct chip_data *chip = drv_data->cur_chip;
277
278 while (drv_data->tx < drv_data->tx_end) {
279 cs_active(drv_data, chip);
280
281 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
282 while (read_STAT(drv_data) & BIT_STAT_TXS)
283 cpu_relax();
284 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
285 cpu_relax();
286
287 cs_deactive(drv_data, chip);
288
289 ++drv_data->tx;
290 }
291 }
292
293 static void u8_reader(struct driver_data *drv_data)
294 {
295 dev_dbg(&drv_data->pdev->dev,
296 "cr-8 is 0x%x\n", read_STAT(drv_data));
297
298 /* poll for SPI completion before start */
299 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
300 cpu_relax();
301
302 /* clear TDBR buffer before read(else it will be shifted out) */
303 write_TDBR(drv_data, 0xFFFF);
304
305 dummy_read(drv_data);
306
307 while (drv_data->rx < drv_data->rx_end - 1) {
308 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
309 cpu_relax();
310 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
311 ++drv_data->rx;
312 }
313
314 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
315 cpu_relax();
316 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
317 ++drv_data->rx;
318 }
319
320 static void u8_cs_chg_reader(struct driver_data *drv_data)
321 {
322 struct chip_data *chip = drv_data->cur_chip;
323
324 while (drv_data->rx < drv_data->rx_end) {
325 cs_active(drv_data, chip);
326 read_RDBR(drv_data); /* kick off */
327
328 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
329 cpu_relax();
330 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
331 cpu_relax();
332
333 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
334 cs_deactive(drv_data, chip);
335
336 ++drv_data->rx;
337 }
338 }
339
340 static void u8_duplex(struct driver_data *drv_data)
341 {
342 /* in duplex mode, clk is triggered by writing of TDBR */
343 while (drv_data->rx < drv_data->rx_end) {
344 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
345 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
346 cpu_relax();
347 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
348 cpu_relax();
349 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
350 ++drv_data->rx;
351 ++drv_data->tx;
352 }
353 }
354
355 static void u8_cs_chg_duplex(struct driver_data *drv_data)
356 {
357 struct chip_data *chip = drv_data->cur_chip;
358
359 while (drv_data->rx < drv_data->rx_end) {
360 cs_active(drv_data, chip);
361
362 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
363
364 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
365 cpu_relax();
366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
367 cpu_relax();
368 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
369
370 cs_deactive(drv_data, chip);
371
372 ++drv_data->rx;
373 ++drv_data->tx;
374 }
375 }
376
377 static void u16_writer(struct driver_data *drv_data)
378 {
379 dev_dbg(&drv_data->pdev->dev,
380 "cr16 is 0x%x\n", read_STAT(drv_data));
381
382 while (drv_data->tx < drv_data->tx_end) {
383 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
384 while ((read_STAT(drv_data) & BIT_STAT_TXS))
385 cpu_relax();
386 drv_data->tx += 2;
387 }
388
389 /* poll for SPI completion before return */
390 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
391 cpu_relax();
392 }
393
394 static void u16_cs_chg_writer(struct driver_data *drv_data)
395 {
396 struct chip_data *chip = drv_data->cur_chip;
397
398 while (drv_data->tx < drv_data->tx_end) {
399 cs_active(drv_data, chip);
400
401 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
402 while ((read_STAT(drv_data) & BIT_STAT_TXS))
403 cpu_relax();
404 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
405 cpu_relax();
406
407 cs_deactive(drv_data, chip);
408
409 drv_data->tx += 2;
410 }
411 }
412
413 static void u16_reader(struct driver_data *drv_data)
414 {
415 dev_dbg(&drv_data->pdev->dev,
416 "cr-16 is 0x%x\n", read_STAT(drv_data));
417
418 /* poll for SPI completion before start */
419 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
420 cpu_relax();
421
422 /* clear TDBR buffer before read(else it will be shifted out) */
423 write_TDBR(drv_data, 0xFFFF);
424
425 dummy_read(drv_data);
426
427 while (drv_data->rx < (drv_data->rx_end - 2)) {
428 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
429 cpu_relax();
430 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
431 drv_data->rx += 2;
432 }
433
434 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
435 cpu_relax();
436 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
437 drv_data->rx += 2;
438 }
439
440 static void u16_cs_chg_reader(struct driver_data *drv_data)
441 {
442 struct chip_data *chip = drv_data->cur_chip;
443
444 /* poll for SPI completion before start */
445 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
446 cpu_relax();
447
448 /* clear TDBR buffer before read(else it will be shifted out) */
449 write_TDBR(drv_data, 0xFFFF);
450
451 cs_active(drv_data, chip);
452 dummy_read(drv_data);
453
454 while (drv_data->rx < drv_data->rx_end - 2) {
455 cs_deactive(drv_data, chip);
456
457 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
458 cpu_relax();
459 cs_active(drv_data, chip);
460 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
461 drv_data->rx += 2;
462 }
463 cs_deactive(drv_data, chip);
464
465 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
466 cpu_relax();
467 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
468 drv_data->rx += 2;
469 }
470
471 static void u16_duplex(struct driver_data *drv_data)
472 {
473 /* in duplex mode, clk is triggered by writing of TDBR */
474 while (drv_data->tx < drv_data->tx_end) {
475 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
476 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
477 cpu_relax();
478 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
479 cpu_relax();
480 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
481 drv_data->rx += 2;
482 drv_data->tx += 2;
483 }
484 }
485
486 static void u16_cs_chg_duplex(struct driver_data *drv_data)
487 {
488 struct chip_data *chip = drv_data->cur_chip;
489
490 while (drv_data->tx < drv_data->tx_end) {
491 cs_active(drv_data, chip);
492
493 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
494 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
495 cpu_relax();
496 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
497 cpu_relax();
498 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
499
500 cs_deactive(drv_data, chip);
501
502 drv_data->rx += 2;
503 drv_data->tx += 2;
504 }
505 }
506
507 /* test if ther is more transfer to be done */
508 static void *next_transfer(struct driver_data *drv_data)
509 {
510 struct spi_message *msg = drv_data->cur_msg;
511 struct spi_transfer *trans = drv_data->cur_transfer;
512
513 /* Move to next transfer */
514 if (trans->transfer_list.next != &msg->transfers) {
515 drv_data->cur_transfer =
516 list_entry(trans->transfer_list.next,
517 struct spi_transfer, transfer_list);
518 return RUNNING_STATE;
519 } else
520 return DONE_STATE;
521 }
522
523 /*
524 * caller already set message->status;
525 * dma and pio irqs are blocked give finished message back
526 */
527 static void giveback(struct driver_data *drv_data)
528 {
529 struct chip_data *chip = drv_data->cur_chip;
530 struct spi_transfer *last_transfer;
531 unsigned long flags;
532 struct spi_message *msg;
533
534 spin_lock_irqsave(&drv_data->lock, flags);
535 msg = drv_data->cur_msg;
536 drv_data->cur_msg = NULL;
537 drv_data->cur_transfer = NULL;
538 drv_data->cur_chip = NULL;
539 queue_work(drv_data->workqueue, &drv_data->pump_messages);
540 spin_unlock_irqrestore(&drv_data->lock, flags);
541
542 last_transfer = list_entry(msg->transfers.prev,
543 struct spi_transfer, transfer_list);
544
545 msg->state = NULL;
546
547 /* disable chip select signal. And not stop spi in autobuffer mode */
548 if (drv_data->tx_dma != 0xFFFF) {
549 cs_deactive(drv_data, chip);
550 bfin_spi_disable(drv_data);
551 }
552
553 if (!drv_data->cs_change)
554 cs_deactive(drv_data, chip);
555
556 if (msg->complete)
557 msg->complete(msg->context);
558 }
559
560 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
561 {
562 struct driver_data *drv_data = dev_id;
563 struct chip_data *chip = drv_data->cur_chip;
564 struct spi_message *msg = drv_data->cur_msg;
565
566 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
567 clear_dma_irqstat(drv_data->dma_channel);
568
569 /* Wait for DMA to complete */
570 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
571 cpu_relax();
572
573 /*
574 * wait for the last transaction shifted out. HRM states:
575 * at this point there may still be data in the SPI DMA FIFO waiting
576 * to be transmitted ... software needs to poll TXS in the SPI_STAT
577 * register until it goes low for 2 successive reads
578 */
579 if (drv_data->tx != NULL) {
580 while ((read_STAT(drv_data) & TXS) ||
581 (read_STAT(drv_data) & TXS))
582 cpu_relax();
583 }
584
585 while (!(read_STAT(drv_data) & SPIF))
586 cpu_relax();
587
588 msg->actual_length += drv_data->len_in_bytes;
589
590 if (drv_data->cs_change)
591 cs_deactive(drv_data, chip);
592
593 /* Move to next transfer */
594 msg->state = next_transfer(drv_data);
595
596 /* Schedule transfer tasklet */
597 tasklet_schedule(&drv_data->pump_transfers);
598
599 /* free the irq handler before next transfer */
600 dev_dbg(&drv_data->pdev->dev,
601 "disable dma channel irq%d\n",
602 drv_data->dma_channel);
603 dma_disable_irq(drv_data->dma_channel);
604
605 return IRQ_HANDLED;
606 }
607
608 static void pump_transfers(unsigned long data)
609 {
610 struct driver_data *drv_data = (struct driver_data *)data;
611 struct spi_message *message = NULL;
612 struct spi_transfer *transfer = NULL;
613 struct spi_transfer *previous = NULL;
614 struct chip_data *chip = NULL;
615 u8 width;
616 u16 cr, dma_width, dma_config;
617 u32 tranf_success = 1;
618 u8 full_duplex = 0;
619
620 /* Get current state information */
621 message = drv_data->cur_msg;
622 transfer = drv_data->cur_transfer;
623 chip = drv_data->cur_chip;
624
625 /*
626 * if msg is error or done, report it back using complete() callback
627 */
628
629 /* Handle for abort */
630 if (message->state == ERROR_STATE) {
631 message->status = -EIO;
632 giveback(drv_data);
633 return;
634 }
635
636 /* Handle end of message */
637 if (message->state == DONE_STATE) {
638 message->status = 0;
639 giveback(drv_data);
640 return;
641 }
642
643 /* Delay if requested at end of transfer */
644 if (message->state == RUNNING_STATE) {
645 previous = list_entry(transfer->transfer_list.prev,
646 struct spi_transfer, transfer_list);
647 if (previous->delay_usecs)
648 udelay(previous->delay_usecs);
649 }
650
651 /* Setup the transfer state based on the type of transfer */
652 if (flush(drv_data) == 0) {
653 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
654 message->status = -EIO;
655 giveback(drv_data);
656 return;
657 }
658
659 if (transfer->tx_buf != NULL) {
660 drv_data->tx = (void *)transfer->tx_buf;
661 drv_data->tx_end = drv_data->tx + transfer->len;
662 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
663 transfer->tx_buf, drv_data->tx_end);
664 } else {
665 drv_data->tx = NULL;
666 }
667
668 if (transfer->rx_buf != NULL) {
669 full_duplex = transfer->tx_buf != NULL;
670 drv_data->rx = transfer->rx_buf;
671 drv_data->rx_end = drv_data->rx + transfer->len;
672 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
673 transfer->rx_buf, drv_data->rx_end);
674 } else {
675 drv_data->rx = NULL;
676 }
677
678 drv_data->rx_dma = transfer->rx_dma;
679 drv_data->tx_dma = transfer->tx_dma;
680 drv_data->len_in_bytes = transfer->len;
681 drv_data->cs_change = transfer->cs_change;
682
683 /* Bits per word setup */
684 switch (transfer->bits_per_word) {
685 case 8:
686 drv_data->n_bytes = 1;
687 width = CFG_SPI_WORDSIZE8;
688 drv_data->read = chip->cs_change_per_word ?
689 u8_cs_chg_reader : u8_reader;
690 drv_data->write = chip->cs_change_per_word ?
691 u8_cs_chg_writer : u8_writer;
692 drv_data->duplex = chip->cs_change_per_word ?
693 u8_cs_chg_duplex : u8_duplex;
694 break;
695
696 case 16:
697 drv_data->n_bytes = 2;
698 width = CFG_SPI_WORDSIZE16;
699 drv_data->read = chip->cs_change_per_word ?
700 u16_cs_chg_reader : u16_reader;
701 drv_data->write = chip->cs_change_per_word ?
702 u16_cs_chg_writer : u16_writer;
703 drv_data->duplex = chip->cs_change_per_word ?
704 u16_cs_chg_duplex : u16_duplex;
705 break;
706
707 default:
708 /* No change, the same as default setting */
709 drv_data->n_bytes = chip->n_bytes;
710 width = chip->width;
711 drv_data->write = drv_data->tx ? chip->write : null_writer;
712 drv_data->read = drv_data->rx ? chip->read : null_reader;
713 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
714 break;
715 }
716 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
717 cr |= (width << 8);
718 write_CTRL(drv_data, cr);
719
720 if (width == CFG_SPI_WORDSIZE16) {
721 drv_data->len = (transfer->len) >> 1;
722 } else {
723 drv_data->len = transfer->len;
724 }
725 dev_dbg(&drv_data->pdev->dev,
726 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
727 drv_data->write, chip->write, null_writer);
728
729 /* speed and width has been set on per message */
730 message->state = RUNNING_STATE;
731 dma_config = 0;
732
733 /* Speed setup (surely valid because already checked) */
734 if (transfer->speed_hz)
735 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
736 else
737 write_BAUD(drv_data, chip->baud);
738
739 write_STAT(drv_data, BIT_STAT_CLR);
740 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
741 cs_active(drv_data, chip);
742
743 dev_dbg(&drv_data->pdev->dev,
744 "now pumping a transfer: width is %d, len is %d\n",
745 width, transfer->len);
746
747 /*
748 * Try to map dma buffer and do a dma transfer. If successful use,
749 * different way to r/w according to the enable_dma settings and if
750 * we are not doing a full duplex transfer (since the hardware does
751 * not support full duplex DMA transfers).
752 */
753 if (!full_duplex && drv_data->cur_chip->enable_dma
754 && drv_data->len > 6) {
755
756 disable_dma(drv_data->dma_channel);
757 clear_dma_irqstat(drv_data->dma_channel);
758 bfin_spi_disable(drv_data);
759
760 /* config dma channel */
761 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
762 if (width == CFG_SPI_WORDSIZE16) {
763 set_dma_x_count(drv_data->dma_channel, drv_data->len);
764 set_dma_x_modify(drv_data->dma_channel, 2);
765 dma_width = WDSIZE_16;
766 } else {
767 set_dma_x_count(drv_data->dma_channel, drv_data->len);
768 set_dma_x_modify(drv_data->dma_channel, 1);
769 dma_width = WDSIZE_8;
770 }
771
772 /* poll for SPI completion before start */
773 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
774 cpu_relax();
775
776 /* dirty hack for autobuffer DMA mode */
777 if (drv_data->tx_dma == 0xFFFF) {
778 dev_dbg(&drv_data->pdev->dev,
779 "doing autobuffer DMA out.\n");
780
781 /* no irq in autobuffer mode */
782 dma_config =
783 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
784 set_dma_config(drv_data->dma_channel, dma_config);
785 set_dma_start_addr(drv_data->dma_channel,
786 (unsigned long)drv_data->tx);
787 enable_dma(drv_data->dma_channel);
788
789 /* start SPI transfer */
790 write_CTRL(drv_data,
791 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
792
793 /* just return here, there can only be one transfer
794 * in this mode
795 */
796 message->status = 0;
797 giveback(drv_data);
798 return;
799 }
800
801 /* In dma mode, rx or tx must be NULL in one transfer */
802 if (drv_data->rx != NULL) {
803 /* set transfer mode, and enable SPI */
804 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
805
806 /* invalidate caches, if needed */
807 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
808 invalidate_dcache_range((unsigned long) drv_data->rx,
809 (unsigned long) (drv_data->rx +
810 drv_data->len));
811
812 /* clear tx reg soformer data is not shifted out */
813 write_TDBR(drv_data, 0xFFFF);
814
815 set_dma_x_count(drv_data->dma_channel, drv_data->len);
816
817 /* start dma */
818 dma_enable_irq(drv_data->dma_channel);
819 dma_config = (WNR | RESTART | dma_width | DI_EN);
820 set_dma_config(drv_data->dma_channel, dma_config);
821 set_dma_start_addr(drv_data->dma_channel,
822 (unsigned long)drv_data->rx);
823 enable_dma(drv_data->dma_channel);
824
825 /* start SPI transfer */
826 write_CTRL(drv_data,
827 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
828
829 } else if (drv_data->tx != NULL) {
830 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
831
832 /* flush caches, if needed */
833 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
834 flush_dcache_range((unsigned long) drv_data->tx,
835 (unsigned long) (drv_data->tx +
836 drv_data->len));
837
838 /* start dma */
839 dma_enable_irq(drv_data->dma_channel);
840 dma_config = (RESTART | dma_width | DI_EN);
841 set_dma_config(drv_data->dma_channel, dma_config);
842 set_dma_start_addr(drv_data->dma_channel,
843 (unsigned long)drv_data->tx);
844 enable_dma(drv_data->dma_channel);
845
846 /* start SPI transfer */
847 write_CTRL(drv_data,
848 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
849 }
850 } else {
851 /* IO mode write then read */
852 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
853
854 if (full_duplex) {
855 /* full duplex mode */
856 BUG_ON((drv_data->tx_end - drv_data->tx) !=
857 (drv_data->rx_end - drv_data->rx));
858 dev_dbg(&drv_data->pdev->dev,
859 "IO duplex: cr is 0x%x\n", cr);
860
861 /* set SPI transfer mode */
862 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
863
864 drv_data->duplex(drv_data);
865
866 if (drv_data->tx != drv_data->tx_end)
867 tranf_success = 0;
868 } else if (drv_data->tx != NULL) {
869 /* write only half duplex */
870 dev_dbg(&drv_data->pdev->dev,
871 "IO write: cr is 0x%x\n", cr);
872
873 /* set SPI transfer mode */
874 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
875
876 drv_data->write(drv_data);
877
878 if (drv_data->tx != drv_data->tx_end)
879 tranf_success = 0;
880 } else if (drv_data->rx != NULL) {
881 /* read only half duplex */
882 dev_dbg(&drv_data->pdev->dev,
883 "IO read: cr is 0x%x\n", cr);
884
885 /* set SPI transfer mode */
886 write_CTRL(drv_data, (cr | CFG_SPI_READ));
887
888 drv_data->read(drv_data);
889 if (drv_data->rx != drv_data->rx_end)
890 tranf_success = 0;
891 }
892
893 if (!tranf_success) {
894 dev_dbg(&drv_data->pdev->dev,
895 "IO write error!\n");
896 message->state = ERROR_STATE;
897 } else {
898 /* Update total byte transfered */
899 message->actual_length += drv_data->len;
900
901 /* Move to next transfer of this msg */
902 message->state = next_transfer(drv_data);
903 }
904
905 /* Schedule next transfer tasklet */
906 tasklet_schedule(&drv_data->pump_transfers);
907
908 }
909 }
910
911 /* pop a msg from queue and kick off real transfer */
912 static void pump_messages(struct work_struct *work)
913 {
914 struct driver_data *drv_data;
915 unsigned long flags;
916
917 drv_data = container_of(work, struct driver_data, pump_messages);
918
919 /* Lock queue and check for queue work */
920 spin_lock_irqsave(&drv_data->lock, flags);
921 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
922 /* pumper kicked off but no work to do */
923 drv_data->busy = 0;
924 spin_unlock_irqrestore(&drv_data->lock, flags);
925 return;
926 }
927
928 /* Make sure we are not already running a message */
929 if (drv_data->cur_msg) {
930 spin_unlock_irqrestore(&drv_data->lock, flags);
931 return;
932 }
933
934 /* Extract head of queue */
935 drv_data->cur_msg = list_entry(drv_data->queue.next,
936 struct spi_message, queue);
937
938 /* Setup the SSP using the per chip configuration */
939 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
940 restore_state(drv_data);
941
942 list_del_init(&drv_data->cur_msg->queue);
943
944 /* Initial message state */
945 drv_data->cur_msg->state = START_STATE;
946 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
947 struct spi_transfer, transfer_list);
948
949 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
950 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
951 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
952 drv_data->cur_chip->ctl_reg);
953
954 dev_dbg(&drv_data->pdev->dev,
955 "the first transfer len is %d\n",
956 drv_data->cur_transfer->len);
957
958 /* Mark as busy and launch transfers */
959 tasklet_schedule(&drv_data->pump_transfers);
960
961 drv_data->busy = 1;
962 spin_unlock_irqrestore(&drv_data->lock, flags);
963 }
964
965 /*
966 * got a msg to transfer, queue it in drv_data->queue.
967 * And kick off message pumper
968 */
969 static int transfer(struct spi_device *spi, struct spi_message *msg)
970 {
971 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
972 unsigned long flags;
973
974 spin_lock_irqsave(&drv_data->lock, flags);
975
976 if (drv_data->run == QUEUE_STOPPED) {
977 spin_unlock_irqrestore(&drv_data->lock, flags);
978 return -ESHUTDOWN;
979 }
980
981 msg->actual_length = 0;
982 msg->status = -EINPROGRESS;
983 msg->state = START_STATE;
984
985 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
986 list_add_tail(&msg->queue, &drv_data->queue);
987
988 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
989 queue_work(drv_data->workqueue, &drv_data->pump_messages);
990
991 spin_unlock_irqrestore(&drv_data->lock, flags);
992
993 return 0;
994 }
995
996 #define MAX_SPI_SSEL 7
997
998 static u16 ssel[3][MAX_SPI_SSEL] = {
999 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1000 P_SPI0_SSEL4, P_SPI0_SSEL5,
1001 P_SPI0_SSEL6, P_SPI0_SSEL7},
1002
1003 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1004 P_SPI1_SSEL4, P_SPI1_SSEL5,
1005 P_SPI1_SSEL6, P_SPI1_SSEL7},
1006
1007 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1008 P_SPI2_SSEL4, P_SPI2_SSEL5,
1009 P_SPI2_SSEL6, P_SPI2_SSEL7},
1010 };
1011
1012 /* first setup for new devices */
1013 static int setup(struct spi_device *spi)
1014 {
1015 struct bfin5xx_spi_chip *chip_info = NULL;
1016 struct chip_data *chip;
1017 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1018 u8 spi_flg;
1019
1020 /* Abort device setup if requested features are not supported */
1021 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1022 dev_err(&spi->dev, "requested mode not fully supported\n");
1023 return -EINVAL;
1024 }
1025
1026 /* Zero (the default) here means 8 bits */
1027 if (!spi->bits_per_word)
1028 spi->bits_per_word = 8;
1029
1030 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1031 return -EINVAL;
1032
1033 /* Only alloc (or use chip_info) on first setup */
1034 chip = spi_get_ctldata(spi);
1035 if (chip == NULL) {
1036 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1037 if (!chip)
1038 return -ENOMEM;
1039
1040 chip->enable_dma = 0;
1041 chip_info = spi->controller_data;
1042 }
1043
1044 /* chip_info isn't always needed */
1045 if (chip_info) {
1046 /* Make sure people stop trying to set fields via ctl_reg
1047 * when they should actually be using common SPI framework.
1048 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1049 * Not sure if a user actually needs/uses any of these,
1050 * but let's assume (for now) they do.
1051 */
1052 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1053 dev_err(&spi->dev, "do not set bits in ctl_reg "
1054 "that the SPI framework manages\n");
1055 return -EINVAL;
1056 }
1057
1058 chip->enable_dma = chip_info->enable_dma != 0
1059 && drv_data->master_info->enable_dma;
1060 chip->ctl_reg = chip_info->ctl_reg;
1061 chip->bits_per_word = chip_info->bits_per_word;
1062 chip->cs_change_per_word = chip_info->cs_change_per_word;
1063 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1064 }
1065
1066 /* translate common spi framework into our register */
1067 if (spi->mode & SPI_CPOL)
1068 chip->ctl_reg |= CPOL;
1069 if (spi->mode & SPI_CPHA)
1070 chip->ctl_reg |= CPHA;
1071 if (spi->mode & SPI_LSB_FIRST)
1072 chip->ctl_reg |= LSBF;
1073 /* we dont support running in slave mode (yet?) */
1074 chip->ctl_reg |= MSTR;
1075
1076 /*
1077 * if any one SPI chip is registered and wants DMA, request the
1078 * DMA channel for it
1079 */
1080 if (chip->enable_dma && !drv_data->dma_requested) {
1081 /* register dma irq handler */
1082 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1083 dev_dbg(&spi->dev,
1084 "Unable to request BlackFin SPI DMA channel\n");
1085 return -ENODEV;
1086 }
1087 if (set_dma_callback(drv_data->dma_channel,
1088 (void *)dma_irq_handler, drv_data) < 0) {
1089 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1090 return -EPERM;
1091 }
1092 dma_disable_irq(drv_data->dma_channel);
1093 drv_data->dma_requested = 1;
1094 }
1095
1096 /*
1097 * Notice: for blackfin, the speed_hz is the value of register
1098 * SPI_BAUD, not the real baudrate
1099 */
1100 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1101 spi_flg = ~(1 << (spi->chip_select));
1102 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1103 chip->chip_select_num = spi->chip_select;
1104
1105 switch (chip->bits_per_word) {
1106 case 8:
1107 chip->n_bytes = 1;
1108 chip->width = CFG_SPI_WORDSIZE8;
1109 chip->read = chip->cs_change_per_word ?
1110 u8_cs_chg_reader : u8_reader;
1111 chip->write = chip->cs_change_per_word ?
1112 u8_cs_chg_writer : u8_writer;
1113 chip->duplex = chip->cs_change_per_word ?
1114 u8_cs_chg_duplex : u8_duplex;
1115 break;
1116
1117 case 16:
1118 chip->n_bytes = 2;
1119 chip->width = CFG_SPI_WORDSIZE16;
1120 chip->read = chip->cs_change_per_word ?
1121 u16_cs_chg_reader : u16_reader;
1122 chip->write = chip->cs_change_per_word ?
1123 u16_cs_chg_writer : u16_writer;
1124 chip->duplex = chip->cs_change_per_word ?
1125 u16_cs_chg_duplex : u16_duplex;
1126 break;
1127
1128 default:
1129 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1130 chip->bits_per_word);
1131 kfree(chip);
1132 return -ENODEV;
1133 }
1134
1135 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1136 spi->modalias, chip->width, chip->enable_dma);
1137 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1138 chip->ctl_reg, chip->flag);
1139
1140 spi_set_ctldata(spi, chip);
1141
1142 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1143 if ((chip->chip_select_num > 0)
1144 && (chip->chip_select_num <= spi->master->num_chipselect))
1145 peripheral_request(ssel[spi->master->bus_num]
1146 [chip->chip_select_num-1], spi->modalias);
1147
1148 cs_deactive(drv_data, chip);
1149
1150 return 0;
1151 }
1152
1153 /*
1154 * callback for spi framework.
1155 * clean driver specific data
1156 */
1157 static void cleanup(struct spi_device *spi)
1158 {
1159 struct chip_data *chip = spi_get_ctldata(spi);
1160
1161 if ((chip->chip_select_num > 0)
1162 && (chip->chip_select_num <= spi->master->num_chipselect))
1163 peripheral_free(ssel[spi->master->bus_num]
1164 [chip->chip_select_num-1]);
1165
1166 kfree(chip);
1167 }
1168
1169 static inline int init_queue(struct driver_data *drv_data)
1170 {
1171 INIT_LIST_HEAD(&drv_data->queue);
1172 spin_lock_init(&drv_data->lock);
1173
1174 drv_data->run = QUEUE_STOPPED;
1175 drv_data->busy = 0;
1176
1177 /* init transfer tasklet */
1178 tasklet_init(&drv_data->pump_transfers,
1179 pump_transfers, (unsigned long)drv_data);
1180
1181 /* init messages workqueue */
1182 INIT_WORK(&drv_data->pump_messages, pump_messages);
1183 drv_data->workqueue = create_singlethread_workqueue(
1184 dev_name(drv_data->master->dev.parent));
1185 if (drv_data->workqueue == NULL)
1186 return -EBUSY;
1187
1188 return 0;
1189 }
1190
1191 static inline int start_queue(struct driver_data *drv_data)
1192 {
1193 unsigned long flags;
1194
1195 spin_lock_irqsave(&drv_data->lock, flags);
1196
1197 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1198 spin_unlock_irqrestore(&drv_data->lock, flags);
1199 return -EBUSY;
1200 }
1201
1202 drv_data->run = QUEUE_RUNNING;
1203 drv_data->cur_msg = NULL;
1204 drv_data->cur_transfer = NULL;
1205 drv_data->cur_chip = NULL;
1206 spin_unlock_irqrestore(&drv_data->lock, flags);
1207
1208 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1209
1210 return 0;
1211 }
1212
1213 static inline int stop_queue(struct driver_data *drv_data)
1214 {
1215 unsigned long flags;
1216 unsigned limit = 500;
1217 int status = 0;
1218
1219 spin_lock_irqsave(&drv_data->lock, flags);
1220
1221 /*
1222 * This is a bit lame, but is optimized for the common execution path.
1223 * A wait_queue on the drv_data->busy could be used, but then the common
1224 * execution path (pump_messages) would be required to call wake_up or
1225 * friends on every SPI message. Do this instead
1226 */
1227 drv_data->run = QUEUE_STOPPED;
1228 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1229 spin_unlock_irqrestore(&drv_data->lock, flags);
1230 msleep(10);
1231 spin_lock_irqsave(&drv_data->lock, flags);
1232 }
1233
1234 if (!list_empty(&drv_data->queue) || drv_data->busy)
1235 status = -EBUSY;
1236
1237 spin_unlock_irqrestore(&drv_data->lock, flags);
1238
1239 return status;
1240 }
1241
1242 static inline int destroy_queue(struct driver_data *drv_data)
1243 {
1244 int status;
1245
1246 status = stop_queue(drv_data);
1247 if (status != 0)
1248 return status;
1249
1250 destroy_workqueue(drv_data->workqueue);
1251
1252 return 0;
1253 }
1254
1255 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1256 {
1257 struct device *dev = &pdev->dev;
1258 struct bfin5xx_spi_master *platform_info;
1259 struct spi_master *master;
1260 struct driver_data *drv_data = 0;
1261 struct resource *res;
1262 int status = 0;
1263
1264 platform_info = dev->platform_data;
1265
1266 /* Allocate master with space for drv_data */
1267 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1268 if (!master) {
1269 dev_err(&pdev->dev, "can not alloc spi_master\n");
1270 return -ENOMEM;
1271 }
1272
1273 drv_data = spi_master_get_devdata(master);
1274 drv_data->master = master;
1275 drv_data->master_info = platform_info;
1276 drv_data->pdev = pdev;
1277 drv_data->pin_req = platform_info->pin_req;
1278
1279 master->bus_num = pdev->id;
1280 master->num_chipselect = platform_info->num_chipselect;
1281 master->cleanup = cleanup;
1282 master->setup = setup;
1283 master->transfer = transfer;
1284
1285 /* Find and map our resources */
1286 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1287 if (res == NULL) {
1288 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1289 status = -ENOENT;
1290 goto out_error_get_res;
1291 }
1292
1293 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1294 if (drv_data->regs_base == NULL) {
1295 dev_err(dev, "Cannot map IO\n");
1296 status = -ENXIO;
1297 goto out_error_ioremap;
1298 }
1299
1300 drv_data->dma_channel = platform_get_irq(pdev, 0);
1301 if (drv_data->dma_channel < 0) {
1302 dev_err(dev, "No DMA channel specified\n");
1303 status = -ENOENT;
1304 goto out_error_no_dma_ch;
1305 }
1306
1307 /* Initial and start queue */
1308 status = init_queue(drv_data);
1309 if (status != 0) {
1310 dev_err(dev, "problem initializing queue\n");
1311 goto out_error_queue_alloc;
1312 }
1313
1314 status = start_queue(drv_data);
1315 if (status != 0) {
1316 dev_err(dev, "problem starting queue\n");
1317 goto out_error_queue_alloc;
1318 }
1319
1320 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1321 if (status != 0) {
1322 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1323 goto out_error_queue_alloc;
1324 }
1325
1326 /* Register with the SPI framework */
1327 platform_set_drvdata(pdev, drv_data);
1328 status = spi_register_master(master);
1329 if (status != 0) {
1330 dev_err(dev, "problem registering spi master\n");
1331 goto out_error_queue_alloc;
1332 }
1333
1334 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1335 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1336 drv_data->dma_channel);
1337 return status;
1338
1339 out_error_queue_alloc:
1340 destroy_queue(drv_data);
1341 out_error_no_dma_ch:
1342 iounmap((void *) drv_data->regs_base);
1343 out_error_ioremap:
1344 out_error_get_res:
1345 spi_master_put(master);
1346
1347 return status;
1348 }
1349
1350 /* stop hardware and remove the driver */
1351 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1352 {
1353 struct driver_data *drv_data = platform_get_drvdata(pdev);
1354 int status = 0;
1355
1356 if (!drv_data)
1357 return 0;
1358
1359 /* Remove the queue */
1360 status = destroy_queue(drv_data);
1361 if (status != 0)
1362 return status;
1363
1364 /* Disable the SSP at the peripheral and SOC level */
1365 bfin_spi_disable(drv_data);
1366
1367 /* Release DMA */
1368 if (drv_data->master_info->enable_dma) {
1369 if (dma_channel_active(drv_data->dma_channel))
1370 free_dma(drv_data->dma_channel);
1371 }
1372
1373 /* Disconnect from the SPI framework */
1374 spi_unregister_master(drv_data->master);
1375
1376 peripheral_free_list(drv_data->pin_req);
1377
1378 /* Prevent double remove */
1379 platform_set_drvdata(pdev, NULL);
1380
1381 return 0;
1382 }
1383
1384 #ifdef CONFIG_PM
1385 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1386 {
1387 struct driver_data *drv_data = platform_get_drvdata(pdev);
1388 int status = 0;
1389
1390 status = stop_queue(drv_data);
1391 if (status != 0)
1392 return status;
1393
1394 /* stop hardware */
1395 bfin_spi_disable(drv_data);
1396
1397 return 0;
1398 }
1399
1400 static int bfin5xx_spi_resume(struct platform_device *pdev)
1401 {
1402 struct driver_data *drv_data = platform_get_drvdata(pdev);
1403 int status = 0;
1404
1405 /* Enable the SPI interface */
1406 bfin_spi_enable(drv_data);
1407
1408 /* Start the queue running */
1409 status = start_queue(drv_data);
1410 if (status != 0) {
1411 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1412 return status;
1413 }
1414
1415 return 0;
1416 }
1417 #else
1418 #define bfin5xx_spi_suspend NULL
1419 #define bfin5xx_spi_resume NULL
1420 #endif /* CONFIG_PM */
1421
1422 MODULE_ALIAS("platform:bfin-spi");
1423 static struct platform_driver bfin5xx_spi_driver = {
1424 .driver = {
1425 .name = DRV_NAME,
1426 .owner = THIS_MODULE,
1427 },
1428 .suspend = bfin5xx_spi_suspend,
1429 .resume = bfin5xx_spi_resume,
1430 .remove = __devexit_p(bfin5xx_spi_remove),
1431 };
1432
1433 static int __init bfin5xx_spi_init(void)
1434 {
1435 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1436 }
1437 module_init(bfin5xx_spi_init);
1438
1439 static void __exit bfin5xx_spi_exit(void)
1440 {
1441 platform_driver_unregister(&bfin5xx_spi_driver);
1442 }
1443 module_exit(bfin5xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)