2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
29 /* reserved_mem_dcache_on and cache friends */
30 #include <asm/cplbinit.h>
31 #include <asm/cacheflush.h>
33 #define DRV_NAME "bfin-spi"
34 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
35 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
36 #define DRV_VERSION "1.0"
38 MODULE_AUTHOR(DRV_AUTHOR
);
39 MODULE_DESCRIPTION(DRV_DESC
);
40 MODULE_LICENSE("GPL");
42 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
44 #define START_STATE ((void *)0)
45 #define RUNNING_STATE ((void *)1)
46 #define DONE_STATE ((void *)2)
47 #define ERROR_STATE ((void *)-1)
48 #define QUEUE_RUNNING 0
49 #define QUEUE_STOPPED 1
52 /* Driver model hookup */
53 struct platform_device
*pdev
;
55 /* SPI framework hookup */
56 struct spi_master
*master
;
58 /* Regs base of SPI controller */
59 void __iomem
*regs_base
;
61 /* Pin request list */
65 struct bfin5xx_spi_master
*master_info
;
67 /* Driver message queue */
68 struct workqueue_struct
*workqueue
;
69 struct work_struct pump_messages
;
71 struct list_head queue
;
75 /* Message Transfer pump */
76 struct tasklet_struct pump_transfers
;
78 /* Current message transfer state info */
79 struct spi_message
*cur_msg
;
80 struct spi_transfer
*cur_transfer
;
81 struct chip_data
*cur_chip
;
100 void (*write
) (struct driver_data
*);
101 void (*read
) (struct driver_data
*);
102 void (*duplex
) (struct driver_data
*);
112 u8 width
; /* 0 or 1 */
114 u8 bits_per_word
; /* 8 or 16 */
115 u8 cs_change_per_word
;
116 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
117 void (*write
) (struct driver_data
*);
118 void (*read
) (struct driver_data
*);
119 void (*duplex
) (struct driver_data
*);
122 #define DEFINE_SPI_REG(reg, off) \
123 static inline u16 read_##reg(struct driver_data *drv_data) \
124 { return bfin_read16(drv_data->regs_base + off); } \
125 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
126 { bfin_write16(drv_data->regs_base + off, v); }
128 DEFINE_SPI_REG(CTRL
, 0x00)
129 DEFINE_SPI_REG(FLAG
, 0x04)
130 DEFINE_SPI_REG(STAT
, 0x08)
131 DEFINE_SPI_REG(TDBR
, 0x0C)
132 DEFINE_SPI_REG(RDBR
, 0x10)
133 DEFINE_SPI_REG(BAUD
, 0x14)
134 DEFINE_SPI_REG(SHAW
, 0x18)
136 static void bfin_spi_enable(struct driver_data
*drv_data
)
140 cr
= read_CTRL(drv_data
);
141 write_CTRL(drv_data
, (cr
| BIT_CTL_ENABLE
));
144 static void bfin_spi_disable(struct driver_data
*drv_data
)
148 cr
= read_CTRL(drv_data
);
149 write_CTRL(drv_data
, (cr
& (~BIT_CTL_ENABLE
)));
152 /* Caculate the SPI_BAUD register value based on input HZ */
153 static u16
hz_to_spi_baud(u32 speed_hz
)
155 u_long sclk
= get_sclk();
156 u16 spi_baud
= (sclk
/ (2 * speed_hz
));
158 if ((sclk
% (2 * speed_hz
)) > 0)
161 if (spi_baud
< MIN_SPI_BAUD_VAL
)
162 spi_baud
= MIN_SPI_BAUD_VAL
;
167 static int flush(struct driver_data
*drv_data
)
169 unsigned long limit
= loops_per_jiffy
<< 1;
171 /* wait for stop and clear stat */
172 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
) && limit
--)
175 write_STAT(drv_data
, BIT_STAT_CLR
);
180 /* Chip select operation functions for cs_change flag */
181 static void cs_active(struct driver_data
*drv_data
, struct chip_data
*chip
)
183 u16 flag
= read_FLAG(drv_data
);
186 flag
&= ~(chip
->flag
<< 8);
188 write_FLAG(drv_data
, flag
);
191 static void cs_deactive(struct driver_data
*drv_data
, struct chip_data
*chip
)
193 u16 flag
= read_FLAG(drv_data
);
195 flag
|= (chip
->flag
<< 8);
197 write_FLAG(drv_data
, flag
);
199 /* Move delay here for consistency */
200 if (chip
->cs_chg_udelay
)
201 udelay(chip
->cs_chg_udelay
);
204 #define MAX_SPI_SSEL 7
206 /* stop controller and re-config current chip*/
207 static void restore_state(struct driver_data
*drv_data
)
209 struct chip_data
*chip
= drv_data
->cur_chip
;
211 /* Clear status and disable clock */
212 write_STAT(drv_data
, BIT_STAT_CLR
);
213 bfin_spi_disable(drv_data
);
214 dev_dbg(&drv_data
->pdev
->dev
, "restoring spi ctl state\n");
216 /* Load the registers */
217 write_CTRL(drv_data
, chip
->ctl_reg
);
218 write_BAUD(drv_data
, chip
->baud
);
220 bfin_spi_enable(drv_data
);
221 cs_active(drv_data
, chip
);
224 /* used to kick off transfer in rx mode */
225 static unsigned short dummy_read(struct driver_data
*drv_data
)
228 tmp
= read_RDBR(drv_data
);
232 static void null_writer(struct driver_data
*drv_data
)
234 u8 n_bytes
= drv_data
->n_bytes
;
236 while (drv_data
->tx
< drv_data
->tx_end
) {
237 write_TDBR(drv_data
, 0);
238 while ((read_STAT(drv_data
) & BIT_STAT_TXS
))
240 drv_data
->tx
+= n_bytes
;
244 static void null_reader(struct driver_data
*drv_data
)
246 u8 n_bytes
= drv_data
->n_bytes
;
247 dummy_read(drv_data
);
249 while (drv_data
->rx
< drv_data
->rx_end
) {
250 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
252 dummy_read(drv_data
);
253 drv_data
->rx
+= n_bytes
;
257 static void u8_writer(struct driver_data
*drv_data
)
259 dev_dbg(&drv_data
->pdev
->dev
,
260 "cr8-s is 0x%x\n", read_STAT(drv_data
));
262 while (drv_data
->tx
< drv_data
->tx_end
) {
263 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
264 while (read_STAT(drv_data
) & BIT_STAT_TXS
)
269 /* poll for SPI completion before return */
270 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
274 static void u8_cs_chg_writer(struct driver_data
*drv_data
)
276 struct chip_data
*chip
= drv_data
->cur_chip
;
278 while (drv_data
->tx
< drv_data
->tx_end
) {
279 cs_active(drv_data
, chip
);
281 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
282 while (read_STAT(drv_data
) & BIT_STAT_TXS
)
284 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
287 cs_deactive(drv_data
, chip
);
293 static void u8_reader(struct driver_data
*drv_data
)
295 dev_dbg(&drv_data
->pdev
->dev
,
296 "cr-8 is 0x%x\n", read_STAT(drv_data
));
298 /* poll for SPI completion before start */
299 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
302 /* clear TDBR buffer before read(else it will be shifted out) */
303 write_TDBR(drv_data
, 0xFFFF);
305 dummy_read(drv_data
);
307 while (drv_data
->rx
< drv_data
->rx_end
- 1) {
308 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
310 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
314 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
316 *(u8
*) (drv_data
->rx
) = read_SHAW(drv_data
);
320 static void u8_cs_chg_reader(struct driver_data
*drv_data
)
322 struct chip_data
*chip
= drv_data
->cur_chip
;
324 while (drv_data
->rx
< drv_data
->rx_end
) {
325 cs_active(drv_data
, chip
);
326 read_RDBR(drv_data
); /* kick off */
328 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
330 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
333 *(u8
*) (drv_data
->rx
) = read_SHAW(drv_data
);
334 cs_deactive(drv_data
, chip
);
340 static void u8_duplex(struct driver_data
*drv_data
)
342 /* in duplex mode, clk is triggered by writing of TDBR */
343 while (drv_data
->rx
< drv_data
->rx_end
) {
344 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
345 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
347 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
349 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
355 static void u8_cs_chg_duplex(struct driver_data
*drv_data
)
357 struct chip_data
*chip
= drv_data
->cur_chip
;
359 while (drv_data
->rx
< drv_data
->rx_end
) {
360 cs_active(drv_data
, chip
);
362 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
364 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
366 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
368 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
370 cs_deactive(drv_data
, chip
);
377 static void u16_writer(struct driver_data
*drv_data
)
379 dev_dbg(&drv_data
->pdev
->dev
,
380 "cr16 is 0x%x\n", read_STAT(drv_data
));
382 while (drv_data
->tx
< drv_data
->tx_end
) {
383 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
384 while ((read_STAT(drv_data
) & BIT_STAT_TXS
))
389 /* poll for SPI completion before return */
390 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
394 static void u16_cs_chg_writer(struct driver_data
*drv_data
)
396 struct chip_data
*chip
= drv_data
->cur_chip
;
398 while (drv_data
->tx
< drv_data
->tx_end
) {
399 cs_active(drv_data
, chip
);
401 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
402 while ((read_STAT(drv_data
) & BIT_STAT_TXS
))
404 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
407 cs_deactive(drv_data
, chip
);
413 static void u16_reader(struct driver_data
*drv_data
)
415 dev_dbg(&drv_data
->pdev
->dev
,
416 "cr-16 is 0x%x\n", read_STAT(drv_data
));
418 /* poll for SPI completion before start */
419 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
422 /* clear TDBR buffer before read(else it will be shifted out) */
423 write_TDBR(drv_data
, 0xFFFF);
425 dummy_read(drv_data
);
427 while (drv_data
->rx
< (drv_data
->rx_end
- 2)) {
428 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
430 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
434 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
436 *(u16
*) (drv_data
->rx
) = read_SHAW(drv_data
);
440 static void u16_cs_chg_reader(struct driver_data
*drv_data
)
442 struct chip_data
*chip
= drv_data
->cur_chip
;
444 /* poll for SPI completion before start */
445 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
448 /* clear TDBR buffer before read(else it will be shifted out) */
449 write_TDBR(drv_data
, 0xFFFF);
451 cs_active(drv_data
, chip
);
452 dummy_read(drv_data
);
454 while (drv_data
->rx
< drv_data
->rx_end
- 2) {
455 cs_deactive(drv_data
, chip
);
457 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
459 cs_active(drv_data
, chip
);
460 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
463 cs_deactive(drv_data
, chip
);
465 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
467 *(u16
*) (drv_data
->rx
) = read_SHAW(drv_data
);
471 static void u16_duplex(struct driver_data
*drv_data
)
473 /* in duplex mode, clk is triggered by writing of TDBR */
474 while (drv_data
->tx
< drv_data
->tx_end
) {
475 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
476 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
478 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
480 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
486 static void u16_cs_chg_duplex(struct driver_data
*drv_data
)
488 struct chip_data
*chip
= drv_data
->cur_chip
;
490 while (drv_data
->tx
< drv_data
->tx_end
) {
491 cs_active(drv_data
, chip
);
493 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
494 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
496 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
498 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
500 cs_deactive(drv_data
, chip
);
507 /* test if ther is more transfer to be done */
508 static void *next_transfer(struct driver_data
*drv_data
)
510 struct spi_message
*msg
= drv_data
->cur_msg
;
511 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
513 /* Move to next transfer */
514 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
515 drv_data
->cur_transfer
=
516 list_entry(trans
->transfer_list
.next
,
517 struct spi_transfer
, transfer_list
);
518 return RUNNING_STATE
;
524 * caller already set message->status;
525 * dma and pio irqs are blocked give finished message back
527 static void giveback(struct driver_data
*drv_data
)
529 struct chip_data
*chip
= drv_data
->cur_chip
;
530 struct spi_transfer
*last_transfer
;
532 struct spi_message
*msg
;
534 spin_lock_irqsave(&drv_data
->lock
, flags
);
535 msg
= drv_data
->cur_msg
;
536 drv_data
->cur_msg
= NULL
;
537 drv_data
->cur_transfer
= NULL
;
538 drv_data
->cur_chip
= NULL
;
539 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
540 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
542 last_transfer
= list_entry(msg
->transfers
.prev
,
543 struct spi_transfer
, transfer_list
);
547 /* disable chip select signal. And not stop spi in autobuffer mode */
548 if (drv_data
->tx_dma
!= 0xFFFF) {
549 cs_deactive(drv_data
, chip
);
550 bfin_spi_disable(drv_data
);
553 if (!drv_data
->cs_change
)
554 cs_deactive(drv_data
, chip
);
557 msg
->complete(msg
->context
);
560 static irqreturn_t
dma_irq_handler(int irq
, void *dev_id
)
562 struct driver_data
*drv_data
= dev_id
;
563 struct chip_data
*chip
= drv_data
->cur_chip
;
564 struct spi_message
*msg
= drv_data
->cur_msg
;
566 dev_dbg(&drv_data
->pdev
->dev
, "in dma_irq_handler\n");
567 clear_dma_irqstat(drv_data
->dma_channel
);
569 /* Wait for DMA to complete */
570 while (get_dma_curr_irqstat(drv_data
->dma_channel
) & DMA_RUN
)
574 * wait for the last transaction shifted out. HRM states:
575 * at this point there may still be data in the SPI DMA FIFO waiting
576 * to be transmitted ... software needs to poll TXS in the SPI_STAT
577 * register until it goes low for 2 successive reads
579 if (drv_data
->tx
!= NULL
) {
580 while ((read_STAT(drv_data
) & TXS
) ||
581 (read_STAT(drv_data
) & TXS
))
585 while (!(read_STAT(drv_data
) & SPIF
))
588 msg
->actual_length
+= drv_data
->len_in_bytes
;
590 if (drv_data
->cs_change
)
591 cs_deactive(drv_data
, chip
);
593 /* Move to next transfer */
594 msg
->state
= next_transfer(drv_data
);
596 /* Schedule transfer tasklet */
597 tasklet_schedule(&drv_data
->pump_transfers
);
599 /* free the irq handler before next transfer */
600 dev_dbg(&drv_data
->pdev
->dev
,
601 "disable dma channel irq%d\n",
602 drv_data
->dma_channel
);
603 dma_disable_irq(drv_data
->dma_channel
);
608 static void pump_transfers(unsigned long data
)
610 struct driver_data
*drv_data
= (struct driver_data
*)data
;
611 struct spi_message
*message
= NULL
;
612 struct spi_transfer
*transfer
= NULL
;
613 struct spi_transfer
*previous
= NULL
;
614 struct chip_data
*chip
= NULL
;
616 u16 cr
, dma_width
, dma_config
;
617 u32 tranf_success
= 1;
620 /* Get current state information */
621 message
= drv_data
->cur_msg
;
622 transfer
= drv_data
->cur_transfer
;
623 chip
= drv_data
->cur_chip
;
626 * if msg is error or done, report it back using complete() callback
629 /* Handle for abort */
630 if (message
->state
== ERROR_STATE
) {
631 message
->status
= -EIO
;
636 /* Handle end of message */
637 if (message
->state
== DONE_STATE
) {
643 /* Delay if requested at end of transfer */
644 if (message
->state
== RUNNING_STATE
) {
645 previous
= list_entry(transfer
->transfer_list
.prev
,
646 struct spi_transfer
, transfer_list
);
647 if (previous
->delay_usecs
)
648 udelay(previous
->delay_usecs
);
651 /* Setup the transfer state based on the type of transfer */
652 if (flush(drv_data
) == 0) {
653 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
654 message
->status
= -EIO
;
659 if (transfer
->tx_buf
!= NULL
) {
660 drv_data
->tx
= (void *)transfer
->tx_buf
;
661 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
662 dev_dbg(&drv_data
->pdev
->dev
, "tx_buf is %p, tx_end is %p\n",
663 transfer
->tx_buf
, drv_data
->tx_end
);
668 if (transfer
->rx_buf
!= NULL
) {
669 full_duplex
= transfer
->tx_buf
!= NULL
;
670 drv_data
->rx
= transfer
->rx_buf
;
671 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
672 dev_dbg(&drv_data
->pdev
->dev
, "rx_buf is %p, rx_end is %p\n",
673 transfer
->rx_buf
, drv_data
->rx_end
);
678 drv_data
->rx_dma
= transfer
->rx_dma
;
679 drv_data
->tx_dma
= transfer
->tx_dma
;
680 drv_data
->len_in_bytes
= transfer
->len
;
681 drv_data
->cs_change
= transfer
->cs_change
;
683 /* Bits per word setup */
684 switch (transfer
->bits_per_word
) {
686 drv_data
->n_bytes
= 1;
687 width
= CFG_SPI_WORDSIZE8
;
688 drv_data
->read
= chip
->cs_change_per_word
?
689 u8_cs_chg_reader
: u8_reader
;
690 drv_data
->write
= chip
->cs_change_per_word
?
691 u8_cs_chg_writer
: u8_writer
;
692 drv_data
->duplex
= chip
->cs_change_per_word
?
693 u8_cs_chg_duplex
: u8_duplex
;
697 drv_data
->n_bytes
= 2;
698 width
= CFG_SPI_WORDSIZE16
;
699 drv_data
->read
= chip
->cs_change_per_word
?
700 u16_cs_chg_reader
: u16_reader
;
701 drv_data
->write
= chip
->cs_change_per_word
?
702 u16_cs_chg_writer
: u16_writer
;
703 drv_data
->duplex
= chip
->cs_change_per_word
?
704 u16_cs_chg_duplex
: u16_duplex
;
708 /* No change, the same as default setting */
709 drv_data
->n_bytes
= chip
->n_bytes
;
711 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
712 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
713 drv_data
->duplex
= chip
->duplex
? chip
->duplex
: null_writer
;
716 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
718 write_CTRL(drv_data
, cr
);
720 if (width
== CFG_SPI_WORDSIZE16
) {
721 drv_data
->len
= (transfer
->len
) >> 1;
723 drv_data
->len
= transfer
->len
;
725 dev_dbg(&drv_data
->pdev
->dev
,
726 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
727 drv_data
->write
, chip
->write
, null_writer
);
729 /* speed and width has been set on per message */
730 message
->state
= RUNNING_STATE
;
733 /* Speed setup (surely valid because already checked) */
734 if (transfer
->speed_hz
)
735 write_BAUD(drv_data
, hz_to_spi_baud(transfer
->speed_hz
));
737 write_BAUD(drv_data
, chip
->baud
);
739 write_STAT(drv_data
, BIT_STAT_CLR
);
740 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
741 cs_active(drv_data
, chip
);
743 dev_dbg(&drv_data
->pdev
->dev
,
744 "now pumping a transfer: width is %d, len is %d\n",
745 width
, transfer
->len
);
748 * Try to map dma buffer and do a dma transfer. If successful use,
749 * different way to r/w according to the enable_dma settings and if
750 * we are not doing a full duplex transfer (since the hardware does
751 * not support full duplex DMA transfers).
753 if (!full_duplex
&& drv_data
->cur_chip
->enable_dma
754 && drv_data
->len
> 6) {
756 disable_dma(drv_data
->dma_channel
);
757 clear_dma_irqstat(drv_data
->dma_channel
);
758 bfin_spi_disable(drv_data
);
760 /* config dma channel */
761 dev_dbg(&drv_data
->pdev
->dev
, "doing dma transfer\n");
762 if (width
== CFG_SPI_WORDSIZE16
) {
763 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
764 set_dma_x_modify(drv_data
->dma_channel
, 2);
765 dma_width
= WDSIZE_16
;
767 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
768 set_dma_x_modify(drv_data
->dma_channel
, 1);
769 dma_width
= WDSIZE_8
;
772 /* poll for SPI completion before start */
773 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
776 /* dirty hack for autobuffer DMA mode */
777 if (drv_data
->tx_dma
== 0xFFFF) {
778 dev_dbg(&drv_data
->pdev
->dev
,
779 "doing autobuffer DMA out.\n");
781 /* no irq in autobuffer mode */
783 (DMAFLOW_AUTO
| RESTART
| dma_width
| DI_EN
);
784 set_dma_config(drv_data
->dma_channel
, dma_config
);
785 set_dma_start_addr(drv_data
->dma_channel
,
786 (unsigned long)drv_data
->tx
);
787 enable_dma(drv_data
->dma_channel
);
789 /* start SPI transfer */
791 (cr
| CFG_SPI_DMAWRITE
| BIT_CTL_ENABLE
));
793 /* just return here, there can only be one transfer
801 /* In dma mode, rx or tx must be NULL in one transfer */
802 if (drv_data
->rx
!= NULL
) {
803 /* set transfer mode, and enable SPI */
804 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA in.\n");
806 /* invalidate caches, if needed */
807 if (bfin_addr_dcachable((unsigned long) drv_data
->rx
))
808 invalidate_dcache_range((unsigned long) drv_data
->rx
,
809 (unsigned long) (drv_data
->rx
+
812 /* clear tx reg soformer data is not shifted out */
813 write_TDBR(drv_data
, 0xFFFF);
815 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
818 dma_enable_irq(drv_data
->dma_channel
);
819 dma_config
= (WNR
| RESTART
| dma_width
| DI_EN
);
820 set_dma_config(drv_data
->dma_channel
, dma_config
);
821 set_dma_start_addr(drv_data
->dma_channel
,
822 (unsigned long)drv_data
->rx
);
823 enable_dma(drv_data
->dma_channel
);
825 /* start SPI transfer */
827 (cr
| CFG_SPI_DMAREAD
| BIT_CTL_ENABLE
));
829 } else if (drv_data
->tx
!= NULL
) {
830 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA out.\n");
832 /* flush caches, if needed */
833 if (bfin_addr_dcachable((unsigned long) drv_data
->tx
))
834 flush_dcache_range((unsigned long) drv_data
->tx
,
835 (unsigned long) (drv_data
->tx
+
839 dma_enable_irq(drv_data
->dma_channel
);
840 dma_config
= (RESTART
| dma_width
| DI_EN
);
841 set_dma_config(drv_data
->dma_channel
, dma_config
);
842 set_dma_start_addr(drv_data
->dma_channel
,
843 (unsigned long)drv_data
->tx
);
844 enable_dma(drv_data
->dma_channel
);
846 /* start SPI transfer */
848 (cr
| CFG_SPI_DMAWRITE
| BIT_CTL_ENABLE
));
851 /* IO mode write then read */
852 dev_dbg(&drv_data
->pdev
->dev
, "doing IO transfer\n");
855 /* full duplex mode */
856 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
857 (drv_data
->rx_end
- drv_data
->rx
));
858 dev_dbg(&drv_data
->pdev
->dev
,
859 "IO duplex: cr is 0x%x\n", cr
);
861 /* set SPI transfer mode */
862 write_CTRL(drv_data
, (cr
| CFG_SPI_WRITE
));
864 drv_data
->duplex(drv_data
);
866 if (drv_data
->tx
!= drv_data
->tx_end
)
868 } else if (drv_data
->tx
!= NULL
) {
869 /* write only half duplex */
870 dev_dbg(&drv_data
->pdev
->dev
,
871 "IO write: cr is 0x%x\n", cr
);
873 /* set SPI transfer mode */
874 write_CTRL(drv_data
, (cr
| CFG_SPI_WRITE
));
876 drv_data
->write(drv_data
);
878 if (drv_data
->tx
!= drv_data
->tx_end
)
880 } else if (drv_data
->rx
!= NULL
) {
881 /* read only half duplex */
882 dev_dbg(&drv_data
->pdev
->dev
,
883 "IO read: cr is 0x%x\n", cr
);
885 /* set SPI transfer mode */
886 write_CTRL(drv_data
, (cr
| CFG_SPI_READ
));
888 drv_data
->read(drv_data
);
889 if (drv_data
->rx
!= drv_data
->rx_end
)
893 if (!tranf_success
) {
894 dev_dbg(&drv_data
->pdev
->dev
,
895 "IO write error!\n");
896 message
->state
= ERROR_STATE
;
898 /* Update total byte transfered */
899 message
->actual_length
+= drv_data
->len
;
901 /* Move to next transfer of this msg */
902 message
->state
= next_transfer(drv_data
);
905 /* Schedule next transfer tasklet */
906 tasklet_schedule(&drv_data
->pump_transfers
);
911 /* pop a msg from queue and kick off real transfer */
912 static void pump_messages(struct work_struct
*work
)
914 struct driver_data
*drv_data
;
917 drv_data
= container_of(work
, struct driver_data
, pump_messages
);
919 /* Lock queue and check for queue work */
920 spin_lock_irqsave(&drv_data
->lock
, flags
);
921 if (list_empty(&drv_data
->queue
) || drv_data
->run
== QUEUE_STOPPED
) {
922 /* pumper kicked off but no work to do */
924 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
928 /* Make sure we are not already running a message */
929 if (drv_data
->cur_msg
) {
930 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
934 /* Extract head of queue */
935 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
936 struct spi_message
, queue
);
938 /* Setup the SSP using the per chip configuration */
939 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
940 restore_state(drv_data
);
942 list_del_init(&drv_data
->cur_msg
->queue
);
944 /* Initial message state */
945 drv_data
->cur_msg
->state
= START_STATE
;
946 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
947 struct spi_transfer
, transfer_list
);
949 dev_dbg(&drv_data
->pdev
->dev
, "got a message to pump, "
950 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
951 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->flag
,
952 drv_data
->cur_chip
->ctl_reg
);
954 dev_dbg(&drv_data
->pdev
->dev
,
955 "the first transfer len is %d\n",
956 drv_data
->cur_transfer
->len
);
958 /* Mark as busy and launch transfers */
959 tasklet_schedule(&drv_data
->pump_transfers
);
962 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
966 * got a msg to transfer, queue it in drv_data->queue.
967 * And kick off message pumper
969 static int transfer(struct spi_device
*spi
, struct spi_message
*msg
)
971 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
974 spin_lock_irqsave(&drv_data
->lock
, flags
);
976 if (drv_data
->run
== QUEUE_STOPPED
) {
977 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
981 msg
->actual_length
= 0;
982 msg
->status
= -EINPROGRESS
;
983 msg
->state
= START_STATE
;
985 dev_dbg(&spi
->dev
, "adding an msg in transfer() \n");
986 list_add_tail(&msg
->queue
, &drv_data
->queue
);
988 if (drv_data
->run
== QUEUE_RUNNING
&& !drv_data
->busy
)
989 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
991 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
996 #define MAX_SPI_SSEL 7
998 static u16 ssel
[3][MAX_SPI_SSEL
] = {
999 {P_SPI0_SSEL1
, P_SPI0_SSEL2
, P_SPI0_SSEL3
,
1000 P_SPI0_SSEL4
, P_SPI0_SSEL5
,
1001 P_SPI0_SSEL6
, P_SPI0_SSEL7
},
1003 {P_SPI1_SSEL1
, P_SPI1_SSEL2
, P_SPI1_SSEL3
,
1004 P_SPI1_SSEL4
, P_SPI1_SSEL5
,
1005 P_SPI1_SSEL6
, P_SPI1_SSEL7
},
1007 {P_SPI2_SSEL1
, P_SPI2_SSEL2
, P_SPI2_SSEL3
,
1008 P_SPI2_SSEL4
, P_SPI2_SSEL5
,
1009 P_SPI2_SSEL6
, P_SPI2_SSEL7
},
1012 /* first setup for new devices */
1013 static int setup(struct spi_device
*spi
)
1015 struct bfin5xx_spi_chip
*chip_info
= NULL
;
1016 struct chip_data
*chip
;
1017 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1020 /* Abort device setup if requested features are not supported */
1021 if (spi
->mode
& ~(SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
)) {
1022 dev_err(&spi
->dev
, "requested mode not fully supported\n");
1026 /* Zero (the default) here means 8 bits */
1027 if (!spi
->bits_per_word
)
1028 spi
->bits_per_word
= 8;
1030 if (spi
->bits_per_word
!= 8 && spi
->bits_per_word
!= 16)
1033 /* Only alloc (or use chip_info) on first setup */
1034 chip
= spi_get_ctldata(spi
);
1036 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
1040 chip
->enable_dma
= 0;
1041 chip_info
= spi
->controller_data
;
1044 /* chip_info isn't always needed */
1046 /* Make sure people stop trying to set fields via ctl_reg
1047 * when they should actually be using common SPI framework.
1048 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1049 * Not sure if a user actually needs/uses any of these,
1050 * but let's assume (for now) they do.
1052 if (chip_info
->ctl_reg
& (SPE
|MSTR
|CPOL
|CPHA
|LSBF
|SIZE
)) {
1053 dev_err(&spi
->dev
, "do not set bits in ctl_reg "
1054 "that the SPI framework manages\n");
1058 chip
->enable_dma
= chip_info
->enable_dma
!= 0
1059 && drv_data
->master_info
->enable_dma
;
1060 chip
->ctl_reg
= chip_info
->ctl_reg
;
1061 chip
->bits_per_word
= chip_info
->bits_per_word
;
1062 chip
->cs_change_per_word
= chip_info
->cs_change_per_word
;
1063 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
1066 /* translate common spi framework into our register */
1067 if (spi
->mode
& SPI_CPOL
)
1068 chip
->ctl_reg
|= CPOL
;
1069 if (spi
->mode
& SPI_CPHA
)
1070 chip
->ctl_reg
|= CPHA
;
1071 if (spi
->mode
& SPI_LSB_FIRST
)
1072 chip
->ctl_reg
|= LSBF
;
1073 /* we dont support running in slave mode (yet?) */
1074 chip
->ctl_reg
|= MSTR
;
1077 * if any one SPI chip is registered and wants DMA, request the
1078 * DMA channel for it
1080 if (chip
->enable_dma
&& !drv_data
->dma_requested
) {
1081 /* register dma irq handler */
1082 if (request_dma(drv_data
->dma_channel
, "BF53x_SPI_DMA") < 0) {
1084 "Unable to request BlackFin SPI DMA channel\n");
1087 if (set_dma_callback(drv_data
->dma_channel
,
1088 (void *)dma_irq_handler
, drv_data
) < 0) {
1089 dev_dbg(&spi
->dev
, "Unable to set dma callback\n");
1092 dma_disable_irq(drv_data
->dma_channel
);
1093 drv_data
->dma_requested
= 1;
1097 * Notice: for blackfin, the speed_hz is the value of register
1098 * SPI_BAUD, not the real baudrate
1100 chip
->baud
= hz_to_spi_baud(spi
->max_speed_hz
);
1101 spi_flg
= ~(1 << (spi
->chip_select
));
1102 chip
->flag
= ((u16
) spi_flg
<< 8) | (1 << (spi
->chip_select
));
1103 chip
->chip_select_num
= spi
->chip_select
;
1105 switch (chip
->bits_per_word
) {
1108 chip
->width
= CFG_SPI_WORDSIZE8
;
1109 chip
->read
= chip
->cs_change_per_word
?
1110 u8_cs_chg_reader
: u8_reader
;
1111 chip
->write
= chip
->cs_change_per_word
?
1112 u8_cs_chg_writer
: u8_writer
;
1113 chip
->duplex
= chip
->cs_change_per_word
?
1114 u8_cs_chg_duplex
: u8_duplex
;
1119 chip
->width
= CFG_SPI_WORDSIZE16
;
1120 chip
->read
= chip
->cs_change_per_word
?
1121 u16_cs_chg_reader
: u16_reader
;
1122 chip
->write
= chip
->cs_change_per_word
?
1123 u16_cs_chg_writer
: u16_writer
;
1124 chip
->duplex
= chip
->cs_change_per_word
?
1125 u16_cs_chg_duplex
: u16_duplex
;
1129 dev_err(&spi
->dev
, "%d bits_per_word is not supported\n",
1130 chip
->bits_per_word
);
1135 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d, dma is %d\n",
1136 spi
->modalias
, chip
->width
, chip
->enable_dma
);
1137 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1138 chip
->ctl_reg
, chip
->flag
);
1140 spi_set_ctldata(spi
, chip
);
1142 dev_dbg(&spi
->dev
, "chip select number is %d\n", chip
->chip_select_num
);
1143 if ((chip
->chip_select_num
> 0)
1144 && (chip
->chip_select_num
<= spi
->master
->num_chipselect
))
1145 peripheral_request(ssel
[spi
->master
->bus_num
]
1146 [chip
->chip_select_num
-1], spi
->modalias
);
1148 cs_deactive(drv_data
, chip
);
1154 * callback for spi framework.
1155 * clean driver specific data
1157 static void cleanup(struct spi_device
*spi
)
1159 struct chip_data
*chip
= spi_get_ctldata(spi
);
1161 if ((chip
->chip_select_num
> 0)
1162 && (chip
->chip_select_num
<= spi
->master
->num_chipselect
))
1163 peripheral_free(ssel
[spi
->master
->bus_num
]
1164 [chip
->chip_select_num
-1]);
1169 static inline int init_queue(struct driver_data
*drv_data
)
1171 INIT_LIST_HEAD(&drv_data
->queue
);
1172 spin_lock_init(&drv_data
->lock
);
1174 drv_data
->run
= QUEUE_STOPPED
;
1177 /* init transfer tasklet */
1178 tasklet_init(&drv_data
->pump_transfers
,
1179 pump_transfers
, (unsigned long)drv_data
);
1181 /* init messages workqueue */
1182 INIT_WORK(&drv_data
->pump_messages
, pump_messages
);
1183 drv_data
->workqueue
= create_singlethread_workqueue(
1184 dev_name(drv_data
->master
->dev
.parent
));
1185 if (drv_data
->workqueue
== NULL
)
1191 static inline int start_queue(struct driver_data
*drv_data
)
1193 unsigned long flags
;
1195 spin_lock_irqsave(&drv_data
->lock
, flags
);
1197 if (drv_data
->run
== QUEUE_RUNNING
|| drv_data
->busy
) {
1198 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1202 drv_data
->run
= QUEUE_RUNNING
;
1203 drv_data
->cur_msg
= NULL
;
1204 drv_data
->cur_transfer
= NULL
;
1205 drv_data
->cur_chip
= NULL
;
1206 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1208 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1213 static inline int stop_queue(struct driver_data
*drv_data
)
1215 unsigned long flags
;
1216 unsigned limit
= 500;
1219 spin_lock_irqsave(&drv_data
->lock
, flags
);
1222 * This is a bit lame, but is optimized for the common execution path.
1223 * A wait_queue on the drv_data->busy could be used, but then the common
1224 * execution path (pump_messages) would be required to call wake_up or
1225 * friends on every SPI message. Do this instead
1227 drv_data
->run
= QUEUE_STOPPED
;
1228 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1229 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1231 spin_lock_irqsave(&drv_data
->lock
, flags
);
1234 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1237 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1242 static inline int destroy_queue(struct driver_data
*drv_data
)
1246 status
= stop_queue(drv_data
);
1250 destroy_workqueue(drv_data
->workqueue
);
1255 static int __init
bfin5xx_spi_probe(struct platform_device
*pdev
)
1257 struct device
*dev
= &pdev
->dev
;
1258 struct bfin5xx_spi_master
*platform_info
;
1259 struct spi_master
*master
;
1260 struct driver_data
*drv_data
= 0;
1261 struct resource
*res
;
1264 platform_info
= dev
->platform_data
;
1266 /* Allocate master with space for drv_data */
1267 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1269 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1273 drv_data
= spi_master_get_devdata(master
);
1274 drv_data
->master
= master
;
1275 drv_data
->master_info
= platform_info
;
1276 drv_data
->pdev
= pdev
;
1277 drv_data
->pin_req
= platform_info
->pin_req
;
1279 master
->bus_num
= pdev
->id
;
1280 master
->num_chipselect
= platform_info
->num_chipselect
;
1281 master
->cleanup
= cleanup
;
1282 master
->setup
= setup
;
1283 master
->transfer
= transfer
;
1285 /* Find and map our resources */
1286 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1288 dev_err(dev
, "Cannot get IORESOURCE_MEM\n");
1290 goto out_error_get_res
;
1293 drv_data
->regs_base
= ioremap(res
->start
, (res
->end
- res
->start
+ 1));
1294 if (drv_data
->regs_base
== NULL
) {
1295 dev_err(dev
, "Cannot map IO\n");
1297 goto out_error_ioremap
;
1300 drv_data
->dma_channel
= platform_get_irq(pdev
, 0);
1301 if (drv_data
->dma_channel
< 0) {
1302 dev_err(dev
, "No DMA channel specified\n");
1304 goto out_error_no_dma_ch
;
1307 /* Initial and start queue */
1308 status
= init_queue(drv_data
);
1310 dev_err(dev
, "problem initializing queue\n");
1311 goto out_error_queue_alloc
;
1314 status
= start_queue(drv_data
);
1316 dev_err(dev
, "problem starting queue\n");
1317 goto out_error_queue_alloc
;
1320 status
= peripheral_request_list(drv_data
->pin_req
, DRV_NAME
);
1322 dev_err(&pdev
->dev
, ": Requesting Peripherals failed\n");
1323 goto out_error_queue_alloc
;
1326 /* Register with the SPI framework */
1327 platform_set_drvdata(pdev
, drv_data
);
1328 status
= spi_register_master(master
);
1330 dev_err(dev
, "problem registering spi master\n");
1331 goto out_error_queue_alloc
;
1334 dev_info(dev
, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1335 DRV_DESC
, DRV_VERSION
, drv_data
->regs_base
,
1336 drv_data
->dma_channel
);
1339 out_error_queue_alloc
:
1340 destroy_queue(drv_data
);
1341 out_error_no_dma_ch
:
1342 iounmap((void *) drv_data
->regs_base
);
1345 spi_master_put(master
);
1350 /* stop hardware and remove the driver */
1351 static int __devexit
bfin5xx_spi_remove(struct platform_device
*pdev
)
1353 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1359 /* Remove the queue */
1360 status
= destroy_queue(drv_data
);
1364 /* Disable the SSP at the peripheral and SOC level */
1365 bfin_spi_disable(drv_data
);
1368 if (drv_data
->master_info
->enable_dma
) {
1369 if (dma_channel_active(drv_data
->dma_channel
))
1370 free_dma(drv_data
->dma_channel
);
1373 /* Disconnect from the SPI framework */
1374 spi_unregister_master(drv_data
->master
);
1376 peripheral_free_list(drv_data
->pin_req
);
1378 /* Prevent double remove */
1379 platform_set_drvdata(pdev
, NULL
);
1385 static int bfin5xx_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1387 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1390 status
= stop_queue(drv_data
);
1395 bfin_spi_disable(drv_data
);
1400 static int bfin5xx_spi_resume(struct platform_device
*pdev
)
1402 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1405 /* Enable the SPI interface */
1406 bfin_spi_enable(drv_data
);
1408 /* Start the queue running */
1409 status
= start_queue(drv_data
);
1411 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1418 #define bfin5xx_spi_suspend NULL
1419 #define bfin5xx_spi_resume NULL
1420 #endif /* CONFIG_PM */
1422 MODULE_ALIAS("platform:bfin-spi");
1423 static struct platform_driver bfin5xx_spi_driver
= {
1426 .owner
= THIS_MODULE
,
1428 .suspend
= bfin5xx_spi_suspend
,
1429 .resume
= bfin5xx_spi_resume
,
1430 .remove
= __devexit_p(bfin5xx_spi_remove
),
1433 static int __init
bfin5xx_spi_init(void)
1435 return platform_driver_probe(&bfin5xx_spi_driver
, bfin5xx_spi_probe
);
1437 module_init(bfin5xx_spi_init
);
1439 static void __exit
bfin5xx_spi_exit(void)
1441 platform_driver_unregister(&bfin5xx_spi_driver
);
1443 module_exit(bfin5xx_spi_exit
);