2 * Copyright (C) 2009 Samsung Electronics Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dmaengine.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/spi/spi.h>
26 #include <linux/gpio.h>
28 #include <linux/of_gpio.h>
30 #include <linux/platform_data/spi-s3c64xx.h>
32 #define MAX_SPI_PORTS 6
33 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
34 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
35 #define AUTOSUSPEND_TIMEOUT 2000
37 /* Registers and bit-fields */
39 #define S3C64XX_SPI_CH_CFG 0x00
40 #define S3C64XX_SPI_CLK_CFG 0x04
41 #define S3C64XX_SPI_MODE_CFG 0x08
42 #define S3C64XX_SPI_SLAVE_SEL 0x0C
43 #define S3C64XX_SPI_INT_EN 0x10
44 #define S3C64XX_SPI_STATUS 0x14
45 #define S3C64XX_SPI_TX_DATA 0x18
46 #define S3C64XX_SPI_RX_DATA 0x1C
47 #define S3C64XX_SPI_PACKET_CNT 0x20
48 #define S3C64XX_SPI_PENDING_CLR 0x24
49 #define S3C64XX_SPI_SWAP_CFG 0x28
50 #define S3C64XX_SPI_FB_CLK 0x2C
52 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
53 #define S3C64XX_SPI_CH_SW_RST (1<<5)
54 #define S3C64XX_SPI_CH_SLAVE (1<<4)
55 #define S3C64XX_SPI_CPOL_L (1<<3)
56 #define S3C64XX_SPI_CPHA_B (1<<2)
57 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
58 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
60 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
61 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
62 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
63 #define S3C64XX_SPI_PSR_MASK 0xff
65 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
66 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
67 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
68 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
69 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
70 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
71 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
72 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
73 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
74 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
75 #define S3C64XX_SPI_MODE_4BURST (1<<0)
77 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
78 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
79 #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
81 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
89 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
96 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
98 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
104 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
113 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
115 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
122 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
123 #define S3C64XX_SPI_TRAILCNT_OFF 19
125 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
130 #define RXBUSY (1<<2)
131 #define TXBUSY (1<<3)
133 struct s3c64xx_spi_dma_data
{
135 enum dma_transfer_direction direction
;
139 * struct s3c64xx_spi_info - SPI Controller hardware info
140 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
141 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
142 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
143 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
144 * @clk_from_cmu: True, if the controller does not include a clock mux and
147 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
148 * differ in some aspects such as the size of the fifo and spi bus clock
149 * setup. Such differences are specified to the driver using this structure
150 * which is provided as driver data to the driver.
152 struct s3c64xx_spi_port_config
{
153 int fifo_lvl_mask
[MAX_SPI_PORTS
];
163 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
164 * @clk: Pointer to the spi clock.
165 * @src_clk: Pointer to the clock used to generate SPI signals.
166 * @ioclk: Pointer to the i/o clock between master and slave
167 * @master: Pointer to the SPI Protocol master.
168 * @cntrlr_info: Platform specific data for the controller this driver manages.
169 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
170 * @lock: Controller specific lock.
171 * @state: Set of FLAGS to indicate status.
172 * @rx_dmach: Controller's DMA channel for Rx.
173 * @tx_dmach: Controller's DMA channel for Tx.
174 * @sfr_start: BUS address of SPI controller regs.
175 * @regs: Pointer to ioremap'ed controller registers.
177 * @xfer_completion: To indicate completion of xfer task.
178 * @cur_mode: Stores the active configuration of the controller.
179 * @cur_bpw: Stores the active bits per word settings.
180 * @cur_speed: Stores the active xfer clock speed.
182 struct s3c64xx_spi_driver_data
{
187 struct platform_device
*pdev
;
188 struct spi_master
*master
;
189 struct s3c64xx_spi_info
*cntrlr_info
;
190 struct spi_device
*tgl_spi
;
192 unsigned long sfr_start
;
193 struct completion xfer_completion
;
195 unsigned cur_mode
, cur_bpw
;
197 struct s3c64xx_spi_dma_data rx_dma
;
198 struct s3c64xx_spi_dma_data tx_dma
;
199 struct s3c64xx_spi_port_config
*port_conf
;
200 unsigned int port_id
;
203 static void flush_fifo(struct s3c64xx_spi_driver_data
*sdd
)
205 void __iomem
*regs
= sdd
->regs
;
209 writel(0, regs
+ S3C64XX_SPI_PACKET_CNT
);
211 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
212 val
&= ~(S3C64XX_SPI_CH_RXCH_ON
| S3C64XX_SPI_CH_TXCH_ON
);
213 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
215 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
216 val
|= S3C64XX_SPI_CH_SW_RST
;
217 val
&= ~S3C64XX_SPI_CH_HS_EN
;
218 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
221 loops
= msecs_to_loops(1);
223 val
= readl(regs
+ S3C64XX_SPI_STATUS
);
224 } while (TX_FIFO_LVL(val
, sdd
) && loops
--);
227 dev_warn(&sdd
->pdev
->dev
, "Timed out flushing TX FIFO\n");
230 loops
= msecs_to_loops(1);
232 val
= readl(regs
+ S3C64XX_SPI_STATUS
);
233 if (RX_FIFO_LVL(val
, sdd
))
234 readl(regs
+ S3C64XX_SPI_RX_DATA
);
240 dev_warn(&sdd
->pdev
->dev
, "Timed out flushing RX FIFO\n");
242 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
243 val
&= ~S3C64XX_SPI_CH_SW_RST
;
244 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
246 val
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
247 val
&= ~(S3C64XX_SPI_MODE_TXDMA_ON
| S3C64XX_SPI_MODE_RXDMA_ON
);
248 writel(val
, regs
+ S3C64XX_SPI_MODE_CFG
);
251 static void s3c64xx_spi_dmacb(void *data
)
253 struct s3c64xx_spi_driver_data
*sdd
;
254 struct s3c64xx_spi_dma_data
*dma
= data
;
257 if (dma
->direction
== DMA_DEV_TO_MEM
)
258 sdd
= container_of(data
,
259 struct s3c64xx_spi_driver_data
, rx_dma
);
261 sdd
= container_of(data
,
262 struct s3c64xx_spi_driver_data
, tx_dma
);
264 spin_lock_irqsave(&sdd
->lock
, flags
);
266 if (dma
->direction
== DMA_DEV_TO_MEM
) {
267 sdd
->state
&= ~RXBUSY
;
268 if (!(sdd
->state
& TXBUSY
))
269 complete(&sdd
->xfer_completion
);
271 sdd
->state
&= ~TXBUSY
;
272 if (!(sdd
->state
& RXBUSY
))
273 complete(&sdd
->xfer_completion
);
276 spin_unlock_irqrestore(&sdd
->lock
, flags
);
279 static void prepare_dma(struct s3c64xx_spi_dma_data
*dma
,
280 struct sg_table
*sgt
)
282 struct s3c64xx_spi_driver_data
*sdd
;
283 struct dma_slave_config config
;
284 struct dma_async_tx_descriptor
*desc
;
286 memset(&config
, 0, sizeof(config
));
288 if (dma
->direction
== DMA_DEV_TO_MEM
) {
289 sdd
= container_of((void *)dma
,
290 struct s3c64xx_spi_driver_data
, rx_dma
);
291 config
.direction
= dma
->direction
;
292 config
.src_addr
= sdd
->sfr_start
+ S3C64XX_SPI_RX_DATA
;
293 config
.src_addr_width
= sdd
->cur_bpw
/ 8;
294 config
.src_maxburst
= 1;
295 dmaengine_slave_config(dma
->ch
, &config
);
297 sdd
= container_of((void *)dma
,
298 struct s3c64xx_spi_driver_data
, tx_dma
);
299 config
.direction
= dma
->direction
;
300 config
.dst_addr
= sdd
->sfr_start
+ S3C64XX_SPI_TX_DATA
;
301 config
.dst_addr_width
= sdd
->cur_bpw
/ 8;
302 config
.dst_maxburst
= 1;
303 dmaengine_slave_config(dma
->ch
, &config
);
306 desc
= dmaengine_prep_slave_sg(dma
->ch
, sgt
->sgl
, sgt
->nents
,
307 dma
->direction
, DMA_PREP_INTERRUPT
);
309 desc
->callback
= s3c64xx_spi_dmacb
;
310 desc
->callback_param
= dma
;
312 dmaengine_submit(desc
);
313 dma_async_issue_pending(dma
->ch
);
316 static void s3c64xx_spi_set_cs(struct spi_device
*spi
, bool enable
)
318 struct s3c64xx_spi_driver_data
*sdd
=
319 spi_master_get_devdata(spi
->master
);
321 if (sdd
->cntrlr_info
->no_cs
)
325 if (!(sdd
->port_conf
->quirks
& S3C64XX_SPI_QUIRK_CS_AUTO
)) {
326 writel(0, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
328 u32 ssel
= readl(sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
330 ssel
|= (S3C64XX_SPI_SLAVE_AUTO
|
331 S3C64XX_SPI_SLAVE_NSC_CNT_2
);
332 writel(ssel
, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
335 if (!(sdd
->port_conf
->quirks
& S3C64XX_SPI_QUIRK_CS_AUTO
))
336 writel(S3C64XX_SPI_SLAVE_SIG_INACT
,
337 sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
341 static int s3c64xx_spi_prepare_transfer(struct spi_master
*spi
)
343 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(spi
);
348 spi
->dma_rx
= sdd
->rx_dma
.ch
;
349 spi
->dma_tx
= sdd
->tx_dma
.ch
;
354 static bool s3c64xx_spi_can_dma(struct spi_master
*master
,
355 struct spi_device
*spi
,
356 struct spi_transfer
*xfer
)
358 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
360 return xfer
->len
> (FIFO_LVL_MASK(sdd
) >> 1) + 1;
363 static void enable_datapath(struct s3c64xx_spi_driver_data
*sdd
,
364 struct spi_device
*spi
,
365 struct spi_transfer
*xfer
, int dma_mode
)
367 void __iomem
*regs
= sdd
->regs
;
370 modecfg
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
371 modecfg
&= ~(S3C64XX_SPI_MODE_TXDMA_ON
| S3C64XX_SPI_MODE_RXDMA_ON
);
373 chcfg
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
374 chcfg
&= ~S3C64XX_SPI_CH_TXCH_ON
;
377 chcfg
&= ~S3C64XX_SPI_CH_RXCH_ON
;
379 /* Always shift in data in FIFO, even if xfer is Tx only,
380 * this helps setting PCKT_CNT value for generating clocks
383 chcfg
|= S3C64XX_SPI_CH_RXCH_ON
;
384 writel(((xfer
->len
* 8 / sdd
->cur_bpw
) & 0xffff)
385 | S3C64XX_SPI_PACKET_CNT_EN
,
386 regs
+ S3C64XX_SPI_PACKET_CNT
);
389 if (xfer
->tx_buf
!= NULL
) {
390 sdd
->state
|= TXBUSY
;
391 chcfg
|= S3C64XX_SPI_CH_TXCH_ON
;
393 modecfg
|= S3C64XX_SPI_MODE_TXDMA_ON
;
394 prepare_dma(&sdd
->tx_dma
, &xfer
->tx_sg
);
396 switch (sdd
->cur_bpw
) {
398 iowrite32_rep(regs
+ S3C64XX_SPI_TX_DATA
,
399 xfer
->tx_buf
, xfer
->len
/ 4);
402 iowrite16_rep(regs
+ S3C64XX_SPI_TX_DATA
,
403 xfer
->tx_buf
, xfer
->len
/ 2);
406 iowrite8_rep(regs
+ S3C64XX_SPI_TX_DATA
,
407 xfer
->tx_buf
, xfer
->len
);
413 if (xfer
->rx_buf
!= NULL
) {
414 sdd
->state
|= RXBUSY
;
416 if (sdd
->port_conf
->high_speed
&& sdd
->cur_speed
>= 30000000UL
417 && !(sdd
->cur_mode
& SPI_CPHA
))
418 chcfg
|= S3C64XX_SPI_CH_HS_EN
;
421 modecfg
|= S3C64XX_SPI_MODE_RXDMA_ON
;
422 chcfg
|= S3C64XX_SPI_CH_RXCH_ON
;
423 writel(((xfer
->len
* 8 / sdd
->cur_bpw
) & 0xffff)
424 | S3C64XX_SPI_PACKET_CNT_EN
,
425 regs
+ S3C64XX_SPI_PACKET_CNT
);
426 prepare_dma(&sdd
->rx_dma
, &xfer
->rx_sg
);
430 writel(modecfg
, regs
+ S3C64XX_SPI_MODE_CFG
);
431 writel(chcfg
, regs
+ S3C64XX_SPI_CH_CFG
);
434 static u32
s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data
*sdd
,
437 void __iomem
*regs
= sdd
->regs
;
438 unsigned long val
= 1;
441 /* max fifo depth available */
442 u32 max_fifo
= (FIFO_LVL_MASK(sdd
) >> 1) + 1;
445 val
= msecs_to_loops(timeout_ms
);
448 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
449 } while (RX_FIFO_LVL(status
, sdd
) < max_fifo
&& --val
);
451 /* return the actual received data length */
452 return RX_FIFO_LVL(status
, sdd
);
455 static int wait_for_dma(struct s3c64xx_spi_driver_data
*sdd
,
456 struct spi_transfer
*xfer
)
458 void __iomem
*regs
= sdd
->regs
;
463 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
464 ms
= xfer
->len
* 8 * 1000 / sdd
->cur_speed
;
465 ms
+= 10; /* some tolerance */
467 val
= msecs_to_jiffies(ms
) + 10;
468 val
= wait_for_completion_timeout(&sdd
->xfer_completion
, val
);
471 * If the previous xfer was completed within timeout, then
472 * proceed further else return -EIO.
473 * DmaTx returns after simply writing data in the FIFO,
474 * w/o waiting for real transmission on the bus to finish.
475 * DmaRx returns only after Dma read data from FIFO which
476 * needs bus transmission to finish, so we don't worry if
477 * Xfer involved Rx(with or without Tx).
479 if (val
&& !xfer
->rx_buf
) {
480 val
= msecs_to_loops(10);
481 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
482 while ((TX_FIFO_LVL(status
, sdd
)
483 || !S3C64XX_SPI_ST_TX_DONE(status
, sdd
))
486 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
491 /* If timed out while checking rx/tx status return error */
498 static int wait_for_pio(struct s3c64xx_spi_driver_data
*sdd
,
499 struct spi_transfer
*xfer
)
501 void __iomem
*regs
= sdd
->regs
;
509 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
510 ms
= xfer
->len
* 8 * 1000 / sdd
->cur_speed
;
511 ms
+= 10; /* some tolerance */
513 val
= msecs_to_loops(ms
);
515 status
= readl(regs
+ S3C64XX_SPI_STATUS
);
516 } while (RX_FIFO_LVL(status
, sdd
) < xfer
->len
&& --val
);
519 /* If it was only Tx */
521 sdd
->state
&= ~TXBUSY
;
526 * If the receive length is bigger than the controller fifo
527 * size, calculate the loops and read the fifo as many times.
528 * loops = length / max fifo size (calculated by using the
530 * For any size less than the fifo size the below code is
531 * executed atleast once.
533 loops
= xfer
->len
/ ((FIFO_LVL_MASK(sdd
) >> 1) + 1);
536 /* wait for data to be received in the fifo */
537 cpy_len
= s3c64xx_spi_wait_for_timeout(sdd
,
540 switch (sdd
->cur_bpw
) {
542 ioread32_rep(regs
+ S3C64XX_SPI_RX_DATA
,
546 ioread16_rep(regs
+ S3C64XX_SPI_RX_DATA
,
550 ioread8_rep(regs
+ S3C64XX_SPI_RX_DATA
,
557 sdd
->state
&= ~RXBUSY
;
562 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data
*sdd
)
564 void __iomem
*regs
= sdd
->regs
;
568 if (!sdd
->port_conf
->clk_from_cmu
) {
569 val
= readl(regs
+ S3C64XX_SPI_CLK_CFG
);
570 val
&= ~S3C64XX_SPI_ENCLK_ENABLE
;
571 writel(val
, regs
+ S3C64XX_SPI_CLK_CFG
);
574 /* Set Polarity and Phase */
575 val
= readl(regs
+ S3C64XX_SPI_CH_CFG
);
576 val
&= ~(S3C64XX_SPI_CH_SLAVE
|
580 if (sdd
->cur_mode
& SPI_CPOL
)
581 val
|= S3C64XX_SPI_CPOL_L
;
583 if (sdd
->cur_mode
& SPI_CPHA
)
584 val
|= S3C64XX_SPI_CPHA_B
;
586 writel(val
, regs
+ S3C64XX_SPI_CH_CFG
);
588 /* Set Channel & DMA Mode */
589 val
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
590 val
&= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
591 | S3C64XX_SPI_MODE_CH_TSZ_MASK
);
593 switch (sdd
->cur_bpw
) {
595 val
|= S3C64XX_SPI_MODE_BUS_TSZ_WORD
;
596 val
|= S3C64XX_SPI_MODE_CH_TSZ_WORD
;
599 val
|= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD
;
600 val
|= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD
;
603 val
|= S3C64XX_SPI_MODE_BUS_TSZ_BYTE
;
604 val
|= S3C64XX_SPI_MODE_CH_TSZ_BYTE
;
608 writel(val
, regs
+ S3C64XX_SPI_MODE_CFG
);
610 if (sdd
->port_conf
->clk_from_cmu
) {
611 /* The src_clk clock is divided internally by 2 */
612 clk_set_rate(sdd
->src_clk
, sdd
->cur_speed
* 2);
614 /* Configure Clock */
615 val
= readl(regs
+ S3C64XX_SPI_CLK_CFG
);
616 val
&= ~S3C64XX_SPI_PSR_MASK
;
617 val
|= ((clk_get_rate(sdd
->src_clk
) / sdd
->cur_speed
/ 2 - 1)
618 & S3C64XX_SPI_PSR_MASK
);
619 writel(val
, regs
+ S3C64XX_SPI_CLK_CFG
);
622 val
= readl(regs
+ S3C64XX_SPI_CLK_CFG
);
623 val
|= S3C64XX_SPI_ENCLK_ENABLE
;
624 writel(val
, regs
+ S3C64XX_SPI_CLK_CFG
);
628 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
630 static int s3c64xx_spi_prepare_message(struct spi_master
*master
,
631 struct spi_message
*msg
)
633 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
634 struct spi_device
*spi
= msg
->spi
;
635 struct s3c64xx_spi_csinfo
*cs
= spi
->controller_data
;
637 /* Configure feedback delay */
638 writel(cs
->fb_delay
& 0x3, sdd
->regs
+ S3C64XX_SPI_FB_CLK
);
643 static int s3c64xx_spi_transfer_one(struct spi_master
*master
,
644 struct spi_device
*spi
,
645 struct spi_transfer
*xfer
)
647 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
654 reinit_completion(&sdd
->xfer_completion
);
656 /* Only BPW and Speed may change across transfers */
657 bpw
= xfer
->bits_per_word
;
658 speed
= xfer
->speed_hz
;
660 if (bpw
!= sdd
->cur_bpw
|| speed
!= sdd
->cur_speed
) {
662 sdd
->cur_speed
= speed
;
663 sdd
->cur_mode
= spi
->mode
;
664 s3c64xx_spi_config(sdd
);
667 /* Polling method for xfers not bigger than FIFO capacity */
669 if (!is_polling(sdd
) &&
670 (sdd
->rx_dma
.ch
&& sdd
->tx_dma
.ch
&&
671 (xfer
->len
> ((FIFO_LVL_MASK(sdd
) >> 1) + 1))))
674 spin_lock_irqsave(&sdd
->lock
, flags
);
676 /* Pending only which is to be done */
677 sdd
->state
&= ~RXBUSY
;
678 sdd
->state
&= ~TXBUSY
;
680 enable_datapath(sdd
, spi
, xfer
, use_dma
);
682 /* Start the signals */
683 s3c64xx_spi_set_cs(spi
, true);
685 spin_unlock_irqrestore(&sdd
->lock
, flags
);
688 status
= wait_for_dma(sdd
, xfer
);
690 status
= wait_for_pio(sdd
, xfer
);
693 dev_err(&spi
->dev
, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
694 xfer
->rx_buf
? 1 : 0, xfer
->tx_buf
? 1 : 0,
695 (sdd
->state
& RXBUSY
) ? 'f' : 'p',
696 (sdd
->state
& TXBUSY
) ? 'f' : 'p',
700 if (xfer
->tx_buf
!= NULL
701 && (sdd
->state
& TXBUSY
))
702 dmaengine_terminate_all(sdd
->tx_dma
.ch
);
703 if (xfer
->rx_buf
!= NULL
704 && (sdd
->state
& RXBUSY
))
705 dmaengine_terminate_all(sdd
->rx_dma
.ch
);
714 static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
715 struct spi_device
*spi
)
717 struct s3c64xx_spi_csinfo
*cs
;
718 struct device_node
*slave_np
, *data_np
= NULL
;
721 slave_np
= spi
->dev
.of_node
;
723 dev_err(&spi
->dev
, "device node not found\n");
724 return ERR_PTR(-EINVAL
);
727 data_np
= of_get_child_by_name(slave_np
, "controller-data");
729 dev_err(&spi
->dev
, "child node 'controller-data' not found\n");
730 return ERR_PTR(-EINVAL
);
733 cs
= kzalloc(sizeof(*cs
), GFP_KERNEL
);
735 of_node_put(data_np
);
736 return ERR_PTR(-ENOMEM
);
739 of_property_read_u32(data_np
, "samsung,spi-feedback-delay", &fb_delay
);
740 cs
->fb_delay
= fb_delay
;
741 of_node_put(data_np
);
746 * Here we only check the validity of requested configuration
747 * and save the configuration in a local data-structure.
748 * The controller is actually configured only just before we
749 * get a message to transfer.
751 static int s3c64xx_spi_setup(struct spi_device
*spi
)
753 struct s3c64xx_spi_csinfo
*cs
= spi
->controller_data
;
754 struct s3c64xx_spi_driver_data
*sdd
;
755 struct s3c64xx_spi_info
*sci
;
758 sdd
= spi_master_get_devdata(spi
->master
);
759 if (spi
->dev
.of_node
) {
760 cs
= s3c64xx_get_slave_ctrldata(spi
);
761 spi
->controller_data
= cs
;
763 /* On non-DT platforms the SPI core will set spi->cs_gpio
764 * to -ENOENT. The GPIO pin used to drive the chip select
765 * is defined by using platform data so spi->cs_gpio value
766 * has to be override to have the proper GPIO pin number.
768 spi
->cs_gpio
= cs
->line
;
771 if (IS_ERR_OR_NULL(cs
)) {
772 dev_err(&spi
->dev
, "No CS for SPI(%d)\n", spi
->chip_select
);
776 if (!spi_get_ctldata(spi
)) {
777 if (gpio_is_valid(spi
->cs_gpio
)) {
778 err
= gpio_request_one(spi
->cs_gpio
, GPIOF_OUT_INIT_HIGH
,
779 dev_name(&spi
->dev
));
782 "Failed to get /CS gpio [%d]: %d\n",
788 spi_set_ctldata(spi
, cs
);
791 sci
= sdd
->cntrlr_info
;
793 pm_runtime_get_sync(&sdd
->pdev
->dev
);
795 /* Check if we can provide the requested rate */
796 if (!sdd
->port_conf
->clk_from_cmu
) {
800 speed
= clk_get_rate(sdd
->src_clk
) / 2 / (0 + 1);
802 if (spi
->max_speed_hz
> speed
)
803 spi
->max_speed_hz
= speed
;
805 psr
= clk_get_rate(sdd
->src_clk
) / 2 / spi
->max_speed_hz
- 1;
806 psr
&= S3C64XX_SPI_PSR_MASK
;
807 if (psr
== S3C64XX_SPI_PSR_MASK
)
810 speed
= clk_get_rate(sdd
->src_clk
) / 2 / (psr
+ 1);
811 if (spi
->max_speed_hz
< speed
) {
812 if (psr
+1 < S3C64XX_SPI_PSR_MASK
) {
820 speed
= clk_get_rate(sdd
->src_clk
) / 2 / (psr
+ 1);
821 if (spi
->max_speed_hz
>= speed
) {
822 spi
->max_speed_hz
= speed
;
824 dev_err(&spi
->dev
, "Can't set %dHz transfer speed\n",
831 pm_runtime_mark_last_busy(&sdd
->pdev
->dev
);
832 pm_runtime_put_autosuspend(&sdd
->pdev
->dev
);
833 s3c64xx_spi_set_cs(spi
, false);
838 pm_runtime_mark_last_busy(&sdd
->pdev
->dev
);
839 pm_runtime_put_autosuspend(&sdd
->pdev
->dev
);
840 /* setup() returns with device de-selected */
841 s3c64xx_spi_set_cs(spi
, false);
843 if (gpio_is_valid(spi
->cs_gpio
))
844 gpio_free(spi
->cs_gpio
);
845 spi_set_ctldata(spi
, NULL
);
848 if (spi
->dev
.of_node
)
854 static void s3c64xx_spi_cleanup(struct spi_device
*spi
)
856 struct s3c64xx_spi_csinfo
*cs
= spi_get_ctldata(spi
);
858 if (gpio_is_valid(spi
->cs_gpio
)) {
859 gpio_free(spi
->cs_gpio
);
860 if (spi
->dev
.of_node
)
863 /* On non-DT platforms, the SPI core sets
864 * spi->cs_gpio to -ENOENT and .setup()
865 * overrides it with the GPIO pin value
866 * passed using platform data.
868 spi
->cs_gpio
= -ENOENT
;
872 spi_set_ctldata(spi
, NULL
);
875 static irqreturn_t
s3c64xx_spi_irq(int irq
, void *data
)
877 struct s3c64xx_spi_driver_data
*sdd
= data
;
878 struct spi_master
*spi
= sdd
->master
;
879 unsigned int val
, clr
= 0;
881 val
= readl(sdd
->regs
+ S3C64XX_SPI_STATUS
);
883 if (val
& S3C64XX_SPI_ST_RX_OVERRUN_ERR
) {
884 clr
= S3C64XX_SPI_PND_RX_OVERRUN_CLR
;
885 dev_err(&spi
->dev
, "RX overrun\n");
887 if (val
& S3C64XX_SPI_ST_RX_UNDERRUN_ERR
) {
888 clr
|= S3C64XX_SPI_PND_RX_UNDERRUN_CLR
;
889 dev_err(&spi
->dev
, "RX underrun\n");
891 if (val
& S3C64XX_SPI_ST_TX_OVERRUN_ERR
) {
892 clr
|= S3C64XX_SPI_PND_TX_OVERRUN_CLR
;
893 dev_err(&spi
->dev
, "TX overrun\n");
895 if (val
& S3C64XX_SPI_ST_TX_UNDERRUN_ERR
) {
896 clr
|= S3C64XX_SPI_PND_TX_UNDERRUN_CLR
;
897 dev_err(&spi
->dev
, "TX underrun\n");
900 /* Clear the pending irq by setting and then clearing it */
901 writel(clr
, sdd
->regs
+ S3C64XX_SPI_PENDING_CLR
);
902 writel(0, sdd
->regs
+ S3C64XX_SPI_PENDING_CLR
);
907 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data
*sdd
, int channel
)
909 struct s3c64xx_spi_info
*sci
= sdd
->cntrlr_info
;
910 void __iomem
*regs
= sdd
->regs
;
916 writel(0, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
917 else if (!(sdd
->port_conf
->quirks
& S3C64XX_SPI_QUIRK_CS_AUTO
))
918 writel(S3C64XX_SPI_SLAVE_SIG_INACT
, sdd
->regs
+ S3C64XX_SPI_SLAVE_SEL
);
920 /* Disable Interrupts - we use Polling if not DMA mode */
921 writel(0, regs
+ S3C64XX_SPI_INT_EN
);
923 if (!sdd
->port_conf
->clk_from_cmu
)
924 writel(sci
->src_clk_nr
<< S3C64XX_SPI_CLKSEL_SRCSHFT
,
925 regs
+ S3C64XX_SPI_CLK_CFG
);
926 writel(0, regs
+ S3C64XX_SPI_MODE_CFG
);
927 writel(0, regs
+ S3C64XX_SPI_PACKET_CNT
);
929 /* Clear any irq pending bits, should set and clear the bits */
930 val
= S3C64XX_SPI_PND_RX_OVERRUN_CLR
|
931 S3C64XX_SPI_PND_RX_UNDERRUN_CLR
|
932 S3C64XX_SPI_PND_TX_OVERRUN_CLR
|
933 S3C64XX_SPI_PND_TX_UNDERRUN_CLR
;
934 writel(val
, regs
+ S3C64XX_SPI_PENDING_CLR
);
935 writel(0, regs
+ S3C64XX_SPI_PENDING_CLR
);
937 writel(0, regs
+ S3C64XX_SPI_SWAP_CFG
);
939 val
= readl(regs
+ S3C64XX_SPI_MODE_CFG
);
940 val
&= ~S3C64XX_SPI_MODE_4BURST
;
941 val
&= ~(S3C64XX_SPI_MAX_TRAILCNT
<< S3C64XX_SPI_TRAILCNT_OFF
);
942 val
|= (S3C64XX_SPI_TRAILCNT
<< S3C64XX_SPI_TRAILCNT_OFF
);
943 writel(val
, regs
+ S3C64XX_SPI_MODE_CFG
);
949 static struct s3c64xx_spi_info
*s3c64xx_spi_parse_dt(struct device
*dev
)
951 struct s3c64xx_spi_info
*sci
;
954 sci
= devm_kzalloc(dev
, sizeof(*sci
), GFP_KERNEL
);
956 return ERR_PTR(-ENOMEM
);
958 if (of_property_read_u32(dev
->of_node
, "samsung,spi-src-clk", &temp
)) {
959 dev_warn(dev
, "spi bus clock parent not specified, using clock at index 0 as parent\n");
962 sci
->src_clk_nr
= temp
;
965 if (of_property_read_u32(dev
->of_node
, "num-cs", &temp
)) {
966 dev_warn(dev
, "number of chip select lines not specified, assuming 1 chip select line\n");
972 sci
->no_cs
= of_property_read_bool(dev
->of_node
, "no-cs-readback");
977 static struct s3c64xx_spi_info
*s3c64xx_spi_parse_dt(struct device
*dev
)
979 return dev_get_platdata(dev
);
983 static const struct of_device_id s3c64xx_spi_dt_match
[];
985 static inline struct s3c64xx_spi_port_config
*s3c64xx_spi_get_port_config(
986 struct platform_device
*pdev
)
989 if (pdev
->dev
.of_node
) {
990 const struct of_device_id
*match
;
991 match
= of_match_node(s3c64xx_spi_dt_match
, pdev
->dev
.of_node
);
992 return (struct s3c64xx_spi_port_config
*)match
->data
;
995 return (struct s3c64xx_spi_port_config
*)
996 platform_get_device_id(pdev
)->driver_data
;
999 static int s3c64xx_spi_probe(struct platform_device
*pdev
)
1001 struct resource
*mem_res
;
1002 struct s3c64xx_spi_driver_data
*sdd
;
1003 struct s3c64xx_spi_info
*sci
= dev_get_platdata(&pdev
->dev
);
1004 struct spi_master
*master
;
1008 if (!sci
&& pdev
->dev
.of_node
) {
1009 sci
= s3c64xx_spi_parse_dt(&pdev
->dev
);
1011 return PTR_ERR(sci
);
1015 dev_err(&pdev
->dev
, "platform_data missing!\n");
1019 mem_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1020 if (mem_res
== NULL
) {
1021 dev_err(&pdev
->dev
, "Unable to get SPI MEM resource\n");
1025 irq
= platform_get_irq(pdev
, 0);
1027 dev_warn(&pdev
->dev
, "Failed to get IRQ: %d\n", irq
);
1031 master
= spi_alloc_master(&pdev
->dev
,
1032 sizeof(struct s3c64xx_spi_driver_data
));
1033 if (master
== NULL
) {
1034 dev_err(&pdev
->dev
, "Unable to allocate SPI Master\n");
1038 platform_set_drvdata(pdev
, master
);
1040 sdd
= spi_master_get_devdata(master
);
1041 sdd
->port_conf
= s3c64xx_spi_get_port_config(pdev
);
1042 sdd
->master
= master
;
1043 sdd
->cntrlr_info
= sci
;
1045 sdd
->sfr_start
= mem_res
->start
;
1046 if (pdev
->dev
.of_node
) {
1047 ret
= of_alias_get_id(pdev
->dev
.of_node
, "spi");
1049 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n",
1051 goto err_deref_master
;
1055 sdd
->port_id
= pdev
->id
;
1060 sdd
->tx_dma
.direction
= DMA_MEM_TO_DEV
;
1061 sdd
->rx_dma
.direction
= DMA_DEV_TO_MEM
;
1063 master
->dev
.of_node
= pdev
->dev
.of_node
;
1064 master
->bus_num
= sdd
->port_id
;
1065 master
->setup
= s3c64xx_spi_setup
;
1066 master
->cleanup
= s3c64xx_spi_cleanup
;
1067 master
->prepare_transfer_hardware
= s3c64xx_spi_prepare_transfer
;
1068 master
->prepare_message
= s3c64xx_spi_prepare_message
;
1069 master
->transfer_one
= s3c64xx_spi_transfer_one
;
1070 master
->num_chipselect
= sci
->num_cs
;
1071 master
->dma_alignment
= 8;
1072 master
->bits_per_word_mask
= SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1074 /* the spi->mode bits understood by this driver: */
1075 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1076 master
->auto_runtime_pm
= true;
1077 if (!is_polling(sdd
))
1078 master
->can_dma
= s3c64xx_spi_can_dma
;
1080 sdd
->regs
= devm_ioremap_resource(&pdev
->dev
, mem_res
);
1081 if (IS_ERR(sdd
->regs
)) {
1082 ret
= PTR_ERR(sdd
->regs
);
1083 goto err_deref_master
;
1086 if (sci
->cfg_gpio
&& sci
->cfg_gpio()) {
1087 dev_err(&pdev
->dev
, "Unable to config gpio\n");
1089 goto err_deref_master
;
1093 sdd
->clk
= devm_clk_get(&pdev
->dev
, "spi");
1094 if (IS_ERR(sdd
->clk
)) {
1095 dev_err(&pdev
->dev
, "Unable to acquire clock 'spi'\n");
1096 ret
= PTR_ERR(sdd
->clk
);
1097 goto err_deref_master
;
1100 ret
= clk_prepare_enable(sdd
->clk
);
1102 dev_err(&pdev
->dev
, "Couldn't enable clock 'spi'\n");
1103 goto err_deref_master
;
1106 sprintf(clk_name
, "spi_busclk%d", sci
->src_clk_nr
);
1107 sdd
->src_clk
= devm_clk_get(&pdev
->dev
, clk_name
);
1108 if (IS_ERR(sdd
->src_clk
)) {
1110 "Unable to acquire clock '%s'\n", clk_name
);
1111 ret
= PTR_ERR(sdd
->src_clk
);
1112 goto err_disable_clk
;
1115 ret
= clk_prepare_enable(sdd
->src_clk
);
1117 dev_err(&pdev
->dev
, "Couldn't enable clock '%s'\n", clk_name
);
1118 goto err_disable_clk
;
1121 if (sdd
->port_conf
->clk_ioclk
) {
1122 sdd
->ioclk
= devm_clk_get(&pdev
->dev
, "spi_ioclk");
1123 if (IS_ERR(sdd
->ioclk
)) {
1124 dev_err(&pdev
->dev
, "Unable to acquire 'ioclk'\n");
1125 ret
= PTR_ERR(sdd
->ioclk
);
1126 goto err_disable_src_clk
;
1129 ret
= clk_prepare_enable(sdd
->ioclk
);
1131 dev_err(&pdev
->dev
, "Couldn't enable clock 'ioclk'\n");
1132 goto err_disable_src_clk
;
1136 if (!is_polling(sdd
)) {
1137 /* Acquire DMA channels */
1138 sdd
->rx_dma
.ch
= dma_request_slave_channel_reason(&pdev
->dev
,
1140 if (IS_ERR(sdd
->rx_dma
.ch
)) {
1141 dev_err(&pdev
->dev
, "Failed to get RX DMA channel\n");
1142 ret
= PTR_ERR(sdd
->rx_dma
.ch
);
1143 goto err_disable_io_clk
;
1145 sdd
->tx_dma
.ch
= dma_request_slave_channel_reason(&pdev
->dev
,
1147 if (IS_ERR(sdd
->tx_dma
.ch
)) {
1148 dev_err(&pdev
->dev
, "Failed to get TX DMA channel\n");
1149 ret
= PTR_ERR(sdd
->tx_dma
.ch
);
1150 goto err_release_rx_dma
;
1154 pm_runtime_set_autosuspend_delay(&pdev
->dev
, AUTOSUSPEND_TIMEOUT
);
1155 pm_runtime_use_autosuspend(&pdev
->dev
);
1156 pm_runtime_set_active(&pdev
->dev
);
1157 pm_runtime_enable(&pdev
->dev
);
1158 pm_runtime_get_sync(&pdev
->dev
);
1160 /* Setup Deufult Mode */
1161 s3c64xx_spi_hwinit(sdd
, sdd
->port_id
);
1163 spin_lock_init(&sdd
->lock
);
1164 init_completion(&sdd
->xfer_completion
);
1166 ret
= devm_request_irq(&pdev
->dev
, irq
, s3c64xx_spi_irq
, 0,
1167 "spi-s3c64xx", sdd
);
1169 dev_err(&pdev
->dev
, "Failed to request IRQ %d: %d\n",
1174 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN
| S3C64XX_SPI_INT_RX_UNDERRUN_EN
|
1175 S3C64XX_SPI_INT_TX_OVERRUN_EN
| S3C64XX_SPI_INT_TX_UNDERRUN_EN
,
1176 sdd
->regs
+ S3C64XX_SPI_INT_EN
);
1178 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1180 dev_err(&pdev
->dev
, "cannot register SPI master: %d\n", ret
);
1184 dev_dbg(&pdev
->dev
, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1185 sdd
->port_id
, master
->num_chipselect
);
1186 dev_dbg(&pdev
->dev
, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1187 mem_res
, (FIFO_LVL_MASK(sdd
) >> 1) + 1);
1189 pm_runtime_mark_last_busy(&pdev
->dev
);
1190 pm_runtime_put_autosuspend(&pdev
->dev
);
1195 pm_runtime_put_noidle(&pdev
->dev
);
1196 pm_runtime_disable(&pdev
->dev
);
1197 pm_runtime_set_suspended(&pdev
->dev
);
1199 if (!is_polling(sdd
))
1200 dma_release_channel(sdd
->tx_dma
.ch
);
1202 if (!is_polling(sdd
))
1203 dma_release_channel(sdd
->rx_dma
.ch
);
1205 clk_disable_unprepare(sdd
->ioclk
);
1206 err_disable_src_clk
:
1207 clk_disable_unprepare(sdd
->src_clk
);
1209 clk_disable_unprepare(sdd
->clk
);
1211 spi_master_put(master
);
1216 static int s3c64xx_spi_remove(struct platform_device
*pdev
)
1218 struct spi_master
*master
= platform_get_drvdata(pdev
);
1219 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1221 pm_runtime_get_sync(&pdev
->dev
);
1223 writel(0, sdd
->regs
+ S3C64XX_SPI_INT_EN
);
1225 if (!is_polling(sdd
)) {
1226 dma_release_channel(sdd
->rx_dma
.ch
);
1227 dma_release_channel(sdd
->tx_dma
.ch
);
1230 clk_disable_unprepare(sdd
->ioclk
);
1232 clk_disable_unprepare(sdd
->src_clk
);
1234 clk_disable_unprepare(sdd
->clk
);
1236 pm_runtime_put_noidle(&pdev
->dev
);
1237 pm_runtime_disable(&pdev
->dev
);
1238 pm_runtime_set_suspended(&pdev
->dev
);
1243 #ifdef CONFIG_PM_SLEEP
1244 static int s3c64xx_spi_suspend(struct device
*dev
)
1246 struct spi_master
*master
= dev_get_drvdata(dev
);
1247 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1249 int ret
= spi_master_suspend(master
);
1253 ret
= pm_runtime_force_suspend(dev
);
1257 sdd
->cur_speed
= 0; /* Output Clock is stopped */
1262 static int s3c64xx_spi_resume(struct device
*dev
)
1264 struct spi_master
*master
= dev_get_drvdata(dev
);
1265 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1266 struct s3c64xx_spi_info
*sci
= sdd
->cntrlr_info
;
1272 ret
= pm_runtime_force_resume(dev
);
1276 s3c64xx_spi_hwinit(sdd
, sdd
->port_id
);
1278 return spi_master_resume(master
);
1280 #endif /* CONFIG_PM_SLEEP */
1283 static int s3c64xx_spi_runtime_suspend(struct device
*dev
)
1285 struct spi_master
*master
= dev_get_drvdata(dev
);
1286 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1288 clk_disable_unprepare(sdd
->clk
);
1289 clk_disable_unprepare(sdd
->src_clk
);
1290 clk_disable_unprepare(sdd
->ioclk
);
1295 static int s3c64xx_spi_runtime_resume(struct device
*dev
)
1297 struct spi_master
*master
= dev_get_drvdata(dev
);
1298 struct s3c64xx_spi_driver_data
*sdd
= spi_master_get_devdata(master
);
1301 if (sdd
->port_conf
->clk_ioclk
) {
1302 ret
= clk_prepare_enable(sdd
->ioclk
);
1307 ret
= clk_prepare_enable(sdd
->src_clk
);
1309 goto err_disable_ioclk
;
1311 ret
= clk_prepare_enable(sdd
->clk
);
1313 goto err_disable_src_clk
;
1317 err_disable_src_clk
:
1318 clk_disable_unprepare(sdd
->src_clk
);
1320 clk_disable_unprepare(sdd
->ioclk
);
1324 #endif /* CONFIG_PM */
1326 static const struct dev_pm_ops s3c64xx_spi_pm
= {
1327 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend
, s3c64xx_spi_resume
)
1328 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend
,
1329 s3c64xx_spi_runtime_resume
, NULL
)
1332 static struct s3c64xx_spi_port_config s3c2443_spi_port_config
= {
1333 .fifo_lvl_mask
= { 0x7f },
1334 .rx_lvl_offset
= 13,
1339 static struct s3c64xx_spi_port_config s3c6410_spi_port_config
= {
1340 .fifo_lvl_mask
= { 0x7f, 0x7F },
1341 .rx_lvl_offset
= 13,
1345 static struct s3c64xx_spi_port_config s5pv210_spi_port_config
= {
1346 .fifo_lvl_mask
= { 0x1ff, 0x7F },
1347 .rx_lvl_offset
= 15,
1352 static struct s3c64xx_spi_port_config exynos4_spi_port_config
= {
1353 .fifo_lvl_mask
= { 0x1ff, 0x7F, 0x7F },
1354 .rx_lvl_offset
= 15,
1357 .clk_from_cmu
= true,
1360 static struct s3c64xx_spi_port_config exynos5440_spi_port_config
= {
1361 .fifo_lvl_mask
= { 0x1ff },
1362 .rx_lvl_offset
= 15,
1365 .clk_from_cmu
= true,
1366 .quirks
= S3C64XX_SPI_QUIRK_POLL
,
1369 static struct s3c64xx_spi_port_config exynos7_spi_port_config
= {
1370 .fifo_lvl_mask
= { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1371 .rx_lvl_offset
= 15,
1374 .clk_from_cmu
= true,
1375 .quirks
= S3C64XX_SPI_QUIRK_CS_AUTO
,
1378 static struct s3c64xx_spi_port_config exynos5433_spi_port_config
= {
1379 .fifo_lvl_mask
= { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1380 .rx_lvl_offset
= 15,
1383 .clk_from_cmu
= true,
1385 .quirks
= S3C64XX_SPI_QUIRK_CS_AUTO
,
1388 static const struct platform_device_id s3c64xx_spi_driver_ids
[] = {
1390 .name
= "s3c2443-spi",
1391 .driver_data
= (kernel_ulong_t
)&s3c2443_spi_port_config
,
1393 .name
= "s3c6410-spi",
1394 .driver_data
= (kernel_ulong_t
)&s3c6410_spi_port_config
,
1399 static const struct of_device_id s3c64xx_spi_dt_match
[] = {
1400 { .compatible
= "samsung,s3c2443-spi",
1401 .data
= (void *)&s3c2443_spi_port_config
,
1403 { .compatible
= "samsung,s3c6410-spi",
1404 .data
= (void *)&s3c6410_spi_port_config
,
1406 { .compatible
= "samsung,s5pv210-spi",
1407 .data
= (void *)&s5pv210_spi_port_config
,
1409 { .compatible
= "samsung,exynos4210-spi",
1410 .data
= (void *)&exynos4_spi_port_config
,
1412 { .compatible
= "samsung,exynos5440-spi",
1413 .data
= (void *)&exynos5440_spi_port_config
,
1415 { .compatible
= "samsung,exynos7-spi",
1416 .data
= (void *)&exynos7_spi_port_config
,
1418 { .compatible
= "samsung,exynos5433-spi",
1419 .data
= (void *)&exynos5433_spi_port_config
,
1423 MODULE_DEVICE_TABLE(of
, s3c64xx_spi_dt_match
);
1425 static struct platform_driver s3c64xx_spi_driver
= {
1427 .name
= "s3c64xx-spi",
1428 .pm
= &s3c64xx_spi_pm
,
1429 .of_match_table
= of_match_ptr(s3c64xx_spi_dt_match
),
1431 .probe
= s3c64xx_spi_probe
,
1432 .remove
= s3c64xx_spi_remove
,
1433 .id_table
= s3c64xx_spi_driver_ids
,
1435 MODULE_ALIAS("platform:s3c64xx-spi");
1437 module_platform_driver(s3c64xx_spi_driver
);
1439 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1440 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1441 MODULE_LICENSE("GPL");