2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/clk.h>
17 #include <linux/dmaengine.h>
18 #include <linux/module.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/scatterlist.h>
26 #define DRIVER_NAME "rockchip-spi"
28 /* SPI register offsets */
29 #define ROCKCHIP_SPI_CTRLR0 0x0000
30 #define ROCKCHIP_SPI_CTRLR1 0x0004
31 #define ROCKCHIP_SPI_SSIENR 0x0008
32 #define ROCKCHIP_SPI_SER 0x000c
33 #define ROCKCHIP_SPI_BAUDR 0x0010
34 #define ROCKCHIP_SPI_TXFTLR 0x0014
35 #define ROCKCHIP_SPI_RXFTLR 0x0018
36 #define ROCKCHIP_SPI_TXFLR 0x001c
37 #define ROCKCHIP_SPI_RXFLR 0x0020
38 #define ROCKCHIP_SPI_SR 0x0024
39 #define ROCKCHIP_SPI_IPR 0x0028
40 #define ROCKCHIP_SPI_IMR 0x002c
41 #define ROCKCHIP_SPI_ISR 0x0030
42 #define ROCKCHIP_SPI_RISR 0x0034
43 #define ROCKCHIP_SPI_ICR 0x0038
44 #define ROCKCHIP_SPI_DMACR 0x003c
45 #define ROCKCHIP_SPI_DMATDLR 0x0040
46 #define ROCKCHIP_SPI_DMARDLR 0x0044
47 #define ROCKCHIP_SPI_TXDR 0x0400
48 #define ROCKCHIP_SPI_RXDR 0x0800
50 /* Bit fields in CTRLR0 */
51 #define CR0_DFS_OFFSET 0
53 #define CR0_CFS_OFFSET 2
55 #define CR0_SCPH_OFFSET 6
57 #define CR0_SCPOL_OFFSET 7
59 #define CR0_CSM_OFFSET 8
60 #define CR0_CSM_KEEP 0x0
61 /* ss_n be high for half sclk_out cycles */
62 #define CR0_CSM_HALF 0X1
63 /* ss_n be high for one sclk_out cycle */
64 #define CR0_CSM_ONE 0x2
66 /* ss_n to sclk_out delay */
67 #define CR0_SSD_OFFSET 10
69 * The period between ss_n active and
70 * sclk_out active is half sclk_out cycles
72 #define CR0_SSD_HALF 0x0
74 * The period between ss_n active and
75 * sclk_out active is one sclk_out cycle
77 #define CR0_SSD_ONE 0x1
79 #define CR0_EM_OFFSET 11
80 #define CR0_EM_LITTLE 0x0
81 #define CR0_EM_BIG 0x1
83 #define CR0_FBM_OFFSET 12
84 #define CR0_FBM_MSB 0x0
85 #define CR0_FBM_LSB 0x1
87 #define CR0_BHT_OFFSET 13
88 #define CR0_BHT_16BIT 0x0
89 #define CR0_BHT_8BIT 0x1
91 #define CR0_RSD_OFFSET 14
93 #define CR0_FRF_OFFSET 16
94 #define CR0_FRF_SPI 0x0
95 #define CR0_FRF_SSP 0x1
96 #define CR0_FRF_MICROWIRE 0x2
98 #define CR0_XFM_OFFSET 18
99 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
100 #define CR0_XFM_TR 0x0
101 #define CR0_XFM_TO 0x1
102 #define CR0_XFM_RO 0x2
104 #define CR0_OPM_OFFSET 20
105 #define CR0_OPM_MASTER 0x0
106 #define CR0_OPM_SLAVE 0x1
108 #define CR0_MTM_OFFSET 0x21
110 /* Bit fields in SER, 2bit */
113 /* Bit fields in SR, 5bit */
115 #define SR_BUSY (1 << 0)
116 #define SR_TF_FULL (1 << 1)
117 #define SR_TF_EMPTY (1 << 2)
118 #define SR_RF_EMPTY (1 << 3)
119 #define SR_RF_FULL (1 << 4)
121 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
122 #define INT_MASK 0x1f
123 #define INT_TF_EMPTY (1 << 0)
124 #define INT_TF_OVERFLOW (1 << 1)
125 #define INT_RF_UNDERFLOW (1 << 2)
126 #define INT_RF_OVERFLOW (1 << 3)
127 #define INT_RF_FULL (1 << 4)
129 /* Bit fields in ICR, 4bit */
130 #define ICR_MASK 0x0f
131 #define ICR_ALL (1 << 0)
132 #define ICR_RF_UNDERFLOW (1 << 1)
133 #define ICR_RF_OVERFLOW (1 << 2)
134 #define ICR_TF_OVERFLOW (1 << 3)
136 /* Bit fields in DMACR */
137 #define RF_DMA_EN (1 << 0)
138 #define TF_DMA_EN (1 << 1)
140 #define RXBUSY (1 << 0)
141 #define TXBUSY (1 << 1)
143 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
144 #define MAX_SCLK_OUT 50000000
147 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
148 * the controller seems to hang when given 0x10000, so stick with this for now.
150 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
152 enum rockchip_ssi_type
{
158 struct rockchip_spi_dma_data
{
160 enum dma_transfer_direction direction
;
164 struct rockchip_spi
{
166 struct spi_master
*master
;
169 struct clk
*apb_pclk
;
172 /*depth of the FIFO buffer */
174 /* max bus freq supported */
176 /* supported slave numbers */
177 enum rockchip_ssi_type type
;
197 struct sg_table tx_sg
;
198 struct sg_table rx_sg
;
199 struct rockchip_spi_dma_data dma_rx
;
200 struct rockchip_spi_dma_data dma_tx
;
201 struct dma_slave_caps dma_caps
;
204 static inline void spi_enable_chip(struct rockchip_spi
*rs
, int enable
)
206 writel_relaxed((enable
? 1 : 0), rs
->regs
+ ROCKCHIP_SPI_SSIENR
);
209 static inline void spi_set_clk(struct rockchip_spi
*rs
, u16 div
)
211 writel_relaxed(div
, rs
->regs
+ ROCKCHIP_SPI_BAUDR
);
214 static inline void flush_fifo(struct rockchip_spi
*rs
)
216 while (readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXFLR
))
217 readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXDR
);
220 static inline void wait_for_idle(struct rockchip_spi
*rs
)
222 unsigned long timeout
= jiffies
+ msecs_to_jiffies(5);
225 if (!(readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SR
) & SR_BUSY
))
227 } while (!time_after(jiffies
, timeout
));
229 dev_warn(rs
->dev
, "spi controller is in busy state!\n");
232 static u32
get_fifo_len(struct rockchip_spi
*rs
)
236 for (fifo
= 2; fifo
< 32; fifo
++) {
237 writel_relaxed(fifo
, rs
->regs
+ ROCKCHIP_SPI_TXFTLR
);
238 if (fifo
!= readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_TXFTLR
))
242 writel_relaxed(0, rs
->regs
+ ROCKCHIP_SPI_TXFTLR
);
244 return (fifo
== 31) ? 0 : fifo
;
247 static inline u32
tx_max(struct rockchip_spi
*rs
)
249 u32 tx_left
, tx_room
;
251 tx_left
= (rs
->tx_end
- rs
->tx
) / rs
->n_bytes
;
252 tx_room
= rs
->fifo_len
- readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_TXFLR
);
254 return min(tx_left
, tx_room
);
257 static inline u32
rx_max(struct rockchip_spi
*rs
)
259 u32 rx_left
= (rs
->rx_end
- rs
->rx
) / rs
->n_bytes
;
260 u32 rx_room
= (u32
)readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXFLR
);
262 return min(rx_left
, rx_room
);
265 static void rockchip_spi_set_cs(struct spi_device
*spi
, bool enable
)
268 struct spi_master
*master
= spi
->master
;
269 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
271 pm_runtime_get_sync(rs
->dev
);
273 ser
= readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SER
) & SER_MASK
;
277 * static void spi_set_cs(struct spi_device *spi, bool enable)
279 * if (spi->mode & SPI_CS_HIGH)
282 * if (spi->cs_gpio >= 0)
283 * gpio_set_value(spi->cs_gpio, !enable);
284 * else if (spi->master->set_cs)
285 * spi->master->set_cs(spi, !enable);
288 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
291 ser
|= 1 << spi
->chip_select
;
293 ser
&= ~(1 << spi
->chip_select
);
295 writel_relaxed(ser
, rs
->regs
+ ROCKCHIP_SPI_SER
);
297 pm_runtime_put_sync(rs
->dev
);
300 static int rockchip_spi_prepare_message(struct spi_master
*master
,
301 struct spi_message
*msg
)
303 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
304 struct spi_device
*spi
= msg
->spi
;
306 rs
->mode
= spi
->mode
;
311 static void rockchip_spi_handle_err(struct spi_master
*master
,
312 struct spi_message
*msg
)
315 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
317 spin_lock_irqsave(&rs
->lock
, flags
);
320 * For DMA mode, we need terminate DMA channel and flush
321 * fifo for the next transfer if DMA thansfer timeout.
322 * handle_err() was called by core if transfer failed.
323 * Maybe it is reasonable for error handling here.
326 if (rs
->state
& RXBUSY
) {
327 dmaengine_terminate_async(rs
->dma_rx
.ch
);
331 if (rs
->state
& TXBUSY
)
332 dmaengine_terminate_async(rs
->dma_tx
.ch
);
335 spin_unlock_irqrestore(&rs
->lock
, flags
);
338 static int rockchip_spi_unprepare_message(struct spi_master
*master
,
339 struct spi_message
*msg
)
341 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
343 spi_enable_chip(rs
, 0);
348 static void rockchip_spi_pio_writer(struct rockchip_spi
*rs
)
350 u32 max
= tx_max(rs
);
354 if (rs
->n_bytes
== 1)
355 txw
= *(u8
*)(rs
->tx
);
357 txw
= *(u16
*)(rs
->tx
);
359 writel_relaxed(txw
, rs
->regs
+ ROCKCHIP_SPI_TXDR
);
360 rs
->tx
+= rs
->n_bytes
;
364 static void rockchip_spi_pio_reader(struct rockchip_spi
*rs
)
366 u32 max
= rx_max(rs
);
370 rxw
= readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_RXDR
);
371 if (rs
->n_bytes
== 1)
372 *(u8
*)(rs
->rx
) = (u8
)rxw
;
374 *(u16
*)(rs
->rx
) = (u16
)rxw
;
375 rs
->rx
+= rs
->n_bytes
;
379 static int rockchip_spi_pio_transfer(struct rockchip_spi
*rs
)
385 remain
= rs
->tx_end
- rs
->tx
;
386 rockchip_spi_pio_writer(rs
);
390 remain
= rs
->rx_end
- rs
->rx
;
391 rockchip_spi_pio_reader(rs
);
397 /* If tx, wait until the FIFO data completely. */
401 spi_enable_chip(rs
, 0);
406 static void rockchip_spi_dma_rxcb(void *data
)
409 struct rockchip_spi
*rs
= data
;
411 spin_lock_irqsave(&rs
->lock
, flags
);
413 rs
->state
&= ~RXBUSY
;
414 if (!(rs
->state
& TXBUSY
)) {
415 spi_enable_chip(rs
, 0);
416 spi_finalize_current_transfer(rs
->master
);
419 spin_unlock_irqrestore(&rs
->lock
, flags
);
422 static void rockchip_spi_dma_txcb(void *data
)
425 struct rockchip_spi
*rs
= data
;
427 /* Wait until the FIFO data completely. */
430 spin_lock_irqsave(&rs
->lock
, flags
);
432 rs
->state
&= ~TXBUSY
;
433 if (!(rs
->state
& RXBUSY
)) {
434 spi_enable_chip(rs
, 0);
435 spi_finalize_current_transfer(rs
->master
);
438 spin_unlock_irqrestore(&rs
->lock
, flags
);
441 static int rockchip_spi_prepare_dma(struct rockchip_spi
*rs
)
444 struct dma_slave_config rxconf
, txconf
;
445 struct dma_async_tx_descriptor
*rxdesc
, *txdesc
;
447 spin_lock_irqsave(&rs
->lock
, flags
);
448 rs
->state
&= ~RXBUSY
;
449 rs
->state
&= ~TXBUSY
;
450 spin_unlock_irqrestore(&rs
->lock
, flags
);
454 rxconf
.direction
= rs
->dma_rx
.direction
;
455 rxconf
.src_addr
= rs
->dma_rx
.addr
;
456 rxconf
.src_addr_width
= rs
->n_bytes
;
457 if (rs
->dma_caps
.max_burst
> 4)
458 rxconf
.src_maxburst
= 4;
460 rxconf
.src_maxburst
= 1;
461 dmaengine_slave_config(rs
->dma_rx
.ch
, &rxconf
);
463 rxdesc
= dmaengine_prep_slave_sg(
465 rs
->rx_sg
.sgl
, rs
->rx_sg
.nents
,
466 rs
->dma_rx
.direction
, DMA_PREP_INTERRUPT
);
470 rxdesc
->callback
= rockchip_spi_dma_rxcb
;
471 rxdesc
->callback_param
= rs
;
476 txconf
.direction
= rs
->dma_tx
.direction
;
477 txconf
.dst_addr
= rs
->dma_tx
.addr
;
478 txconf
.dst_addr_width
= rs
->n_bytes
;
479 if (rs
->dma_caps
.max_burst
> 4)
480 txconf
.dst_maxburst
= 4;
482 txconf
.dst_maxburst
= 1;
483 dmaengine_slave_config(rs
->dma_tx
.ch
, &txconf
);
485 txdesc
= dmaengine_prep_slave_sg(
487 rs
->tx_sg
.sgl
, rs
->tx_sg
.nents
,
488 rs
->dma_tx
.direction
, DMA_PREP_INTERRUPT
);
491 dmaengine_terminate_sync(rs
->dma_rx
.ch
);
495 txdesc
->callback
= rockchip_spi_dma_txcb
;
496 txdesc
->callback_param
= rs
;
499 /* rx must be started before tx due to spi instinct */
501 spin_lock_irqsave(&rs
->lock
, flags
);
503 spin_unlock_irqrestore(&rs
->lock
, flags
);
504 dmaengine_submit(rxdesc
);
505 dma_async_issue_pending(rs
->dma_rx
.ch
);
509 spin_lock_irqsave(&rs
->lock
, flags
);
511 spin_unlock_irqrestore(&rs
->lock
, flags
);
512 dmaengine_submit(txdesc
);
513 dma_async_issue_pending(rs
->dma_tx
.ch
);
519 static void rockchip_spi_config(struct rockchip_spi
*rs
)
525 u32 cr0
= (CR0_BHT_8BIT
<< CR0_BHT_OFFSET
)
526 | (CR0_SSD_ONE
<< CR0_SSD_OFFSET
)
527 | (CR0_EM_BIG
<< CR0_EM_OFFSET
);
529 cr0
|= (rs
->n_bytes
<< CR0_DFS_OFFSET
);
530 cr0
|= ((rs
->mode
& 0x3) << CR0_SCPH_OFFSET
);
531 cr0
|= (rs
->tmode
<< CR0_XFM_OFFSET
);
532 cr0
|= (rs
->type
<< CR0_FRF_OFFSET
);
541 if (WARN_ON(rs
->speed
> MAX_SCLK_OUT
))
542 rs
->speed
= MAX_SCLK_OUT
;
544 /* the minimum divisor is 2 */
545 if (rs
->max_freq
< 2 * rs
->speed
) {
546 clk_set_rate(rs
->spiclk
, 2 * rs
->speed
);
547 rs
->max_freq
= clk_get_rate(rs
->spiclk
);
550 /* div doesn't support odd number */
551 div
= DIV_ROUND_UP(rs
->max_freq
, rs
->speed
);
552 div
= (div
+ 1) & 0xfffe;
554 /* Rx sample delay is expressed in parent clock cycles (max 3) */
555 rsd
= DIV_ROUND_CLOSEST(rs
->rsd_nsecs
* (rs
->max_freq
>> 8),
557 if (!rsd
&& rs
->rsd_nsecs
) {
558 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
559 rs
->max_freq
, rs
->rsd_nsecs
);
560 } else if (rsd
> 3) {
562 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
563 rs
->max_freq
, rs
->rsd_nsecs
,
564 rsd
* 1000000000U / rs
->max_freq
);
566 cr0
|= rsd
<< CR0_RSD_OFFSET
;
568 writel_relaxed(cr0
, rs
->regs
+ ROCKCHIP_SPI_CTRLR0
);
570 writel_relaxed(rs
->len
- 1, rs
->regs
+ ROCKCHIP_SPI_CTRLR1
);
571 writel_relaxed(rs
->fifo_len
/ 2 - 1, rs
->regs
+ ROCKCHIP_SPI_TXFTLR
);
572 writel_relaxed(rs
->fifo_len
/ 2 - 1, rs
->regs
+ ROCKCHIP_SPI_RXFTLR
);
574 writel_relaxed(0, rs
->regs
+ ROCKCHIP_SPI_DMATDLR
);
575 writel_relaxed(0, rs
->regs
+ ROCKCHIP_SPI_DMARDLR
);
576 writel_relaxed(dmacr
, rs
->regs
+ ROCKCHIP_SPI_DMACR
);
578 spi_set_clk(rs
, div
);
580 dev_dbg(rs
->dev
, "cr0 0x%x, div %d\n", cr0
, div
);
583 static size_t rockchip_spi_max_transfer_size(struct spi_device
*spi
)
585 return ROCKCHIP_SPI_MAX_TRANLEN
;
588 static int rockchip_spi_transfer_one(
589 struct spi_master
*master
,
590 struct spi_device
*spi
,
591 struct spi_transfer
*xfer
)
594 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
596 WARN_ON(readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SSIENR
) &&
597 (readl_relaxed(rs
->regs
+ ROCKCHIP_SPI_SR
) & SR_BUSY
));
599 if (!xfer
->tx_buf
&& !xfer
->rx_buf
) {
600 dev_err(rs
->dev
, "No buffer for transfer\n");
604 if (xfer
->len
> ROCKCHIP_SPI_MAX_TRANLEN
) {
605 dev_err(rs
->dev
, "Transfer is too long (%d)\n", xfer
->len
);
609 rs
->speed
= xfer
->speed_hz
;
610 rs
->bpw
= xfer
->bits_per_word
;
611 rs
->n_bytes
= rs
->bpw
>> 3;
613 rs
->tx
= xfer
->tx_buf
;
614 rs
->tx_end
= rs
->tx
+ xfer
->len
;
615 rs
->rx
= xfer
->rx_buf
;
616 rs
->rx_end
= rs
->rx
+ xfer
->len
;
619 rs
->tx_sg
= xfer
->tx_sg
;
620 rs
->rx_sg
= xfer
->rx_sg
;
622 if (rs
->tx
&& rs
->rx
)
623 rs
->tmode
= CR0_XFM_TR
;
625 rs
->tmode
= CR0_XFM_TO
;
627 rs
->tmode
= CR0_XFM_RO
;
629 /* we need prepare dma before spi was enabled */
630 if (master
->can_dma
&& master
->can_dma(master
, spi
, xfer
))
635 rockchip_spi_config(rs
);
638 if (rs
->tmode
== CR0_XFM_RO
) {
639 /* rx: dma must be prepared first */
640 ret
= rockchip_spi_prepare_dma(rs
);
641 spi_enable_chip(rs
, 1);
643 /* tx or tr: spi must be enabled first */
644 spi_enable_chip(rs
, 1);
645 ret
= rockchip_spi_prepare_dma(rs
);
647 /* successful DMA prepare means the transfer is in progress */
650 spi_enable_chip(rs
, 1);
651 ret
= rockchip_spi_pio_transfer(rs
);
657 static bool rockchip_spi_can_dma(struct spi_master
*master
,
658 struct spi_device
*spi
,
659 struct spi_transfer
*xfer
)
661 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
663 return (xfer
->len
> rs
->fifo_len
);
666 static int rockchip_spi_probe(struct platform_device
*pdev
)
669 struct rockchip_spi
*rs
;
670 struct spi_master
*master
;
671 struct resource
*mem
;
674 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct rockchip_spi
));
678 platform_set_drvdata(pdev
, master
);
680 rs
= spi_master_get_devdata(master
);
682 /* Get basic io resource and map it */
683 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
684 rs
->regs
= devm_ioremap_resource(&pdev
->dev
, mem
);
685 if (IS_ERR(rs
->regs
)) {
686 ret
= PTR_ERR(rs
->regs
);
687 goto err_ioremap_resource
;
690 rs
->apb_pclk
= devm_clk_get(&pdev
->dev
, "apb_pclk");
691 if (IS_ERR(rs
->apb_pclk
)) {
692 dev_err(&pdev
->dev
, "Failed to get apb_pclk\n");
693 ret
= PTR_ERR(rs
->apb_pclk
);
694 goto err_ioremap_resource
;
697 rs
->spiclk
= devm_clk_get(&pdev
->dev
, "spiclk");
698 if (IS_ERR(rs
->spiclk
)) {
699 dev_err(&pdev
->dev
, "Failed to get spi_pclk\n");
700 ret
= PTR_ERR(rs
->spiclk
);
701 goto err_ioremap_resource
;
704 ret
= clk_prepare_enable(rs
->apb_pclk
);
706 dev_err(&pdev
->dev
, "Failed to enable apb_pclk\n");
707 goto err_ioremap_resource
;
710 ret
= clk_prepare_enable(rs
->spiclk
);
712 dev_err(&pdev
->dev
, "Failed to enable spi_clk\n");
713 goto err_spiclk_enable
;
716 spi_enable_chip(rs
, 0);
718 rs
->type
= SSI_MOTO_SPI
;
720 rs
->dev
= &pdev
->dev
;
721 rs
->max_freq
= clk_get_rate(rs
->spiclk
);
723 if (!of_property_read_u32(pdev
->dev
.of_node
, "rx-sample-delay-ns",
725 rs
->rsd_nsecs
= rsd_nsecs
;
727 rs
->fifo_len
= get_fifo_len(rs
);
729 dev_err(&pdev
->dev
, "Failed to get fifo length\n");
731 goto err_get_fifo_len
;
734 spin_lock_init(&rs
->lock
);
736 pm_runtime_set_active(&pdev
->dev
);
737 pm_runtime_enable(&pdev
->dev
);
739 master
->auto_runtime_pm
= true;
740 master
->bus_num
= pdev
->id
;
741 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LOOP
;
742 master
->num_chipselect
= 2;
743 master
->dev
.of_node
= pdev
->dev
.of_node
;
744 master
->bits_per_word_mask
= SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
746 master
->set_cs
= rockchip_spi_set_cs
;
747 master
->prepare_message
= rockchip_spi_prepare_message
;
748 master
->unprepare_message
= rockchip_spi_unprepare_message
;
749 master
->transfer_one
= rockchip_spi_transfer_one
;
750 master
->max_transfer_size
= rockchip_spi_max_transfer_size
;
751 master
->handle_err
= rockchip_spi_handle_err
;
753 rs
->dma_tx
.ch
= dma_request_chan(rs
->dev
, "tx");
754 if (IS_ERR(rs
->dma_tx
.ch
)) {
755 /* Check tx to see if we need defer probing driver */
756 if (PTR_ERR(rs
->dma_tx
.ch
) == -EPROBE_DEFER
) {
758 goto err_get_fifo_len
;
760 dev_warn(rs
->dev
, "Failed to request TX DMA channel\n");
761 rs
->dma_tx
.ch
= NULL
;
764 rs
->dma_rx
.ch
= dma_request_chan(rs
->dev
, "rx");
765 if (IS_ERR(rs
->dma_rx
.ch
)) {
766 if (PTR_ERR(rs
->dma_rx
.ch
) == -EPROBE_DEFER
) {
768 goto err_free_dma_tx
;
770 dev_warn(rs
->dev
, "Failed to request RX DMA channel\n");
771 rs
->dma_rx
.ch
= NULL
;
774 if (rs
->dma_tx
.ch
&& rs
->dma_rx
.ch
) {
775 dma_get_slave_caps(rs
->dma_rx
.ch
, &(rs
->dma_caps
));
776 rs
->dma_tx
.addr
= (dma_addr_t
)(mem
->start
+ ROCKCHIP_SPI_TXDR
);
777 rs
->dma_rx
.addr
= (dma_addr_t
)(mem
->start
+ ROCKCHIP_SPI_RXDR
);
778 rs
->dma_tx
.direction
= DMA_MEM_TO_DEV
;
779 rs
->dma_rx
.direction
= DMA_DEV_TO_MEM
;
781 master
->can_dma
= rockchip_spi_can_dma
;
782 master
->dma_tx
= rs
->dma_tx
.ch
;
783 master
->dma_rx
= rs
->dma_rx
.ch
;
786 ret
= devm_spi_register_master(&pdev
->dev
, master
);
788 dev_err(&pdev
->dev
, "Failed to register master\n");
789 goto err_register_master
;
795 pm_runtime_disable(&pdev
->dev
);
797 dma_release_channel(rs
->dma_rx
.ch
);
800 dma_release_channel(rs
->dma_tx
.ch
);
802 clk_disable_unprepare(rs
->spiclk
);
804 clk_disable_unprepare(rs
->apb_pclk
);
805 err_ioremap_resource
:
806 spi_master_put(master
);
811 static int rockchip_spi_remove(struct platform_device
*pdev
)
813 struct spi_master
*master
= spi_master_get(platform_get_drvdata(pdev
));
814 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
816 pm_runtime_disable(&pdev
->dev
);
818 clk_disable_unprepare(rs
->spiclk
);
819 clk_disable_unprepare(rs
->apb_pclk
);
822 dma_release_channel(rs
->dma_tx
.ch
);
824 dma_release_channel(rs
->dma_rx
.ch
);
826 spi_master_put(master
);
831 #ifdef CONFIG_PM_SLEEP
832 static int rockchip_spi_suspend(struct device
*dev
)
835 struct spi_master
*master
= dev_get_drvdata(dev
);
836 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
838 ret
= spi_master_suspend(rs
->master
);
842 if (!pm_runtime_suspended(dev
)) {
843 clk_disable_unprepare(rs
->spiclk
);
844 clk_disable_unprepare(rs
->apb_pclk
);
847 pinctrl_pm_select_sleep_state(dev
);
852 static int rockchip_spi_resume(struct device
*dev
)
855 struct spi_master
*master
= dev_get_drvdata(dev
);
856 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
858 pinctrl_pm_select_default_state(dev
);
860 if (!pm_runtime_suspended(dev
)) {
861 ret
= clk_prepare_enable(rs
->apb_pclk
);
865 ret
= clk_prepare_enable(rs
->spiclk
);
867 clk_disable_unprepare(rs
->apb_pclk
);
872 ret
= spi_master_resume(rs
->master
);
874 clk_disable_unprepare(rs
->spiclk
);
875 clk_disable_unprepare(rs
->apb_pclk
);
880 #endif /* CONFIG_PM_SLEEP */
883 static int rockchip_spi_runtime_suspend(struct device
*dev
)
885 struct spi_master
*master
= dev_get_drvdata(dev
);
886 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
888 clk_disable_unprepare(rs
->spiclk
);
889 clk_disable_unprepare(rs
->apb_pclk
);
894 static int rockchip_spi_runtime_resume(struct device
*dev
)
897 struct spi_master
*master
= dev_get_drvdata(dev
);
898 struct rockchip_spi
*rs
= spi_master_get_devdata(master
);
900 ret
= clk_prepare_enable(rs
->apb_pclk
);
904 ret
= clk_prepare_enable(rs
->spiclk
);
906 clk_disable_unprepare(rs
->apb_pclk
);
910 #endif /* CONFIG_PM */
912 static const struct dev_pm_ops rockchip_spi_pm
= {
913 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend
, rockchip_spi_resume
)
914 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend
,
915 rockchip_spi_runtime_resume
, NULL
)
918 static const struct of_device_id rockchip_spi_dt_match
[] = {
919 { .compatible
= "rockchip,rk3036-spi", },
920 { .compatible
= "rockchip,rk3066-spi", },
921 { .compatible
= "rockchip,rk3188-spi", },
922 { .compatible
= "rockchip,rk3228-spi", },
923 { .compatible
= "rockchip,rk3288-spi", },
924 { .compatible
= "rockchip,rk3368-spi", },
925 { .compatible
= "rockchip,rk3399-spi", },
928 MODULE_DEVICE_TABLE(of
, rockchip_spi_dt_match
);
930 static struct platform_driver rockchip_spi_driver
= {
933 .pm
= &rockchip_spi_pm
,
934 .of_match_table
= of_match_ptr(rockchip_spi_dt_match
),
936 .probe
= rockchip_spi_probe
,
937 .remove
= rockchip_spi_remove
,
940 module_platform_driver(rockchip_spi_driver
);
942 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
943 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
944 MODULE_LICENSE("GPL v2");