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Merge tag 'ipvs-fixes-for-v4.12' of http://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / spi / spi-imx.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/irq.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/slab.h>
35 #include <linux/spi/spi.h>
36 #include <linux/spi/spi_bitbang.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/of_gpio.h>
41
42 #include <linux/platform_data/dma-imx.h>
43 #include <linux/platform_data/spi-imx.h>
44
45 #define DRIVER_NAME "spi_imx"
46
47 #define MXC_CSPIRXDATA 0x00
48 #define MXC_CSPITXDATA 0x04
49 #define MXC_CSPICTRL 0x08
50 #define MXC_CSPIINT 0x0c
51 #define MXC_RESET 0x1c
52
53 /* generic defines to abstract from the different register layouts */
54 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56
57 /* The maximum bytes that a sdma BD can transfer.*/
58 #define MAX_SDMA_BD_BYTES (1 << 15)
59 struct spi_imx_config {
60 unsigned int speed_hz;
61 unsigned int bpw;
62 };
63
64 enum spi_imx_devtype {
65 IMX1_CSPI,
66 IMX21_CSPI,
67 IMX27_CSPI,
68 IMX31_CSPI,
69 IMX35_CSPI, /* CSPI on all i.mx except above */
70 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
71 };
72
73 struct spi_imx_data;
74
75 struct spi_imx_devtype_data {
76 void (*intctrl)(struct spi_imx_data *, int);
77 int (*config)(struct spi_device *, struct spi_imx_config *);
78 void (*trigger)(struct spi_imx_data *);
79 int (*rx_available)(struct spi_imx_data *);
80 void (*reset)(struct spi_imx_data *);
81 enum spi_imx_devtype devtype;
82 };
83
84 struct spi_imx_data {
85 struct spi_bitbang bitbang;
86 struct device *dev;
87
88 struct completion xfer_done;
89 void __iomem *base;
90 unsigned long base_phys;
91
92 struct clk *clk_per;
93 struct clk *clk_ipg;
94 unsigned long spi_clk;
95 unsigned int spi_bus_clk;
96
97 unsigned int bytes_per_word;
98 unsigned int spi_drctl;
99
100 unsigned int count;
101 void (*tx)(struct spi_imx_data *);
102 void (*rx)(struct spi_imx_data *);
103 void *rx_buf;
104 const void *tx_buf;
105 unsigned int txfifo; /* number of words pushed in tx FIFO */
106
107 /* DMA */
108 bool usedma;
109 u32 wml;
110 struct completion dma_rx_completion;
111 struct completion dma_tx_completion;
112
113 const struct spi_imx_devtype_data *devtype_data;
114 };
115
116 static inline int is_imx27_cspi(struct spi_imx_data *d)
117 {
118 return d->devtype_data->devtype == IMX27_CSPI;
119 }
120
121 static inline int is_imx35_cspi(struct spi_imx_data *d)
122 {
123 return d->devtype_data->devtype == IMX35_CSPI;
124 }
125
126 static inline int is_imx51_ecspi(struct spi_imx_data *d)
127 {
128 return d->devtype_data->devtype == IMX51_ECSPI;
129 }
130
131 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
132 {
133 return is_imx51_ecspi(d) ? 64 : 8;
134 }
135
136 #define MXC_SPI_BUF_RX(type) \
137 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
138 { \
139 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
140 \
141 if (spi_imx->rx_buf) { \
142 *(type *)spi_imx->rx_buf = val; \
143 spi_imx->rx_buf += sizeof(type); \
144 } \
145 }
146
147 #define MXC_SPI_BUF_TX(type) \
148 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
149 { \
150 type val = 0; \
151 \
152 if (spi_imx->tx_buf) { \
153 val = *(type *)spi_imx->tx_buf; \
154 spi_imx->tx_buf += sizeof(type); \
155 } \
156 \
157 spi_imx->count -= sizeof(type); \
158 \
159 writel(val, spi_imx->base + MXC_CSPITXDATA); \
160 }
161
162 MXC_SPI_BUF_RX(u8)
163 MXC_SPI_BUF_TX(u8)
164 MXC_SPI_BUF_RX(u16)
165 MXC_SPI_BUF_TX(u16)
166 MXC_SPI_BUF_RX(u32)
167 MXC_SPI_BUF_TX(u32)
168
169 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
170 * (which is currently not the case in this driver)
171 */
172 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
173 256, 384, 512, 768, 1024};
174
175 /* MX21, MX27 */
176 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
177 unsigned int fspi, unsigned int max, unsigned int *fres)
178 {
179 int i;
180
181 for (i = 2; i < max; i++)
182 if (fspi * mxc_clkdivs[i] >= fin)
183 break;
184
185 *fres = fin / mxc_clkdivs[i];
186 return i;
187 }
188
189 /* MX1, MX31, MX35, MX51 CSPI */
190 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
191 unsigned int fspi, unsigned int *fres)
192 {
193 int i, div = 4;
194
195 for (i = 0; i < 7; i++) {
196 if (fspi * div >= fin)
197 goto out;
198 div <<= 1;
199 }
200
201 out:
202 *fres = fin / div;
203 return i;
204 }
205
206 static int spi_imx_bytes_per_word(const int bpw)
207 {
208 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
209 }
210
211 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
212 struct spi_transfer *transfer)
213 {
214 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
215 unsigned int bpw, i;
216
217 if (!master->dma_rx)
218 return false;
219
220 if (!transfer)
221 return false;
222
223 bpw = transfer->bits_per_word;
224 if (!bpw)
225 bpw = spi->bits_per_word;
226
227 bpw = spi_imx_bytes_per_word(bpw);
228
229 if (bpw != 1 && bpw != 2 && bpw != 4)
230 return false;
231
232 for (i = spi_imx_get_fifosize(spi_imx) / 2; i > 0; i--) {
233 if (!(transfer->len % (i * bpw)))
234 break;
235 }
236
237 if (i == 0)
238 return false;
239
240 spi_imx->wml = i;
241
242 return true;
243 }
244
245 #define MX51_ECSPI_CTRL 0x08
246 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
247 #define MX51_ECSPI_CTRL_XCH (1 << 2)
248 #define MX51_ECSPI_CTRL_SMC (1 << 3)
249 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
250 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
251 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
252 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
253 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
254 #define MX51_ECSPI_CTRL_BL_OFFSET 20
255
256 #define MX51_ECSPI_CONFIG 0x0c
257 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
258 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
259 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
260 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
261 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
262
263 #define MX51_ECSPI_INT 0x10
264 #define MX51_ECSPI_INT_TEEN (1 << 0)
265 #define MX51_ECSPI_INT_RREN (1 << 3)
266
267 #define MX51_ECSPI_DMA 0x14
268 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
269 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
270 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
271
272 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
273 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
274 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
275
276 #define MX51_ECSPI_STAT 0x18
277 #define MX51_ECSPI_STAT_RR (1 << 3)
278
279 #define MX51_ECSPI_TESTREG 0x20
280 #define MX51_ECSPI_TESTREG_LBC BIT(31)
281
282 /* MX51 eCSPI */
283 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
284 unsigned int fspi, unsigned int *fres)
285 {
286 /*
287 * there are two 4-bit dividers, the pre-divider divides by
288 * $pre, the post-divider by 2^$post
289 */
290 unsigned int pre, post;
291 unsigned int fin = spi_imx->spi_clk;
292
293 if (unlikely(fspi > fin))
294 return 0;
295
296 post = fls(fin) - fls(fspi);
297 if (fin > fspi << post)
298 post++;
299
300 /* now we have: (fin <= fspi << post) with post being minimal */
301
302 post = max(4U, post) - 4;
303 if (unlikely(post > 0xf)) {
304 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
305 fspi, fin);
306 return 0xff;
307 }
308
309 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
310
311 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
312 __func__, fin, fspi, post, pre);
313
314 /* Resulting frequency for the SCLK line. */
315 *fres = (fin / (pre + 1)) >> post;
316
317 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
318 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
319 }
320
321 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
322 {
323 unsigned val = 0;
324
325 if (enable & MXC_INT_TE)
326 val |= MX51_ECSPI_INT_TEEN;
327
328 if (enable & MXC_INT_RR)
329 val |= MX51_ECSPI_INT_RREN;
330
331 writel(val, spi_imx->base + MX51_ECSPI_INT);
332 }
333
334 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
335 {
336 u32 reg;
337
338 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
339 reg |= MX51_ECSPI_CTRL_XCH;
340 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
341 }
342
343 static int mx51_ecspi_config(struct spi_device *spi,
344 struct spi_imx_config *config)
345 {
346 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
347 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
348 u32 clk = config->speed_hz, delay, reg;
349 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
350
351 /*
352 * The hardware seems to have a race condition when changing modes. The
353 * current assumption is that the selection of the channel arrives
354 * earlier in the hardware than the mode bits when they are written at
355 * the same time.
356 * So set master mode for all channels as we do not support slave mode.
357 */
358 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
359
360 /*
361 * Enable SPI_RDY handling (falling edge/level triggered).
362 */
363 if (spi->mode & SPI_READY)
364 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
365
366 /* set clock speed */
367 ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
368 spi_imx->spi_bus_clk = clk;
369
370 /* set chip select to use */
371 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
372
373 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
374
375 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
376
377 if (spi->mode & SPI_CPHA)
378 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
379 else
380 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
381
382 if (spi->mode & SPI_CPOL) {
383 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
384 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
385 } else {
386 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
387 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
388 }
389 if (spi->mode & SPI_CS_HIGH)
390 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
391 else
392 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
393
394 if (spi_imx->usedma)
395 ctrl |= MX51_ECSPI_CTRL_SMC;
396
397 /* CTRL register always go first to bring out controller from reset */
398 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
399
400 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
401 if (spi->mode & SPI_LOOP)
402 reg |= MX51_ECSPI_TESTREG_LBC;
403 else
404 reg &= ~MX51_ECSPI_TESTREG_LBC;
405 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
406
407 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
408
409 /*
410 * Wait until the changes in the configuration register CONFIGREG
411 * propagate into the hardware. It takes exactly one tick of the
412 * SCLK clock, but we will wait two SCLK clock just to be sure. The
413 * effect of the delay it takes for the hardware to apply changes
414 * is noticable if the SCLK clock run very slow. In such a case, if
415 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
416 * be asserted before the SCLK polarity changes, which would disrupt
417 * the SPI communication as the device on the other end would consider
418 * the change of SCLK polarity as a clock tick already.
419 */
420 delay = (2 * 1000000) / clk;
421 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
422 udelay(delay);
423 else /* SCLK is _very_ slow */
424 usleep_range(delay, delay + 10);
425
426 /*
427 * Configure the DMA register: setup the watermark
428 * and enable DMA request.
429 */
430
431 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
432 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
433 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
434 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
435 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
436
437 return 0;
438 }
439
440 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
441 {
442 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
443 }
444
445 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
446 {
447 /* drain receive buffer */
448 while (mx51_ecspi_rx_available(spi_imx))
449 readl(spi_imx->base + MXC_CSPIRXDATA);
450 }
451
452 #define MX31_INTREG_TEEN (1 << 0)
453 #define MX31_INTREG_RREN (1 << 3)
454
455 #define MX31_CSPICTRL_ENABLE (1 << 0)
456 #define MX31_CSPICTRL_MASTER (1 << 1)
457 #define MX31_CSPICTRL_XCH (1 << 2)
458 #define MX31_CSPICTRL_SMC (1 << 3)
459 #define MX31_CSPICTRL_POL (1 << 4)
460 #define MX31_CSPICTRL_PHA (1 << 5)
461 #define MX31_CSPICTRL_SSCTL (1 << 6)
462 #define MX31_CSPICTRL_SSPOL (1 << 7)
463 #define MX31_CSPICTRL_BC_SHIFT 8
464 #define MX35_CSPICTRL_BL_SHIFT 20
465 #define MX31_CSPICTRL_CS_SHIFT 24
466 #define MX35_CSPICTRL_CS_SHIFT 12
467 #define MX31_CSPICTRL_DR_SHIFT 16
468
469 #define MX31_CSPI_DMAREG 0x10
470 #define MX31_DMAREG_RH_DEN (1<<4)
471 #define MX31_DMAREG_TH_DEN (1<<1)
472
473 #define MX31_CSPISTATUS 0x14
474 #define MX31_STATUS_RR (1 << 3)
475
476 #define MX31_CSPI_TESTREG 0x1C
477 #define MX31_TEST_LBC (1 << 14)
478
479 /* These functions also work for the i.MX35, but be aware that
480 * the i.MX35 has a slightly different register layout for bits
481 * we do not use here.
482 */
483 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
484 {
485 unsigned int val = 0;
486
487 if (enable & MXC_INT_TE)
488 val |= MX31_INTREG_TEEN;
489 if (enable & MXC_INT_RR)
490 val |= MX31_INTREG_RREN;
491
492 writel(val, spi_imx->base + MXC_CSPIINT);
493 }
494
495 static void mx31_trigger(struct spi_imx_data *spi_imx)
496 {
497 unsigned int reg;
498
499 reg = readl(spi_imx->base + MXC_CSPICTRL);
500 reg |= MX31_CSPICTRL_XCH;
501 writel(reg, spi_imx->base + MXC_CSPICTRL);
502 }
503
504 static int mx31_config(struct spi_device *spi, struct spi_imx_config *config)
505 {
506 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
507 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
508 unsigned int clk;
509
510 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) <<
511 MX31_CSPICTRL_DR_SHIFT;
512 spi_imx->spi_bus_clk = clk;
513
514 if (is_imx35_cspi(spi_imx)) {
515 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
516 reg |= MX31_CSPICTRL_SSCTL;
517 } else {
518 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
519 }
520
521 if (spi->mode & SPI_CPHA)
522 reg |= MX31_CSPICTRL_PHA;
523 if (spi->mode & SPI_CPOL)
524 reg |= MX31_CSPICTRL_POL;
525 if (spi->mode & SPI_CS_HIGH)
526 reg |= MX31_CSPICTRL_SSPOL;
527 if (spi->cs_gpio < 0)
528 reg |= (spi->cs_gpio + 32) <<
529 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
530 MX31_CSPICTRL_CS_SHIFT);
531
532 if (spi_imx->usedma)
533 reg |= MX31_CSPICTRL_SMC;
534
535 writel(reg, spi_imx->base + MXC_CSPICTRL);
536
537 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
538 if (spi->mode & SPI_LOOP)
539 reg |= MX31_TEST_LBC;
540 else
541 reg &= ~MX31_TEST_LBC;
542 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
543
544 if (spi_imx->usedma) {
545 /* configure DMA requests when RXFIFO is half full and
546 when TXFIFO is half empty */
547 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
548 spi_imx->base + MX31_CSPI_DMAREG);
549 }
550
551 return 0;
552 }
553
554 static int mx31_rx_available(struct spi_imx_data *spi_imx)
555 {
556 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
557 }
558
559 static void mx31_reset(struct spi_imx_data *spi_imx)
560 {
561 /* drain receive buffer */
562 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
563 readl(spi_imx->base + MXC_CSPIRXDATA);
564 }
565
566 #define MX21_INTREG_RR (1 << 4)
567 #define MX21_INTREG_TEEN (1 << 9)
568 #define MX21_INTREG_RREN (1 << 13)
569
570 #define MX21_CSPICTRL_POL (1 << 5)
571 #define MX21_CSPICTRL_PHA (1 << 6)
572 #define MX21_CSPICTRL_SSPOL (1 << 8)
573 #define MX21_CSPICTRL_XCH (1 << 9)
574 #define MX21_CSPICTRL_ENABLE (1 << 10)
575 #define MX21_CSPICTRL_MASTER (1 << 11)
576 #define MX21_CSPICTRL_DR_SHIFT 14
577 #define MX21_CSPICTRL_CS_SHIFT 19
578
579 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
580 {
581 unsigned int val = 0;
582
583 if (enable & MXC_INT_TE)
584 val |= MX21_INTREG_TEEN;
585 if (enable & MXC_INT_RR)
586 val |= MX21_INTREG_RREN;
587
588 writel(val, spi_imx->base + MXC_CSPIINT);
589 }
590
591 static void mx21_trigger(struct spi_imx_data *spi_imx)
592 {
593 unsigned int reg;
594
595 reg = readl(spi_imx->base + MXC_CSPICTRL);
596 reg |= MX21_CSPICTRL_XCH;
597 writel(reg, spi_imx->base + MXC_CSPICTRL);
598 }
599
600 static int mx21_config(struct spi_device *spi, struct spi_imx_config *config)
601 {
602 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
603 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
604 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
605 unsigned int clk;
606
607 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max, &clk)
608 << MX21_CSPICTRL_DR_SHIFT;
609 spi_imx->spi_bus_clk = clk;
610
611 reg |= config->bpw - 1;
612
613 if (spi->mode & SPI_CPHA)
614 reg |= MX21_CSPICTRL_PHA;
615 if (spi->mode & SPI_CPOL)
616 reg |= MX21_CSPICTRL_POL;
617 if (spi->mode & SPI_CS_HIGH)
618 reg |= MX21_CSPICTRL_SSPOL;
619 if (spi->cs_gpio < 0)
620 reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT;
621
622 writel(reg, spi_imx->base + MXC_CSPICTRL);
623
624 return 0;
625 }
626
627 static int mx21_rx_available(struct spi_imx_data *spi_imx)
628 {
629 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
630 }
631
632 static void mx21_reset(struct spi_imx_data *spi_imx)
633 {
634 writel(1, spi_imx->base + MXC_RESET);
635 }
636
637 #define MX1_INTREG_RR (1 << 3)
638 #define MX1_INTREG_TEEN (1 << 8)
639 #define MX1_INTREG_RREN (1 << 11)
640
641 #define MX1_CSPICTRL_POL (1 << 4)
642 #define MX1_CSPICTRL_PHA (1 << 5)
643 #define MX1_CSPICTRL_XCH (1 << 8)
644 #define MX1_CSPICTRL_ENABLE (1 << 9)
645 #define MX1_CSPICTRL_MASTER (1 << 10)
646 #define MX1_CSPICTRL_DR_SHIFT 13
647
648 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
649 {
650 unsigned int val = 0;
651
652 if (enable & MXC_INT_TE)
653 val |= MX1_INTREG_TEEN;
654 if (enable & MXC_INT_RR)
655 val |= MX1_INTREG_RREN;
656
657 writel(val, spi_imx->base + MXC_CSPIINT);
658 }
659
660 static void mx1_trigger(struct spi_imx_data *spi_imx)
661 {
662 unsigned int reg;
663
664 reg = readl(spi_imx->base + MXC_CSPICTRL);
665 reg |= MX1_CSPICTRL_XCH;
666 writel(reg, spi_imx->base + MXC_CSPICTRL);
667 }
668
669 static int mx1_config(struct spi_device *spi, struct spi_imx_config *config)
670 {
671 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
672 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
673 unsigned int clk;
674
675 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz, &clk) <<
676 MX1_CSPICTRL_DR_SHIFT;
677 spi_imx->spi_bus_clk = clk;
678
679 reg |= config->bpw - 1;
680
681 if (spi->mode & SPI_CPHA)
682 reg |= MX1_CSPICTRL_PHA;
683 if (spi->mode & SPI_CPOL)
684 reg |= MX1_CSPICTRL_POL;
685
686 writel(reg, spi_imx->base + MXC_CSPICTRL);
687
688 return 0;
689 }
690
691 static int mx1_rx_available(struct spi_imx_data *spi_imx)
692 {
693 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
694 }
695
696 static void mx1_reset(struct spi_imx_data *spi_imx)
697 {
698 writel(1, spi_imx->base + MXC_RESET);
699 }
700
701 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
702 .intctrl = mx1_intctrl,
703 .config = mx1_config,
704 .trigger = mx1_trigger,
705 .rx_available = mx1_rx_available,
706 .reset = mx1_reset,
707 .devtype = IMX1_CSPI,
708 };
709
710 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
711 .intctrl = mx21_intctrl,
712 .config = mx21_config,
713 .trigger = mx21_trigger,
714 .rx_available = mx21_rx_available,
715 .reset = mx21_reset,
716 .devtype = IMX21_CSPI,
717 };
718
719 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
720 /* i.mx27 cspi shares the functions with i.mx21 one */
721 .intctrl = mx21_intctrl,
722 .config = mx21_config,
723 .trigger = mx21_trigger,
724 .rx_available = mx21_rx_available,
725 .reset = mx21_reset,
726 .devtype = IMX27_CSPI,
727 };
728
729 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
730 .intctrl = mx31_intctrl,
731 .config = mx31_config,
732 .trigger = mx31_trigger,
733 .rx_available = mx31_rx_available,
734 .reset = mx31_reset,
735 .devtype = IMX31_CSPI,
736 };
737
738 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
739 /* i.mx35 and later cspi shares the functions with i.mx31 one */
740 .intctrl = mx31_intctrl,
741 .config = mx31_config,
742 .trigger = mx31_trigger,
743 .rx_available = mx31_rx_available,
744 .reset = mx31_reset,
745 .devtype = IMX35_CSPI,
746 };
747
748 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
749 .intctrl = mx51_ecspi_intctrl,
750 .config = mx51_ecspi_config,
751 .trigger = mx51_ecspi_trigger,
752 .rx_available = mx51_ecspi_rx_available,
753 .reset = mx51_ecspi_reset,
754 .devtype = IMX51_ECSPI,
755 };
756
757 static const struct platform_device_id spi_imx_devtype[] = {
758 {
759 .name = "imx1-cspi",
760 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
761 }, {
762 .name = "imx21-cspi",
763 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
764 }, {
765 .name = "imx27-cspi",
766 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
767 }, {
768 .name = "imx31-cspi",
769 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
770 }, {
771 .name = "imx35-cspi",
772 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
773 }, {
774 .name = "imx51-ecspi",
775 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
776 }, {
777 /* sentinel */
778 }
779 };
780
781 static const struct of_device_id spi_imx_dt_ids[] = {
782 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
783 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
784 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
785 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
786 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
787 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
788 { /* sentinel */ }
789 };
790 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
791
792 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
793 {
794 int active = is_active != BITBANG_CS_INACTIVE;
795 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
796
797 if (!gpio_is_valid(spi->cs_gpio))
798 return;
799
800 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
801 }
802
803 static void spi_imx_push(struct spi_imx_data *spi_imx)
804 {
805 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
806 if (!spi_imx->count)
807 break;
808 spi_imx->tx(spi_imx);
809 spi_imx->txfifo++;
810 }
811
812 spi_imx->devtype_data->trigger(spi_imx);
813 }
814
815 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
816 {
817 struct spi_imx_data *spi_imx = dev_id;
818
819 while (spi_imx->devtype_data->rx_available(spi_imx)) {
820 spi_imx->rx(spi_imx);
821 spi_imx->txfifo--;
822 }
823
824 if (spi_imx->count) {
825 spi_imx_push(spi_imx);
826 return IRQ_HANDLED;
827 }
828
829 if (spi_imx->txfifo) {
830 /* No data left to push, but still waiting for rx data,
831 * enable receive data available interrupt.
832 */
833 spi_imx->devtype_data->intctrl(
834 spi_imx, MXC_INT_RR);
835 return IRQ_HANDLED;
836 }
837
838 spi_imx->devtype_data->intctrl(spi_imx, 0);
839 complete(&spi_imx->xfer_done);
840
841 return IRQ_HANDLED;
842 }
843
844 static int spi_imx_dma_configure(struct spi_master *master,
845 int bytes_per_word)
846 {
847 int ret;
848 enum dma_slave_buswidth buswidth;
849 struct dma_slave_config rx = {}, tx = {};
850 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
851
852 switch (bytes_per_word) {
853 case 4:
854 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
855 break;
856 case 2:
857 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
858 break;
859 case 1:
860 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
861 break;
862 default:
863 return -EINVAL;
864 }
865
866 tx.direction = DMA_MEM_TO_DEV;
867 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
868 tx.dst_addr_width = buswidth;
869 tx.dst_maxburst = spi_imx->wml;
870 ret = dmaengine_slave_config(master->dma_tx, &tx);
871 if (ret) {
872 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
873 return ret;
874 }
875
876 rx.direction = DMA_DEV_TO_MEM;
877 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
878 rx.src_addr_width = buswidth;
879 rx.src_maxburst = spi_imx->wml;
880 ret = dmaengine_slave_config(master->dma_rx, &rx);
881 if (ret) {
882 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
883 return ret;
884 }
885
886 spi_imx->bytes_per_word = bytes_per_word;
887
888 return 0;
889 }
890
891 static int spi_imx_setupxfer(struct spi_device *spi,
892 struct spi_transfer *t)
893 {
894 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
895 struct spi_imx_config config;
896 int ret;
897
898 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
899 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
900
901 if (!config.speed_hz)
902 config.speed_hz = spi->max_speed_hz;
903 if (!config.bpw)
904 config.bpw = spi->bits_per_word;
905
906 /* Initialize the functions for transfer */
907 if (config.bpw <= 8) {
908 spi_imx->rx = spi_imx_buf_rx_u8;
909 spi_imx->tx = spi_imx_buf_tx_u8;
910 } else if (config.bpw <= 16) {
911 spi_imx->rx = spi_imx_buf_rx_u16;
912 spi_imx->tx = spi_imx_buf_tx_u16;
913 } else {
914 spi_imx->rx = spi_imx_buf_rx_u32;
915 spi_imx->tx = spi_imx_buf_tx_u32;
916 }
917
918 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
919 spi_imx->usedma = 1;
920 else
921 spi_imx->usedma = 0;
922
923 if (spi_imx->usedma) {
924 ret = spi_imx_dma_configure(spi->master,
925 spi_imx_bytes_per_word(config.bpw));
926 if (ret)
927 return ret;
928 }
929
930 spi_imx->devtype_data->config(spi, &config);
931
932 return 0;
933 }
934
935 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
936 {
937 struct spi_master *master = spi_imx->bitbang.master;
938
939 if (master->dma_rx) {
940 dma_release_channel(master->dma_rx);
941 master->dma_rx = NULL;
942 }
943
944 if (master->dma_tx) {
945 dma_release_channel(master->dma_tx);
946 master->dma_tx = NULL;
947 }
948 }
949
950 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
951 struct spi_master *master)
952 {
953 int ret;
954
955 /* use pio mode for i.mx6dl chip TKT238285 */
956 if (of_machine_is_compatible("fsl,imx6dl"))
957 return 0;
958
959 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
960
961 /* Prepare for TX DMA: */
962 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
963 if (IS_ERR(master->dma_tx)) {
964 ret = PTR_ERR(master->dma_tx);
965 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
966 master->dma_tx = NULL;
967 goto err;
968 }
969
970 /* Prepare for RX : */
971 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
972 if (IS_ERR(master->dma_rx)) {
973 ret = PTR_ERR(master->dma_rx);
974 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
975 master->dma_rx = NULL;
976 goto err;
977 }
978
979 spi_imx_dma_configure(master, 1);
980
981 init_completion(&spi_imx->dma_rx_completion);
982 init_completion(&spi_imx->dma_tx_completion);
983 master->can_dma = spi_imx_can_dma;
984 master->max_dma_len = MAX_SDMA_BD_BYTES;
985 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
986 SPI_MASTER_MUST_TX;
987
988 return 0;
989 err:
990 spi_imx_sdma_exit(spi_imx);
991 return ret;
992 }
993
994 static void spi_imx_dma_rx_callback(void *cookie)
995 {
996 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
997
998 complete(&spi_imx->dma_rx_completion);
999 }
1000
1001 static void spi_imx_dma_tx_callback(void *cookie)
1002 {
1003 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1004
1005 complete(&spi_imx->dma_tx_completion);
1006 }
1007
1008 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1009 {
1010 unsigned long timeout = 0;
1011
1012 /* Time with actual data transfer and CS change delay related to HW */
1013 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1014
1015 /* Add extra second for scheduler related activities */
1016 timeout += 1;
1017
1018 /* Double calculated timeout */
1019 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1020 }
1021
1022 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1023 struct spi_transfer *transfer)
1024 {
1025 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1026 unsigned long transfer_timeout;
1027 unsigned long timeout;
1028 struct spi_master *master = spi_imx->bitbang.master;
1029 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1030
1031 /*
1032 * The TX DMA setup starts the transfer, so make sure RX is configured
1033 * before TX.
1034 */
1035 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1036 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1037 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1038 if (!desc_rx)
1039 return -EINVAL;
1040
1041 desc_rx->callback = spi_imx_dma_rx_callback;
1042 desc_rx->callback_param = (void *)spi_imx;
1043 dmaengine_submit(desc_rx);
1044 reinit_completion(&spi_imx->dma_rx_completion);
1045 dma_async_issue_pending(master->dma_rx);
1046
1047 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1048 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1049 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1050 if (!desc_tx) {
1051 dmaengine_terminate_all(master->dma_tx);
1052 return -EINVAL;
1053 }
1054
1055 desc_tx->callback = spi_imx_dma_tx_callback;
1056 desc_tx->callback_param = (void *)spi_imx;
1057 dmaengine_submit(desc_tx);
1058 reinit_completion(&spi_imx->dma_tx_completion);
1059 dma_async_issue_pending(master->dma_tx);
1060
1061 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1062
1063 /* Wait SDMA to finish the data transfer.*/
1064 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1065 transfer_timeout);
1066 if (!timeout) {
1067 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1068 dmaengine_terminate_all(master->dma_tx);
1069 dmaengine_terminate_all(master->dma_rx);
1070 return -ETIMEDOUT;
1071 }
1072
1073 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1074 transfer_timeout);
1075 if (!timeout) {
1076 dev_err(&master->dev, "I/O Error in DMA RX\n");
1077 spi_imx->devtype_data->reset(spi_imx);
1078 dmaengine_terminate_all(master->dma_rx);
1079 return -ETIMEDOUT;
1080 }
1081
1082 return transfer->len;
1083 }
1084
1085 static int spi_imx_pio_transfer(struct spi_device *spi,
1086 struct spi_transfer *transfer)
1087 {
1088 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1089 unsigned long transfer_timeout;
1090 unsigned long timeout;
1091
1092 spi_imx->tx_buf = transfer->tx_buf;
1093 spi_imx->rx_buf = transfer->rx_buf;
1094 spi_imx->count = transfer->len;
1095 spi_imx->txfifo = 0;
1096
1097 reinit_completion(&spi_imx->xfer_done);
1098
1099 spi_imx_push(spi_imx);
1100
1101 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1102
1103 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1104
1105 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1106 transfer_timeout);
1107 if (!timeout) {
1108 dev_err(&spi->dev, "I/O Error in PIO\n");
1109 spi_imx->devtype_data->reset(spi_imx);
1110 return -ETIMEDOUT;
1111 }
1112
1113 return transfer->len;
1114 }
1115
1116 static int spi_imx_transfer(struct spi_device *spi,
1117 struct spi_transfer *transfer)
1118 {
1119 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1120
1121 if (spi_imx->usedma)
1122 return spi_imx_dma_transfer(spi_imx, transfer);
1123 else
1124 return spi_imx_pio_transfer(spi, transfer);
1125 }
1126
1127 static int spi_imx_setup(struct spi_device *spi)
1128 {
1129 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1130 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1131
1132 if (gpio_is_valid(spi->cs_gpio))
1133 gpio_direction_output(spi->cs_gpio,
1134 spi->mode & SPI_CS_HIGH ? 0 : 1);
1135
1136 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1137
1138 return 0;
1139 }
1140
1141 static void spi_imx_cleanup(struct spi_device *spi)
1142 {
1143 }
1144
1145 static int
1146 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1147 {
1148 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1149 int ret;
1150
1151 ret = clk_enable(spi_imx->clk_per);
1152 if (ret)
1153 return ret;
1154
1155 ret = clk_enable(spi_imx->clk_ipg);
1156 if (ret) {
1157 clk_disable(spi_imx->clk_per);
1158 return ret;
1159 }
1160
1161 return 0;
1162 }
1163
1164 static int
1165 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1166 {
1167 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1168
1169 clk_disable(spi_imx->clk_ipg);
1170 clk_disable(spi_imx->clk_per);
1171 return 0;
1172 }
1173
1174 static int spi_imx_probe(struct platform_device *pdev)
1175 {
1176 struct device_node *np = pdev->dev.of_node;
1177 const struct of_device_id *of_id =
1178 of_match_device(spi_imx_dt_ids, &pdev->dev);
1179 struct spi_imx_master *mxc_platform_info =
1180 dev_get_platdata(&pdev->dev);
1181 struct spi_master *master;
1182 struct spi_imx_data *spi_imx;
1183 struct resource *res;
1184 int i, ret, irq, spi_drctl;
1185
1186 if (!np && !mxc_platform_info) {
1187 dev_err(&pdev->dev, "can't get the platform data\n");
1188 return -EINVAL;
1189 }
1190
1191 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
1192 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1193 if ((ret < 0) || (spi_drctl >= 0x3)) {
1194 /* '11' is reserved */
1195 spi_drctl = 0;
1196 }
1197
1198 if (!master)
1199 return -ENOMEM;
1200
1201 platform_set_drvdata(pdev, master);
1202
1203 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1204 master->bus_num = np ? -1 : pdev->id;
1205
1206 spi_imx = spi_master_get_devdata(master);
1207 spi_imx->bitbang.master = master;
1208 spi_imx->dev = &pdev->dev;
1209
1210 spi_imx->devtype_data = of_id ? of_id->data :
1211 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1212
1213 if (mxc_platform_info) {
1214 master->num_chipselect = mxc_platform_info->num_chipselect;
1215 master->cs_gpios = devm_kzalloc(&master->dev,
1216 sizeof(int) * master->num_chipselect, GFP_KERNEL);
1217 if (!master->cs_gpios)
1218 return -ENOMEM;
1219
1220 for (i = 0; i < master->num_chipselect; i++)
1221 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1222 }
1223
1224 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1225 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1226 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1227 spi_imx->bitbang.master->setup = spi_imx_setup;
1228 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1229 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1230 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1231 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1232 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx))
1233 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1234
1235 spi_imx->spi_drctl = spi_drctl;
1236
1237 init_completion(&spi_imx->xfer_done);
1238
1239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1240 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1241 if (IS_ERR(spi_imx->base)) {
1242 ret = PTR_ERR(spi_imx->base);
1243 goto out_master_put;
1244 }
1245 spi_imx->base_phys = res->start;
1246
1247 irq = platform_get_irq(pdev, 0);
1248 if (irq < 0) {
1249 ret = irq;
1250 goto out_master_put;
1251 }
1252
1253 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1254 dev_name(&pdev->dev), spi_imx);
1255 if (ret) {
1256 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1257 goto out_master_put;
1258 }
1259
1260 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1261 if (IS_ERR(spi_imx->clk_ipg)) {
1262 ret = PTR_ERR(spi_imx->clk_ipg);
1263 goto out_master_put;
1264 }
1265
1266 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1267 if (IS_ERR(spi_imx->clk_per)) {
1268 ret = PTR_ERR(spi_imx->clk_per);
1269 goto out_master_put;
1270 }
1271
1272 ret = clk_prepare_enable(spi_imx->clk_per);
1273 if (ret)
1274 goto out_master_put;
1275
1276 ret = clk_prepare_enable(spi_imx->clk_ipg);
1277 if (ret)
1278 goto out_put_per;
1279
1280 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1281 /*
1282 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1283 * if validated on other chips.
1284 */
1285 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) {
1286 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1287 if (ret == -EPROBE_DEFER)
1288 goto out_clk_put;
1289
1290 if (ret < 0)
1291 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1292 ret);
1293 }
1294
1295 spi_imx->devtype_data->reset(spi_imx);
1296
1297 spi_imx->devtype_data->intctrl(spi_imx, 0);
1298
1299 master->dev.of_node = pdev->dev.of_node;
1300 ret = spi_bitbang_start(&spi_imx->bitbang);
1301 if (ret) {
1302 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1303 goto out_clk_put;
1304 }
1305
1306 if (!master->cs_gpios) {
1307 dev_err(&pdev->dev, "No CS GPIOs available\n");
1308 ret = -EINVAL;
1309 goto out_clk_put;
1310 }
1311
1312 for (i = 0; i < master->num_chipselect; i++) {
1313 if (!gpio_is_valid(master->cs_gpios[i]))
1314 continue;
1315
1316 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1317 DRIVER_NAME);
1318 if (ret) {
1319 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1320 master->cs_gpios[i]);
1321 goto out_clk_put;
1322 }
1323 }
1324
1325 dev_info(&pdev->dev, "probed\n");
1326
1327 clk_disable(spi_imx->clk_ipg);
1328 clk_disable(spi_imx->clk_per);
1329 return ret;
1330
1331 out_clk_put:
1332 clk_disable_unprepare(spi_imx->clk_ipg);
1333 out_put_per:
1334 clk_disable_unprepare(spi_imx->clk_per);
1335 out_master_put:
1336 spi_master_put(master);
1337
1338 return ret;
1339 }
1340
1341 static int spi_imx_remove(struct platform_device *pdev)
1342 {
1343 struct spi_master *master = platform_get_drvdata(pdev);
1344 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1345
1346 spi_bitbang_stop(&spi_imx->bitbang);
1347
1348 writel(0, spi_imx->base + MXC_CSPICTRL);
1349 clk_unprepare(spi_imx->clk_ipg);
1350 clk_unprepare(spi_imx->clk_per);
1351 spi_imx_sdma_exit(spi_imx);
1352 spi_master_put(master);
1353
1354 return 0;
1355 }
1356
1357 static struct platform_driver spi_imx_driver = {
1358 .driver = {
1359 .name = DRIVER_NAME,
1360 .of_match_table = spi_imx_dt_ids,
1361 },
1362 .id_table = spi_imx_devtype,
1363 .probe = spi_imx_probe,
1364 .remove = spi_imx_remove,
1365 };
1366 module_platform_driver(spi_imx_driver);
1367
1368 MODULE_DESCRIPTION("SPI Master Controller driver");
1369 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1370 MODULE_LICENSE("GPL");
1371 MODULE_ALIAS("platform:" DRIVER_NAME);