2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/interrupt.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/platform_device.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/spi_bitbang.h>
31 #include <linux/slab.h>
33 #include <linux/platform_data/spi-davinci.h>
35 #define CS_DEFAULT 0xFF
37 #define SPIFMT_PHASE_MASK BIT(16)
38 #define SPIFMT_POLARITY_MASK BIT(17)
39 #define SPIFMT_DISTIMER_MASK BIT(18)
40 #define SPIFMT_SHIFTDIR_MASK BIT(20)
41 #define SPIFMT_WAITENA_MASK BIT(21)
42 #define SPIFMT_PARITYENA_MASK BIT(22)
43 #define SPIFMT_ODD_PARITY_MASK BIT(23)
44 #define SPIFMT_WDELAY_MASK 0x3f000000u
45 #define SPIFMT_WDELAY_SHIFT 24
46 #define SPIFMT_PRESCALE_SHIFT 8
49 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
50 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
51 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
52 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
54 #define SPIINT_MASKALL 0x0101035F
55 #define SPIINT_MASKINT 0x0000015F
56 #define SPI_INTLVL_1 0x000001FF
57 #define SPI_INTLVL_0 0x00000000
59 /* SPIDAT1 (upper 16 bit defines) */
60 #define SPIDAT1_CSHOLD_MASK BIT(12)
61 #define SPIDAT1_WDEL BIT(10)
64 #define SPIGCR1_CLKMOD_MASK BIT(1)
65 #define SPIGCR1_MASTER_MASK BIT(0)
66 #define SPIGCR1_POWERDOWN_MASK BIT(8)
67 #define SPIGCR1_LOOPBACK_MASK BIT(16)
68 #define SPIGCR1_SPIENA_MASK BIT(24)
71 #define SPIBUF_TXFULL_MASK BIT(29)
72 #define SPIBUF_RXEMPTY_MASK BIT(31)
75 #define SPIDELAY_C2TDELAY_SHIFT 24
76 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
77 #define SPIDELAY_T2CDELAY_SHIFT 16
78 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
79 #define SPIDELAY_T2EDELAY_SHIFT 8
80 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
81 #define SPIDELAY_C2EDELAY_SHIFT 0
82 #define SPIDELAY_C2EDELAY_MASK 0xFF
85 #define SPIFLG_DLEN_ERR_MASK BIT(0)
86 #define SPIFLG_TIMEOUT_MASK BIT(1)
87 #define SPIFLG_PARERR_MASK BIT(2)
88 #define SPIFLG_DESYNC_MASK BIT(3)
89 #define SPIFLG_BITERR_MASK BIT(4)
90 #define SPIFLG_OVRRUN_MASK BIT(6)
91 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
92 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
93 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
94 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
97 #define SPIINT_DMA_REQ_EN BIT(16)
99 /* SPI Controller registers */
108 #define SPIDELAY 0x48
112 #define DMA_MIN_BYTES 16
114 /* SPI Controller driver's private data. */
116 struct spi_bitbang bitbang
;
120 resource_size_t pbase
;
123 struct completion done
;
130 struct dma_chan
*dma_rx
;
131 struct dma_chan
*dma_tx
;
133 struct davinci_spi_platform_data pdata
;
135 void (*get_rx
)(u32 rx_data
, struct davinci_spi
*);
136 u32 (*get_tx
)(struct davinci_spi
*);
143 static struct davinci_spi_config davinci_spi_default_cfg
;
145 static void davinci_spi_rx_buf_u8(u32 data
, struct davinci_spi
*dspi
)
154 static void davinci_spi_rx_buf_u16(u32 data
, struct davinci_spi
*dspi
)
163 static u32
davinci_spi_tx_buf_u8(struct davinci_spi
*dspi
)
168 const u8
*tx
= dspi
->tx
;
176 static u32
davinci_spi_tx_buf_u16(struct davinci_spi
*dspi
)
181 const u16
*tx
= dspi
->tx
;
189 static inline void set_io_bits(void __iomem
*addr
, u32 bits
)
191 u32 v
= ioread32(addr
);
197 static inline void clear_io_bits(void __iomem
*addr
, u32 bits
)
199 u32 v
= ioread32(addr
);
206 * Interface to control the chip select signal
208 static void davinci_spi_chipselect(struct spi_device
*spi
, int value
)
210 struct davinci_spi
*dspi
;
211 struct davinci_spi_platform_data
*pdata
;
212 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
213 u8 chip_sel
= spi
->chip_select
;
214 u16 spidat1
= CS_DEFAULT
;
216 dspi
= spi_master_get_devdata(spi
->master
);
217 pdata
= &dspi
->pdata
;
219 /* program delay transfers if tx_delay is non zero */
221 spidat1
|= SPIDAT1_WDEL
;
224 * Board specific chip select logic decides the polarity and cs
225 * line for the controller
227 if (spi
->cs_gpio
>= 0) {
228 if (value
== BITBANG_CS_ACTIVE
)
229 gpio_set_value(spi
->cs_gpio
, spi
->mode
& SPI_CS_HIGH
);
231 gpio_set_value(spi
->cs_gpio
,
232 !(spi
->mode
& SPI_CS_HIGH
));
234 if (value
== BITBANG_CS_ACTIVE
) {
235 spidat1
|= SPIDAT1_CSHOLD_MASK
;
236 spidat1
&= ~(0x1 << chip_sel
);
240 iowrite16(spidat1
, dspi
->base
+ SPIDAT1
+ 2);
244 * davinci_spi_get_prescale - Calculates the correct prescale value
245 * @maxspeed_hz: the maximum rate the SPI clock can run at
247 * This function calculates the prescale value that generates a clock rate
248 * less than or equal to the specified maximum.
250 * Returns: calculated prescale value for easy programming into SPI registers
251 * or negative error number if valid prescalar cannot be updated.
253 static inline int davinci_spi_get_prescale(struct davinci_spi
*dspi
,
258 /* Subtract 1 to match what will be programmed into SPI register. */
259 ret
= DIV_ROUND_UP(clk_get_rate(dspi
->clk
), max_speed_hz
) - 1;
261 if (ret
< dspi
->prescaler_limit
|| ret
> 255)
268 * davinci_spi_setup_transfer - This functions will determine transfer method
269 * @spi: spi device on which data transfer to be done
270 * @t: spi transfer in which transfer info is filled
272 * This function determines data transfer method (8/16/32 bit transfer).
273 * It will also set the SPI Clock Control register according to
274 * SPI slave device freq.
276 static int davinci_spi_setup_transfer(struct spi_device
*spi
,
277 struct spi_transfer
*t
)
280 struct davinci_spi
*dspi
;
281 struct davinci_spi_config
*spicfg
;
282 u8 bits_per_word
= 0;
283 u32 hz
= 0, spifmt
= 0;
286 dspi
= spi_master_get_devdata(spi
->master
);
287 spicfg
= spi
->controller_data
;
289 spicfg
= &davinci_spi_default_cfg
;
292 bits_per_word
= t
->bits_per_word
;
296 /* if bits_per_word is not set then set it default */
298 bits_per_word
= spi
->bits_per_word
;
301 * Assign function pointer to appropriate transfer method
302 * 8bit, 16bit or 32bit transfer
304 if (bits_per_word
<= 8) {
305 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
306 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
307 dspi
->bytes_per_word
[spi
->chip_select
] = 1;
309 dspi
->get_rx
= davinci_spi_rx_buf_u16
;
310 dspi
->get_tx
= davinci_spi_tx_buf_u16
;
311 dspi
->bytes_per_word
[spi
->chip_select
] = 2;
315 hz
= spi
->max_speed_hz
;
317 /* Set up SPIFMTn register, unique to this chipselect. */
319 prescale
= davinci_spi_get_prescale(dspi
, hz
);
323 spifmt
= (prescale
<< SPIFMT_PRESCALE_SHIFT
) | (bits_per_word
& 0x1f);
325 if (spi
->mode
& SPI_LSB_FIRST
)
326 spifmt
|= SPIFMT_SHIFTDIR_MASK
;
328 if (spi
->mode
& SPI_CPOL
)
329 spifmt
|= SPIFMT_POLARITY_MASK
;
331 if (!(spi
->mode
& SPI_CPHA
))
332 spifmt
|= SPIFMT_PHASE_MASK
;
335 * Assume wdelay is used only on SPI peripherals that has this field
336 * in SPIFMTn register and when it's configured from board file or DT.
339 spifmt
|= ((spicfg
->wdelay
<< SPIFMT_WDELAY_SHIFT
)
340 & SPIFMT_WDELAY_MASK
);
343 * Version 1 hardware supports two basic SPI modes:
344 * - Standard SPI mode uses 4 pins, with chipselect
345 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
346 * (distinct from SPI_3WIRE, with just one data wire;
347 * or similar variants without MOSI or without MISO)
349 * Version 2 hardware supports an optional handshaking signal,
350 * so it can support two more modes:
351 * - 5 pin SPI variant is standard SPI plus SPI_READY
352 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
355 if (dspi
->version
== SPI_VERSION_2
) {
359 if (spicfg
->odd_parity
)
360 spifmt
|= SPIFMT_ODD_PARITY_MASK
;
362 if (spicfg
->parity_enable
)
363 spifmt
|= SPIFMT_PARITYENA_MASK
;
365 if (spicfg
->timer_disable
) {
366 spifmt
|= SPIFMT_DISTIMER_MASK
;
368 delay
|= (spicfg
->c2tdelay
<< SPIDELAY_C2TDELAY_SHIFT
)
369 & SPIDELAY_C2TDELAY_MASK
;
370 delay
|= (spicfg
->t2cdelay
<< SPIDELAY_T2CDELAY_SHIFT
)
371 & SPIDELAY_T2CDELAY_MASK
;
374 if (spi
->mode
& SPI_READY
) {
375 spifmt
|= SPIFMT_WAITENA_MASK
;
376 delay
|= (spicfg
->t2edelay
<< SPIDELAY_T2EDELAY_SHIFT
)
377 & SPIDELAY_T2EDELAY_MASK
;
378 delay
|= (spicfg
->c2edelay
<< SPIDELAY_C2EDELAY_SHIFT
)
379 & SPIDELAY_C2EDELAY_MASK
;
382 iowrite32(delay
, dspi
->base
+ SPIDELAY
);
385 iowrite32(spifmt
, dspi
->base
+ SPIFMT0
);
390 static int davinci_spi_of_setup(struct spi_device
*spi
)
392 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
393 struct device_node
*np
= spi
->dev
.of_node
;
394 struct davinci_spi
*dspi
= spi_master_get_devdata(spi
->master
);
397 if (spicfg
== NULL
&& np
) {
398 spicfg
= kzalloc(sizeof(*spicfg
), GFP_KERNEL
);
401 *spicfg
= davinci_spi_default_cfg
;
402 /* override with dt configured values */
403 if (!of_property_read_u32(np
, "ti,spi-wdelay", &prop
))
404 spicfg
->wdelay
= (u8
)prop
;
405 spi
->controller_data
= spicfg
;
407 if (dspi
->dma_rx
&& dspi
->dma_tx
)
408 spicfg
->io_type
= SPI_IO_TYPE_DMA
;
415 * davinci_spi_setup - This functions will set default transfer method
416 * @spi: spi device on which data transfer to be done
418 * This functions sets the default transfer method.
420 static int davinci_spi_setup(struct spi_device
*spi
)
423 struct davinci_spi
*dspi
;
424 struct davinci_spi_platform_data
*pdata
;
425 struct spi_master
*master
= spi
->master
;
426 struct device_node
*np
= spi
->dev
.of_node
;
427 bool internal_cs
= true;
429 dspi
= spi_master_get_devdata(spi
->master
);
430 pdata
= &dspi
->pdata
;
432 if (!(spi
->mode
& SPI_NO_CS
)) {
433 if (np
&& (master
->cs_gpios
!= NULL
) && (spi
->cs_gpio
>= 0)) {
434 retval
= gpio_direction_output(
435 spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
437 } else if (pdata
->chip_sel
&&
438 spi
->chip_select
< pdata
->num_chipselect
&&
439 pdata
->chip_sel
[spi
->chip_select
] != SPI_INTERN_CS
) {
440 spi
->cs_gpio
= pdata
->chip_sel
[spi
->chip_select
];
441 retval
= gpio_direction_output(
442 spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
447 dev_err(&spi
->dev
, "GPIO %d setup failed (%d)\n",
448 spi
->cs_gpio
, retval
);
453 set_io_bits(dspi
->base
+ SPIPC0
, 1 << spi
->chip_select
);
456 if (spi
->mode
& SPI_READY
)
457 set_io_bits(dspi
->base
+ SPIPC0
, SPIPC0_SPIENA_MASK
);
459 if (spi
->mode
& SPI_LOOP
)
460 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
462 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_LOOPBACK_MASK
);
464 return davinci_spi_of_setup(spi
);
467 static void davinci_spi_cleanup(struct spi_device
*spi
)
469 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
471 spi
->controller_data
= NULL
;
472 if (spi
->dev
.of_node
)
476 static bool davinci_spi_can_dma(struct spi_master
*master
,
477 struct spi_device
*spi
,
478 struct spi_transfer
*xfer
)
480 struct davinci_spi_config
*spicfg
= spi
->controller_data
;
481 bool can_dma
= false;
484 can_dma
= (spicfg
->io_type
== SPI_IO_TYPE_DMA
) &&
485 (xfer
->len
>= DMA_MIN_BYTES
) &&
486 !is_vmalloc_addr(xfer
->rx_buf
) &&
487 !is_vmalloc_addr(xfer
->tx_buf
);
492 static int davinci_spi_check_error(struct davinci_spi
*dspi
, int int_status
)
494 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
496 if (int_status
& SPIFLG_TIMEOUT_MASK
) {
497 dev_err(sdev
, "SPI Time-out Error\n");
500 if (int_status
& SPIFLG_DESYNC_MASK
) {
501 dev_err(sdev
, "SPI Desynchronization Error\n");
504 if (int_status
& SPIFLG_BITERR_MASK
) {
505 dev_err(sdev
, "SPI Bit error\n");
509 if (dspi
->version
== SPI_VERSION_2
) {
510 if (int_status
& SPIFLG_DLEN_ERR_MASK
) {
511 dev_err(sdev
, "SPI Data Length Error\n");
514 if (int_status
& SPIFLG_PARERR_MASK
) {
515 dev_err(sdev
, "SPI Parity Error\n");
518 if (int_status
& SPIFLG_OVRRUN_MASK
) {
519 dev_err(sdev
, "SPI Data Overrun error\n");
522 if (int_status
& SPIFLG_BUF_INIT_ACTIVE_MASK
) {
523 dev_err(sdev
, "SPI Buffer Init Active\n");
532 * davinci_spi_process_events - check for and handle any SPI controller events
533 * @dspi: the controller data
535 * This function will check the SPIFLG register and handle any events that are
538 static int davinci_spi_process_events(struct davinci_spi
*dspi
)
540 u32 buf
, status
, errors
= 0, spidat1
;
542 buf
= ioread32(dspi
->base
+ SPIBUF
);
544 if (dspi
->rcount
> 0 && !(buf
& SPIBUF_RXEMPTY_MASK
)) {
545 dspi
->get_rx(buf
& 0xFFFF, dspi
);
549 status
= ioread32(dspi
->base
+ SPIFLG
);
551 if (unlikely(status
& SPIFLG_ERROR_MASK
)) {
552 errors
= status
& SPIFLG_ERROR_MASK
;
556 if (dspi
->wcount
> 0 && !(buf
& SPIBUF_TXFULL_MASK
)) {
557 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
560 spidat1
|= 0xFFFF & dspi
->get_tx(dspi
);
561 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
568 static void davinci_spi_dma_rx_callback(void *data
)
570 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
574 if (!dspi
->wcount
&& !dspi
->rcount
)
575 complete(&dspi
->done
);
578 static void davinci_spi_dma_tx_callback(void *data
)
580 struct davinci_spi
*dspi
= (struct davinci_spi
*)data
;
584 if (!dspi
->wcount
&& !dspi
->rcount
)
585 complete(&dspi
->done
);
589 * davinci_spi_bufs - functions which will handle transfer data
590 * @spi: spi device on which data transfer to be done
591 * @t: spi transfer in which transfer info is filled
593 * This function will put data to be transferred into data register
594 * of SPI controller and then wait until the completion will be marked
595 * by the IRQ Handler.
597 static int davinci_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
)
599 struct davinci_spi
*dspi
;
600 int data_type
, ret
= -ENOMEM
;
601 u32 tx_data
, spidat1
;
603 struct davinci_spi_config
*spicfg
;
604 struct davinci_spi_platform_data
*pdata
;
605 unsigned uninitialized_var(rx_buf_count
);
607 dspi
= spi_master_get_devdata(spi
->master
);
608 pdata
= &dspi
->pdata
;
609 spicfg
= (struct davinci_spi_config
*)spi
->controller_data
;
611 spicfg
= &davinci_spi_default_cfg
;
613 /* convert len to words based on bits_per_word */
614 data_type
= dspi
->bytes_per_word
[spi
->chip_select
];
616 dspi
->tx
= t
->tx_buf
;
617 dspi
->rx
= t
->rx_buf
;
618 dspi
->wcount
= t
->len
/ data_type
;
619 dspi
->rcount
= dspi
->wcount
;
621 spidat1
= ioread32(dspi
->base
+ SPIDAT1
);
623 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
624 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
626 reinit_completion(&dspi
->done
);
628 if (!davinci_spi_can_dma(spi
->master
, spi
, t
)) {
629 if (spicfg
->io_type
!= SPI_IO_TYPE_POLL
)
630 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
631 /* start the transfer */
633 tx_data
= dspi
->get_tx(dspi
);
634 spidat1
&= 0xFFFF0000;
635 spidat1
|= tx_data
& 0xFFFF;
636 iowrite32(spidat1
, dspi
->base
+ SPIDAT1
);
638 struct dma_slave_config dma_rx_conf
= {
639 .direction
= DMA_DEV_TO_MEM
,
640 .src_addr
= (unsigned long)dspi
->pbase
+ SPIBUF
,
641 .src_addr_width
= data_type
,
644 struct dma_slave_config dma_tx_conf
= {
645 .direction
= DMA_MEM_TO_DEV
,
646 .dst_addr
= (unsigned long)dspi
->pbase
+ SPIDAT1
,
647 .dst_addr_width
= data_type
,
650 struct dma_async_tx_descriptor
*rxdesc
;
651 struct dma_async_tx_descriptor
*txdesc
;
653 dmaengine_slave_config(dspi
->dma_rx
, &dma_rx_conf
);
654 dmaengine_slave_config(dspi
->dma_tx
, &dma_tx_conf
);
656 rxdesc
= dmaengine_prep_slave_sg(dspi
->dma_rx
,
657 t
->rx_sg
.sgl
, t
->rx_sg
.nents
, DMA_DEV_TO_MEM
,
658 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
663 /* use rx buffer as dummy tx buffer */
664 t
->tx_sg
.sgl
= t
->rx_sg
.sgl
;
665 t
->tx_sg
.nents
= t
->rx_sg
.nents
;
668 txdesc
= dmaengine_prep_slave_sg(dspi
->dma_tx
,
669 t
->tx_sg
.sgl
, t
->tx_sg
.nents
, DMA_MEM_TO_DEV
,
670 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
674 rxdesc
->callback
= davinci_spi_dma_rx_callback
;
675 rxdesc
->callback_param
= (void *)dspi
;
676 txdesc
->callback
= davinci_spi_dma_tx_callback
;
677 txdesc
->callback_param
= (void *)dspi
;
679 if (pdata
->cshold_bug
)
680 iowrite16(spidat1
>> 16, dspi
->base
+ SPIDAT1
+ 2);
682 dmaengine_submit(rxdesc
);
683 dmaengine_submit(txdesc
);
685 dma_async_issue_pending(dspi
->dma_rx
);
686 dma_async_issue_pending(dspi
->dma_tx
);
688 set_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
691 /* Wait for the transfer to complete */
692 if (spicfg
->io_type
!= SPI_IO_TYPE_POLL
) {
693 if (wait_for_completion_timeout(&dspi
->done
, HZ
) == 0)
694 errors
= SPIFLG_TIMEOUT_MASK
;
696 while (dspi
->rcount
> 0 || dspi
->wcount
> 0) {
697 errors
= davinci_spi_process_events(dspi
);
704 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKALL
);
705 if (davinci_spi_can_dma(spi
->master
, spi
, t
))
706 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_DMA_REQ_EN
);
708 clear_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_SPIENA_MASK
);
709 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
712 * Check for bit error, desync error,parity error,timeout error and
713 * receive overflow errors
716 ret
= davinci_spi_check_error(dspi
, errors
);
717 WARN(!ret
, "%s: error reported but no error found!\n",
718 dev_name(&spi
->dev
));
722 if (dspi
->rcount
!= 0 || dspi
->wcount
!= 0) {
723 dev_err(&spi
->dev
, "SPI data transfer error\n");
734 * dummy_thread_fn - dummy thread function
735 * @irq: IRQ number for this SPI Master
736 * @context_data: structure for SPI Master controller davinci_spi
738 * This is to satisfy the request_threaded_irq() API so that the irq
739 * handler is called in interrupt context.
741 static irqreturn_t
dummy_thread_fn(s32 irq
, void *data
)
747 * davinci_spi_irq - Interrupt handler for SPI Master Controller
748 * @irq: IRQ number for this SPI Master
749 * @context_data: structure for SPI Master controller davinci_spi
751 * ISR will determine that interrupt arrives either for READ or WRITE command.
752 * According to command it will do the appropriate action. It will check
753 * transfer length and if it is not zero then dispatch transfer command again.
754 * If transfer length is zero then it will indicate the COMPLETION so that
755 * davinci_spi_bufs function can go ahead.
757 static irqreturn_t
davinci_spi_irq(s32 irq
, void *data
)
759 struct davinci_spi
*dspi
= data
;
762 status
= davinci_spi_process_events(dspi
);
763 if (unlikely(status
!= 0))
764 clear_io_bits(dspi
->base
+ SPIINT
, SPIINT_MASKINT
);
766 if ((!dspi
->rcount
&& !dspi
->wcount
) || status
)
767 complete(&dspi
->done
);
772 static int davinci_spi_request_dma(struct davinci_spi
*dspi
)
774 struct device
*sdev
= dspi
->bitbang
.master
->dev
.parent
;
776 dspi
->dma_rx
= dma_request_chan(sdev
, "rx");
777 if (IS_ERR(dspi
->dma_rx
))
778 return PTR_ERR(dspi
->dma_rx
);
780 dspi
->dma_tx
= dma_request_chan(sdev
, "tx");
781 if (IS_ERR(dspi
->dma_tx
)) {
782 dma_release_channel(dspi
->dma_rx
);
783 return PTR_ERR(dspi
->dma_tx
);
789 #if defined(CONFIG_OF)
791 /* OF SPI data structure */
792 struct davinci_spi_of_data
{
797 static const struct davinci_spi_of_data dm6441_spi_data
= {
798 .version
= SPI_VERSION_1
,
799 .prescaler_limit
= 2,
802 static const struct davinci_spi_of_data da830_spi_data
= {
803 .version
= SPI_VERSION_2
,
804 .prescaler_limit
= 2,
807 static const struct davinci_spi_of_data keystone_spi_data
= {
808 .version
= SPI_VERSION_1
,
809 .prescaler_limit
= 0,
812 static const struct of_device_id davinci_spi_of_match
[] = {
814 .compatible
= "ti,dm6441-spi",
815 .data
= &dm6441_spi_data
,
818 .compatible
= "ti,da830-spi",
819 .data
= &da830_spi_data
,
822 .compatible
= "ti,keystone-spi",
823 .data
= &keystone_spi_data
,
827 MODULE_DEVICE_TABLE(of
, davinci_spi_of_match
);
830 * spi_davinci_get_pdata - Get platform data from DTS binding
831 * @pdev: ptr to platform data
832 * @dspi: ptr to driver data
834 * Parses and populates pdata in dspi from device tree bindings.
836 * NOTE: Not all platform data params are supported currently.
838 static int spi_davinci_get_pdata(struct platform_device
*pdev
,
839 struct davinci_spi
*dspi
)
841 struct device_node
*node
= pdev
->dev
.of_node
;
842 struct davinci_spi_of_data
*spi_data
;
843 struct davinci_spi_platform_data
*pdata
;
844 unsigned int num_cs
, intr_line
= 0;
845 const struct of_device_id
*match
;
847 pdata
= &dspi
->pdata
;
849 match
= of_match_device(davinci_spi_of_match
, &pdev
->dev
);
853 spi_data
= (struct davinci_spi_of_data
*)match
->data
;
855 pdata
->version
= spi_data
->version
;
856 pdata
->prescaler_limit
= spi_data
->prescaler_limit
;
858 * default num_cs is 1 and all chipsel are internal to the chip
859 * indicated by chip_sel being NULL or cs_gpios being NULL or
860 * set to -ENOENT. num-cs includes internal as well as gpios.
861 * indicated by chip_sel being NULL. GPIO based CS is not
862 * supported yet in DT bindings.
865 of_property_read_u32(node
, "num-cs", &num_cs
);
866 pdata
->num_chipselect
= num_cs
;
867 of_property_read_u32(node
, "ti,davinci-spi-intr-line", &intr_line
);
868 pdata
->intr_line
= intr_line
;
872 static struct davinci_spi_platform_data
873 *spi_davinci_get_pdata(struct platform_device
*pdev
,
874 struct davinci_spi
*dspi
)
881 * davinci_spi_probe - probe function for SPI Master Controller
882 * @pdev: platform_device structure which contains plateform specific data
884 * According to Linux Device Model this function will be invoked by Linux
885 * with platform_device struct which contains the device specific info.
886 * This function will map the SPI controller's memory, register IRQ,
887 * Reset SPI controller and setting its registers to default value.
888 * It will invoke spi_bitbang_start to create work queue so that client driver
889 * can register transfer method to work queue.
891 static int davinci_spi_probe(struct platform_device
*pdev
)
893 struct spi_master
*master
;
894 struct davinci_spi
*dspi
;
895 struct davinci_spi_platform_data
*pdata
;
900 master
= spi_alloc_master(&pdev
->dev
, sizeof(struct davinci_spi
));
901 if (master
== NULL
) {
906 platform_set_drvdata(pdev
, master
);
908 dspi
= spi_master_get_devdata(master
);
910 if (dev_get_platdata(&pdev
->dev
)) {
911 pdata
= dev_get_platdata(&pdev
->dev
);
912 dspi
->pdata
= *pdata
;
914 /* update dspi pdata with that from the DT */
915 ret
= spi_davinci_get_pdata(pdev
, dspi
);
920 /* pdata in dspi is now updated and point pdata to that */
921 pdata
= &dspi
->pdata
;
923 dspi
->bytes_per_word
= devm_kzalloc(&pdev
->dev
,
924 sizeof(*dspi
->bytes_per_word
) *
925 pdata
->num_chipselect
, GFP_KERNEL
);
926 if (dspi
->bytes_per_word
== NULL
) {
931 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
937 dspi
->pbase
= r
->start
;
939 dspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
940 if (IS_ERR(dspi
->base
)) {
941 ret
= PTR_ERR(dspi
->base
);
945 ret
= platform_get_irq(pdev
, 0);
952 ret
= devm_request_threaded_irq(&pdev
->dev
, dspi
->irq
, davinci_spi_irq
,
953 dummy_thread_fn
, 0, dev_name(&pdev
->dev
), dspi
);
957 dspi
->bitbang
.master
= master
;
959 dspi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
960 if (IS_ERR(dspi
->clk
)) {
964 clk_prepare_enable(dspi
->clk
);
966 master
->dev
.of_node
= pdev
->dev
.of_node
;
967 master
->bus_num
= pdev
->id
;
968 master
->num_chipselect
= pdata
->num_chipselect
;
969 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(2, 16);
970 master
->flags
= SPI_MASTER_MUST_RX
;
971 master
->setup
= davinci_spi_setup
;
972 master
->cleanup
= davinci_spi_cleanup
;
973 master
->can_dma
= davinci_spi_can_dma
;
975 dspi
->bitbang
.chipselect
= davinci_spi_chipselect
;
976 dspi
->bitbang
.setup_transfer
= davinci_spi_setup_transfer
;
977 dspi
->prescaler_limit
= pdata
->prescaler_limit
;
978 dspi
->version
= pdata
->version
;
980 dspi
->bitbang
.flags
= SPI_NO_CS
| SPI_LSB_FIRST
| SPI_LOOP
;
981 if (dspi
->version
== SPI_VERSION_2
)
982 dspi
->bitbang
.flags
|= SPI_READY
;
984 if (pdev
->dev
.of_node
) {
987 for (i
= 0; i
< pdata
->num_chipselect
; i
++) {
988 int cs_gpio
= of_get_named_gpio(pdev
->dev
.of_node
,
991 if (cs_gpio
== -EPROBE_DEFER
) {
996 if (gpio_is_valid(cs_gpio
)) {
997 ret
= devm_gpio_request(&pdev
->dev
, cs_gpio
,
998 dev_name(&pdev
->dev
));
1005 dspi
->bitbang
.txrx_bufs
= davinci_spi_bufs
;
1007 ret
= davinci_spi_request_dma(dspi
);
1008 if (ret
== -EPROBE_DEFER
) {
1011 dev_info(&pdev
->dev
, "DMA is not supported (%d)\n", ret
);
1012 dspi
->dma_rx
= NULL
;
1013 dspi
->dma_tx
= NULL
;
1016 dspi
->get_rx
= davinci_spi_rx_buf_u8
;
1017 dspi
->get_tx
= davinci_spi_tx_buf_u8
;
1019 init_completion(&dspi
->done
);
1021 /* Reset In/OUT SPI module */
1022 iowrite32(0, dspi
->base
+ SPIGCR0
);
1024 iowrite32(1, dspi
->base
+ SPIGCR0
);
1026 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
1027 spipc0
= SPIPC0_DIFUN_MASK
| SPIPC0_DOFUN_MASK
| SPIPC0_CLKFUN_MASK
;
1028 iowrite32(spipc0
, dspi
->base
+ SPIPC0
);
1030 if (pdata
->intr_line
)
1031 iowrite32(SPI_INTLVL_1
, dspi
->base
+ SPILVL
);
1033 iowrite32(SPI_INTLVL_0
, dspi
->base
+ SPILVL
);
1035 iowrite32(CS_DEFAULT
, dspi
->base
+ SPIDEF
);
1037 /* master mode default */
1038 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_CLKMOD_MASK
);
1039 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_MASTER_MASK
);
1040 set_io_bits(dspi
->base
+ SPIGCR1
, SPIGCR1_POWERDOWN_MASK
);
1042 ret
= spi_bitbang_start(&dspi
->bitbang
);
1046 dev_info(&pdev
->dev
, "Controller at 0x%p\n", dspi
->base
);
1052 dma_release_channel(dspi
->dma_rx
);
1053 dma_release_channel(dspi
->dma_tx
);
1056 clk_disable_unprepare(dspi
->clk
);
1058 spi_master_put(master
);
1064 * davinci_spi_remove - remove function for SPI Master Controller
1065 * @pdev: platform_device structure which contains plateform specific data
1067 * This function will do the reverse action of davinci_spi_probe function
1068 * It will free the IRQ and SPI controller's memory region.
1069 * It will also call spi_bitbang_stop to destroy the work queue which was
1070 * created by spi_bitbang_start.
1072 static int davinci_spi_remove(struct platform_device
*pdev
)
1074 struct davinci_spi
*dspi
;
1075 struct spi_master
*master
;
1077 master
= platform_get_drvdata(pdev
);
1078 dspi
= spi_master_get_devdata(master
);
1080 spi_bitbang_stop(&dspi
->bitbang
);
1082 clk_disable_unprepare(dspi
->clk
);
1083 spi_master_put(master
);
1086 dma_release_channel(dspi
->dma_rx
);
1087 dma_release_channel(dspi
->dma_tx
);
1093 static struct platform_driver davinci_spi_driver
= {
1095 .name
= "spi_davinci",
1096 .of_match_table
= of_match_ptr(davinci_spi_of_match
),
1098 .probe
= davinci_spi_probe
,
1099 .remove
= davinci_spi_remove
,
1101 module_platform_driver(davinci_spi_driver
);
1103 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1104 MODULE_LICENSE("GPL");