drivers/spi/spi-cadence.c

   1 /*
   2  * Cadence SPI controller driver (master mode only)
   3  *
   4  * Copyright (C) 2008 - 2014 Xilinx, Inc.
   5  *
   6  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
   7  *
   8  * This program is free software; you can redistribute it and/or modify it under
   9  * the terms of the GNU General Public License version 2 as published by the
  10  * Free Software Foundation; either version 2 of the License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_address.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/spi/spi.h>
  25
  26 /* Name of this driver */
  27 #define CDNS_SPI_NAME           "cdns-spi"
  28
  29 /* Register offset definitions */
  30 #define CDNS_SPI_CR     0x00 /* Configuration  Register, RW */
  31 #define CDNS_SPI_ISR    0x04 /* Interrupt Status Register, RO */
  32 #define CDNS_SPI_IER    0x08 /* Interrupt Enable Register, WO */
  33 #define CDNS_SPI_IDR    0x0c /* Interrupt Disable Register, WO */
  34 #define CDNS_SPI_IMR    0x10 /* Interrupt Enabled Mask Register, RO */
  35 #define CDNS_SPI_ER     0x14 /* Enable/Disable Register, RW */
  36 #define CDNS_SPI_DR     0x18 /* Delay Register, RW */
  37 #define CDNS_SPI_TXD    0x1C /* Data Transmit Register, WO */
  38 #define CDNS_SPI_RXD    0x20 /* Data Receive Register, RO */
  39 #define CDNS_SPI_SICR   0x24 /* Slave Idle Count Register, RW */
  40 #define CDNS_SPI_THLD   0x28 /* Transmit FIFO Watermark Register,RW */
  41
  42 #define SPI_AUTOSUSPEND_TIMEOUT         3000
  43 /*
  44  * SPI Configuration Register bit Masks
  45  *
  46  * This register contains various control bits that affect the operation
  47  * of the SPI controller
  48  */
  49 #define CDNS_SPI_CR_MANSTRT     0x00010000 /* Manual TX Start */
  50 #define CDNS_SPI_CR_CPHA                0x00000004 /* Clock Phase Control */
  51 #define CDNS_SPI_CR_CPOL                0x00000002 /* Clock Polarity Control */
  52 #define CDNS_SPI_CR_SSCTRL              0x00003C00 /* Slave Select Mask */
  53 #define CDNS_SPI_CR_PERI_SEL    0x00000200 /* Peripheral Select Decode */
  54 #define CDNS_SPI_CR_BAUD_DIV    0x00000038 /* Baud Rate Divisor Mask */
  55 #define CDNS_SPI_CR_MSTREN              0x00000001 /* Master Enable Mask */
  56 #define CDNS_SPI_CR_MANSTRTEN   0x00008000 /* Manual TX Enable Mask */
  57 #define CDNS_SPI_CR_SSFORCE     0x00004000 /* Manual SS Enable Mask */
  58 #define CDNS_SPI_CR_BAUD_DIV_4  0x00000008 /* Default Baud Div Mask */
  59 #define CDNS_SPI_CR_DEFAULT     (CDNS_SPI_CR_MSTREN | \
  60                                         CDNS_SPI_CR_SSCTRL | \
  61                                         CDNS_SPI_CR_SSFORCE | \
  62                                         CDNS_SPI_CR_BAUD_DIV_4)
  63
  64 /*
  65  * SPI Configuration Register - Baud rate and slave select
  66  *
  67  * These are the values used in the calculation of baud rate divisor and
  68  * setting the slave select.
  69  */
  70
  71 #define CDNS_SPI_BAUD_DIV_MAX           7 /* Baud rate divisor maximum */
  72 #define CDNS_SPI_BAUD_DIV_MIN           1 /* Baud rate divisor minimum */
  73 #define CDNS_SPI_BAUD_DIV_SHIFT         3 /* Baud rate divisor shift in CR */
  74 #define CDNS_SPI_SS_SHIFT               10 /* Slave Select field shift in CR */
  75 #define CDNS_SPI_SS0                    0x1 /* Slave Select zero */
  76
  77 /*
  78  * SPI Interrupt Registers bit Masks
  79  *
  80  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  81  * bit definitions.
  82  */
  83 #define CDNS_SPI_IXR_TXOW       0x00000004 /* SPI TX FIFO Overwater */
  84 #define CDNS_SPI_IXR_MODF       0x00000002 /* SPI Mode Fault */
  85 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  86 #define CDNS_SPI_IXR_DEFAULT    (CDNS_SPI_IXR_TXOW | \
  87                                         CDNS_SPI_IXR_MODF)
  88 #define CDNS_SPI_IXR_TXFULL     0x00000008 /* SPI TX Full */
  89 #define CDNS_SPI_IXR_ALL        0x0000007F /* SPI all interrupts */
  90
  91 /*
  92  * SPI Enable Register bit Masks
  93  *
  94  * This register is used to enable or disable the SPI controller
  95  */
  96 #define CDNS_SPI_ER_ENABLE      0x00000001 /* SPI Enable Bit Mask */
  97 #define CDNS_SPI_ER_DISABLE     0x0 /* SPI Disable Bit Mask */
  98
  99 /* SPI FIFO depth in bytes */
 100 #define CDNS_SPI_FIFO_DEPTH     128
 101
 102 /* Default number of chip select lines */
 103 #define CDNS_SPI_DEFAULT_NUM_CS         4
 104
 105 /**
 106  * struct cdns_spi - This definition defines spi driver instance
 107  * @regs:               Virtual address of the SPI controller registers
 108  * @ref_clk:            Pointer to the peripheral clock
 109  * @pclk:               Pointer to the APB clock
 110  * @speed_hz:           Current SPI bus clock speed in Hz
 111  * @txbuf:              Pointer to the TX buffer
 112  * @rxbuf:              Pointer to the RX buffer
 113  * @tx_bytes:           Number of bytes left to transfer
 114  * @rx_bytes:           Number of bytes requested
 115  * @dev_busy:           Device busy flag
 116  * @is_decoded_cs:      Flag for decoder property set or not
 117  */
 118 struct cdns_spi {
 119         void __iomem *regs;
 120         struct clk *ref_clk;
 121         struct clk *pclk;
 122         u32 speed_hz;
 123         const u8 *txbuf;
 124         u8 *rxbuf;
 125         int tx_bytes;
 126         int rx_bytes;
 127         u8 dev_busy;
 128         u32 is_decoded_cs;
 129 };
 130
 131 struct cdns_spi_device_data {
 132         bool gpio_requested;
 133 };
 134
 135 /* Macros for the SPI controller read/write */
 136 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
 137 {
 138         return readl_relaxed(xspi->regs + offset);
 139 }
 140
 141 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
 142 {
 143         writel_relaxed(val, xspi->regs + offset);
 144 }
 145
 146 /**
 147  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
 148  * @xspi:       Pointer to the cdns_spi structure
 149  *
 150  * On reset the SPI controller is configured to be in master mode, baud rate
 151  * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
 152  * to 1 and size of the word to be transferred as 8 bit.
 153  * This function initializes the SPI controller to disable and clear all the
 154  * interrupts, enable manual slave select and manual start, deselect all the
 155  * chip select lines, and enable the SPI controller.
 156  */
 157 static void cdns_spi_init_hw(struct cdns_spi *xspi)
 158 {
 159         u32 ctrl_reg = CDNS_SPI_CR_DEFAULT;
 160
 161         if (xspi->is_decoded_cs)
 162                 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
 163
 164         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 165         cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
 166
 167         /* Clear the RX FIFO */
 168         while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
 169                 cdns_spi_read(xspi, CDNS_SPI_RXD);
 170
 171         cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
 172         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 173         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 174 }
 175
 176 /**
 177  * cdns_spi_chipselect - Select or deselect the chip select line
 178  * @spi:        Pointer to the spi_device structure
 179  * @is_high:    Select(0) or deselect (1) the chip select line
 180  */
 181 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
 182 {
 183         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 184         u32 ctrl_reg;
 185
 186         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 187
 188         if (is_high) {
 189                 /* Deselect the slave */
 190                 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
 191         } else {
 192                 /* Select the slave */
 193                 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
 194                 if (!(xspi->is_decoded_cs))
 195                         ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
 196                                      CDNS_SPI_SS_SHIFT) &
 197                                      CDNS_SPI_CR_SSCTRL;
 198                 else
 199                         ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
 200                                      CDNS_SPI_CR_SSCTRL;
 201         }
 202
 203         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 204 }
 205
 206 /**
 207  * cdns_spi_config_clock_mode - Sets clock polarity and phase
 208  * @spi:        Pointer to the spi_device structure
 209  *
 210  * Sets the requested clock polarity and phase.
 211  */
 212 static void cdns_spi_config_clock_mode(struct spi_device *spi)
 213 {
 214         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 215         u32 ctrl_reg, new_ctrl_reg;
 216
 217         new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 218         ctrl_reg = new_ctrl_reg;
 219
 220         /* Set the SPI clock phase and clock polarity */
 221         new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
 222         if (spi->mode & SPI_CPHA)
 223                 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
 224         if (spi->mode & SPI_CPOL)
 225                 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
 226
 227         if (new_ctrl_reg != ctrl_reg) {
 228                 /*
 229                  * Just writing the CR register does not seem to apply the clock
 230                  * setting changes. This is problematic when changing the clock
 231                  * polarity as it will cause the SPI slave to see spurious clock
 232                  * transitions. To workaround the issue toggle the ER register.
 233                  */
 234                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 235                 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
 236                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 237         }
 238 }
 239
 240 /**
 241  * cdns_spi_config_clock_freq - Sets clock frequency
 242  * @spi:        Pointer to the spi_device structure
 243  * @transfer:   Pointer to the spi_transfer structure which provides
 244  *              information about next transfer setup parameters
 245  *
 246  * Sets the requested clock frequency.
 247  * Note: If the requested frequency is not an exact match with what can be
 248  * obtained using the prescalar value the driver sets the clock frequency which
 249  * is lower than the requested frequency (maximum lower) for the transfer. If
 250  * the requested frequency is higher or lower than that is supported by the SPI
 251  * controller the driver will set the highest or lowest frequency supported by
 252  * controller.
 253  */
 254 static void cdns_spi_config_clock_freq(struct spi_device *spi,
 255                                        struct spi_transfer *transfer)
 256 {
 257         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 258         u32 ctrl_reg, baud_rate_val;
 259         unsigned long frequency;
 260
 261         frequency = clk_get_rate(xspi->ref_clk);
 262
 263         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 264
 265         /* Set the clock frequency */
 266         if (xspi->speed_hz != transfer->speed_hz) {
 267                 /* first valid value is 1 */
 268                 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
 269                 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
 270                        (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
 271                         baud_rate_val++;
 272
 273                 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
 274                 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
 275
 276                 xspi->speed_hz = frequency / (2 << baud_rate_val);
 277         }
 278         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 279 }
 280
 281 /**
 282  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
 283  * @spi:        Pointer to the spi_device structure
 284  * @transfer:   Pointer to the spi_transfer structure which provides
 285  *              information about next transfer setup parameters
 286  *
 287  * Sets the operational mode of SPI controller for the next SPI transfer and
 288  * sets the requested clock frequency.
 289  *
 290  * Return:      Always 0
 291  */
 292 static int cdns_spi_setup_transfer(struct spi_device *spi,
 293                                    struct spi_transfer *transfer)
 294 {
 295         struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
 296
 297         cdns_spi_config_clock_freq(spi, transfer);
 298
 299         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
 300                 __func__, spi->mode, spi->bits_per_word,
 301                 xspi->speed_hz);
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
 308  * @xspi:       Pointer to the cdns_spi structure
 309  */
 310 static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
 311 {
 312         unsigned long trans_cnt = 0;
 313
 314         while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
 315                (xspi->tx_bytes > 0)) {
 316
 317                 /* When xspi in busy condition, bytes may send failed,
 318                  * then spi control did't work thoroughly, add one byte delay
 319                  */
 320                 if (cdns_spi_read(xspi, CDNS_SPI_ISR) &
 321                     CDNS_SPI_IXR_TXFULL)
 322                         udelay(10);
 323
 324                 if (xspi->txbuf)
 325                         cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
 326                 else
 327                         cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
 328
 329                 xspi->tx_bytes--;
 330                 trans_cnt++;
 331         }
 332 }
 333
 334 /**
 335  * cdns_spi_irq - Interrupt service routine of the SPI controller
 336  * @irq:        IRQ number
 337  * @dev_id:     Pointer to the xspi structure
 338  *
 339  * This function handles TX empty and Mode Fault interrupts only.
 340  * On TX empty interrupt this function reads the received data from RX FIFO and
 341  * fills the TX FIFO if there is any data remaining to be transferred.
 342  * On Mode Fault interrupt this function indicates that transfer is completed,
 343  * the SPI subsystem will identify the error as the remaining bytes to be
 344  * transferred is non-zero.
 345  *
 346  * Return:      IRQ_HANDLED when handled; IRQ_NONE otherwise.
 347  */
 348 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
 349 {
 350         struct spi_master *master = dev_id;
 351         struct cdns_spi *xspi = spi_master_get_devdata(master);
 352         u32 intr_status, status;
 353
 354         status = IRQ_NONE;
 355         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 356         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 357
 358         if (intr_status & CDNS_SPI_IXR_MODF) {
 359                 /* Indicate that transfer is completed, the SPI subsystem will
 360                  * identify the error as the remaining bytes to be
 361                  * transferred is non-zero
 362                  */
 363                 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
 364                 spi_finalize_current_transfer(master);
 365                 status = IRQ_HANDLED;
 366         } else if (intr_status & CDNS_SPI_IXR_TXOW) {
 367                 unsigned long trans_cnt;
 368
 369                 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
 370
 371                 /* Read out the data from the RX FIFO */
 372                 while (trans_cnt) {
 373                         u8 data;
 374
 375                         data = cdns_spi_read(xspi, CDNS_SPI_RXD);
 376                         if (xspi->rxbuf)
 377                                 *xspi->rxbuf++ = data;
 378
 379                         xspi->rx_bytes--;
 380                         trans_cnt--;
 381                 }
 382
 383                 if (xspi->tx_bytes) {
 384                         /* There is more data to send */
 385                         cdns_spi_fill_tx_fifo(xspi);
 386                 } else {
 387                         /* Transfer is completed */
 388                         cdns_spi_write(xspi, CDNS_SPI_IDR,
 389                                        CDNS_SPI_IXR_DEFAULT);
 390                         spi_finalize_current_transfer(master);
 391                 }
 392                 status = IRQ_HANDLED;
 393         }
 394
 395         return status;
 396 }
 397
 398 static int cdns_prepare_message(struct spi_master *master,
 399                                 struct spi_message *msg)
 400 {
 401         cdns_spi_config_clock_mode(msg->spi);
 402         return 0;
 403 }
 404
 405 /**
 406  * cdns_transfer_one - Initiates the SPI transfer
 407  * @master:     Pointer to spi_master structure
 408  * @spi:        Pointer to the spi_device structure
 409  * @transfer:   Pointer to the spi_transfer structure which provides
 410  *              information about next transfer parameters
 411  *
 412  * This function fills the TX FIFO, starts the SPI transfer and
 413  * returns a positive transfer count so that core will wait for completion.
 414  *
 415  * Return:      Number of bytes transferred in the last transfer
 416  */
 417 static int cdns_transfer_one(struct spi_master *master,
 418                              struct spi_device *spi,
 419                              struct spi_transfer *transfer)
 420 {
 421         struct cdns_spi *xspi = spi_master_get_devdata(master);
 422
 423         xspi->txbuf = transfer->tx_buf;
 424         xspi->rxbuf = transfer->rx_buf;
 425         xspi->tx_bytes = transfer->len;
 426         xspi->rx_bytes = transfer->len;
 427
 428         cdns_spi_setup_transfer(spi, transfer);
 429
 430         cdns_spi_fill_tx_fifo(xspi);
 431
 432         cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
 433         return transfer->len;
 434 }
 435
 436 /**
 437  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
 438  * @master:     Pointer to the spi_master structure which provides
 439  *              information about the controller.
 440  *
 441  * This function enables SPI master controller.
 442  *
 443  * Return:      0 always
 444  */
 445 static int cdns_prepare_transfer_hardware(struct spi_master *master)
 446 {
 447         struct cdns_spi *xspi = spi_master_get_devdata(master);
 448
 449         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 450
 451         return 0;
 452 }
 453
 454 /**
 455  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
 456  * @master:     Pointer to the spi_master structure which provides
 457  *              information about the controller.
 458  *
 459  * This function disables the SPI master controller.
 460  *
 461  * Return:      0 always
 462  */
 463 static int cdns_unprepare_transfer_hardware(struct spi_master *master)
 464 {
 465         struct cdns_spi *xspi = spi_master_get_devdata(master);
 466
 467         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 468
 469         return 0;
 470 }
 471
 472 static int cdns_spi_setup(struct spi_device *spi)
 473 {
 474
 475         int ret = -EINVAL;
 476         struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi);
 477
 478         /* this is a pin managed by the controller, leave it alone */
 479         if (spi->cs_gpio == -ENOENT)
 480                 return 0;
 481
 482         /* this seems to be the first time we're here */
 483         if (!cdns_spi_data) {
 484                 cdns_spi_data = kzalloc(sizeof(*cdns_spi_data), GFP_KERNEL);
 485                 if (!cdns_spi_data)
 486                         return -ENOMEM;
 487                 cdns_spi_data->gpio_requested = false;
 488                 spi_set_ctldata(spi, cdns_spi_data);
 489         }
 490
 491         /* if we haven't done so, grab the gpio */
 492         if (!cdns_spi_data->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
 493                 ret = gpio_request_one(spi->cs_gpio,
 494                                        (spi->mode & SPI_CS_HIGH) ?
 495                                        GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
 496                                        dev_name(&spi->dev));
 497                 if (ret)
 498                         dev_err(&spi->dev, "can't request chipselect gpio %d\n",
 499                                 spi->cs_gpio);
 500                 else
 501                         cdns_spi_data->gpio_requested = true;
 502         } else {
 503                 if (gpio_is_valid(spi->cs_gpio)) {
 504                         int mode = ((spi->mode & SPI_CS_HIGH) ?
 505                                     GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH);
 506
 507                         ret = gpio_direction_output(spi->cs_gpio, mode);
 508                         if (ret)
 509                                 dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
 510                                         spi->cs_gpio, ret);
 511                 }
 512         }
 513
 514         return ret;
 515 }
 516
 517 static void cdns_spi_cleanup(struct spi_device *spi)
 518 {
 519         struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi);
 520
 521         if (cdns_spi_data) {
 522                 if (cdns_spi_data->gpio_requested)
 523                         gpio_free(spi->cs_gpio);
 524                 kfree(cdns_spi_data);
 525                 spi_set_ctldata(spi, NULL);
 526         }
 527
 528 }
 529
 530 /**
 531  * cdns_spi_probe - Probe method for the SPI driver
 532  * @pdev:       Pointer to the platform_device structure
 533  *
 534  * This function initializes the driver data structures and the hardware.
 535  *
 536  * Return:      0 on success and error value on error
 537  */
 538 static int cdns_spi_probe(struct platform_device *pdev)
 539 {
 540         int ret = 0, irq;
 541         struct spi_master *master;
 542         struct cdns_spi *xspi;
 543         struct resource *res;
 544         u32 num_cs;
 545
 546         master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
 547         if (!master)
 548                 return -ENOMEM;
 549
 550         xspi = spi_master_get_devdata(master);
 551         master->dev.of_node = pdev->dev.of_node;
 552         platform_set_drvdata(pdev, master);
 553
 554         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 555         xspi->regs = devm_ioremap_resource(&pdev->dev, res);
 556         if (IS_ERR(xspi->regs)) {
 557                 ret = PTR_ERR(xspi->regs);
 558                 goto remove_master;
 559         }
 560
 561         xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
 562         if (IS_ERR(xspi->pclk)) {
 563                 dev_err(&pdev->dev, "pclk clock not found.\n");
 564                 ret = PTR_ERR(xspi->pclk);
 565                 goto remove_master;
 566         }
 567
 568         xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
 569         if (IS_ERR(xspi->ref_clk)) {
 570                 dev_err(&pdev->dev, "ref_clk clock not found.\n");
 571                 ret = PTR_ERR(xspi->ref_clk);
 572                 goto remove_master;
 573         }
 574
 575         ret = clk_prepare_enable(xspi->pclk);
 576         if (ret) {
 577                 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
 578                 goto remove_master;
 579         }
 580
 581         ret = clk_prepare_enable(xspi->ref_clk);
 582         if (ret) {
 583                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
 584                 goto clk_dis_apb;
 585         }
 586
 587         pm_runtime_use_autosuspend(&pdev->dev);
 588         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 589         pm_runtime_set_active(&pdev->dev);
 590         pm_runtime_enable(&pdev->dev);
 591
 592         ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 593         if (ret < 0)
 594                 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
 595         else
 596                 master->num_chipselect = num_cs;
 597
 598         ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
 599                                    &xspi->is_decoded_cs);
 600         if (ret < 0)
 601                 xspi->is_decoded_cs = 0;
 602
 603         /* SPI controller initializations */
 604         cdns_spi_init_hw(xspi);
 605
 606         pm_runtime_mark_last_busy(&pdev->dev);
 607         pm_runtime_put_autosuspend(&pdev->dev);
 608
 609         irq = platform_get_irq(pdev, 0);
 610         if (irq <= 0) {
 611                 ret = -ENXIO;
 612                 dev_err(&pdev->dev, "irq number is invalid\n");
 613                 goto clk_dis_all;
 614         }
 615
 616         ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
 617                                0, pdev->name, master);
 618         if (ret != 0) {
 619                 ret = -ENXIO;
 620                 dev_err(&pdev->dev, "request_irq failed\n");
 621                 goto clk_dis_all;
 622         }
 623
 624         master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
 625         master->prepare_message = cdns_prepare_message;
 626         master->transfer_one = cdns_transfer_one;
 627         master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 628         master->set_cs = cdns_spi_chipselect;
 629         master->setup = cdns_spi_setup;
 630         master->cleanup = cdns_spi_cleanup;
 631         master->auto_runtime_pm = true;
 632         master->mode_bits = SPI_CPOL | SPI_CPHA;
 633
 634         /* Set to default valid value */
 635         master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
 636         xspi->speed_hz = master->max_speed_hz;
 637
 638         master->bits_per_word_mask = SPI_BPW_MASK(8);
 639
 640         ret = spi_register_master(master);
 641         if (ret) {
 642                 dev_err(&pdev->dev, "spi_register_master failed\n");
 643                 goto clk_dis_all;
 644         }
 645
 646         return ret;
 647
 648 clk_dis_all:
 649         pm_runtime_set_suspended(&pdev->dev);
 650         pm_runtime_disable(&pdev->dev);
 651         clk_disable_unprepare(xspi->ref_clk);
 652 clk_dis_apb:
 653         clk_disable_unprepare(xspi->pclk);
 654 remove_master:
 655         spi_master_put(master);
 656         return ret;
 657 }
 658
 659 /**
 660  * cdns_spi_remove - Remove method for the SPI driver
 661  * @pdev:       Pointer to the platform_device structure
 662  *
 663  * This function is called if a device is physically removed from the system or
 664  * if the driver module is being unloaded. It frees all resources allocated to
 665  * the device.
 666  *
 667  * Return:      0 on success and error value on error
 668  */
 669 static int cdns_spi_remove(struct platform_device *pdev)
 670 {
 671         struct spi_master *master = platform_get_drvdata(pdev);
 672         struct cdns_spi *xspi = spi_master_get_devdata(master);
 673
 674         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 675
 676         clk_disable_unprepare(xspi->ref_clk);
 677         clk_disable_unprepare(xspi->pclk);
 678         pm_runtime_set_suspended(&pdev->dev);
 679         pm_runtime_disable(&pdev->dev);
 680
 681         spi_unregister_master(master);
 682
 683         return 0;
 684 }
 685
 686 /**
 687  * cdns_spi_suspend - Suspend method for the SPI driver
 688  * @dev:        Address of the platform_device structure
 689  *
 690  * This function disables the SPI controller and
 691  * changes the driver state to "suspend"
 692  *
 693  * Return:      0 on success and error value on error
 694  */
 695 static int __maybe_unused cdns_spi_suspend(struct device *dev)
 696 {
 697         struct platform_device *pdev = to_platform_device(dev);
 698         struct spi_master *master = platform_get_drvdata(pdev);
 699
 700         return spi_master_suspend(master);
 701 }
 702
 703 /**
 704  * cdns_spi_resume - Resume method for the SPI driver
 705  * @dev:        Address of the platform_device structure
 706  *
 707  * This function changes the driver state to "ready"
 708  *
 709  * Return:      0 on success and error value on error
 710  */
 711 static int __maybe_unused cdns_spi_resume(struct device *dev)
 712 {
 713         struct platform_device *pdev = to_platform_device(dev);
 714         struct spi_master *master = platform_get_drvdata(pdev);
 715         struct cdns_spi *xspi = spi_master_get_devdata(master);
 716
 717         cdns_spi_init_hw(xspi);
 718         return spi_master_resume(master);
 719 }
 720
 721 /**
 722  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
 723  * @dev:        Address of the platform_device structure
 724  *
 725  * This function enables the clocks
 726  *
 727  * Return:      0 on success and error value on error
 728  */
 729 static int __maybe_unused cnds_runtime_resume(struct device *dev)
 730 {
 731         struct spi_master *master = dev_get_drvdata(dev);
 732         struct cdns_spi *xspi = spi_master_get_devdata(master);
 733         int ret;
 734
 735         ret = clk_prepare_enable(xspi->pclk);
 736         if (ret) {
 737                 dev_err(dev, "Cannot enable APB clock.\n");
 738                 return ret;
 739         }
 740
 741         ret = clk_prepare_enable(xspi->ref_clk);
 742         if (ret) {
 743                 dev_err(dev, "Cannot enable device clock.\n");
 744                 clk_disable(xspi->pclk);
 745                 return ret;
 746         }
 747         return 0;
 748 }
 749
 750 /**
 751  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
 752  * @dev:        Address of the platform_device structure
 753  *
 754  * This function disables the clocks
 755  *
 756  * Return:      Always 0
 757  */
 758 static int __maybe_unused cnds_runtime_suspend(struct device *dev)
 759 {
 760         struct spi_master *master = dev_get_drvdata(dev);
 761         struct cdns_spi *xspi = spi_master_get_devdata(master);
 762
 763         clk_disable_unprepare(xspi->ref_clk);
 764         clk_disable_unprepare(xspi->pclk);
 765
 766         return 0;
 767 }
 768
 769 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
 770         SET_RUNTIME_PM_OPS(cnds_runtime_suspend,
 771                            cnds_runtime_resume, NULL)
 772         SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
 773 };
 774
 775 static const struct of_device_id cdns_spi_of_match[] = {
 776         { .compatible = "xlnx,zynq-spi-r1p6" },
 777         { .compatible = "cdns,spi-r1p6" },
 778         { /* end of table */ }
 779 };
 780 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
 781
 782 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
 783 static struct platform_driver cdns_spi_driver = {
 784         .probe  = cdns_spi_probe,
 785         .remove = cdns_spi_remove,
 786         .driver = {
 787                 .name = CDNS_SPI_NAME,
 788                 .of_match_table = cdns_spi_of_match,
 789                 .pm = &cdns_spi_dev_pm_ops,
 790         },
 791 };
 792
 793 module_platform_driver(cdns_spi_driver);
 794
 795 MODULE_AUTHOR("Xilinx, Inc.");
 796 MODULE_DESCRIPTION("Cadence SPI driver");
 797 MODULE_LICENSE("GPL");