2 * Analog Devices SPI3 controller driver
4 * Copyright (c) 2014 Analog Devices Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/errno.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/adi_spi3.h>
30 #include <linux/types.h>
33 #include <asm/portmux.h>
42 struct adi_spi_master
;
44 struct adi_spi_transfer_ops
{
45 void (*write
) (struct adi_spi_master
*);
46 void (*read
) (struct adi_spi_master
*);
47 void (*duplex
) (struct adi_spi_master
*);
50 /* runtime info for spi master */
51 struct adi_spi_master
{
52 /* SPI framework hookup */
53 struct spi_master
*master
;
55 /* Regs base of SPI controller */
56 struct adi_spi_regs __iomem
*regs
;
58 /* Pin request list */
61 /* Message Transfer pump */
62 struct tasklet_struct pump_transfers
;
64 /* Current message transfer state info */
65 struct spi_message
*cur_msg
;
66 struct spi_transfer
*cur_transfer
;
67 struct adi_spi_device
*cur_chip
;
68 unsigned transfer_len
;
79 dma_addr_t tx_dma_addr
;
80 dma_addr_t rx_dma_addr
;
81 unsigned long dummy_buffer
; /* used in unidirectional transfer */
82 unsigned long tx_dma_size
;
83 unsigned long rx_dma_size
;
87 /* store register value for suspend/resume */
92 enum adi_spi_state state
;
94 const struct adi_spi_transfer_ops
*ops
;
97 struct adi_spi_device
{
103 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
105 u32 tx_dummy_val
; /* tx value for rx only transfer */
107 const struct adi_spi_transfer_ops
*ops
;
110 static void adi_spi_enable(struct adi_spi_master
*drv_data
)
114 ctl
= ioread32(&drv_data
->regs
->control
);
116 iowrite32(ctl
, &drv_data
->regs
->control
);
119 static void adi_spi_disable(struct adi_spi_master
*drv_data
)
123 ctl
= ioread32(&drv_data
->regs
->control
);
125 iowrite32(ctl
, &drv_data
->regs
->control
);
128 /* Caculate the SPI_CLOCK register value based on input HZ */
129 static u32
hz_to_spi_clock(u32 sclk
, u32 speed_hz
)
131 u32 spi_clock
= sclk
/ speed_hz
;
138 static int adi_spi_flush(struct adi_spi_master
*drv_data
)
140 unsigned long limit
= loops_per_jiffy
<< 1;
142 /* wait for stop and clear stat */
143 while (!(ioread32(&drv_data
->regs
->status
) & SPI_STAT_SPIF
) && --limit
)
146 iowrite32(0xFFFFFFFF, &drv_data
->regs
->status
);
151 /* Chip select operation functions for cs_change flag */
152 static void adi_spi_cs_active(struct adi_spi_master
*drv_data
, struct adi_spi_device
*chip
)
154 if (likely(chip
->cs
< MAX_CTRL_CS
)) {
156 reg
= ioread32(&drv_data
->regs
->ssel
);
158 iowrite32(reg
, &drv_data
->regs
->ssel
);
160 gpio_set_value(chip
->cs_gpio
, 0);
164 static void adi_spi_cs_deactive(struct adi_spi_master
*drv_data
,
165 struct adi_spi_device
*chip
)
167 if (likely(chip
->cs
< MAX_CTRL_CS
)) {
169 reg
= ioread32(&drv_data
->regs
->ssel
);
171 iowrite32(reg
, &drv_data
->regs
->ssel
);
173 gpio_set_value(chip
->cs_gpio
, 1);
176 /* Move delay here for consistency */
177 if (chip
->cs_chg_udelay
)
178 udelay(chip
->cs_chg_udelay
);
181 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
182 static inline void adi_spi_cs_enable(struct adi_spi_master
*drv_data
,
183 struct adi_spi_device
*chip
)
185 if (chip
->cs
< MAX_CTRL_CS
) {
187 reg
= ioread32(&drv_data
->regs
->ssel
);
188 reg
|= chip
->ssel
>> 8;
189 iowrite32(reg
, &drv_data
->regs
->ssel
);
193 static inline void adi_spi_cs_disable(struct adi_spi_master
*drv_data
,
194 struct adi_spi_device
*chip
)
196 if (chip
->cs
< MAX_CTRL_CS
) {
198 reg
= ioread32(&drv_data
->regs
->ssel
);
199 reg
&= ~(chip
->ssel
>> 8);
200 iowrite32(reg
, &drv_data
->regs
->ssel
);
204 /* stop controller and re-config current chip*/
205 static void adi_spi_restore_state(struct adi_spi_master
*drv_data
)
207 struct adi_spi_device
*chip
= drv_data
->cur_chip
;
209 /* Clear status and disable clock */
210 iowrite32(0xFFFFFFFF, &drv_data
->regs
->status
);
211 iowrite32(0x0, &drv_data
->regs
->rx_control
);
212 iowrite32(0x0, &drv_data
->regs
->tx_control
);
213 adi_spi_disable(drv_data
);
215 /* Load the registers */
216 iowrite32(chip
->control
, &drv_data
->regs
->control
);
217 iowrite32(chip
->clock
, &drv_data
->regs
->clock
);
219 adi_spi_enable(drv_data
);
220 drv_data
->tx_num
= drv_data
->rx_num
= 0;
221 /* we always choose tx transfer initiate */
222 iowrite32(SPI_RXCTL_REN
, &drv_data
->regs
->rx_control
);
223 iowrite32(SPI_TXCTL_TEN
| SPI_TXCTL_TTI
, &drv_data
->regs
->tx_control
);
224 adi_spi_cs_active(drv_data
, chip
);
227 /* discard invalid rx data and empty rfifo */
228 static inline void dummy_read(struct adi_spi_master
*drv_data
)
230 while (!(ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
))
231 ioread32(&drv_data
->regs
->rfifo
);
234 static void adi_spi_u8_write(struct adi_spi_master
*drv_data
)
236 dummy_read(drv_data
);
237 while (drv_data
->tx
< drv_data
->tx_end
) {
238 iowrite32(*(u8
*)(drv_data
->tx
++), &drv_data
->regs
->tfifo
);
239 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
241 ioread32(&drv_data
->regs
->rfifo
);
245 static void adi_spi_u8_read(struct adi_spi_master
*drv_data
)
247 u32 tx_val
= drv_data
->cur_chip
->tx_dummy_val
;
249 dummy_read(drv_data
);
250 while (drv_data
->rx
< drv_data
->rx_end
) {
251 iowrite32(tx_val
, &drv_data
->regs
->tfifo
);
252 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
254 *(u8
*)(drv_data
->rx
++) = ioread32(&drv_data
->regs
->rfifo
);
258 static void adi_spi_u8_duplex(struct adi_spi_master
*drv_data
)
260 dummy_read(drv_data
);
261 while (drv_data
->rx
< drv_data
->rx_end
) {
262 iowrite32(*(u8
*)(drv_data
->tx
++), &drv_data
->regs
->tfifo
);
263 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
265 *(u8
*)(drv_data
->rx
++) = ioread32(&drv_data
->regs
->rfifo
);
269 static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u8
= {
270 .write
= adi_spi_u8_write
,
271 .read
= adi_spi_u8_read
,
272 .duplex
= adi_spi_u8_duplex
,
275 static void adi_spi_u16_write(struct adi_spi_master
*drv_data
)
277 dummy_read(drv_data
);
278 while (drv_data
->tx
< drv_data
->tx_end
) {
279 iowrite32(*(u16
*)drv_data
->tx
, &drv_data
->regs
->tfifo
);
281 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
283 ioread32(&drv_data
->regs
->rfifo
);
287 static void adi_spi_u16_read(struct adi_spi_master
*drv_data
)
289 u32 tx_val
= drv_data
->cur_chip
->tx_dummy_val
;
291 dummy_read(drv_data
);
292 while (drv_data
->rx
< drv_data
->rx_end
) {
293 iowrite32(tx_val
, &drv_data
->regs
->tfifo
);
294 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
296 *(u16
*)drv_data
->rx
= ioread32(&drv_data
->regs
->rfifo
);
301 static void adi_spi_u16_duplex(struct adi_spi_master
*drv_data
)
303 dummy_read(drv_data
);
304 while (drv_data
->rx
< drv_data
->rx_end
) {
305 iowrite32(*(u16
*)drv_data
->tx
, &drv_data
->regs
->tfifo
);
307 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
309 *(u16
*)drv_data
->rx
= ioread32(&drv_data
->regs
->rfifo
);
314 static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u16
= {
315 .write
= adi_spi_u16_write
,
316 .read
= adi_spi_u16_read
,
317 .duplex
= adi_spi_u16_duplex
,
320 static void adi_spi_u32_write(struct adi_spi_master
*drv_data
)
322 dummy_read(drv_data
);
323 while (drv_data
->tx
< drv_data
->tx_end
) {
324 iowrite32(*(u32
*)drv_data
->tx
, &drv_data
->regs
->tfifo
);
326 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
328 ioread32(&drv_data
->regs
->rfifo
);
332 static void adi_spi_u32_read(struct adi_spi_master
*drv_data
)
334 u32 tx_val
= drv_data
->cur_chip
->tx_dummy_val
;
336 dummy_read(drv_data
);
337 while (drv_data
->rx
< drv_data
->rx_end
) {
338 iowrite32(tx_val
, &drv_data
->regs
->tfifo
);
339 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
341 *(u32
*)drv_data
->rx
= ioread32(&drv_data
->regs
->rfifo
);
346 static void adi_spi_u32_duplex(struct adi_spi_master
*drv_data
)
348 dummy_read(drv_data
);
349 while (drv_data
->rx
< drv_data
->rx_end
) {
350 iowrite32(*(u32
*)drv_data
->tx
, &drv_data
->regs
->tfifo
);
352 while (ioread32(&drv_data
->regs
->status
) & SPI_STAT_RFE
)
354 *(u32
*)drv_data
->rx
= ioread32(&drv_data
->regs
->rfifo
);
359 static const struct adi_spi_transfer_ops adi_spi_transfer_ops_u32
= {
360 .write
= adi_spi_u32_write
,
361 .read
= adi_spi_u32_read
,
362 .duplex
= adi_spi_u32_duplex
,
366 /* test if there is more transfer to be done */
367 static void adi_spi_next_transfer(struct adi_spi_master
*drv
)
369 struct spi_message
*msg
= drv
->cur_msg
;
370 struct spi_transfer
*t
= drv
->cur_transfer
;
372 /* Move to next transfer */
373 if (t
->transfer_list
.next
!= &msg
->transfers
) {
374 drv
->cur_transfer
= list_entry(t
->transfer_list
.next
,
375 struct spi_transfer
, transfer_list
);
376 drv
->state
= RUNNING_STATE
;
378 drv
->state
= DONE_STATE
;
379 drv
->cur_transfer
= NULL
;
383 static void adi_spi_giveback(struct adi_spi_master
*drv_data
)
385 struct adi_spi_device
*chip
= drv_data
->cur_chip
;
387 adi_spi_cs_deactive(drv_data
, chip
);
388 spi_finalize_current_message(drv_data
->master
);
391 static int adi_spi_setup_transfer(struct adi_spi_master
*drv
)
393 struct spi_transfer
*t
= drv
->cur_transfer
;
397 drv
->tx
= (void *)t
->tx_buf
;
398 drv
->tx_end
= drv
->tx
+ t
->len
;
405 drv
->rx_end
= drv
->rx
+ t
->len
;
410 drv
->transfer_len
= t
->len
;
412 /* bits per word setup */
413 switch (t
->bits_per_word
) {
415 cr_width
= SPI_CTL_SIZE08
;
416 drv
->ops
= &adi_spi_transfer_ops_u8
;
419 cr_width
= SPI_CTL_SIZE16
;
420 drv
->ops
= &adi_spi_transfer_ops_u16
;
423 cr_width
= SPI_CTL_SIZE32
;
424 drv
->ops
= &adi_spi_transfer_ops_u32
;
429 cr
= ioread32(&drv
->regs
->control
) & ~SPI_CTL_SIZE
;
431 iowrite32(cr
, &drv
->regs
->control
);
434 iowrite32(hz_to_spi_clock(drv
->sclk
, t
->speed_hz
), &drv
->regs
->clock
);
438 static int adi_spi_dma_xfer(struct adi_spi_master
*drv_data
)
440 struct spi_transfer
*t
= drv_data
->cur_transfer
;
441 struct spi_message
*msg
= drv_data
->cur_msg
;
442 struct adi_spi_device
*chip
= drv_data
->cur_chip
;
444 unsigned long word_count
, word_size
;
445 void *tx_buf
, *rx_buf
;
447 switch (t
->bits_per_word
) {
449 dma_config
= WDSIZE_8
| PSIZE_8
;
450 word_count
= drv_data
->transfer_len
;
454 dma_config
= WDSIZE_16
| PSIZE_16
;
455 word_count
= drv_data
->transfer_len
/ 2;
459 dma_config
= WDSIZE_32
| PSIZE_32
;
460 word_count
= drv_data
->transfer_len
/ 4;
466 tx_buf
= drv_data
->tx
;
467 rx_buf
= &drv_data
->dummy_buffer
;
468 drv_data
->tx_dma_size
= drv_data
->transfer_len
;
469 drv_data
->rx_dma_size
= sizeof(drv_data
->dummy_buffer
);
470 set_dma_x_modify(drv_data
->tx_dma
, word_size
);
471 set_dma_x_modify(drv_data
->rx_dma
, 0);
472 } else if (!drv_data
->tx
) {
473 drv_data
->dummy_buffer
= chip
->tx_dummy_val
;
474 tx_buf
= &drv_data
->dummy_buffer
;
475 rx_buf
= drv_data
->rx
;
476 drv_data
->tx_dma_size
= sizeof(drv_data
->dummy_buffer
);
477 drv_data
->rx_dma_size
= drv_data
->transfer_len
;
478 set_dma_x_modify(drv_data
->tx_dma
, 0);
479 set_dma_x_modify(drv_data
->rx_dma
, word_size
);
481 tx_buf
= drv_data
->tx
;
482 rx_buf
= drv_data
->rx
;
483 drv_data
->tx_dma_size
= drv_data
->rx_dma_size
484 = drv_data
->transfer_len
;
485 set_dma_x_modify(drv_data
->tx_dma
, word_size
);
486 set_dma_x_modify(drv_data
->rx_dma
, word_size
);
489 drv_data
->tx_dma_addr
= dma_map_single(&msg
->spi
->dev
,
491 drv_data
->tx_dma_size
,
493 if (dma_mapping_error(&msg
->spi
->dev
,
494 drv_data
->tx_dma_addr
))
497 drv_data
->rx_dma_addr
= dma_map_single(&msg
->spi
->dev
,
499 drv_data
->rx_dma_size
,
501 if (dma_mapping_error(&msg
->spi
->dev
,
502 drv_data
->rx_dma_addr
)) {
503 dma_unmap_single(&msg
->spi
->dev
,
504 drv_data
->tx_dma_addr
,
505 drv_data
->tx_dma_size
,
510 dummy_read(drv_data
);
511 set_dma_x_count(drv_data
->tx_dma
, word_count
);
512 set_dma_x_count(drv_data
->rx_dma
, word_count
);
513 set_dma_start_addr(drv_data
->tx_dma
, drv_data
->tx_dma_addr
);
514 set_dma_start_addr(drv_data
->rx_dma
, drv_data
->rx_dma_addr
);
515 dma_config
|= DMAFLOW_STOP
| RESTART
| DI_EN
;
516 set_dma_config(drv_data
->tx_dma
, dma_config
);
517 set_dma_config(drv_data
->rx_dma
, dma_config
| WNR
);
518 enable_dma(drv_data
->tx_dma
);
519 enable_dma(drv_data
->rx_dma
);
521 iowrite32(SPI_RXCTL_REN
| SPI_RXCTL_RDR_NE
,
522 &drv_data
->regs
->rx_control
);
523 iowrite32(SPI_TXCTL_TEN
| SPI_TXCTL_TTI
| SPI_TXCTL_TDR_NF
,
524 &drv_data
->regs
->tx_control
);
529 static int adi_spi_pio_xfer(struct adi_spi_master
*drv_data
)
531 struct spi_message
*msg
= drv_data
->cur_msg
;
534 /* write only half duplex */
535 drv_data
->ops
->write(drv_data
);
536 if (drv_data
->tx
!= drv_data
->tx_end
)
538 } else if (!drv_data
->tx
) {
539 /* read only half duplex */
540 drv_data
->ops
->read(drv_data
);
541 if (drv_data
->rx
!= drv_data
->rx_end
)
544 /* full duplex mode */
545 drv_data
->ops
->duplex(drv_data
);
546 if (drv_data
->tx
!= drv_data
->tx_end
)
550 if (!adi_spi_flush(drv_data
))
552 msg
->actual_length
+= drv_data
->transfer_len
;
553 tasklet_schedule(&drv_data
->pump_transfers
);
557 static void adi_spi_pump_transfers(unsigned long data
)
559 struct adi_spi_master
*drv_data
= (struct adi_spi_master
*)data
;
560 struct spi_message
*msg
= NULL
;
561 struct spi_transfer
*t
= NULL
;
562 struct adi_spi_device
*chip
= NULL
;
565 /* Get current state information */
566 msg
= drv_data
->cur_msg
;
567 t
= drv_data
->cur_transfer
;
568 chip
= drv_data
->cur_chip
;
570 /* Handle for abort */
571 if (drv_data
->state
== ERROR_STATE
) {
573 adi_spi_giveback(drv_data
);
577 if (drv_data
->state
== RUNNING_STATE
) {
579 udelay(t
->delay_usecs
);
581 adi_spi_cs_deactive(drv_data
, chip
);
582 adi_spi_next_transfer(drv_data
);
583 t
= drv_data
->cur_transfer
;
585 /* Handle end of message */
586 if (drv_data
->state
== DONE_STATE
) {
588 adi_spi_giveback(drv_data
);
592 if ((t
->len
== 0) || (t
->tx_buf
== NULL
&& t
->rx_buf
== NULL
)) {
593 /* Schedule next transfer tasklet */
594 tasklet_schedule(&drv_data
->pump_transfers
);
598 ret
= adi_spi_setup_transfer(drv_data
);
601 adi_spi_giveback(drv_data
);
604 iowrite32(0xFFFFFFFF, &drv_data
->regs
->status
);
605 adi_spi_cs_active(drv_data
, chip
);
606 drv_data
->state
= RUNNING_STATE
;
608 if (chip
->enable_dma
)
609 ret
= adi_spi_dma_xfer(drv_data
);
611 ret
= adi_spi_pio_xfer(drv_data
);
614 adi_spi_giveback(drv_data
);
618 static int adi_spi_transfer_one_message(struct spi_master
*master
,
619 struct spi_message
*m
)
621 struct adi_spi_master
*drv_data
= spi_master_get_devdata(master
);
623 drv_data
->cur_msg
= m
;
624 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
625 adi_spi_restore_state(drv_data
);
627 drv_data
->state
= START_STATE
;
628 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
629 struct spi_transfer
, transfer_list
);
631 tasklet_schedule(&drv_data
->pump_transfers
);
635 #define MAX_SPI_SSEL 7
637 static const u16 ssel
[][MAX_SPI_SSEL
] = {
638 {P_SPI0_SSEL1
, P_SPI0_SSEL2
, P_SPI0_SSEL3
,
639 P_SPI0_SSEL4
, P_SPI0_SSEL5
,
640 P_SPI0_SSEL6
, P_SPI0_SSEL7
},
642 {P_SPI1_SSEL1
, P_SPI1_SSEL2
, P_SPI1_SSEL3
,
643 P_SPI1_SSEL4
, P_SPI1_SSEL5
,
644 P_SPI1_SSEL6
, P_SPI1_SSEL7
},
646 {P_SPI2_SSEL1
, P_SPI2_SSEL2
, P_SPI2_SSEL3
,
647 P_SPI2_SSEL4
, P_SPI2_SSEL5
,
648 P_SPI2_SSEL6
, P_SPI2_SSEL7
},
651 static int adi_spi_setup(struct spi_device
*spi
)
653 struct adi_spi_master
*drv_data
= spi_master_get_devdata(spi
->master
);
654 struct adi_spi_device
*chip
= spi_get_ctldata(spi
);
655 u32 ctl_reg
= SPI_CTL_ODM
| SPI_CTL_PSSE
;
659 struct adi_spi3_chip
*chip_info
= spi
->controller_data
;
661 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
663 dev_err(&spi
->dev
, "can not allocate chip data\n");
667 if (chip_info
->control
& ~ctl_reg
) {
669 "do not set bits that the SPI framework manages\n");
672 chip
->control
= chip_info
->control
;
673 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
674 chip
->tx_dummy_val
= chip_info
->tx_dummy_val
;
675 chip
->enable_dma
= chip_info
->enable_dma
;
677 chip
->cs
= spi
->chip_select
;
679 if (chip
->cs
< MAX_CTRL_CS
) {
680 chip
->ssel
= (1 << chip
->cs
) << 8;
681 ret
= peripheral_request(ssel
[spi
->master
->bus_num
]
682 [chip
->cs
-1], dev_name(&spi
->dev
));
684 dev_err(&spi
->dev
, "peripheral_request() error\n");
688 chip
->cs_gpio
= chip
->cs
- MAX_CTRL_CS
;
689 ret
= gpio_request_one(chip
->cs_gpio
, GPIOF_OUT_INIT_HIGH
,
690 dev_name(&spi
->dev
));
692 dev_err(&spi
->dev
, "gpio_request_one() error\n");
696 spi_set_ctldata(spi
, chip
);
699 /* force a default base state */
700 chip
->control
&= ctl_reg
;
702 if (spi
->mode
& SPI_CPOL
)
703 chip
->control
|= SPI_CTL_CPOL
;
704 if (spi
->mode
& SPI_CPHA
)
705 chip
->control
|= SPI_CTL_CPHA
;
706 if (spi
->mode
& SPI_LSB_FIRST
)
707 chip
->control
|= SPI_CTL_LSBF
;
708 chip
->control
|= SPI_CTL_MSTR
;
709 /* we choose software to controll cs */
710 chip
->control
&= ~SPI_CTL_ASSEL
;
712 chip
->clock
= hz_to_spi_clock(drv_data
->sclk
, spi
->max_speed_hz
);
714 adi_spi_cs_enable(drv_data
, chip
);
715 adi_spi_cs_deactive(drv_data
, chip
);
721 spi_set_ctldata(spi
, NULL
);
727 static void adi_spi_cleanup(struct spi_device
*spi
)
729 struct adi_spi_device
*chip
= spi_get_ctldata(spi
);
730 struct adi_spi_master
*drv_data
= spi_master_get_devdata(spi
->master
);
735 if (chip
->cs
< MAX_CTRL_CS
) {
736 peripheral_free(ssel
[spi
->master
->bus_num
]
738 adi_spi_cs_disable(drv_data
, chip
);
740 gpio_free(chip
->cs_gpio
);
744 spi_set_ctldata(spi
, NULL
);
747 static irqreturn_t
adi_spi_tx_dma_isr(int irq
, void *dev_id
)
749 struct adi_spi_master
*drv_data
= dev_id
;
750 u32 dma_stat
= get_dma_curr_irqstat(drv_data
->tx_dma
);
753 clear_dma_irqstat(drv_data
->tx_dma
);
754 if (dma_stat
& DMA_DONE
) {
757 dev_err(&drv_data
->master
->dev
,
758 "spi tx dma error: %d\n", dma_stat
);
760 drv_data
->state
= ERROR_STATE
;
762 tx_ctl
= ioread32(&drv_data
->regs
->tx_control
);
763 tx_ctl
&= ~SPI_TXCTL_TDR_NF
;
764 iowrite32(tx_ctl
, &drv_data
->regs
->tx_control
);
768 static irqreturn_t
adi_spi_rx_dma_isr(int irq
, void *dev_id
)
770 struct adi_spi_master
*drv_data
= dev_id
;
771 struct spi_message
*msg
= drv_data
->cur_msg
;
772 u32 dma_stat
= get_dma_curr_irqstat(drv_data
->rx_dma
);
774 clear_dma_irqstat(drv_data
->rx_dma
);
775 if (dma_stat
& DMA_DONE
) {
777 /* we may fail on tx dma */
778 if (drv_data
->state
!= ERROR_STATE
)
779 msg
->actual_length
+= drv_data
->transfer_len
;
781 drv_data
->state
= ERROR_STATE
;
782 dev_err(&drv_data
->master
->dev
,
783 "spi rx dma error: %d\n", dma_stat
);
785 iowrite32(0, &drv_data
->regs
->tx_control
);
786 iowrite32(0, &drv_data
->regs
->rx_control
);
787 if (drv_data
->rx_num
!= drv_data
->tx_num
)
788 dev_dbg(&drv_data
->master
->dev
,
789 "dma interrupt missing: tx=%d,rx=%d\n",
790 drv_data
->tx_num
, drv_data
->rx_num
);
791 tasklet_schedule(&drv_data
->pump_transfers
);
795 static int adi_spi_probe(struct platform_device
*pdev
)
797 struct device
*dev
= &pdev
->dev
;
798 struct adi_spi3_master
*info
= dev_get_platdata(dev
);
799 struct spi_master
*master
;
800 struct adi_spi_master
*drv_data
;
801 struct resource
*mem
, *res
;
802 unsigned int tx_dma
, rx_dma
;
807 dev_err(dev
, "platform data missing!\n");
813 dev_err(dev
, "can not get sclk1\n");
817 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
819 dev_err(dev
, "can not get tx dma resource\n");
824 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 1);
826 dev_err(dev
, "can not get rx dma resource\n");
831 /* allocate master with space for drv_data */
832 master
= spi_alloc_master(dev
, sizeof(*drv_data
));
834 dev_err(dev
, "can not alloc spi_master\n");
837 platform_set_drvdata(pdev
, master
);
839 /* the mode bits supported by this driver */
840 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
842 master
->bus_num
= pdev
->id
;
843 master
->num_chipselect
= info
->num_chipselect
;
844 master
->cleanup
= adi_spi_cleanup
;
845 master
->setup
= adi_spi_setup
;
846 master
->transfer_one_message
= adi_spi_transfer_one_message
;
847 master
->bits_per_word_mask
= SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
850 drv_data
= spi_master_get_devdata(master
);
851 drv_data
->master
= master
;
852 drv_data
->tx_dma
= tx_dma
;
853 drv_data
->rx_dma
= rx_dma
;
854 drv_data
->pin_req
= info
->pin_req
;
855 drv_data
->sclk
= sclk
;
857 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
858 drv_data
->regs
= devm_ioremap_resource(dev
, mem
);
859 if (IS_ERR(drv_data
->regs
)) {
860 ret
= PTR_ERR(drv_data
->regs
);
864 /* request tx and rx dma */
865 ret
= request_dma(tx_dma
, "SPI_TX_DMA");
867 dev_err(dev
, "can not request SPI TX DMA channel\n");
870 set_dma_callback(tx_dma
, adi_spi_tx_dma_isr
, drv_data
);
872 ret
= request_dma(rx_dma
, "SPI_RX_DMA");
874 dev_err(dev
, "can not request SPI RX DMA channel\n");
875 goto err_free_tx_dma
;
877 set_dma_callback(drv_data
->rx_dma
, adi_spi_rx_dma_isr
, drv_data
);
879 /* request CLK, MOSI and MISO */
880 ret
= peripheral_request_list(drv_data
->pin_req
, "adi-spi3");
882 dev_err(dev
, "can not request spi pins\n");
883 goto err_free_rx_dma
;
886 iowrite32(SPI_CTL_MSTR
| SPI_CTL_CPHA
, &drv_data
->regs
->control
);
887 iowrite32(0x0000FE00, &drv_data
->regs
->ssel
);
888 iowrite32(0x0, &drv_data
->regs
->delay
);
890 tasklet_init(&drv_data
->pump_transfers
,
891 adi_spi_pump_transfers
, (unsigned long)drv_data
);
892 /* register with the SPI framework */
893 ret
= devm_spi_register_master(dev
, master
);
895 dev_err(dev
, "can not register spi master\n");
896 goto err_free_peripheral
;
902 peripheral_free_list(drv_data
->pin_req
);
908 spi_master_put(master
);
913 static int adi_spi_remove(struct platform_device
*pdev
)
915 struct spi_master
*master
= platform_get_drvdata(pdev
);
916 struct adi_spi_master
*drv_data
= spi_master_get_devdata(master
);
918 adi_spi_disable(drv_data
);
919 peripheral_free_list(drv_data
->pin_req
);
920 free_dma(drv_data
->rx_dma
);
921 free_dma(drv_data
->tx_dma
);
926 static int adi_spi_suspend(struct device
*dev
)
928 struct spi_master
*master
= dev_get_drvdata(dev
);
929 struct adi_spi_master
*drv_data
= spi_master_get_devdata(master
);
931 spi_master_suspend(master
);
933 drv_data
->control
= ioread32(&drv_data
->regs
->control
);
934 drv_data
->ssel
= ioread32(&drv_data
->regs
->ssel
);
936 iowrite32(SPI_CTL_MSTR
| SPI_CTL_CPHA
, &drv_data
->regs
->control
);
937 iowrite32(0x0000FE00, &drv_data
->regs
->ssel
);
938 dma_disable_irq(drv_data
->rx_dma
);
939 dma_disable_irq(drv_data
->tx_dma
);
944 static int adi_spi_resume(struct device
*dev
)
946 struct spi_master
*master
= dev_get_drvdata(dev
);
947 struct adi_spi_master
*drv_data
= spi_master_get_devdata(master
);
950 /* bootrom may modify spi and dma status when resume in spi boot mode */
951 disable_dma(drv_data
->rx_dma
);
953 dma_enable_irq(drv_data
->rx_dma
);
954 dma_enable_irq(drv_data
->tx_dma
);
955 iowrite32(drv_data
->control
, &drv_data
->regs
->control
);
956 iowrite32(drv_data
->ssel
, &drv_data
->regs
->ssel
);
958 ret
= spi_master_resume(master
);
960 free_dma(drv_data
->rx_dma
);
961 free_dma(drv_data
->tx_dma
);
967 static const struct dev_pm_ops adi_spi_pm_ops
= {
968 SET_SYSTEM_SLEEP_PM_OPS(adi_spi_suspend
, adi_spi_resume
)
971 MODULE_ALIAS("platform:adi-spi3");
972 static struct platform_driver adi_spi_driver
= {
975 .owner
= THIS_MODULE
,
976 .pm
= &adi_spi_pm_ops
,
978 .remove
= adi_spi_remove
,
981 module_platform_driver_probe(adi_spi_driver
, adi_spi_probe
);
983 MODULE_DESCRIPTION("Analog Devices SPI3 controller driver");
984 MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
985 MODULE_LICENSE("GPL v2");