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[ARM] pxa: correct SSCR0_SCR to support multiple SoCs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / pxa2xx_spi.c
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/spi/spi.h>
28 #include <linux/workqueue.h>
29 #include <linux/delay.h>
30 #include <linux/clk.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/delay.h>
37
38 #include <mach/dma.h>
39 #include <mach/regs-ssp.h>
40 #include <mach/ssp.h>
41 #include <mach/pxa2xx_spi.h>
42
43 MODULE_AUTHOR("Stephen Street");
44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:pxa2xx-spi");
47
48 #define MAX_BUSES 3
49
50 #define RX_THRESH_DFLT 8
51 #define TX_THRESH_DFLT 8
52 #define TIMOUT_DFLT 1000
53
54 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
55 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
56 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
57 #define MAX_DMA_LEN 8191
58 #define DMA_ALIGNMENT 8
59
60 /*
61 * for testing SSCR1 changes that require SSP restart, basically
62 * everything except the service and interrupt enables, the pxa270 developer
63 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
64 * list, but the PXA255 dev man says all bits without really meaning the
65 * service and interrupt enables
66 */
67 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
68 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
69 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
70 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
71 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
72 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
73
74 #define DEFINE_SSP_REG(reg, off) \
75 static inline u32 read_##reg(void const __iomem *p) \
76 { return __raw_readl(p + (off)); } \
77 \
78 static inline void write_##reg(u32 v, void __iomem *p) \
79 { __raw_writel(v, p + (off)); }
80
81 DEFINE_SSP_REG(SSCR0, 0x00)
82 DEFINE_SSP_REG(SSCR1, 0x04)
83 DEFINE_SSP_REG(SSSR, 0x08)
84 DEFINE_SSP_REG(SSITR, 0x0c)
85 DEFINE_SSP_REG(SSDR, 0x10)
86 DEFINE_SSP_REG(SSTO, 0x28)
87 DEFINE_SSP_REG(SSPSP, 0x2c)
88
89 #define START_STATE ((void*)0)
90 #define RUNNING_STATE ((void*)1)
91 #define DONE_STATE ((void*)2)
92 #define ERROR_STATE ((void*)-1)
93
94 #define QUEUE_RUNNING 0
95 #define QUEUE_STOPPED 1
96
97 struct driver_data {
98 /* Driver model hookup */
99 struct platform_device *pdev;
100
101 /* SSP Info */
102 struct ssp_device *ssp;
103
104 /* SPI framework hookup */
105 enum pxa_ssp_type ssp_type;
106 struct spi_master *master;
107
108 /* PXA hookup */
109 struct pxa2xx_spi_master *master_info;
110
111 /* DMA setup stuff */
112 int rx_channel;
113 int tx_channel;
114 u32 *null_dma_buf;
115
116 /* SSP register addresses */
117 void __iomem *ioaddr;
118 u32 ssdr_physical;
119
120 /* SSP masks*/
121 u32 dma_cr1;
122 u32 int_cr1;
123 u32 clear_sr;
124 u32 mask_sr;
125
126 /* Driver message queue */
127 struct workqueue_struct *workqueue;
128 struct work_struct pump_messages;
129 spinlock_t lock;
130 struct list_head queue;
131 int busy;
132 int run;
133
134 /* Message Transfer pump */
135 struct tasklet_struct pump_transfers;
136
137 /* Current message transfer state info */
138 struct spi_message* cur_msg;
139 struct spi_transfer* cur_transfer;
140 struct chip_data *cur_chip;
141 size_t len;
142 void *tx;
143 void *tx_end;
144 void *rx;
145 void *rx_end;
146 int dma_mapped;
147 dma_addr_t rx_dma;
148 dma_addr_t tx_dma;
149 size_t rx_map_len;
150 size_t tx_map_len;
151 u8 n_bytes;
152 u32 dma_width;
153 int (*write)(struct driver_data *drv_data);
154 int (*read)(struct driver_data *drv_data);
155 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
156 void (*cs_control)(u32 command);
157 };
158
159 struct chip_data {
160 u32 cr0;
161 u32 cr1;
162 u32 psp;
163 u32 timeout;
164 u8 n_bytes;
165 u32 dma_width;
166 u32 dma_burst_size;
167 u32 threshold;
168 u32 dma_threshold;
169 u8 enable_dma;
170 u8 bits_per_word;
171 u32 speed_hz;
172 int gpio_cs;
173 int gpio_cs_inverted;
174 int (*write)(struct driver_data *drv_data);
175 int (*read)(struct driver_data *drv_data);
176 void (*cs_control)(u32 command);
177 };
178
179 static void pump_messages(struct work_struct *work);
180
181 static void cs_assert(struct driver_data *drv_data)
182 {
183 struct chip_data *chip = drv_data->cur_chip;
184
185 if (chip->cs_control) {
186 chip->cs_control(PXA2XX_CS_ASSERT);
187 return;
188 }
189
190 if (gpio_is_valid(chip->gpio_cs))
191 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
192 }
193
194 static void cs_deassert(struct driver_data *drv_data)
195 {
196 struct chip_data *chip = drv_data->cur_chip;
197
198 if (chip->cs_control) {
199 chip->cs_control(PXA2XX_CS_DEASSERT);
200 return;
201 }
202
203 if (gpio_is_valid(chip->gpio_cs))
204 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
205 }
206
207 static int flush(struct driver_data *drv_data)
208 {
209 unsigned long limit = loops_per_jiffy << 1;
210
211 void __iomem *reg = drv_data->ioaddr;
212
213 do {
214 while (read_SSSR(reg) & SSSR_RNE) {
215 read_SSDR(reg);
216 }
217 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
218 write_SSSR(SSSR_ROR, reg);
219
220 return limit;
221 }
222
223 static int null_writer(struct driver_data *drv_data)
224 {
225 void __iomem *reg = drv_data->ioaddr;
226 u8 n_bytes = drv_data->n_bytes;
227
228 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
229 || (drv_data->tx == drv_data->tx_end))
230 return 0;
231
232 write_SSDR(0, reg);
233 drv_data->tx += n_bytes;
234
235 return 1;
236 }
237
238 static int null_reader(struct driver_data *drv_data)
239 {
240 void __iomem *reg = drv_data->ioaddr;
241 u8 n_bytes = drv_data->n_bytes;
242
243 while ((read_SSSR(reg) & SSSR_RNE)
244 && (drv_data->rx < drv_data->rx_end)) {
245 read_SSDR(reg);
246 drv_data->rx += n_bytes;
247 }
248
249 return drv_data->rx == drv_data->rx_end;
250 }
251
252 static int u8_writer(struct driver_data *drv_data)
253 {
254 void __iomem *reg = drv_data->ioaddr;
255
256 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
257 || (drv_data->tx == drv_data->tx_end))
258 return 0;
259
260 write_SSDR(*(u8 *)(drv_data->tx), reg);
261 ++drv_data->tx;
262
263 return 1;
264 }
265
266 static int u8_reader(struct driver_data *drv_data)
267 {
268 void __iomem *reg = drv_data->ioaddr;
269
270 while ((read_SSSR(reg) & SSSR_RNE)
271 && (drv_data->rx < drv_data->rx_end)) {
272 *(u8 *)(drv_data->rx) = read_SSDR(reg);
273 ++drv_data->rx;
274 }
275
276 return drv_data->rx == drv_data->rx_end;
277 }
278
279 static int u16_writer(struct driver_data *drv_data)
280 {
281 void __iomem *reg = drv_data->ioaddr;
282
283 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
284 || (drv_data->tx == drv_data->tx_end))
285 return 0;
286
287 write_SSDR(*(u16 *)(drv_data->tx), reg);
288 drv_data->tx += 2;
289
290 return 1;
291 }
292
293 static int u16_reader(struct driver_data *drv_data)
294 {
295 void __iomem *reg = drv_data->ioaddr;
296
297 while ((read_SSSR(reg) & SSSR_RNE)
298 && (drv_data->rx < drv_data->rx_end)) {
299 *(u16 *)(drv_data->rx) = read_SSDR(reg);
300 drv_data->rx += 2;
301 }
302
303 return drv_data->rx == drv_data->rx_end;
304 }
305
306 static int u32_writer(struct driver_data *drv_data)
307 {
308 void __iomem *reg = drv_data->ioaddr;
309
310 if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
311 || (drv_data->tx == drv_data->tx_end))
312 return 0;
313
314 write_SSDR(*(u32 *)(drv_data->tx), reg);
315 drv_data->tx += 4;
316
317 return 1;
318 }
319
320 static int u32_reader(struct driver_data *drv_data)
321 {
322 void __iomem *reg = drv_data->ioaddr;
323
324 while ((read_SSSR(reg) & SSSR_RNE)
325 && (drv_data->rx < drv_data->rx_end)) {
326 *(u32 *)(drv_data->rx) = read_SSDR(reg);
327 drv_data->rx += 4;
328 }
329
330 return drv_data->rx == drv_data->rx_end;
331 }
332
333 static void *next_transfer(struct driver_data *drv_data)
334 {
335 struct spi_message *msg = drv_data->cur_msg;
336 struct spi_transfer *trans = drv_data->cur_transfer;
337
338 /* Move to next transfer */
339 if (trans->transfer_list.next != &msg->transfers) {
340 drv_data->cur_transfer =
341 list_entry(trans->transfer_list.next,
342 struct spi_transfer,
343 transfer_list);
344 return RUNNING_STATE;
345 } else
346 return DONE_STATE;
347 }
348
349 static int map_dma_buffers(struct driver_data *drv_data)
350 {
351 struct spi_message *msg = drv_data->cur_msg;
352 struct device *dev = &msg->spi->dev;
353
354 if (!drv_data->cur_chip->enable_dma)
355 return 0;
356
357 if (msg->is_dma_mapped)
358 return drv_data->rx_dma && drv_data->tx_dma;
359
360 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
361 return 0;
362
363 /* Modify setup if rx buffer is null */
364 if (drv_data->rx == NULL) {
365 *drv_data->null_dma_buf = 0;
366 drv_data->rx = drv_data->null_dma_buf;
367 drv_data->rx_map_len = 4;
368 } else
369 drv_data->rx_map_len = drv_data->len;
370
371
372 /* Modify setup if tx buffer is null */
373 if (drv_data->tx == NULL) {
374 *drv_data->null_dma_buf = 0;
375 drv_data->tx = drv_data->null_dma_buf;
376 drv_data->tx_map_len = 4;
377 } else
378 drv_data->tx_map_len = drv_data->len;
379
380 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
381 * so we flush the cache *before* invalidating it, in case
382 * the tx and rx buffers overlap.
383 */
384 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
385 drv_data->tx_map_len, DMA_TO_DEVICE);
386 if (dma_mapping_error(dev, drv_data->tx_dma))
387 return 0;
388
389 /* Stream map the rx buffer */
390 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
391 drv_data->rx_map_len, DMA_FROM_DEVICE);
392 if (dma_mapping_error(dev, drv_data->rx_dma)) {
393 dma_unmap_single(dev, drv_data->tx_dma,
394 drv_data->tx_map_len, DMA_TO_DEVICE);
395 return 0;
396 }
397
398 return 1;
399 }
400
401 static void unmap_dma_buffers(struct driver_data *drv_data)
402 {
403 struct device *dev;
404
405 if (!drv_data->dma_mapped)
406 return;
407
408 if (!drv_data->cur_msg->is_dma_mapped) {
409 dev = &drv_data->cur_msg->spi->dev;
410 dma_unmap_single(dev, drv_data->rx_dma,
411 drv_data->rx_map_len, DMA_FROM_DEVICE);
412 dma_unmap_single(dev, drv_data->tx_dma,
413 drv_data->tx_map_len, DMA_TO_DEVICE);
414 }
415
416 drv_data->dma_mapped = 0;
417 }
418
419 /* caller already set message->status; dma and pio irqs are blocked */
420 static void giveback(struct driver_data *drv_data)
421 {
422 struct spi_transfer* last_transfer;
423 unsigned long flags;
424 struct spi_message *msg;
425
426 spin_lock_irqsave(&drv_data->lock, flags);
427 msg = drv_data->cur_msg;
428 drv_data->cur_msg = NULL;
429 drv_data->cur_transfer = NULL;
430 queue_work(drv_data->workqueue, &drv_data->pump_messages);
431 spin_unlock_irqrestore(&drv_data->lock, flags);
432
433 last_transfer = list_entry(msg->transfers.prev,
434 struct spi_transfer,
435 transfer_list);
436
437 /* Delay if requested before any change in chip select */
438 if (last_transfer->delay_usecs)
439 udelay(last_transfer->delay_usecs);
440
441 /* Drop chip select UNLESS cs_change is true or we are returning
442 * a message with an error, or next message is for another chip
443 */
444 if (!last_transfer->cs_change)
445 cs_deassert(drv_data);
446 else {
447 struct spi_message *next_msg;
448
449 /* Holding of cs was hinted, but we need to make sure
450 * the next message is for the same chip. Don't waste
451 * time with the following tests unless this was hinted.
452 *
453 * We cannot postpone this until pump_messages, because
454 * after calling msg->complete (below) the driver that
455 * sent the current message could be unloaded, which
456 * could invalidate the cs_control() callback...
457 */
458
459 /* get a pointer to the next message, if any */
460 spin_lock_irqsave(&drv_data->lock, flags);
461 if (list_empty(&drv_data->queue))
462 next_msg = NULL;
463 else
464 next_msg = list_entry(drv_data->queue.next,
465 struct spi_message, queue);
466 spin_unlock_irqrestore(&drv_data->lock, flags);
467
468 /* see if the next and current messages point
469 * to the same chip
470 */
471 if (next_msg && next_msg->spi != msg->spi)
472 next_msg = NULL;
473 if (!next_msg || msg->state == ERROR_STATE)
474 cs_deassert(drv_data);
475 }
476
477 msg->state = NULL;
478 if (msg->complete)
479 msg->complete(msg->context);
480
481 drv_data->cur_chip = NULL;
482 }
483
484 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
485 {
486 unsigned long limit = loops_per_jiffy << 1;
487
488 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
489 cpu_relax();
490
491 return limit;
492 }
493
494 static int wait_dma_channel_stop(int channel)
495 {
496 unsigned long limit = loops_per_jiffy << 1;
497
498 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
499 cpu_relax();
500
501 return limit;
502 }
503
504 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
505 {
506 void __iomem *reg = drv_data->ioaddr;
507
508 /* Stop and reset */
509 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
510 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
511 write_SSSR(drv_data->clear_sr, reg);
512 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
513 if (drv_data->ssp_type != PXA25x_SSP)
514 write_SSTO(0, reg);
515 flush(drv_data);
516 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
517
518 unmap_dma_buffers(drv_data);
519
520 dev_err(&drv_data->pdev->dev, "%s\n", msg);
521
522 drv_data->cur_msg->state = ERROR_STATE;
523 tasklet_schedule(&drv_data->pump_transfers);
524 }
525
526 static void dma_transfer_complete(struct driver_data *drv_data)
527 {
528 void __iomem *reg = drv_data->ioaddr;
529 struct spi_message *msg = drv_data->cur_msg;
530
531 /* Clear and disable interrupts on SSP and DMA channels*/
532 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
533 write_SSSR(drv_data->clear_sr, reg);
534 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
535 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
536
537 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
538 dev_err(&drv_data->pdev->dev,
539 "dma_handler: dma rx channel stop failed\n");
540
541 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
542 dev_err(&drv_data->pdev->dev,
543 "dma_transfer: ssp rx stall failed\n");
544
545 unmap_dma_buffers(drv_data);
546
547 /* update the buffer pointer for the amount completed in dma */
548 drv_data->rx += drv_data->len -
549 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
550
551 /* read trailing data from fifo, it does not matter how many
552 * bytes are in the fifo just read until buffer is full
553 * or fifo is empty, which ever occurs first */
554 drv_data->read(drv_data);
555
556 /* return count of what was actually read */
557 msg->actual_length += drv_data->len -
558 (drv_data->rx_end - drv_data->rx);
559
560 /* Transfer delays and chip select release are
561 * handled in pump_transfers or giveback
562 */
563
564 /* Move to next transfer */
565 msg->state = next_transfer(drv_data);
566
567 /* Schedule transfer tasklet */
568 tasklet_schedule(&drv_data->pump_transfers);
569 }
570
571 static void dma_handler(int channel, void *data)
572 {
573 struct driver_data *drv_data = data;
574 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
575
576 if (irq_status & DCSR_BUSERR) {
577
578 if (channel == drv_data->tx_channel)
579 dma_error_stop(drv_data,
580 "dma_handler: "
581 "bad bus address on tx channel");
582 else
583 dma_error_stop(drv_data,
584 "dma_handler: "
585 "bad bus address on rx channel");
586 return;
587 }
588
589 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
590 if ((channel == drv_data->tx_channel)
591 && (irq_status & DCSR_ENDINTR)
592 && (drv_data->ssp_type == PXA25x_SSP)) {
593
594 /* Wait for rx to stall */
595 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
596 dev_err(&drv_data->pdev->dev,
597 "dma_handler: ssp rx stall failed\n");
598
599 /* finish this transfer, start the next */
600 dma_transfer_complete(drv_data);
601 }
602 }
603
604 static irqreturn_t dma_transfer(struct driver_data *drv_data)
605 {
606 u32 irq_status;
607 void __iomem *reg = drv_data->ioaddr;
608
609 irq_status = read_SSSR(reg) & drv_data->mask_sr;
610 if (irq_status & SSSR_ROR) {
611 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
612 return IRQ_HANDLED;
613 }
614
615 /* Check for false positive timeout */
616 if ((irq_status & SSSR_TINT)
617 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
618 write_SSSR(SSSR_TINT, reg);
619 return IRQ_HANDLED;
620 }
621
622 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
623
624 /* Clear and disable timeout interrupt, do the rest in
625 * dma_transfer_complete */
626 if (drv_data->ssp_type != PXA25x_SSP)
627 write_SSTO(0, reg);
628
629 /* finish this transfer, start the next */
630 dma_transfer_complete(drv_data);
631
632 return IRQ_HANDLED;
633 }
634
635 /* Opps problem detected */
636 return IRQ_NONE;
637 }
638
639 static void int_error_stop(struct driver_data *drv_data, const char* msg)
640 {
641 void __iomem *reg = drv_data->ioaddr;
642
643 /* Stop and reset SSP */
644 write_SSSR(drv_data->clear_sr, reg);
645 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
646 if (drv_data->ssp_type != PXA25x_SSP)
647 write_SSTO(0, reg);
648 flush(drv_data);
649 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
650
651 dev_err(&drv_data->pdev->dev, "%s\n", msg);
652
653 drv_data->cur_msg->state = ERROR_STATE;
654 tasklet_schedule(&drv_data->pump_transfers);
655 }
656
657 static void int_transfer_complete(struct driver_data *drv_data)
658 {
659 void __iomem *reg = drv_data->ioaddr;
660
661 /* Stop SSP */
662 write_SSSR(drv_data->clear_sr, reg);
663 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
664 if (drv_data->ssp_type != PXA25x_SSP)
665 write_SSTO(0, reg);
666
667 /* Update total byte transfered return count actual bytes read */
668 drv_data->cur_msg->actual_length += drv_data->len -
669 (drv_data->rx_end - drv_data->rx);
670
671 /* Transfer delays and chip select release are
672 * handled in pump_transfers or giveback
673 */
674
675 /* Move to next transfer */
676 drv_data->cur_msg->state = next_transfer(drv_data);
677
678 /* Schedule transfer tasklet */
679 tasklet_schedule(&drv_data->pump_transfers);
680 }
681
682 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
683 {
684 void __iomem *reg = drv_data->ioaddr;
685
686 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
687 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
688
689 u32 irq_status = read_SSSR(reg) & irq_mask;
690
691 if (irq_status & SSSR_ROR) {
692 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
693 return IRQ_HANDLED;
694 }
695
696 if (irq_status & SSSR_TINT) {
697 write_SSSR(SSSR_TINT, reg);
698 if (drv_data->read(drv_data)) {
699 int_transfer_complete(drv_data);
700 return IRQ_HANDLED;
701 }
702 }
703
704 /* Drain rx fifo, Fill tx fifo and prevent overruns */
705 do {
706 if (drv_data->read(drv_data)) {
707 int_transfer_complete(drv_data);
708 return IRQ_HANDLED;
709 }
710 } while (drv_data->write(drv_data));
711
712 if (drv_data->read(drv_data)) {
713 int_transfer_complete(drv_data);
714 return IRQ_HANDLED;
715 }
716
717 if (drv_data->tx == drv_data->tx_end) {
718 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
719 /* PXA25x_SSP has no timeout, read trailing bytes */
720 if (drv_data->ssp_type == PXA25x_SSP) {
721 if (!wait_ssp_rx_stall(reg))
722 {
723 int_error_stop(drv_data, "interrupt_transfer: "
724 "rx stall failed");
725 return IRQ_HANDLED;
726 }
727 if (!drv_data->read(drv_data))
728 {
729 int_error_stop(drv_data,
730 "interrupt_transfer: "
731 "trailing byte read failed");
732 return IRQ_HANDLED;
733 }
734 int_transfer_complete(drv_data);
735 }
736 }
737
738 /* We did something */
739 return IRQ_HANDLED;
740 }
741
742 static irqreturn_t ssp_int(int irq, void *dev_id)
743 {
744 struct driver_data *drv_data = dev_id;
745 void __iomem *reg = drv_data->ioaddr;
746
747 if (!drv_data->cur_msg) {
748
749 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
750 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
751 if (drv_data->ssp_type != PXA25x_SSP)
752 write_SSTO(0, reg);
753 write_SSSR(drv_data->clear_sr, reg);
754
755 dev_err(&drv_data->pdev->dev, "bad message state "
756 "in interrupt handler\n");
757
758 /* Never fail */
759 return IRQ_HANDLED;
760 }
761
762 return drv_data->transfer_handler(drv_data);
763 }
764
765 static int set_dma_burst_and_threshold(struct chip_data *chip,
766 struct spi_device *spi,
767 u8 bits_per_word, u32 *burst_code,
768 u32 *threshold)
769 {
770 struct pxa2xx_spi_chip *chip_info =
771 (struct pxa2xx_spi_chip *)spi->controller_data;
772 int bytes_per_word;
773 int burst_bytes;
774 int thresh_words;
775 int req_burst_size;
776 int retval = 0;
777
778 /* Set the threshold (in registers) to equal the same amount of data
779 * as represented by burst size (in bytes). The computation below
780 * is (burst_size rounded up to nearest 8 byte, word or long word)
781 * divided by (bytes/register); the tx threshold is the inverse of
782 * the rx, so that there will always be enough data in the rx fifo
783 * to satisfy a burst, and there will always be enough space in the
784 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
785 * there is not enough space), there must always remain enough empty
786 * space in the rx fifo for any data loaded to the tx fifo.
787 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
788 * will be 8, or half the fifo;
789 * The threshold can only be set to 2, 4 or 8, but not 16, because
790 * to burst 16 to the tx fifo, the fifo would have to be empty;
791 * however, the minimum fifo trigger level is 1, and the tx will
792 * request service when the fifo is at this level, with only 15 spaces.
793 */
794
795 /* find bytes/word */
796 if (bits_per_word <= 8)
797 bytes_per_word = 1;
798 else if (bits_per_word <= 16)
799 bytes_per_word = 2;
800 else
801 bytes_per_word = 4;
802
803 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
804 if (chip_info)
805 req_burst_size = chip_info->dma_burst_size;
806 else {
807 switch (chip->dma_burst_size) {
808 default:
809 /* if the default burst size is not set,
810 * do it now */
811 chip->dma_burst_size = DCMD_BURST8;
812 case DCMD_BURST8:
813 req_burst_size = 8;
814 break;
815 case DCMD_BURST16:
816 req_burst_size = 16;
817 break;
818 case DCMD_BURST32:
819 req_burst_size = 32;
820 break;
821 }
822 }
823 if (req_burst_size <= 8) {
824 *burst_code = DCMD_BURST8;
825 burst_bytes = 8;
826 } else if (req_burst_size <= 16) {
827 if (bytes_per_word == 1) {
828 /* don't burst more than 1/2 the fifo */
829 *burst_code = DCMD_BURST8;
830 burst_bytes = 8;
831 retval = 1;
832 } else {
833 *burst_code = DCMD_BURST16;
834 burst_bytes = 16;
835 }
836 } else {
837 if (bytes_per_word == 1) {
838 /* don't burst more than 1/2 the fifo */
839 *burst_code = DCMD_BURST8;
840 burst_bytes = 8;
841 retval = 1;
842 } else if (bytes_per_word == 2) {
843 /* don't burst more than 1/2 the fifo */
844 *burst_code = DCMD_BURST16;
845 burst_bytes = 16;
846 retval = 1;
847 } else {
848 *burst_code = DCMD_BURST32;
849 burst_bytes = 32;
850 }
851 }
852
853 thresh_words = burst_bytes / bytes_per_word;
854
855 /* thresh_words will be between 2 and 8 */
856 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
857 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
858
859 return retval;
860 }
861
862 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
863 {
864 unsigned long ssp_clk = clk_get_rate(ssp->clk);
865
866 if (ssp->type == PXA25x_SSP)
867 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
868 else
869 return ((ssp_clk / rate - 1) & 0xfff) << 8;
870 }
871
872 static void pump_transfers(unsigned long data)
873 {
874 struct driver_data *drv_data = (struct driver_data *)data;
875 struct spi_message *message = NULL;
876 struct spi_transfer *transfer = NULL;
877 struct spi_transfer *previous = NULL;
878 struct chip_data *chip = NULL;
879 struct ssp_device *ssp = drv_data->ssp;
880 void __iomem *reg = drv_data->ioaddr;
881 u32 clk_div = 0;
882 u8 bits = 0;
883 u32 speed = 0;
884 u32 cr0;
885 u32 cr1;
886 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
887 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
888
889 /* Get current state information */
890 message = drv_data->cur_msg;
891 transfer = drv_data->cur_transfer;
892 chip = drv_data->cur_chip;
893
894 /* Handle for abort */
895 if (message->state == ERROR_STATE) {
896 message->status = -EIO;
897 giveback(drv_data);
898 return;
899 }
900
901 /* Handle end of message */
902 if (message->state == DONE_STATE) {
903 message->status = 0;
904 giveback(drv_data);
905 return;
906 }
907
908 /* Delay if requested at end of transfer before CS change */
909 if (message->state == RUNNING_STATE) {
910 previous = list_entry(transfer->transfer_list.prev,
911 struct spi_transfer,
912 transfer_list);
913 if (previous->delay_usecs)
914 udelay(previous->delay_usecs);
915
916 /* Drop chip select only if cs_change is requested */
917 if (previous->cs_change)
918 cs_deassert(drv_data);
919 }
920
921 /* Check for transfers that need multiple DMA segments */
922 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
923
924 /* reject already-mapped transfers; PIO won't always work */
925 if (message->is_dma_mapped
926 || transfer->rx_dma || transfer->tx_dma) {
927 dev_err(&drv_data->pdev->dev,
928 "pump_transfers: mapped transfer length "
929 "of %u is greater than %d\n",
930 transfer->len, MAX_DMA_LEN);
931 message->status = -EINVAL;
932 giveback(drv_data);
933 return;
934 }
935
936 /* warn ... we force this to PIO mode */
937 if (printk_ratelimit())
938 dev_warn(&message->spi->dev, "pump_transfers: "
939 "DMA disabled for transfer length %ld "
940 "greater than %d\n",
941 (long)drv_data->len, MAX_DMA_LEN);
942 }
943
944 /* Setup the transfer state based on the type of transfer */
945 if (flush(drv_data) == 0) {
946 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
947 message->status = -EIO;
948 giveback(drv_data);
949 return;
950 }
951 drv_data->n_bytes = chip->n_bytes;
952 drv_data->dma_width = chip->dma_width;
953 drv_data->tx = (void *)transfer->tx_buf;
954 drv_data->tx_end = drv_data->tx + transfer->len;
955 drv_data->rx = transfer->rx_buf;
956 drv_data->rx_end = drv_data->rx + transfer->len;
957 drv_data->rx_dma = transfer->rx_dma;
958 drv_data->tx_dma = transfer->tx_dma;
959 drv_data->len = transfer->len & DCMD_LENGTH;
960 drv_data->write = drv_data->tx ? chip->write : null_writer;
961 drv_data->read = drv_data->rx ? chip->read : null_reader;
962
963 /* Change speed and bit per word on a per transfer */
964 cr0 = chip->cr0;
965 if (transfer->speed_hz || transfer->bits_per_word) {
966
967 bits = chip->bits_per_word;
968 speed = chip->speed_hz;
969
970 if (transfer->speed_hz)
971 speed = transfer->speed_hz;
972
973 if (transfer->bits_per_word)
974 bits = transfer->bits_per_word;
975
976 clk_div = ssp_get_clk_div(ssp, speed);
977
978 if (bits <= 8) {
979 drv_data->n_bytes = 1;
980 drv_data->dma_width = DCMD_WIDTH1;
981 drv_data->read = drv_data->read != null_reader ?
982 u8_reader : null_reader;
983 drv_data->write = drv_data->write != null_writer ?
984 u8_writer : null_writer;
985 } else if (bits <= 16) {
986 drv_data->n_bytes = 2;
987 drv_data->dma_width = DCMD_WIDTH2;
988 drv_data->read = drv_data->read != null_reader ?
989 u16_reader : null_reader;
990 drv_data->write = drv_data->write != null_writer ?
991 u16_writer : null_writer;
992 } else if (bits <= 32) {
993 drv_data->n_bytes = 4;
994 drv_data->dma_width = DCMD_WIDTH4;
995 drv_data->read = drv_data->read != null_reader ?
996 u32_reader : null_reader;
997 drv_data->write = drv_data->write != null_writer ?
998 u32_writer : null_writer;
999 }
1000 /* if bits/word is changed in dma mode, then must check the
1001 * thresholds and burst also */
1002 if (chip->enable_dma) {
1003 if (set_dma_burst_and_threshold(chip, message->spi,
1004 bits, &dma_burst,
1005 &dma_thresh))
1006 if (printk_ratelimit())
1007 dev_warn(&message->spi->dev,
1008 "pump_transfers: "
1009 "DMA burst size reduced to "
1010 "match bits_per_word\n");
1011 }
1012
1013 cr0 = clk_div
1014 | SSCR0_Motorola
1015 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1016 | SSCR0_SSE
1017 | (bits > 16 ? SSCR0_EDSS : 0);
1018 }
1019
1020 message->state = RUNNING_STATE;
1021
1022 /* Try to map dma buffer and do a dma transfer if successful, but
1023 * only if the length is non-zero and less than MAX_DMA_LEN.
1024 *
1025 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1026 * of PIO instead. Care is needed above because the transfer may
1027 * have have been passed with buffers that are already dma mapped.
1028 * A zero-length transfer in PIO mode will not try to write/read
1029 * to/from the buffers
1030 *
1031 * REVISIT large transfers are exactly where we most want to be
1032 * using DMA. If this happens much, split those transfers into
1033 * multiple DMA segments rather than forcing PIO.
1034 */
1035 drv_data->dma_mapped = 0;
1036 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1037 drv_data->dma_mapped = map_dma_buffers(drv_data);
1038 if (drv_data->dma_mapped) {
1039
1040 /* Ensure we have the correct interrupt handler */
1041 drv_data->transfer_handler = dma_transfer;
1042
1043 /* Setup rx DMA Channel */
1044 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1045 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1046 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1047 if (drv_data->rx == drv_data->null_dma_buf)
1048 /* No target address increment */
1049 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1050 | drv_data->dma_width
1051 | dma_burst
1052 | drv_data->len;
1053 else
1054 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1055 | DCMD_FLOWSRC
1056 | drv_data->dma_width
1057 | dma_burst
1058 | drv_data->len;
1059
1060 /* Setup tx DMA Channel */
1061 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1062 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1063 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1064 if (drv_data->tx == drv_data->null_dma_buf)
1065 /* No source address increment */
1066 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1067 | drv_data->dma_width
1068 | dma_burst
1069 | drv_data->len;
1070 else
1071 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1072 | DCMD_FLOWTRG
1073 | drv_data->dma_width
1074 | dma_burst
1075 | drv_data->len;
1076
1077 /* Enable dma end irqs on SSP to detect end of transfer */
1078 if (drv_data->ssp_type == PXA25x_SSP)
1079 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1080
1081 /* Clear status and start DMA engine */
1082 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1083 write_SSSR(drv_data->clear_sr, reg);
1084 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1085 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1086 } else {
1087 /* Ensure we have the correct interrupt handler */
1088 drv_data->transfer_handler = interrupt_transfer;
1089
1090 /* Clear status */
1091 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1092 write_SSSR(drv_data->clear_sr, reg);
1093 }
1094
1095 /* see if we need to reload the config registers */
1096 if ((read_SSCR0(reg) != cr0)
1097 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1098 (cr1 & SSCR1_CHANGE_MASK)) {
1099
1100 /* stop the SSP, and update the other bits */
1101 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1102 if (drv_data->ssp_type != PXA25x_SSP)
1103 write_SSTO(chip->timeout, reg);
1104 /* first set CR1 without interrupt and service enables */
1105 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1106 /* restart the SSP */
1107 write_SSCR0(cr0, reg);
1108
1109 } else {
1110 if (drv_data->ssp_type != PXA25x_SSP)
1111 write_SSTO(chip->timeout, reg);
1112 }
1113
1114 cs_assert(drv_data);
1115
1116 /* after chip select, release the data by enabling service
1117 * requests and interrupts, without changing any mode bits */
1118 write_SSCR1(cr1, reg);
1119 }
1120
1121 static void pump_messages(struct work_struct *work)
1122 {
1123 struct driver_data *drv_data =
1124 container_of(work, struct driver_data, pump_messages);
1125 unsigned long flags;
1126
1127 /* Lock queue and check for queue work */
1128 spin_lock_irqsave(&drv_data->lock, flags);
1129 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1130 drv_data->busy = 0;
1131 spin_unlock_irqrestore(&drv_data->lock, flags);
1132 return;
1133 }
1134
1135 /* Make sure we are not already running a message */
1136 if (drv_data->cur_msg) {
1137 spin_unlock_irqrestore(&drv_data->lock, flags);
1138 return;
1139 }
1140
1141 /* Extract head of queue */
1142 drv_data->cur_msg = list_entry(drv_data->queue.next,
1143 struct spi_message, queue);
1144 list_del_init(&drv_data->cur_msg->queue);
1145
1146 /* Initial message state*/
1147 drv_data->cur_msg->state = START_STATE;
1148 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1149 struct spi_transfer,
1150 transfer_list);
1151
1152 /* prepare to setup the SSP, in pump_transfers, using the per
1153 * chip configuration */
1154 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1155
1156 /* Mark as busy and launch transfers */
1157 tasklet_schedule(&drv_data->pump_transfers);
1158
1159 drv_data->busy = 1;
1160 spin_unlock_irqrestore(&drv_data->lock, flags);
1161 }
1162
1163 static int transfer(struct spi_device *spi, struct spi_message *msg)
1164 {
1165 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1166 unsigned long flags;
1167
1168 spin_lock_irqsave(&drv_data->lock, flags);
1169
1170 if (drv_data->run == QUEUE_STOPPED) {
1171 spin_unlock_irqrestore(&drv_data->lock, flags);
1172 return -ESHUTDOWN;
1173 }
1174
1175 msg->actual_length = 0;
1176 msg->status = -EINPROGRESS;
1177 msg->state = START_STATE;
1178
1179 list_add_tail(&msg->queue, &drv_data->queue);
1180
1181 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1182 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1183
1184 spin_unlock_irqrestore(&drv_data->lock, flags);
1185
1186 return 0;
1187 }
1188
1189 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1190 struct pxa2xx_spi_chip *chip_info)
1191 {
1192 int err = 0;
1193
1194 if (chip == NULL || chip_info == NULL)
1195 return 0;
1196
1197 /* NOTE: setup() can be called multiple times, possibly with
1198 * different chip_info, release previously requested GPIO
1199 */
1200 if (gpio_is_valid(chip->gpio_cs))
1201 gpio_free(chip->gpio_cs);
1202
1203 /* If (*cs_control) is provided, ignore GPIO chip select */
1204 if (chip_info->cs_control) {
1205 chip->cs_control = chip_info->cs_control;
1206 return 0;
1207 }
1208
1209 if (gpio_is_valid(chip_info->gpio_cs)) {
1210 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1211 if (err) {
1212 dev_err(&spi->dev, "failed to request chip select "
1213 "GPIO%d\n", chip_info->gpio_cs);
1214 return err;
1215 }
1216
1217 chip->gpio_cs = chip_info->gpio_cs;
1218 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1219
1220 err = gpio_direction_output(chip->gpio_cs,
1221 !chip->gpio_cs_inverted);
1222 }
1223
1224 return err;
1225 }
1226
1227 static int setup(struct spi_device *spi)
1228 {
1229 struct pxa2xx_spi_chip *chip_info = NULL;
1230 struct chip_data *chip;
1231 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1232 struct ssp_device *ssp = drv_data->ssp;
1233 unsigned int clk_div;
1234 uint tx_thres = TX_THRESH_DFLT;
1235 uint rx_thres = RX_THRESH_DFLT;
1236
1237 if (drv_data->ssp_type != PXA25x_SSP
1238 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1239 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1240 "b/w not 4-32 for type non-PXA25x_SSP\n",
1241 drv_data->ssp_type, spi->bits_per_word);
1242 return -EINVAL;
1243 }
1244 else if (drv_data->ssp_type == PXA25x_SSP
1245 && (spi->bits_per_word < 4
1246 || spi->bits_per_word > 16)) {
1247 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1248 "b/w not 4-16 for type PXA25x_SSP\n",
1249 drv_data->ssp_type, spi->bits_per_word);
1250 return -EINVAL;
1251 }
1252
1253 /* Only alloc on first setup */
1254 chip = spi_get_ctldata(spi);
1255 if (!chip) {
1256 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1257 if (!chip) {
1258 dev_err(&spi->dev,
1259 "failed setup: can't allocate chip data\n");
1260 return -ENOMEM;
1261 }
1262
1263 chip->gpio_cs = -1;
1264 chip->enable_dma = 0;
1265 chip->timeout = TIMOUT_DFLT;
1266 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1267 DCMD_BURST8 : 0;
1268 }
1269
1270 /* protocol drivers may change the chip settings, so...
1271 * if chip_info exists, use it */
1272 chip_info = spi->controller_data;
1273
1274 /* chip_info isn't always needed */
1275 chip->cr1 = 0;
1276 if (chip_info) {
1277 if (chip_info->timeout)
1278 chip->timeout = chip_info->timeout;
1279 if (chip_info->tx_threshold)
1280 tx_thres = chip_info->tx_threshold;
1281 if (chip_info->rx_threshold)
1282 rx_thres = chip_info->rx_threshold;
1283 chip->enable_dma = drv_data->master_info->enable_dma;
1284 chip->dma_threshold = 0;
1285 if (chip_info->enable_loopback)
1286 chip->cr1 = SSCR1_LBM;
1287 }
1288
1289 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1290 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1291
1292 /* set dma burst and threshold outside of chip_info path so that if
1293 * chip_info goes away after setting chip->enable_dma, the
1294 * burst and threshold can still respond to changes in bits_per_word */
1295 if (chip->enable_dma) {
1296 /* set up legal burst and threshold for dma */
1297 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1298 &chip->dma_burst_size,
1299 &chip->dma_threshold)) {
1300 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1301 "to match bits_per_word\n");
1302 }
1303 }
1304
1305 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1306 chip->speed_hz = spi->max_speed_hz;
1307
1308 chip->cr0 = clk_div
1309 | SSCR0_Motorola
1310 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1311 spi->bits_per_word - 16 : spi->bits_per_word)
1312 | SSCR0_SSE
1313 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1314 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1315 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1316 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1317
1318 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1319 if (drv_data->ssp_type != PXA25x_SSP)
1320 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1321 clk_get_rate(ssp->clk)
1322 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1323 chip->enable_dma ? "DMA" : "PIO");
1324 else
1325 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1326 clk_get_rate(ssp->clk) / 2
1327 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1328 chip->enable_dma ? "DMA" : "PIO");
1329
1330 if (spi->bits_per_word <= 8) {
1331 chip->n_bytes = 1;
1332 chip->dma_width = DCMD_WIDTH1;
1333 chip->read = u8_reader;
1334 chip->write = u8_writer;
1335 } else if (spi->bits_per_word <= 16) {
1336 chip->n_bytes = 2;
1337 chip->dma_width = DCMD_WIDTH2;
1338 chip->read = u16_reader;
1339 chip->write = u16_writer;
1340 } else if (spi->bits_per_word <= 32) {
1341 chip->cr0 |= SSCR0_EDSS;
1342 chip->n_bytes = 4;
1343 chip->dma_width = DCMD_WIDTH4;
1344 chip->read = u32_reader;
1345 chip->write = u32_writer;
1346 } else {
1347 dev_err(&spi->dev, "invalid wordsize\n");
1348 return -ENODEV;
1349 }
1350 chip->bits_per_word = spi->bits_per_word;
1351
1352 spi_set_ctldata(spi, chip);
1353
1354 return setup_cs(spi, chip, chip_info);
1355 }
1356
1357 static void cleanup(struct spi_device *spi)
1358 {
1359 struct chip_data *chip = spi_get_ctldata(spi);
1360
1361 if (!chip)
1362 return;
1363
1364 if (gpio_is_valid(chip->gpio_cs))
1365 gpio_free(chip->gpio_cs);
1366
1367 kfree(chip);
1368 }
1369
1370 static int __init init_queue(struct driver_data *drv_data)
1371 {
1372 INIT_LIST_HEAD(&drv_data->queue);
1373 spin_lock_init(&drv_data->lock);
1374
1375 drv_data->run = QUEUE_STOPPED;
1376 drv_data->busy = 0;
1377
1378 tasklet_init(&drv_data->pump_transfers,
1379 pump_transfers, (unsigned long)drv_data);
1380
1381 INIT_WORK(&drv_data->pump_messages, pump_messages);
1382 drv_data->workqueue = create_singlethread_workqueue(
1383 dev_name(drv_data->master->dev.parent));
1384 if (drv_data->workqueue == NULL)
1385 return -EBUSY;
1386
1387 return 0;
1388 }
1389
1390 static int start_queue(struct driver_data *drv_data)
1391 {
1392 unsigned long flags;
1393
1394 spin_lock_irqsave(&drv_data->lock, flags);
1395
1396 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1397 spin_unlock_irqrestore(&drv_data->lock, flags);
1398 return -EBUSY;
1399 }
1400
1401 drv_data->run = QUEUE_RUNNING;
1402 drv_data->cur_msg = NULL;
1403 drv_data->cur_transfer = NULL;
1404 drv_data->cur_chip = NULL;
1405 spin_unlock_irqrestore(&drv_data->lock, flags);
1406
1407 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1408
1409 return 0;
1410 }
1411
1412 static int stop_queue(struct driver_data *drv_data)
1413 {
1414 unsigned long flags;
1415 unsigned limit = 500;
1416 int status = 0;
1417
1418 spin_lock_irqsave(&drv_data->lock, flags);
1419
1420 /* This is a bit lame, but is optimized for the common execution path.
1421 * A wait_queue on the drv_data->busy could be used, but then the common
1422 * execution path (pump_messages) would be required to call wake_up or
1423 * friends on every SPI message. Do this instead */
1424 drv_data->run = QUEUE_STOPPED;
1425 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1426 spin_unlock_irqrestore(&drv_data->lock, flags);
1427 msleep(10);
1428 spin_lock_irqsave(&drv_data->lock, flags);
1429 }
1430
1431 if (!list_empty(&drv_data->queue) || drv_data->busy)
1432 status = -EBUSY;
1433
1434 spin_unlock_irqrestore(&drv_data->lock, flags);
1435
1436 return status;
1437 }
1438
1439 static int destroy_queue(struct driver_data *drv_data)
1440 {
1441 int status;
1442
1443 status = stop_queue(drv_data);
1444 /* we are unloading the module or failing to load (only two calls
1445 * to this routine), and neither call can handle a return value.
1446 * However, destroy_workqueue calls flush_workqueue, and that will
1447 * block until all work is done. If the reason that stop_queue
1448 * timed out is that the work will never finish, then it does no
1449 * good to call destroy_workqueue, so return anyway. */
1450 if (status != 0)
1451 return status;
1452
1453 destroy_workqueue(drv_data->workqueue);
1454
1455 return 0;
1456 }
1457
1458 static int __init pxa2xx_spi_probe(struct platform_device *pdev)
1459 {
1460 struct device *dev = &pdev->dev;
1461 struct pxa2xx_spi_master *platform_info;
1462 struct spi_master *master;
1463 struct driver_data *drv_data;
1464 struct ssp_device *ssp;
1465 int status;
1466
1467 platform_info = dev->platform_data;
1468
1469 ssp = ssp_request(pdev->id, pdev->name);
1470 if (ssp == NULL) {
1471 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1472 return -ENODEV;
1473 }
1474
1475 /* Allocate master with space for drv_data and null dma buffer */
1476 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1477 if (!master) {
1478 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1479 ssp_free(ssp);
1480 return -ENOMEM;
1481 }
1482 drv_data = spi_master_get_devdata(master);
1483 drv_data->master = master;
1484 drv_data->master_info = platform_info;
1485 drv_data->pdev = pdev;
1486 drv_data->ssp = ssp;
1487
1488 /* the spi->mode bits understood by this driver: */
1489 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1490
1491 master->bus_num = pdev->id;
1492 master->num_chipselect = platform_info->num_chipselect;
1493 master->dma_alignment = DMA_ALIGNMENT;
1494 master->cleanup = cleanup;
1495 master->setup = setup;
1496 master->transfer = transfer;
1497
1498 drv_data->ssp_type = ssp->type;
1499 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1500 sizeof(struct driver_data)), 8);
1501
1502 drv_data->ioaddr = ssp->mmio_base;
1503 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1504 if (ssp->type == PXA25x_SSP) {
1505 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1506 drv_data->dma_cr1 = 0;
1507 drv_data->clear_sr = SSSR_ROR;
1508 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1509 } else {
1510 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1511 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1512 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1513 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1514 }
1515
1516 status = request_irq(ssp->irq, ssp_int, 0, dev_name(dev), drv_data);
1517 if (status < 0) {
1518 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1519 goto out_error_master_alloc;
1520 }
1521
1522 /* Setup DMA if requested */
1523 drv_data->tx_channel = -1;
1524 drv_data->rx_channel = -1;
1525 if (platform_info->enable_dma) {
1526
1527 /* Get two DMA channels (rx and tx) */
1528 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1529 DMA_PRIO_HIGH,
1530 dma_handler,
1531 drv_data);
1532 if (drv_data->rx_channel < 0) {
1533 dev_err(dev, "problem (%d) requesting rx channel\n",
1534 drv_data->rx_channel);
1535 status = -ENODEV;
1536 goto out_error_irq_alloc;
1537 }
1538 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1539 DMA_PRIO_MEDIUM,
1540 dma_handler,
1541 drv_data);
1542 if (drv_data->tx_channel < 0) {
1543 dev_err(dev, "problem (%d) requesting tx channel\n",
1544 drv_data->tx_channel);
1545 status = -ENODEV;
1546 goto out_error_dma_alloc;
1547 }
1548
1549 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1550 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1551 }
1552
1553 /* Enable SOC clock */
1554 clk_enable(ssp->clk);
1555
1556 /* Load default SSP configuration */
1557 write_SSCR0(0, drv_data->ioaddr);
1558 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1559 SSCR1_TxTresh(TX_THRESH_DFLT),
1560 drv_data->ioaddr);
1561 write_SSCR0(SSCR0_SCR(2)
1562 | SSCR0_Motorola
1563 | SSCR0_DataSize(8),
1564 drv_data->ioaddr);
1565 if (drv_data->ssp_type != PXA25x_SSP)
1566 write_SSTO(0, drv_data->ioaddr);
1567 write_SSPSP(0, drv_data->ioaddr);
1568
1569 /* Initial and start queue */
1570 status = init_queue(drv_data);
1571 if (status != 0) {
1572 dev_err(&pdev->dev, "problem initializing queue\n");
1573 goto out_error_clock_enabled;
1574 }
1575 status = start_queue(drv_data);
1576 if (status != 0) {
1577 dev_err(&pdev->dev, "problem starting queue\n");
1578 goto out_error_clock_enabled;
1579 }
1580
1581 /* Register with the SPI framework */
1582 platform_set_drvdata(pdev, drv_data);
1583 status = spi_register_master(master);
1584 if (status != 0) {
1585 dev_err(&pdev->dev, "problem registering spi master\n");
1586 goto out_error_queue_alloc;
1587 }
1588
1589 return status;
1590
1591 out_error_queue_alloc:
1592 destroy_queue(drv_data);
1593
1594 out_error_clock_enabled:
1595 clk_disable(ssp->clk);
1596
1597 out_error_dma_alloc:
1598 if (drv_data->tx_channel != -1)
1599 pxa_free_dma(drv_data->tx_channel);
1600 if (drv_data->rx_channel != -1)
1601 pxa_free_dma(drv_data->rx_channel);
1602
1603 out_error_irq_alloc:
1604 free_irq(ssp->irq, drv_data);
1605
1606 out_error_master_alloc:
1607 spi_master_put(master);
1608 ssp_free(ssp);
1609 return status;
1610 }
1611
1612 static int pxa2xx_spi_remove(struct platform_device *pdev)
1613 {
1614 struct driver_data *drv_data = platform_get_drvdata(pdev);
1615 struct ssp_device *ssp;
1616 int status = 0;
1617
1618 if (!drv_data)
1619 return 0;
1620 ssp = drv_data->ssp;
1621
1622 /* Remove the queue */
1623 status = destroy_queue(drv_data);
1624 if (status != 0)
1625 /* the kernel does not check the return status of this
1626 * this routine (mod->exit, within the kernel). Therefore
1627 * nothing is gained by returning from here, the module is
1628 * going away regardless, and we should not leave any more
1629 * resources allocated than necessary. We cannot free the
1630 * message memory in drv_data->queue, but we can release the
1631 * resources below. I think the kernel should honor -EBUSY
1632 * returns but... */
1633 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1634 "complete, message memory not freed\n");
1635
1636 /* Disable the SSP at the peripheral and SOC level */
1637 write_SSCR0(0, drv_data->ioaddr);
1638 clk_disable(ssp->clk);
1639
1640 /* Release DMA */
1641 if (drv_data->master_info->enable_dma) {
1642 DRCMR(ssp->drcmr_rx) = 0;
1643 DRCMR(ssp->drcmr_tx) = 0;
1644 pxa_free_dma(drv_data->tx_channel);
1645 pxa_free_dma(drv_data->rx_channel);
1646 }
1647
1648 /* Release IRQ */
1649 free_irq(ssp->irq, drv_data);
1650
1651 /* Release SSP */
1652 ssp_free(ssp);
1653
1654 /* Disconnect from the SPI framework */
1655 spi_unregister_master(drv_data->master);
1656
1657 /* Prevent double remove */
1658 platform_set_drvdata(pdev, NULL);
1659
1660 return 0;
1661 }
1662
1663 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1664 {
1665 int status = 0;
1666
1667 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1668 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1669 }
1670
1671 #ifdef CONFIG_PM
1672 static int pxa2xx_spi_suspend(struct device *dev)
1673 {
1674 struct driver_data *drv_data = dev_get_drvdata(dev);
1675 struct ssp_device *ssp = drv_data->ssp;
1676 int status = 0;
1677
1678 status = stop_queue(drv_data);
1679 if (status != 0)
1680 return status;
1681 write_SSCR0(0, drv_data->ioaddr);
1682 clk_disable(ssp->clk);
1683
1684 return 0;
1685 }
1686
1687 static int pxa2xx_spi_resume(struct device *dev)
1688 {
1689 struct driver_data *drv_data = dev_get_drvdata(dev);
1690 struct ssp_device *ssp = drv_data->ssp;
1691 int status = 0;
1692
1693 if (drv_data->rx_channel != -1)
1694 DRCMR(drv_data->ssp->drcmr_rx) =
1695 DRCMR_MAPVLD | drv_data->rx_channel;
1696 if (drv_data->tx_channel != -1)
1697 DRCMR(drv_data->ssp->drcmr_tx) =
1698 DRCMR_MAPVLD | drv_data->tx_channel;
1699
1700 /* Enable the SSP clock */
1701 clk_enable(ssp->clk);
1702
1703 /* Start the queue running */
1704 status = start_queue(drv_data);
1705 if (status != 0) {
1706 dev_err(dev, "problem starting queue (%d)\n", status);
1707 return status;
1708 }
1709
1710 return 0;
1711 }
1712
1713 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1714 .suspend = pxa2xx_spi_suspend,
1715 .resume = pxa2xx_spi_resume,
1716 };
1717 #endif
1718
1719 static struct platform_driver driver = {
1720 .driver = {
1721 .name = "pxa2xx-spi",
1722 .owner = THIS_MODULE,
1723 #ifdef CONFIG_PM
1724 .pm = &pxa2xx_spi_pm_ops,
1725 #endif
1726 },
1727 .remove = pxa2xx_spi_remove,
1728 .shutdown = pxa2xx_spi_shutdown,
1729 };
1730
1731 static int __init pxa2xx_spi_init(void)
1732 {
1733 return platform_driver_probe(&driver, pxa2xx_spi_probe);
1734 }
1735 subsys_initcall(pxa2xx_spi_init);
1736
1737 static void __exit pxa2xx_spi_exit(void)
1738 {
1739 platform_driver_unregister(&driver);
1740 }
1741 module_exit(pxa2xx_spi_exit);
kernel source for telekom puls (alcatel/mediatek)