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serial: sh-sci: Add DMA support.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / sh-sci.c
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50 #include <linux/list.h>
51 #include <linux/dmaengine.h>
52 #include <linux/scatterlist.h>
53 #include <linux/timer.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #ifdef CONFIG_H8300
60 #include <asm/gpio.h>
61 #endif
62
63 #include "sh-sci.h"
64
65 struct sci_port {
66 struct uart_port port;
67
68 /* Port type */
69 unsigned int type;
70
71 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
72 unsigned int irqs[SCIx_NR_IRQS];
73
74 /* Port enable callback */
75 void (*enable)(struct uart_port *port);
76
77 /* Port disable callback */
78 void (*disable)(struct uart_port *port);
79
80 /* Break timer */
81 struct timer_list break_timer;
82 int break_flag;
83
84 /* Interface clock */
85 struct clk *iclk;
86 /* Data clock */
87 struct clk *dclk;
88
89 struct list_head node;
90 struct dma_chan *chan_tx;
91 struct dma_chan *chan_rx;
92 #ifdef CONFIG_SERIAL_SH_SCI_DMA
93 struct device *dma_dev;
94 enum sh_dmae_slave_chan_id slave_tx;
95 enum sh_dmae_slave_chan_id slave_rx;
96 struct dma_async_tx_descriptor *desc_tx;
97 struct dma_async_tx_descriptor *desc_rx[2];
98 dma_cookie_t cookie_tx;
99 dma_cookie_t cookie_rx[2];
100 dma_cookie_t active_rx;
101 struct scatterlist sg_tx;
102 unsigned int sg_len_tx;
103 struct scatterlist sg_rx[2];
104 size_t buf_len_rx;
105 struct sh_dmae_slave param_tx;
106 struct sh_dmae_slave param_rx;
107 struct work_struct work_tx;
108 struct work_struct work_rx;
109 struct timer_list rx_timer;
110 #endif
111 };
112
113 struct sh_sci_priv {
114 spinlock_t lock;
115 struct list_head ports;
116 struct notifier_block clk_nb;
117 };
118
119 /* Function prototypes */
120 static void sci_stop_tx(struct uart_port *port);
121
122 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
123
124 static struct sci_port sci_ports[SCI_NPORTS];
125 static struct uart_driver sci_uart_driver;
126
127 static inline struct sci_port *
128 to_sci_port(struct uart_port *uart)
129 {
130 return container_of(uart, struct sci_port, port);
131 }
132
133 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
134
135 #ifdef CONFIG_CONSOLE_POLL
136 static inline void handle_error(struct uart_port *port)
137 {
138 /* Clear error flags */
139 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
140 }
141
142 static int sci_poll_get_char(struct uart_port *port)
143 {
144 unsigned short status;
145 int c;
146
147 do {
148 status = sci_in(port, SCxSR);
149 if (status & SCxSR_ERRORS(port)) {
150 handle_error(port);
151 continue;
152 }
153 } while (!(status & SCxSR_RDxF(port)));
154
155 c = sci_in(port, SCxRDR);
156
157 /* Dummy read */
158 sci_in(port, SCxSR);
159 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
160
161 return c;
162 }
163 #endif
164
165 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
166 {
167 unsigned short status;
168
169 do {
170 status = sci_in(port, SCxSR);
171 } while (!(status & SCxSR_TDxE(port)));
172
173 sci_out(port, SCxTDR, c);
174 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
175 }
176 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
177
178 #if defined(__H8300H__) || defined(__H8300S__)
179 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
180 {
181 int ch = (port->mapbase - SMR0) >> 3;
182
183 /* set DDR regs */
184 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
185 h8300_sci_pins[ch].rx,
186 H8300_GPIO_INPUT);
187 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
188 h8300_sci_pins[ch].tx,
189 H8300_GPIO_OUTPUT);
190
191 /* tx mark output*/
192 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
193 }
194 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
195 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
196 {
197 if (port->mapbase == 0xA4400000) {
198 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
199 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
200 } else if (port->mapbase == 0xA4410000)
201 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
202 }
203 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
204 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
205 {
206 unsigned short data;
207
208 if (cflag & CRTSCTS) {
209 /* enable RTS/CTS */
210 if (port->mapbase == 0xa4430000) { /* SCIF0 */
211 /* Clear PTCR bit 9-2; enable all scif pins but sck */
212 data = __raw_readw(PORT_PTCR);
213 __raw_writew((data & 0xfc03), PORT_PTCR);
214 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
215 /* Clear PVCR bit 9-2 */
216 data = __raw_readw(PORT_PVCR);
217 __raw_writew((data & 0xfc03), PORT_PVCR);
218 }
219 } else {
220 if (port->mapbase == 0xa4430000) { /* SCIF0 */
221 /* Clear PTCR bit 5-2; enable only tx and rx */
222 data = __raw_readw(PORT_PTCR);
223 __raw_writew((data & 0xffc3), PORT_PTCR);
224 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
225 /* Clear PVCR bit 5-2 */
226 data = __raw_readw(PORT_PVCR);
227 __raw_writew((data & 0xffc3), PORT_PVCR);
228 }
229 }
230 }
231 #elif defined(CONFIG_CPU_SH3)
232 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
233 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
234 {
235 unsigned short data;
236
237 /* We need to set SCPCR to enable RTS/CTS */
238 data = __raw_readw(SCPCR);
239 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
240 __raw_writew(data & 0x0fcf, SCPCR);
241
242 if (!(cflag & CRTSCTS)) {
243 /* We need to set SCPCR to enable RTS/CTS */
244 data = __raw_readw(SCPCR);
245 /* Clear out SCP7MD1,0, SCP4MD1,0,
246 Set SCP6MD1,0 = {01} (output) */
247 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
248
249 data = __raw_readb(SCPDR);
250 /* Set /RTS2 (bit6) = 0 */
251 __raw_writeb(data & 0xbf, SCPDR);
252 }
253 }
254 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
255 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
256 {
257 unsigned short data;
258
259 if (port->mapbase == 0xffe00000) {
260 data = __raw_readw(PSCR);
261 data &= ~0x03cf;
262 if (!(cflag & CRTSCTS))
263 data |= 0x0340;
264
265 __raw_writew(data, PSCR);
266 }
267 }
268 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
269 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
270 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
272 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
273 defined(CONFIG_CPU_SUBTYPE_SHX3)
274 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
275 {
276 if (!(cflag & CRTSCTS))
277 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
278 }
279 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
280 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
281 {
282 if (!(cflag & CRTSCTS))
283 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
284 }
285 #else
286 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
287 {
288 /* Nothing to do */
289 }
290 #endif
291
292 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
293 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
294 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
295 defined(CONFIG_CPU_SUBTYPE_SH7786)
296 static int scif_txfill(struct uart_port *port)
297 {
298 return sci_in(port, SCTFDR) & 0xff;
299 }
300
301 static int scif_txroom(struct uart_port *port)
302 {
303 return SCIF_TXROOM_MAX - scif_txfill(port);
304 }
305
306 static int scif_rxfill(struct uart_port *port)
307 {
308 return sci_in(port, SCRFDR) & 0xff;
309 }
310 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
311 static int scif_txfill(struct uart_port *port)
312 {
313 if (port->mapbase == 0xffe00000 ||
314 port->mapbase == 0xffe08000)
315 /* SCIF0/1*/
316 return sci_in(port, SCTFDR) & 0xff;
317 else
318 /* SCIF2 */
319 return sci_in(port, SCFDR) >> 8;
320 }
321
322 static int scif_txroom(struct uart_port *port)
323 {
324 if (port->mapbase == 0xffe00000 ||
325 port->mapbase == 0xffe08000)
326 /* SCIF0/1*/
327 return SCIF_TXROOM_MAX - scif_txfill(port);
328 else
329 /* SCIF2 */
330 return SCIF2_TXROOM_MAX - scif_txfill(port);
331 }
332
333 static int scif_rxfill(struct uart_port *port)
334 {
335 if ((port->mapbase == 0xffe00000) ||
336 (port->mapbase == 0xffe08000)) {
337 /* SCIF0/1*/
338 return sci_in(port, SCRFDR) & 0xff;
339 } else {
340 /* SCIF2 */
341 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
342 }
343 }
344 #else
345 static int scif_txfill(struct uart_port *port)
346 {
347 return sci_in(port, SCFDR) >> 8;
348 }
349
350 static int scif_txroom(struct uart_port *port)
351 {
352 return SCIF_TXROOM_MAX - scif_txfill(port);
353 }
354
355 static int scif_rxfill(struct uart_port *port)
356 {
357 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
358 }
359 #endif
360
361 static int sci_txfill(struct uart_port *port)
362 {
363 return !(sci_in(port, SCxSR) & SCI_TDRE);
364 }
365
366 static int sci_txroom(struct uart_port *port)
367 {
368 return !sci_txfill(port);
369 }
370
371 static int sci_rxfill(struct uart_port *port)
372 {
373 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
374 }
375
376 /* ********************************************************************** *
377 * the interrupt related routines *
378 * ********************************************************************** */
379
380 static void sci_transmit_chars(struct uart_port *port)
381 {
382 struct circ_buf *xmit = &port->state->xmit;
383 unsigned int stopped = uart_tx_stopped(port);
384 unsigned short status;
385 unsigned short ctrl;
386 int count;
387
388 status = sci_in(port, SCxSR);
389 if (!(status & SCxSR_TDxE(port))) {
390 ctrl = sci_in(port, SCSCR);
391 if (uart_circ_empty(xmit))
392 ctrl &= ~SCI_CTRL_FLAGS_TIE;
393 else
394 ctrl |= SCI_CTRL_FLAGS_TIE;
395 sci_out(port, SCSCR, ctrl);
396 return;
397 }
398
399 if (port->type == PORT_SCI)
400 count = sci_txroom(port);
401 else
402 count = scif_txroom(port);
403
404 do {
405 unsigned char c;
406
407 if (port->x_char) {
408 c = port->x_char;
409 port->x_char = 0;
410 } else if (!uart_circ_empty(xmit) && !stopped) {
411 c = xmit->buf[xmit->tail];
412 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
413 } else {
414 break;
415 }
416
417 sci_out(port, SCxTDR, c);
418
419 port->icount.tx++;
420 } while (--count > 0);
421
422 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
423
424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
425 uart_write_wakeup(port);
426 if (uart_circ_empty(xmit)) {
427 sci_stop_tx(port);
428 } else {
429 ctrl = sci_in(port, SCSCR);
430
431 if (port->type != PORT_SCI) {
432 sci_in(port, SCxSR); /* Dummy read */
433 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
434 }
435
436 ctrl |= SCI_CTRL_FLAGS_TIE;
437 sci_out(port, SCSCR, ctrl);
438 }
439 }
440
441 /* On SH3, SCIF may read end-of-break as a space->mark char */
442 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
443
444 static inline void sci_receive_chars(struct uart_port *port)
445 {
446 struct sci_port *sci_port = to_sci_port(port);
447 struct tty_struct *tty = port->state->port.tty;
448 int i, count, copied = 0;
449 unsigned short status;
450 unsigned char flag;
451
452 status = sci_in(port, SCxSR);
453 if (!(status & SCxSR_RDxF(port)))
454 return;
455
456 while (1) {
457 if (port->type == PORT_SCI)
458 count = sci_rxfill(port);
459 else
460 count = scif_rxfill(port);
461
462 /* Don't copy more bytes than there is room for in the buffer */
463 count = tty_buffer_request_room(tty, count);
464
465 /* If for any reason we can't copy more data, we're done! */
466 if (count == 0)
467 break;
468
469 if (port->type == PORT_SCI) {
470 char c = sci_in(port, SCxRDR);
471 if (uart_handle_sysrq_char(port, c) ||
472 sci_port->break_flag)
473 count = 0;
474 else
475 tty_insert_flip_char(tty, c, TTY_NORMAL);
476 } else {
477 for (i = 0; i < count; i++) {
478 char c = sci_in(port, SCxRDR);
479 status = sci_in(port, SCxSR);
480 #if defined(CONFIG_CPU_SH3)
481 /* Skip "chars" during break */
482 if (sci_port->break_flag) {
483 if ((c == 0) &&
484 (status & SCxSR_FER(port))) {
485 count--; i--;
486 continue;
487 }
488
489 /* Nonzero => end-of-break */
490 dev_dbg(port->dev, "debounce<%02x>\n", c);
491 sci_port->break_flag = 0;
492
493 if (STEPFN(c)) {
494 count--; i--;
495 continue;
496 }
497 }
498 #endif /* CONFIG_CPU_SH3 */
499 if (uart_handle_sysrq_char(port, c)) {
500 count--; i--;
501 continue;
502 }
503
504 /* Store data and status */
505 if (status & SCxSR_FER(port)) {
506 flag = TTY_FRAME;
507 dev_notice(port->dev, "frame error\n");
508 } else if (status & SCxSR_PER(port)) {
509 flag = TTY_PARITY;
510 dev_notice(port->dev, "parity error\n");
511 } else
512 flag = TTY_NORMAL;
513
514 tty_insert_flip_char(tty, c, flag);
515 }
516 }
517
518 sci_in(port, SCxSR); /* dummy read */
519 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
520
521 copied += count;
522 port->icount.rx += count;
523 }
524
525 if (copied) {
526 /* Tell the rest of the system the news. New characters! */
527 tty_flip_buffer_push(tty);
528 } else {
529 sci_in(port, SCxSR); /* dummy read */
530 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
531 }
532 }
533
534 #define SCI_BREAK_JIFFIES (HZ/20)
535 /* The sci generates interrupts during the break,
536 * 1 per millisecond or so during the break period, for 9600 baud.
537 * So dont bother disabling interrupts.
538 * But dont want more than 1 break event.
539 * Use a kernel timer to periodically poll the rx line until
540 * the break is finished.
541 */
542 static void sci_schedule_break_timer(struct sci_port *port)
543 {
544 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
545 add_timer(&port->break_timer);
546 }
547 /* Ensure that two consecutive samples find the break over. */
548 static void sci_break_timer(unsigned long data)
549 {
550 struct sci_port *port = (struct sci_port *)data;
551
552 if (sci_rxd_in(&port->port) == 0) {
553 port->break_flag = 1;
554 sci_schedule_break_timer(port);
555 } else if (port->break_flag == 1) {
556 /* break is over. */
557 port->break_flag = 2;
558 sci_schedule_break_timer(port);
559 } else
560 port->break_flag = 0;
561 }
562
563 static inline int sci_handle_errors(struct uart_port *port)
564 {
565 int copied = 0;
566 unsigned short status = sci_in(port, SCxSR);
567 struct tty_struct *tty = port->state->port.tty;
568
569 if (status & SCxSR_ORER(port)) {
570 /* overrun error */
571 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
572 copied++;
573
574 dev_notice(port->dev, "overrun error");
575 }
576
577 if (status & SCxSR_FER(port)) {
578 if (sci_rxd_in(port) == 0) {
579 /* Notify of BREAK */
580 struct sci_port *sci_port = to_sci_port(port);
581
582 if (!sci_port->break_flag) {
583 sci_port->break_flag = 1;
584 sci_schedule_break_timer(sci_port);
585
586 /* Do sysrq handling. */
587 if (uart_handle_break(port))
588 return 0;
589
590 dev_dbg(port->dev, "BREAK detected\n");
591
592 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
593 copied++;
594 }
595
596 } else {
597 /* frame error */
598 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
599 copied++;
600
601 dev_notice(port->dev, "frame error\n");
602 }
603 }
604
605 if (status & SCxSR_PER(port)) {
606 /* parity error */
607 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
608 copied++;
609
610 dev_notice(port->dev, "parity error");
611 }
612
613 if (copied)
614 tty_flip_buffer_push(tty);
615
616 return copied;
617 }
618
619 static inline int sci_handle_fifo_overrun(struct uart_port *port)
620 {
621 struct tty_struct *tty = port->state->port.tty;
622 int copied = 0;
623
624 if (port->type != PORT_SCIF)
625 return 0;
626
627 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
628 sci_out(port, SCLSR, 0);
629
630 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
631 tty_flip_buffer_push(tty);
632
633 dev_notice(port->dev, "overrun error\n");
634 copied++;
635 }
636
637 return copied;
638 }
639
640 static inline int sci_handle_breaks(struct uart_port *port)
641 {
642 int copied = 0;
643 unsigned short status = sci_in(port, SCxSR);
644 struct tty_struct *tty = port->state->port.tty;
645 struct sci_port *s = to_sci_port(port);
646
647 if (uart_handle_break(port))
648 return 0;
649
650 if (!s->break_flag && status & SCxSR_BRK(port)) {
651 #if defined(CONFIG_CPU_SH3)
652 /* Debounce break */
653 s->break_flag = 1;
654 #endif
655 /* Notify of BREAK */
656 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
657 copied++;
658
659 dev_dbg(port->dev, "BREAK detected\n");
660 }
661
662 if (copied)
663 tty_flip_buffer_push(tty);
664
665 copied += sci_handle_fifo_overrun(port);
666
667 return copied;
668 }
669
670 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
671 {
672 #ifdef CONFIG_SERIAL_SH_SCI_DMA
673 struct uart_port *port = ptr;
674 struct sci_port *s = to_sci_port(port);
675
676 if (s->chan_rx) {
677 unsigned long tout;
678 u16 scr = sci_in(port, SCSCR);
679 u16 ssr = sci_in(port, SCxSR);
680
681 /* Disable future Rx interrupts */
682 sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
683 /* Clear current interrupt */
684 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
685 /* Calculate delay for 1.5 DMA buffers */
686 tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
687 port->fifosize / 2;
688 dev_dbg(port->dev, "Rx IRQ: setup timeout in %u ms\n",
689 tout * 1000 / HZ);
690 if (tout < 2)
691 tout = 2;
692 mod_timer(&s->rx_timer, jiffies + tout);
693
694 return IRQ_HANDLED;
695 }
696 #endif
697
698 /* I think sci_receive_chars has to be called irrespective
699 * of whether the I_IXOFF is set, otherwise, how is the interrupt
700 * to be disabled?
701 */
702 sci_receive_chars(ptr);
703
704 return IRQ_HANDLED;
705 }
706
707 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
708 {
709 struct uart_port *port = ptr;
710 unsigned long flags;
711
712 spin_lock_irqsave(&port->lock, flags);
713 sci_transmit_chars(port);
714 spin_unlock_irqrestore(&port->lock, flags);
715
716 return IRQ_HANDLED;
717 }
718
719 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
720 {
721 struct uart_port *port = ptr;
722
723 /* Handle errors */
724 if (port->type == PORT_SCI) {
725 if (sci_handle_errors(port)) {
726 /* discard character in rx buffer */
727 sci_in(port, SCxSR);
728 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
729 }
730 } else {
731 sci_handle_fifo_overrun(port);
732 sci_rx_interrupt(irq, ptr);
733 }
734
735 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
736
737 /* Kick the transmission */
738 sci_tx_interrupt(irq, ptr);
739
740 return IRQ_HANDLED;
741 }
742
743 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
744 {
745 struct uart_port *port = ptr;
746
747 /* Handle BREAKs */
748 sci_handle_breaks(port);
749 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
750
751 return IRQ_HANDLED;
752 }
753
754 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
755 {
756 unsigned short ssr_status, scr_status, err_enabled;
757 struct uart_port *port = ptr;
758 struct sci_port *s = to_sci_port(port);
759 irqreturn_t ret = IRQ_NONE;
760
761 ssr_status = sci_in(port, SCxSR);
762 scr_status = sci_in(port, SCSCR);
763 err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
764
765 /* Tx Interrupt */
766 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
767 !s->chan_tx)
768 ret = sci_tx_interrupt(irq, ptr);
769 /*
770 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
771 * DR flags
772 */
773 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
774 (scr_status & SCI_CTRL_FLAGS_RIE))
775 ret = sci_rx_interrupt(irq, ptr);
776 /* Error Interrupt */
777 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
778 ret = sci_er_interrupt(irq, ptr);
779 /* Break Interrupt */
780 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
781 ret = sci_br_interrupt(irq, ptr);
782
783 WARN_ONCE(ret == IRQ_NONE,
784 "%s: %d IRQ %d, status %x, control %x\n", __func__,
785 irq, port->line, ssr_status, scr_status);
786
787 return ret;
788 }
789
790 /*
791 * Here we define a transistion notifier so that we can update all of our
792 * ports' baud rate when the peripheral clock changes.
793 */
794 static int sci_notifier(struct notifier_block *self,
795 unsigned long phase, void *p)
796 {
797 struct sh_sci_priv *priv = container_of(self,
798 struct sh_sci_priv, clk_nb);
799 struct sci_port *sci_port;
800 unsigned long flags;
801
802 if ((phase == CPUFREQ_POSTCHANGE) ||
803 (phase == CPUFREQ_RESUMECHANGE)) {
804 spin_lock_irqsave(&priv->lock, flags);
805 list_for_each_entry(sci_port, &priv->ports, node)
806 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
807 spin_unlock_irqrestore(&priv->lock, flags);
808 }
809
810 return NOTIFY_OK;
811 }
812
813 static void sci_clk_enable(struct uart_port *port)
814 {
815 struct sci_port *sci_port = to_sci_port(port);
816
817 clk_enable(sci_port->dclk);
818 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
819
820 if (sci_port->iclk)
821 clk_enable(sci_port->iclk);
822 }
823
824 static void sci_clk_disable(struct uart_port *port)
825 {
826 struct sci_port *sci_port = to_sci_port(port);
827
828 if (sci_port->iclk)
829 clk_disable(sci_port->iclk);
830
831 clk_disable(sci_port->dclk);
832 }
833
834 static int sci_request_irq(struct sci_port *port)
835 {
836 int i;
837 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
838 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
839 sci_br_interrupt,
840 };
841 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
842 "SCI Transmit Data Empty", "SCI Break" };
843
844 if (port->irqs[0] == port->irqs[1]) {
845 if (unlikely(!port->irqs[0]))
846 return -ENODEV;
847
848 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
849 IRQF_DISABLED, "sci", port)) {
850 dev_err(port->port.dev, "Can't allocate IRQ\n");
851 return -ENODEV;
852 }
853 } else {
854 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
855 if (unlikely(!port->irqs[i]))
856 continue;
857
858 if (request_irq(port->irqs[i], handlers[i],
859 IRQF_DISABLED, desc[i], port)) {
860 dev_err(port->port.dev, "Can't allocate IRQ\n");
861 return -ENODEV;
862 }
863 }
864 }
865
866 return 0;
867 }
868
869 static void sci_free_irq(struct sci_port *port)
870 {
871 int i;
872
873 if (port->irqs[0] == port->irqs[1])
874 free_irq(port->irqs[0], port);
875 else {
876 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
877 if (!port->irqs[i])
878 continue;
879
880 free_irq(port->irqs[i], port);
881 }
882 }
883 }
884
885 static unsigned int sci_tx_empty(struct uart_port *port)
886 {
887 unsigned short status = sci_in(port, SCxSR);
888 unsigned short in_tx_fifo = scif_txfill(port);
889
890 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
891 }
892
893 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
894 {
895 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
896 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
897 /* If you have signals for DTR and DCD, please implement here. */
898 }
899
900 static unsigned int sci_get_mctrl(struct uart_port *port)
901 {
902 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
903 and CTS/RTS */
904
905 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
906 }
907
908 #ifdef CONFIG_SERIAL_SH_SCI_DMA
909 static void sci_dma_tx_complete(void *arg)
910 {
911 struct sci_port *s = arg;
912 struct uart_port *port = &s->port;
913 struct circ_buf *xmit = &port->state->xmit;
914 unsigned long flags;
915
916 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
917
918 spin_lock_irqsave(&port->lock, flags);
919
920 xmit->tail += s->sg_tx.length;
921 xmit->tail &= UART_XMIT_SIZE - 1;
922
923 port->icount.tx += s->sg_tx.length;
924
925 async_tx_ack(s->desc_tx);
926 s->cookie_tx = -EINVAL;
927 s->desc_tx = NULL;
928
929 spin_unlock_irqrestore(&port->lock, flags);
930
931 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
932 uart_write_wakeup(port);
933
934 if (uart_circ_chars_pending(xmit))
935 schedule_work(&s->work_tx);
936 }
937
938 /* Locking: called with port lock held */
939 static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
940 size_t count)
941 {
942 struct uart_port *port = &s->port;
943 int i, active, room;
944
945 room = tty_buffer_request_room(tty, count);
946
947 if (s->active_rx == s->cookie_rx[0]) {
948 active = 0;
949 } else if (s->active_rx == s->cookie_rx[1]) {
950 active = 1;
951 } else {
952 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
953 return 0;
954 }
955
956 if (room < count)
957 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
958 count - room);
959 if (!room)
960 return room;
961
962 for (i = 0; i < room; i++)
963 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
964 TTY_NORMAL);
965
966 port->icount.rx += room;
967
968 return room;
969 }
970
971 static void sci_dma_rx_complete(void *arg)
972 {
973 struct sci_port *s = arg;
974 struct uart_port *port = &s->port;
975 struct tty_struct *tty = port->state->port.tty;
976 unsigned long flags;
977 int count;
978
979 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
980
981 spin_lock_irqsave(&port->lock, flags);
982
983 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
984
985 mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
986
987 spin_unlock_irqrestore(&port->lock, flags);
988
989 if (count)
990 tty_flip_buffer_push(tty);
991
992 schedule_work(&s->work_rx);
993 }
994
995 static void sci_start_rx(struct uart_port *port);
996 static void sci_start_tx(struct uart_port *port);
997
998 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
999 {
1000 struct dma_chan *chan = s->chan_rx;
1001 struct uart_port *port = &s->port;
1002 unsigned long flags;
1003
1004 s->chan_rx = NULL;
1005 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1006 dma_release_channel(chan);
1007 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1008 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1009 if (enable_pio)
1010 sci_start_rx(port);
1011 }
1012
1013 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1014 {
1015 struct dma_chan *chan = s->chan_tx;
1016 struct uart_port *port = &s->port;
1017 unsigned long flags;
1018
1019 s->chan_tx = NULL;
1020 s->cookie_tx = -EINVAL;
1021 dma_release_channel(chan);
1022 if (enable_pio)
1023 sci_start_tx(port);
1024 }
1025
1026 static void sci_submit_rx(struct sci_port *s)
1027 {
1028 struct dma_chan *chan = s->chan_rx;
1029 int i;
1030
1031 for (i = 0; i < 2; i++) {
1032 struct scatterlist *sg = &s->sg_rx[i];
1033 struct dma_async_tx_descriptor *desc;
1034
1035 desc = chan->device->device_prep_slave_sg(chan,
1036 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1037
1038 if (desc) {
1039 s->desc_rx[i] = desc;
1040 desc->callback = sci_dma_rx_complete;
1041 desc->callback_param = s;
1042 s->cookie_rx[i] = desc->tx_submit(desc);
1043 }
1044
1045 if (!desc || s->cookie_rx[i] < 0) {
1046 if (i) {
1047 async_tx_ack(s->desc_rx[0]);
1048 s->cookie_rx[0] = -EINVAL;
1049 }
1050 if (desc) {
1051 async_tx_ack(desc);
1052 s->cookie_rx[i] = -EINVAL;
1053 }
1054 dev_warn(s->port.dev,
1055 "failed to re-start DMA, using PIO\n");
1056 sci_rx_dma_release(s, true);
1057 return;
1058 }
1059 }
1060
1061 s->active_rx = s->cookie_rx[0];
1062
1063 dma_async_issue_pending(chan);
1064 }
1065
1066 static void work_fn_rx(struct work_struct *work)
1067 {
1068 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1069 struct uart_port *port = &s->port;
1070 struct dma_async_tx_descriptor *desc;
1071 int new;
1072
1073 if (s->active_rx == s->cookie_rx[0]) {
1074 new = 0;
1075 } else if (s->active_rx == s->cookie_rx[1]) {
1076 new = 1;
1077 } else {
1078 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1079 return;
1080 }
1081 desc = s->desc_rx[new];
1082
1083 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1084 DMA_SUCCESS) {
1085 /* Handle incomplete DMA receive */
1086 struct tty_struct *tty = port->state->port.tty;
1087 struct dma_chan *chan = s->chan_rx;
1088 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1089 async_tx);
1090 unsigned long flags;
1091 int count;
1092
1093 chan->device->device_terminate_all(chan);
1094 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1095 sh_desc->partial, sh_desc->cookie);
1096
1097 spin_lock_irqsave(&port->lock, flags);
1098 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1099 spin_unlock_irqrestore(&port->lock, flags);
1100
1101 if (count)
1102 tty_flip_buffer_push(tty);
1103
1104 sci_submit_rx(s);
1105
1106 return;
1107 }
1108
1109 s->cookie_rx[new] = desc->tx_submit(desc);
1110 if (s->cookie_rx[new] < 0) {
1111 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1112 sci_rx_dma_release(s, true);
1113 return;
1114 }
1115
1116 dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
1117 s->cookie_rx[new], new);
1118
1119 s->active_rx = s->cookie_rx[!new];
1120 }
1121
1122 static void work_fn_tx(struct work_struct *work)
1123 {
1124 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1125 struct dma_async_tx_descriptor *desc;
1126 struct dma_chan *chan = s->chan_tx;
1127 struct uart_port *port = &s->port;
1128 struct circ_buf *xmit = &port->state->xmit;
1129 struct scatterlist *sg = &s->sg_tx;
1130
1131 /*
1132 * DMA is idle now.
1133 * Port xmit buffer is already mapped, and it is one page... Just adjust
1134 * offsets and lengths. Since it is a circular buffer, we have to
1135 * transmit till the end, and then the rest. Take the port lock to get a
1136 * consistent xmit buffer state.
1137 */
1138 spin_lock_irq(&port->lock);
1139 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1140 sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1141 sg->offset;
1142 sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1143 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1144 sg->dma_length = sg->length;
1145 spin_unlock_irq(&port->lock);
1146
1147 BUG_ON(!sg->length);
1148
1149 desc = chan->device->device_prep_slave_sg(chan,
1150 sg, s->sg_len_tx, DMA_TO_DEVICE,
1151 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1152 if (!desc) {
1153 /* switch to PIO */
1154 sci_tx_dma_release(s, true);
1155 return;
1156 }
1157
1158 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1159
1160 spin_lock_irq(&port->lock);
1161 s->desc_tx = desc;
1162 desc->callback = sci_dma_tx_complete;
1163 desc->callback_param = s;
1164 spin_unlock_irq(&port->lock);
1165 s->cookie_tx = desc->tx_submit(desc);
1166 if (s->cookie_tx < 0) {
1167 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1168 /* switch to PIO */
1169 sci_tx_dma_release(s, true);
1170 return;
1171 }
1172
1173 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1174 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1175
1176 dma_async_issue_pending(chan);
1177 }
1178 #endif
1179
1180 static void sci_start_tx(struct uart_port *port)
1181 {
1182 unsigned short ctrl;
1183
1184 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1185 struct sci_port *s = to_sci_port(port);
1186
1187 if (s->chan_tx) {
1188 if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
1189 schedule_work(&s->work_tx);
1190
1191 return;
1192 }
1193 #endif
1194
1195 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1196 ctrl = sci_in(port, SCSCR);
1197 ctrl |= SCI_CTRL_FLAGS_TIE;
1198 sci_out(port, SCSCR, ctrl);
1199 }
1200
1201 static void sci_stop_tx(struct uart_port *port)
1202 {
1203 unsigned short ctrl;
1204
1205 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1206 ctrl = sci_in(port, SCSCR);
1207 ctrl &= ~SCI_CTRL_FLAGS_TIE;
1208 sci_out(port, SCSCR, ctrl);
1209 }
1210
1211 static void sci_start_rx(struct uart_port *port)
1212 {
1213 unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
1214
1215 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
1216 ctrl |= sci_in(port, SCSCR);
1217 sci_out(port, SCSCR, ctrl);
1218 }
1219
1220 static void sci_stop_rx(struct uart_port *port)
1221 {
1222 unsigned short ctrl;
1223
1224 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
1225 ctrl = sci_in(port, SCSCR);
1226 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
1227 sci_out(port, SCSCR, ctrl);
1228 }
1229
1230 static void sci_enable_ms(struct uart_port *port)
1231 {
1232 /* Nothing here yet .. */
1233 }
1234
1235 static void sci_break_ctl(struct uart_port *port, int break_state)
1236 {
1237 /* Nothing here yet .. */
1238 }
1239
1240 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1241 static bool filter(struct dma_chan *chan, void *slave)
1242 {
1243 struct sh_dmae_slave *param = slave;
1244
1245 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1246 param->slave_id);
1247
1248 if (param->dma_dev == chan->device->dev) {
1249 chan->private = param;
1250 return true;
1251 } else {
1252 return false;
1253 }
1254 }
1255
1256 static void rx_timer_fn(unsigned long arg)
1257 {
1258 struct sci_port *s = (struct sci_port *)arg;
1259 struct uart_port *port = &s->port;
1260
1261 u16 scr = sci_in(port, SCSCR);
1262 sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
1263 dev_dbg(port->dev, "DMA Rx timed out\n");
1264 schedule_work(&s->work_rx);
1265 }
1266
1267 static void sci_request_dma(struct uart_port *port)
1268 {
1269 struct sci_port *s = to_sci_port(port);
1270 struct sh_dmae_slave *param;
1271 struct dma_chan *chan;
1272 dma_cap_mask_t mask;
1273 int nent;
1274
1275 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
1276 port->line, s->dma_dev);
1277
1278 if (!s->dma_dev)
1279 return;
1280
1281 dma_cap_zero(mask);
1282 dma_cap_set(DMA_SLAVE, mask);
1283
1284 param = &s->param_tx;
1285
1286 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1287 param->slave_id = s->slave_tx;
1288 param->dma_dev = s->dma_dev;
1289
1290 s->cookie_tx = -EINVAL;
1291 chan = dma_request_channel(mask, filter, param);
1292 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1293 if (chan) {
1294 s->chan_tx = chan;
1295 sg_init_table(&s->sg_tx, 1);
1296 /* UART circular tx buffer is an aligned page. */
1297 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1298 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1299 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1300 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1301 if (!nent)
1302 sci_tx_dma_release(s, false);
1303 else
1304 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1305 sg_dma_len(&s->sg_tx),
1306 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1307
1308 s->sg_len_tx = nent;
1309
1310 INIT_WORK(&s->work_tx, work_fn_tx);
1311 }
1312
1313 param = &s->param_rx;
1314
1315 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1316 param->slave_id = s->slave_rx;
1317 param->dma_dev = s->dma_dev;
1318
1319 chan = dma_request_channel(mask, filter, param);
1320 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1321 if (chan) {
1322 dma_addr_t dma[2];
1323 void *buf[2];
1324 int i;
1325
1326 s->chan_rx = chan;
1327
1328 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1329 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1330 &dma[0], GFP_KERNEL);
1331
1332 if (!buf[0]) {
1333 dev_warn(port->dev,
1334 "failed to allocate dma buffer, using PIO\n");
1335 sci_rx_dma_release(s, true);
1336 return;
1337 }
1338
1339 buf[1] = buf[0] + s->buf_len_rx;
1340 dma[1] = dma[0] + s->buf_len_rx;
1341
1342 for (i = 0; i < 2; i++) {
1343 struct scatterlist *sg = &s->sg_rx[i];
1344
1345 sg_init_table(sg, 1);
1346 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1347 (int)buf[i] & ~PAGE_MASK);
1348 sg->dma_address = dma[i];
1349 sg->dma_length = sg->length;
1350 }
1351
1352 INIT_WORK(&s->work_rx, work_fn_rx);
1353 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1354
1355 sci_submit_rx(s);
1356 }
1357 }
1358
1359 static void sci_free_dma(struct uart_port *port)
1360 {
1361 struct sci_port *s = to_sci_port(port);
1362
1363 if (!s->dma_dev)
1364 return;
1365
1366 if (s->chan_tx)
1367 sci_tx_dma_release(s, false);
1368 if (s->chan_rx)
1369 sci_rx_dma_release(s, false);
1370 }
1371 #endif
1372
1373 static int sci_startup(struct uart_port *port)
1374 {
1375 struct sci_port *s = to_sci_port(port);
1376
1377 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1378
1379 if (s->enable)
1380 s->enable(port);
1381
1382 sci_request_irq(s);
1383 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1384 sci_request_dma(port);
1385 #endif
1386 sci_start_tx(port);
1387 sci_start_rx(port);
1388
1389 return 0;
1390 }
1391
1392 static void sci_shutdown(struct uart_port *port)
1393 {
1394 struct sci_port *s = to_sci_port(port);
1395
1396 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1397
1398 sci_stop_rx(port);
1399 sci_stop_tx(port);
1400 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1401 sci_free_dma(port);
1402 #endif
1403 sci_free_irq(s);
1404
1405 if (s->disable)
1406 s->disable(port);
1407 }
1408
1409 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1410 struct ktermios *old)
1411 {
1412 unsigned int status, baud, smr_val, max_baud;
1413 int t = -1;
1414
1415 /*
1416 * earlyprintk comes here early on with port->uartclk set to zero.
1417 * the clock framework is not up and running at this point so here
1418 * we assume that 115200 is the maximum baud rate. please note that
1419 * the baud rate is not programmed during earlyprintk - it is assumed
1420 * that the previous boot loader has enabled required clocks and
1421 * setup the baud rate generator hardware for us already.
1422 */
1423 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1424
1425 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1426 if (likely(baud && port->uartclk))
1427 t = SCBRR_VALUE(baud, port->uartclk);
1428
1429 do {
1430 status = sci_in(port, SCxSR);
1431 } while (!(status & SCxSR_TEND(port)));
1432
1433 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1434
1435 if (port->type != PORT_SCI)
1436 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1437
1438 smr_val = sci_in(port, SCSMR) & 3;
1439 if ((termios->c_cflag & CSIZE) == CS7)
1440 smr_val |= 0x40;
1441 if (termios->c_cflag & PARENB)
1442 smr_val |= 0x20;
1443 if (termios->c_cflag & PARODD)
1444 smr_val |= 0x30;
1445 if (termios->c_cflag & CSTOPB)
1446 smr_val |= 0x08;
1447
1448 uart_update_timeout(port, termios->c_cflag, baud);
1449
1450 sci_out(port, SCSMR, smr_val);
1451
1452 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
1453 SCSCR_INIT(port));
1454
1455 if (t > 0) {
1456 if (t >= 256) {
1457 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1458 t >>= 2;
1459 } else
1460 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1461
1462 sci_out(port, SCBRR, t);
1463 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1464 }
1465
1466 sci_init_pins(port, termios->c_cflag);
1467 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
1468
1469 sci_out(port, SCSCR, SCSCR_INIT(port));
1470
1471 if ((termios->c_cflag & CREAD) != 0)
1472 sci_start_rx(port);
1473 }
1474
1475 static const char *sci_type(struct uart_port *port)
1476 {
1477 switch (port->type) {
1478 case PORT_IRDA:
1479 return "irda";
1480 case PORT_SCI:
1481 return "sci";
1482 case PORT_SCIF:
1483 return "scif";
1484 case PORT_SCIFA:
1485 return "scifa";
1486 }
1487
1488 return NULL;
1489 }
1490
1491 static void sci_release_port(struct uart_port *port)
1492 {
1493 /* Nothing here yet .. */
1494 }
1495
1496 static int sci_request_port(struct uart_port *port)
1497 {
1498 /* Nothing here yet .. */
1499 return 0;
1500 }
1501
1502 static void sci_config_port(struct uart_port *port, int flags)
1503 {
1504 struct sci_port *s = to_sci_port(port);
1505
1506 port->type = s->type;
1507
1508 if (port->membase)
1509 return;
1510
1511 if (port->flags & UPF_IOREMAP) {
1512 port->membase = ioremap_nocache(port->mapbase, 0x40);
1513
1514 if (IS_ERR(port->membase))
1515 dev_err(port->dev, "can't remap port#%d\n", port->line);
1516 } else {
1517 /*
1518 * For the simple (and majority of) cases where we don't
1519 * need to do any remapping, just cast the cookie
1520 * directly.
1521 */
1522 port->membase = (void __iomem *)port->mapbase;
1523 }
1524 }
1525
1526 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1527 {
1528 struct sci_port *s = to_sci_port(port);
1529
1530 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1531 return -EINVAL;
1532 if (ser->baud_base < 2400)
1533 /* No paper tape reader for Mitch.. */
1534 return -EINVAL;
1535
1536 return 0;
1537 }
1538
1539 static struct uart_ops sci_uart_ops = {
1540 .tx_empty = sci_tx_empty,
1541 .set_mctrl = sci_set_mctrl,
1542 .get_mctrl = sci_get_mctrl,
1543 .start_tx = sci_start_tx,
1544 .stop_tx = sci_stop_tx,
1545 .stop_rx = sci_stop_rx,
1546 .enable_ms = sci_enable_ms,
1547 .break_ctl = sci_break_ctl,
1548 .startup = sci_startup,
1549 .shutdown = sci_shutdown,
1550 .set_termios = sci_set_termios,
1551 .type = sci_type,
1552 .release_port = sci_release_port,
1553 .request_port = sci_request_port,
1554 .config_port = sci_config_port,
1555 .verify_port = sci_verify_port,
1556 #ifdef CONFIG_CONSOLE_POLL
1557 .poll_get_char = sci_poll_get_char,
1558 .poll_put_char = sci_poll_put_char,
1559 #endif
1560 };
1561
1562 static void __devinit sci_init_single(struct platform_device *dev,
1563 struct sci_port *sci_port,
1564 unsigned int index,
1565 struct plat_sci_port *p)
1566 {
1567 struct uart_port *port = &sci_port->port;
1568
1569 port->ops = &sci_uart_ops;
1570 port->iotype = UPIO_MEM;
1571 port->line = index;
1572
1573 switch (p->type) {
1574 case PORT_SCIFA:
1575 port->fifosize = 64;
1576 break;
1577 case PORT_SCIF:
1578 port->fifosize = 16;
1579 break;
1580 default:
1581 port->fifosize = 1;
1582 break;
1583 }
1584
1585 if (dev) {
1586 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1587 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1588 sci_port->enable = sci_clk_enable;
1589 sci_port->disable = sci_clk_disable;
1590 port->dev = &dev->dev;
1591 }
1592
1593 sci_port->break_timer.data = (unsigned long)sci_port;
1594 sci_port->break_timer.function = sci_break_timer;
1595 init_timer(&sci_port->break_timer);
1596
1597 port->mapbase = p->mapbase;
1598 port->membase = p->membase;
1599
1600 port->irq = p->irqs[SCIx_TXI_IRQ];
1601 port->flags = p->flags;
1602 sci_port->type = port->type = p->type;
1603
1604 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1605 sci_port->dma_dev = p->dma_dev;
1606 sci_port->slave_tx = p->dma_slave_tx;
1607 sci_port->slave_rx = p->dma_slave_rx;
1608
1609 dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
1610 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
1611 #endif
1612
1613 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1614 }
1615
1616 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1617 static struct tty_driver *serial_console_device(struct console *co, int *index)
1618 {
1619 struct uart_driver *p = &sci_uart_driver;
1620 *index = co->index;
1621 return p->tty_driver;
1622 }
1623
1624 static void serial_console_putchar(struct uart_port *port, int ch)
1625 {
1626 sci_poll_put_char(port, ch);
1627 }
1628
1629 /*
1630 * Print a string to the serial port trying not to disturb
1631 * any possible real use of the port...
1632 */
1633 static void serial_console_write(struct console *co, const char *s,
1634 unsigned count)
1635 {
1636 struct uart_port *port = co->data;
1637 struct sci_port *sci_port = to_sci_port(port);
1638 unsigned short bits;
1639
1640 if (sci_port->enable)
1641 sci_port->enable(port);
1642
1643 uart_console_write(port, s, count, serial_console_putchar);
1644
1645 /* wait until fifo is empty and last bit has been transmitted */
1646 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1647 while ((sci_in(port, SCxSR) & bits) != bits)
1648 cpu_relax();
1649
1650 if (sci_port->disable)
1651 sci_port->disable(port);
1652 }
1653
1654 static int __devinit serial_console_setup(struct console *co, char *options)
1655 {
1656 struct sci_port *sci_port;
1657 struct uart_port *port;
1658 int baud = 115200;
1659 int bits = 8;
1660 int parity = 'n';
1661 int flow = 'n';
1662 int ret;
1663
1664 /*
1665 * Check whether an invalid uart number has been specified, and
1666 * if so, search for the first available port that does have
1667 * console support.
1668 */
1669 if (co->index >= SCI_NPORTS)
1670 co->index = 0;
1671
1672 if (co->data) {
1673 port = co->data;
1674 sci_port = to_sci_port(port);
1675 } else {
1676 sci_port = &sci_ports[co->index];
1677 port = &sci_port->port;
1678 co->data = port;
1679 }
1680
1681 /*
1682 * Also need to check port->type, we don't actually have any
1683 * UPIO_PORT ports, but uart_report_port() handily misreports
1684 * it anyways if we don't have a port available by the time this is
1685 * called.
1686 */
1687 if (!port->type)
1688 return -ENODEV;
1689
1690 sci_config_port(port, 0);
1691
1692 if (sci_port->enable)
1693 sci_port->enable(port);
1694
1695 if (options)
1696 uart_parse_options(options, &baud, &parity, &bits, &flow);
1697
1698 ret = uart_set_options(port, co, baud, parity, bits, flow);
1699 #if defined(__H8300H__) || defined(__H8300S__)
1700 /* disable rx interrupt */
1701 if (ret == 0)
1702 sci_stop_rx(port);
1703 #endif
1704 /* TODO: disable clock */
1705 return ret;
1706 }
1707
1708 static struct console serial_console = {
1709 .name = "ttySC",
1710 .device = serial_console_device,
1711 .write = serial_console_write,
1712 .setup = serial_console_setup,
1713 .flags = CON_PRINTBUFFER,
1714 .index = -1,
1715 };
1716
1717 static int __init sci_console_init(void)
1718 {
1719 register_console(&serial_console);
1720 return 0;
1721 }
1722 console_initcall(sci_console_init);
1723
1724 static struct sci_port early_serial_port;
1725 static struct console early_serial_console = {
1726 .name = "early_ttySC",
1727 .write = serial_console_write,
1728 .flags = CON_PRINTBUFFER,
1729 };
1730 static char early_serial_buf[32];
1731
1732 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1733
1734 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1735 #define SCI_CONSOLE (&serial_console)
1736 #else
1737 #define SCI_CONSOLE 0
1738 #endif
1739
1740 static char banner[] __initdata =
1741 KERN_INFO "SuperH SCI(F) driver initialized\n";
1742
1743 static struct uart_driver sci_uart_driver = {
1744 .owner = THIS_MODULE,
1745 .driver_name = "sci",
1746 .dev_name = "ttySC",
1747 .major = SCI_MAJOR,
1748 .minor = SCI_MINOR_START,
1749 .nr = SCI_NPORTS,
1750 .cons = SCI_CONSOLE,
1751 };
1752
1753
1754 static int sci_remove(struct platform_device *dev)
1755 {
1756 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1757 struct sci_port *p;
1758 unsigned long flags;
1759
1760 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1761
1762 spin_lock_irqsave(&priv->lock, flags);
1763 list_for_each_entry(p, &priv->ports, node)
1764 uart_remove_one_port(&sci_uart_driver, &p->port);
1765 spin_unlock_irqrestore(&priv->lock, flags);
1766
1767 kfree(priv);
1768 return 0;
1769 }
1770
1771 static int __devinit sci_probe_single(struct platform_device *dev,
1772 unsigned int index,
1773 struct plat_sci_port *p,
1774 struct sci_port *sciport)
1775 {
1776 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1777 unsigned long flags;
1778 int ret;
1779
1780 /* Sanity check */
1781 if (unlikely(index >= SCI_NPORTS)) {
1782 dev_notice(&dev->dev, "Attempting to register port "
1783 "%d when only %d are available.\n",
1784 index+1, SCI_NPORTS);
1785 dev_notice(&dev->dev, "Consider bumping "
1786 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1787 return 0;
1788 }
1789
1790 sci_init_single(dev, sciport, index, p);
1791
1792 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1793 if (ret)
1794 return ret;
1795
1796 INIT_LIST_HEAD(&sciport->node);
1797
1798 spin_lock_irqsave(&priv->lock, flags);
1799 list_add(&sciport->node, &priv->ports);
1800 spin_unlock_irqrestore(&priv->lock, flags);
1801
1802 return 0;
1803 }
1804
1805 /*
1806 * Register a set of serial devices attached to a platform device. The
1807 * list is terminated with a zero flags entry, which means we expect
1808 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1809 * remapping (such as sh64) should also set UPF_IOREMAP.
1810 */
1811 static int __devinit sci_probe(struct platform_device *dev)
1812 {
1813 struct plat_sci_port *p = dev->dev.platform_data;
1814 struct sh_sci_priv *priv;
1815 int i, ret = -EINVAL;
1816
1817 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1818 if (is_early_platform_device(dev)) {
1819 if (dev->id == -1)
1820 return -ENOTSUPP;
1821 early_serial_console.index = dev->id;
1822 early_serial_console.data = &early_serial_port.port;
1823 sci_init_single(NULL, &early_serial_port, dev->id, p);
1824 serial_console_setup(&early_serial_console, early_serial_buf);
1825 if (!strstr(early_serial_buf, "keep"))
1826 early_serial_console.flags |= CON_BOOT;
1827 register_console(&early_serial_console);
1828 return 0;
1829 }
1830 #endif
1831
1832 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1833 if (!priv)
1834 return -ENOMEM;
1835
1836 INIT_LIST_HEAD(&priv->ports);
1837 spin_lock_init(&priv->lock);
1838 platform_set_drvdata(dev, priv);
1839
1840 priv->clk_nb.notifier_call = sci_notifier;
1841 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1842
1843 if (dev->id != -1) {
1844 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1845 if (ret)
1846 goto err_unreg;
1847 } else {
1848 for (i = 0; p && p->flags != 0; p++, i++) {
1849 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1850 if (ret)
1851 goto err_unreg;
1852 }
1853 }
1854
1855 #ifdef CONFIG_SH_STANDARD_BIOS
1856 sh_bios_gdb_detach();
1857 #endif
1858
1859 return 0;
1860
1861 err_unreg:
1862 sci_remove(dev);
1863 return ret;
1864 }
1865
1866 static int sci_suspend(struct device *dev)
1867 {
1868 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1869 struct sci_port *p;
1870 unsigned long flags;
1871
1872 spin_lock_irqsave(&priv->lock, flags);
1873 list_for_each_entry(p, &priv->ports, node)
1874 uart_suspend_port(&sci_uart_driver, &p->port);
1875 spin_unlock_irqrestore(&priv->lock, flags);
1876
1877 return 0;
1878 }
1879
1880 static int sci_resume(struct device *dev)
1881 {
1882 struct sh_sci_priv *priv = dev_get_drvdata(dev);
1883 struct sci_port *p;
1884 unsigned long flags;
1885
1886 spin_lock_irqsave(&priv->lock, flags);
1887 list_for_each_entry(p, &priv->ports, node)
1888 uart_resume_port(&sci_uart_driver, &p->port);
1889 spin_unlock_irqrestore(&priv->lock, flags);
1890
1891 return 0;
1892 }
1893
1894 static const struct dev_pm_ops sci_dev_pm_ops = {
1895 .suspend = sci_suspend,
1896 .resume = sci_resume,
1897 };
1898
1899 static struct platform_driver sci_driver = {
1900 .probe = sci_probe,
1901 .remove = sci_remove,
1902 .driver = {
1903 .name = "sh-sci",
1904 .owner = THIS_MODULE,
1905 .pm = &sci_dev_pm_ops,
1906 },
1907 };
1908
1909 static int __init sci_init(void)
1910 {
1911 int ret;
1912
1913 printk(banner);
1914
1915 ret = uart_register_driver(&sci_uart_driver);
1916 if (likely(ret == 0)) {
1917 ret = platform_driver_register(&sci_driver);
1918 if (unlikely(ret))
1919 uart_unregister_driver(&sci_uart_driver);
1920 }
1921
1922 return ret;
1923 }
1924
1925 static void __exit sci_exit(void)
1926 {
1927 platform_driver_unregister(&sci_driver);
1928 uart_unregister_driver(&sci_uart_driver);
1929 }
1930
1931 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1932 early_platform_init_buffer("earlyprintk", &sci_driver,
1933 early_serial_buf, ARRAY_SIZE(early_serial_buf));
1934 #endif
1935 module_init(sci_init);
1936 module_exit(sci_exit);
1937
1938 MODULE_LICENSE("GPL");
1939 MODULE_ALIAS("platform:sh-sci");
kernel source for telekom puls (alcatel/mediatek)