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Blackfin Serial Driver: fix error while transferring large files
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / sh-sci.c
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50
51 #ifdef CONFIG_SUPERH
52 #include <asm/clock.h>
53 #include <asm/sh_bios.h>
54 #endif
55
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port enable callback */
68 void (*enable)(struct uart_port *port);
69
70 /* Port disable callback */
71 void (*disable)(struct uart_port *port);
72
73 /* Break timer */
74 struct timer_list break_timer;
75 int break_flag;
76
77 #ifdef CONFIG_HAVE_CLK
78 /* Port clock */
79 struct clk *clk;
80 #endif
81 };
82
83 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
84 static struct sci_port *serial_console_port;
85 #endif
86
87 /* Function prototypes */
88 static void sci_stop_tx(struct uart_port *port);
89
90 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
91
92 static struct sci_port sci_ports[SCI_NPORTS];
93 static struct uart_driver sci_uart_driver;
94
95 static inline struct sci_port *
96 to_sci_port(struct uart_port *uart)
97 {
98 return container_of(uart, struct sci_port, port);
99 }
100
101 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
102
103 #ifdef CONFIG_CONSOLE_POLL
104 static inline void handle_error(struct uart_port *port)
105 {
106 /* Clear error flags */
107 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
108 }
109
110 static int sci_poll_get_char(struct uart_port *port)
111 {
112 unsigned short status;
113 int c;
114
115 do {
116 status = sci_in(port, SCxSR);
117 if (status & SCxSR_ERRORS(port)) {
118 handle_error(port);
119 continue;
120 }
121 } while (!(status & SCxSR_RDxF(port)));
122
123 c = sci_in(port, SCxRDR);
124
125 /* Dummy read */
126 sci_in(port, SCxSR);
127 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
128
129 return c;
130 }
131 #endif
132
133 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
134 {
135 unsigned short status;
136
137 do {
138 status = sci_in(port, SCxSR);
139 } while (!(status & SCxSR_TDxE(port)));
140
141 sci_in(port, SCxSR); /* Dummy read */
142 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
143 sci_out(port, SCxTDR, c);
144 }
145 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
146
147 #if defined(__H8300S__)
148 enum { sci_disable, sci_enable };
149
150 static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
151 {
152 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
153 int ch = (port->mapbase - SMR0) >> 3;
154 unsigned char mask = 1 << (ch+1);
155
156 if (ctrl == sci_disable)
157 *mstpcrl |= mask;
158 else
159 *mstpcrl &= ~mask;
160 }
161
162 static inline void h8300_sci_enable(struct uart_port *port)
163 {
164 h8300_sci_config(port, sci_enable);
165 }
166
167 static inline void h8300_sci_disable(struct uart_port *port)
168 {
169 h8300_sci_config(port, sci_disable);
170 }
171 #endif
172
173 #if defined(__H8300H__) || defined(__H8300S__)
174 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
175 {
176 int ch = (port->mapbase - SMR0) >> 3;
177
178 /* set DDR regs */
179 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
180 h8300_sci_pins[ch].rx,
181 H8300_GPIO_INPUT);
182 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
183 h8300_sci_pins[ch].tx,
184 H8300_GPIO_OUTPUT);
185
186 /* tx mark output*/
187 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
188 }
189 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
190 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
191 {
192 if (port->mapbase == 0xA4400000) {
193 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
194 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
195 } else if (port->mapbase == 0xA4410000)
196 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
197 }
198 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
199 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
200 {
201 unsigned short data;
202
203 if (cflag & CRTSCTS) {
204 /* enable RTS/CTS */
205 if (port->mapbase == 0xa4430000) { /* SCIF0 */
206 /* Clear PTCR bit 9-2; enable all scif pins but sck */
207 data = __raw_readw(PORT_PTCR);
208 __raw_writew((data & 0xfc03), PORT_PTCR);
209 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
210 /* Clear PVCR bit 9-2 */
211 data = __raw_readw(PORT_PVCR);
212 __raw_writew((data & 0xfc03), PORT_PVCR);
213 }
214 } else {
215 if (port->mapbase == 0xa4430000) { /* SCIF0 */
216 /* Clear PTCR bit 5-2; enable only tx and rx */
217 data = __raw_readw(PORT_PTCR);
218 __raw_writew((data & 0xffc3), PORT_PTCR);
219 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
220 /* Clear PVCR bit 5-2 */
221 data = __raw_readw(PORT_PVCR);
222 __raw_writew((data & 0xffc3), PORT_PVCR);
223 }
224 }
225 }
226 #elif defined(CONFIG_CPU_SH3)
227 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
228 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
229 {
230 unsigned short data;
231
232 /* We need to set SCPCR to enable RTS/CTS */
233 data = __raw_readw(SCPCR);
234 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
235 __raw_writew(data & 0x0fcf, SCPCR);
236
237 if (!(cflag & CRTSCTS)) {
238 /* We need to set SCPCR to enable RTS/CTS */
239 data = __raw_readw(SCPCR);
240 /* Clear out SCP7MD1,0, SCP4MD1,0,
241 Set SCP6MD1,0 = {01} (output) */
242 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
243
244 data = ctrl_inb(SCPDR);
245 /* Set /RTS2 (bit6) = 0 */
246 ctrl_outb(data & 0xbf, SCPDR);
247 }
248 }
249 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
250 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
251 {
252 unsigned short data;
253
254 if (port->mapbase == 0xffe00000) {
255 data = __raw_readw(PSCR);
256 data &= ~0x03cf;
257 if (!(cflag & CRTSCTS))
258 data |= 0x0340;
259
260 __raw_writew(data, PSCR);
261 }
262 }
263 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
266 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
267 defined(CONFIG_CPU_SUBTYPE_SHX3)
268 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
269 {
270 if (!(cflag & CRTSCTS))
271 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
272 }
273 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
274 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
275 {
276 if (!(cflag & CRTSCTS))
277 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
278 }
279 #else
280 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
281 {
282 /* Nothing to do */
283 }
284 #endif
285
286 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
287 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
288 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
289 defined(CONFIG_CPU_SUBTYPE_SH7786)
290 static inline int scif_txroom(struct uart_port *port)
291 {
292 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
293 }
294
295 static inline int scif_rxroom(struct uart_port *port)
296 {
297 return sci_in(port, SCRFDR) & 0xff;
298 }
299 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
300 static inline int scif_txroom(struct uart_port *port)
301 {
302 if ((port->mapbase == 0xffe00000) ||
303 (port->mapbase == 0xffe08000)) {
304 /* SCIF0/1*/
305 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
306 } else {
307 /* SCIF2 */
308 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
309 }
310 }
311
312 static inline int scif_rxroom(struct uart_port *port)
313 {
314 if ((port->mapbase == 0xffe00000) ||
315 (port->mapbase == 0xffe08000)) {
316 /* SCIF0/1*/
317 return sci_in(port, SCRFDR) & 0xff;
318 } else {
319 /* SCIF2 */
320 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
321 }
322 }
323 #else
324 static inline int scif_txroom(struct uart_port *port)
325 {
326 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
327 }
328
329 static inline int scif_rxroom(struct uart_port *port)
330 {
331 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
332 }
333 #endif
334
335 static inline int sci_txroom(struct uart_port *port)
336 {
337 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
338 }
339
340 static inline int sci_rxroom(struct uart_port *port)
341 {
342 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
343 }
344
345 /* ********************************************************************** *
346 * the interrupt related routines *
347 * ********************************************************************** */
348
349 static void sci_transmit_chars(struct uart_port *port)
350 {
351 struct circ_buf *xmit = &port->info->xmit;
352 unsigned int stopped = uart_tx_stopped(port);
353 unsigned short status;
354 unsigned short ctrl;
355 int count;
356
357 status = sci_in(port, SCxSR);
358 if (!(status & SCxSR_TDxE(port))) {
359 ctrl = sci_in(port, SCSCR);
360 if (uart_circ_empty(xmit))
361 ctrl &= ~SCI_CTRL_FLAGS_TIE;
362 else
363 ctrl |= SCI_CTRL_FLAGS_TIE;
364 sci_out(port, SCSCR, ctrl);
365 return;
366 }
367
368 if (port->type == PORT_SCI)
369 count = sci_txroom(port);
370 else
371 count = scif_txroom(port);
372
373 do {
374 unsigned char c;
375
376 if (port->x_char) {
377 c = port->x_char;
378 port->x_char = 0;
379 } else if (!uart_circ_empty(xmit) && !stopped) {
380 c = xmit->buf[xmit->tail];
381 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
382 } else {
383 break;
384 }
385
386 sci_out(port, SCxTDR, c);
387
388 port->icount.tx++;
389 } while (--count > 0);
390
391 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
392
393 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
394 uart_write_wakeup(port);
395 if (uart_circ_empty(xmit)) {
396 sci_stop_tx(port);
397 } else {
398 ctrl = sci_in(port, SCSCR);
399
400 if (port->type != PORT_SCI) {
401 sci_in(port, SCxSR); /* Dummy read */
402 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
403 }
404
405 ctrl |= SCI_CTRL_FLAGS_TIE;
406 sci_out(port, SCSCR, ctrl);
407 }
408 }
409
410 /* On SH3, SCIF may read end-of-break as a space->mark char */
411 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
412
413 static inline void sci_receive_chars(struct uart_port *port)
414 {
415 struct sci_port *sci_port = to_sci_port(port);
416 struct tty_struct *tty = port->info->port.tty;
417 int i, count, copied = 0;
418 unsigned short status;
419 unsigned char flag;
420
421 status = sci_in(port, SCxSR);
422 if (!(status & SCxSR_RDxF(port)))
423 return;
424
425 while (1) {
426 if (port->type == PORT_SCI)
427 count = sci_rxroom(port);
428 else
429 count = scif_rxroom(port);
430
431 /* Don't copy more bytes than there is room for in the buffer */
432 count = tty_buffer_request_room(tty, count);
433
434 /* If for any reason we can't copy more data, we're done! */
435 if (count == 0)
436 break;
437
438 if (port->type == PORT_SCI) {
439 char c = sci_in(port, SCxRDR);
440 if (uart_handle_sysrq_char(port, c) ||
441 sci_port->break_flag)
442 count = 0;
443 else
444 tty_insert_flip_char(tty, c, TTY_NORMAL);
445 } else {
446 for (i = 0; i < count; i++) {
447 char c = sci_in(port, SCxRDR);
448 status = sci_in(port, SCxSR);
449 #if defined(CONFIG_CPU_SH3)
450 /* Skip "chars" during break */
451 if (sci_port->break_flag) {
452 if ((c == 0) &&
453 (status & SCxSR_FER(port))) {
454 count--; i--;
455 continue;
456 }
457
458 /* Nonzero => end-of-break */
459 dev_dbg(port->dev, "debounce<%02x>\n", c);
460 sci_port->break_flag = 0;
461
462 if (STEPFN(c)) {
463 count--; i--;
464 continue;
465 }
466 }
467 #endif /* CONFIG_CPU_SH3 */
468 if (uart_handle_sysrq_char(port, c)) {
469 count--; i--;
470 continue;
471 }
472
473 /* Store data and status */
474 if (status&SCxSR_FER(port)) {
475 flag = TTY_FRAME;
476 dev_notice(port->dev, "frame error\n");
477 } else if (status&SCxSR_PER(port)) {
478 flag = TTY_PARITY;
479 dev_notice(port->dev, "parity error\n");
480 } else
481 flag = TTY_NORMAL;
482
483 tty_insert_flip_char(tty, c, flag);
484 }
485 }
486
487 sci_in(port, SCxSR); /* dummy read */
488 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
489
490 copied += count;
491 port->icount.rx += count;
492 }
493
494 if (copied) {
495 /* Tell the rest of the system the news. New characters! */
496 tty_flip_buffer_push(tty);
497 } else {
498 sci_in(port, SCxSR); /* dummy read */
499 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
500 }
501 }
502
503 #define SCI_BREAK_JIFFIES (HZ/20)
504 /* The sci generates interrupts during the break,
505 * 1 per millisecond or so during the break period, for 9600 baud.
506 * So dont bother disabling interrupts.
507 * But dont want more than 1 break event.
508 * Use a kernel timer to periodically poll the rx line until
509 * the break is finished.
510 */
511 static void sci_schedule_break_timer(struct sci_port *port)
512 {
513 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
514 add_timer(&port->break_timer);
515 }
516 /* Ensure that two consecutive samples find the break over. */
517 static void sci_break_timer(unsigned long data)
518 {
519 struct sci_port *port = (struct sci_port *)data;
520
521 if (sci_rxd_in(&port->port) == 0) {
522 port->break_flag = 1;
523 sci_schedule_break_timer(port);
524 } else if (port->break_flag == 1) {
525 /* break is over. */
526 port->break_flag = 2;
527 sci_schedule_break_timer(port);
528 } else
529 port->break_flag = 0;
530 }
531
532 static inline int sci_handle_errors(struct uart_port *port)
533 {
534 int copied = 0;
535 unsigned short status = sci_in(port, SCxSR);
536 struct tty_struct *tty = port->info->port.tty;
537
538 if (status & SCxSR_ORER(port)) {
539 /* overrun error */
540 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
541 copied++;
542
543 dev_notice(port->dev, "overrun error");
544 }
545
546 if (status & SCxSR_FER(port)) {
547 if (sci_rxd_in(port) == 0) {
548 /* Notify of BREAK */
549 struct sci_port *sci_port = to_sci_port(port);
550
551 if (!sci_port->break_flag) {
552 sci_port->break_flag = 1;
553 sci_schedule_break_timer(sci_port);
554
555 /* Do sysrq handling. */
556 if (uart_handle_break(port))
557 return 0;
558
559 dev_dbg(port->dev, "BREAK detected\n");
560
561 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
562 copied++;
563 }
564
565 } else {
566 /* frame error */
567 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
568 copied++;
569
570 dev_notice(port->dev, "frame error\n");
571 }
572 }
573
574 if (status & SCxSR_PER(port)) {
575 /* parity error */
576 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
577 copied++;
578
579 dev_notice(port->dev, "parity error");
580 }
581
582 if (copied)
583 tty_flip_buffer_push(tty);
584
585 return copied;
586 }
587
588 static inline int sci_handle_fifo_overrun(struct uart_port *port)
589 {
590 struct tty_struct *tty = port->info->port.tty;
591 int copied = 0;
592
593 if (port->type != PORT_SCIF)
594 return 0;
595
596 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
597 sci_out(port, SCLSR, 0);
598
599 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
600 tty_flip_buffer_push(tty);
601
602 dev_notice(port->dev, "overrun error\n");
603 copied++;
604 }
605
606 return copied;
607 }
608
609 static inline int sci_handle_breaks(struct uart_port *port)
610 {
611 int copied = 0;
612 unsigned short status = sci_in(port, SCxSR);
613 struct tty_struct *tty = port->info->port.tty;
614 struct sci_port *s = &sci_ports[port->line];
615
616 if (uart_handle_break(port))
617 return 0;
618
619 if (!s->break_flag && status & SCxSR_BRK(port)) {
620 #if defined(CONFIG_CPU_SH3)
621 /* Debounce break */
622 s->break_flag = 1;
623 #endif
624 /* Notify of BREAK */
625 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
626 copied++;
627
628 dev_dbg(port->dev, "BREAK detected\n");
629 }
630
631 if (copied)
632 tty_flip_buffer_push(tty);
633
634 copied += sci_handle_fifo_overrun(port);
635
636 return copied;
637 }
638
639 static irqreturn_t sci_rx_interrupt(int irq, void *port)
640 {
641 /* I think sci_receive_chars has to be called irrespective
642 * of whether the I_IXOFF is set, otherwise, how is the interrupt
643 * to be disabled?
644 */
645 sci_receive_chars(port);
646
647 return IRQ_HANDLED;
648 }
649
650 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
651 {
652 struct uart_port *port = ptr;
653
654 spin_lock_irq(&port->lock);
655 sci_transmit_chars(port);
656 spin_unlock_irq(&port->lock);
657
658 return IRQ_HANDLED;
659 }
660
661 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
662 {
663 struct uart_port *port = ptr;
664
665 /* Handle errors */
666 if (port->type == PORT_SCI) {
667 if (sci_handle_errors(port)) {
668 /* discard character in rx buffer */
669 sci_in(port, SCxSR);
670 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
671 }
672 } else {
673 sci_handle_fifo_overrun(port);
674 sci_rx_interrupt(irq, ptr);
675 }
676
677 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
678
679 /* Kick the transmission */
680 sci_tx_interrupt(irq, ptr);
681
682 return IRQ_HANDLED;
683 }
684
685 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
686 {
687 struct uart_port *port = ptr;
688
689 /* Handle BREAKs */
690 sci_handle_breaks(port);
691 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
692
693 return IRQ_HANDLED;
694 }
695
696 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
697 {
698 unsigned short ssr_status, scr_status;
699 struct uart_port *port = ptr;
700 irqreturn_t ret = IRQ_NONE;
701
702 ssr_status = sci_in(port, SCxSR);
703 scr_status = sci_in(port, SCSCR);
704
705 /* Tx Interrupt */
706 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
707 ret = sci_tx_interrupt(irq, ptr);
708 /* Rx Interrupt */
709 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
710 ret = sci_rx_interrupt(irq, ptr);
711 /* Error Interrupt */
712 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
713 ret = sci_er_interrupt(irq, ptr);
714 /* Break Interrupt */
715 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
716 ret = sci_br_interrupt(irq, ptr);
717
718 return ret;
719 }
720
721 #ifdef CONFIG_HAVE_CLK
722 /*
723 * Here we define a transistion notifier so that we can update all of our
724 * ports' baud rate when the peripheral clock changes.
725 */
726 static int sci_notifier(struct notifier_block *self,
727 unsigned long phase, void *p)
728 {
729 int i;
730
731 if ((phase == CPUFREQ_POSTCHANGE) ||
732 (phase == CPUFREQ_RESUMECHANGE))
733 for (i = 0; i < SCI_NPORTS; i++) {
734 struct sci_port *s = &sci_ports[i];
735 s->port.uartclk = clk_get_rate(s->clk);
736 }
737
738 return NOTIFY_OK;
739 }
740
741 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
742 #endif
743
744 static int sci_request_irq(struct sci_port *port)
745 {
746 int i;
747 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
748 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
749 sci_br_interrupt,
750 };
751 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
752 "SCI Transmit Data Empty", "SCI Break" };
753
754 if (port->irqs[0] == port->irqs[1]) {
755 if (unlikely(!port->irqs[0]))
756 return -ENODEV;
757
758 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
759 IRQF_DISABLED, "sci", port)) {
760 dev_err(port->port.dev, "Can't allocate IRQ\n");
761 return -ENODEV;
762 }
763 } else {
764 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
765 if (unlikely(!port->irqs[i]))
766 continue;
767
768 if (request_irq(port->irqs[i], handlers[i],
769 IRQF_DISABLED, desc[i], port)) {
770 dev_err(port->port.dev, "Can't allocate IRQ\n");
771 return -ENODEV;
772 }
773 }
774 }
775
776 return 0;
777 }
778
779 static void sci_free_irq(struct sci_port *port)
780 {
781 int i;
782
783 if (port->irqs[0] == port->irqs[1])
784 free_irq(port->irqs[0], port);
785 else {
786 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
787 if (!port->irqs[i])
788 continue;
789
790 free_irq(port->irqs[i], port);
791 }
792 }
793 }
794
795 static unsigned int sci_tx_empty(struct uart_port *port)
796 {
797 /* Can't detect */
798 return TIOCSER_TEMT;
799 }
800
801 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
802 {
803 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
804 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
805 /* If you have signals for DTR and DCD, please implement here. */
806 }
807
808 static unsigned int sci_get_mctrl(struct uart_port *port)
809 {
810 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
811 and CTS/RTS */
812
813 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
814 }
815
816 static void sci_start_tx(struct uart_port *port)
817 {
818 unsigned short ctrl;
819
820 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
821 ctrl = sci_in(port, SCSCR);
822 ctrl |= SCI_CTRL_FLAGS_TIE;
823 sci_out(port, SCSCR, ctrl);
824 }
825
826 static void sci_stop_tx(struct uart_port *port)
827 {
828 unsigned short ctrl;
829
830 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
831 ctrl = sci_in(port, SCSCR);
832 ctrl &= ~SCI_CTRL_FLAGS_TIE;
833 sci_out(port, SCSCR, ctrl);
834 }
835
836 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
837 {
838 unsigned short ctrl;
839
840 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
841 ctrl = sci_in(port, SCSCR);
842 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
843 sci_out(port, SCSCR, ctrl);
844 }
845
846 static void sci_stop_rx(struct uart_port *port)
847 {
848 unsigned short ctrl;
849
850 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
851 ctrl = sci_in(port, SCSCR);
852 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
853 sci_out(port, SCSCR, ctrl);
854 }
855
856 static void sci_enable_ms(struct uart_port *port)
857 {
858 /* Nothing here yet .. */
859 }
860
861 static void sci_break_ctl(struct uart_port *port, int break_state)
862 {
863 /* Nothing here yet .. */
864 }
865
866 static int sci_startup(struct uart_port *port)
867 {
868 struct sci_port *s = &sci_ports[port->line];
869
870 if (s->enable)
871 s->enable(port);
872
873 #ifdef CONFIG_HAVE_CLK
874 s->clk = clk_get(NULL, "module_clk");
875 #endif
876
877 sci_request_irq(s);
878 sci_start_tx(port);
879 sci_start_rx(port, 1);
880
881 return 0;
882 }
883
884 static void sci_shutdown(struct uart_port *port)
885 {
886 struct sci_port *s = &sci_ports[port->line];
887
888 sci_stop_rx(port);
889 sci_stop_tx(port);
890 sci_free_irq(s);
891
892 if (s->disable)
893 s->disable(port);
894
895 #ifdef CONFIG_HAVE_CLK
896 clk_put(s->clk);
897 s->clk = NULL;
898 #endif
899 }
900
901 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
902 struct ktermios *old)
903 {
904 unsigned int status, baud, smr_val;
905 int t = -1;
906
907 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
908 if (likely(baud))
909 t = SCBRR_VALUE(baud, port->uartclk);
910
911 do {
912 status = sci_in(port, SCxSR);
913 } while (!(status & SCxSR_TEND(port)));
914
915 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
916
917 if (port->type != PORT_SCI)
918 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
919
920 smr_val = sci_in(port, SCSMR) & 3;
921 if ((termios->c_cflag & CSIZE) == CS7)
922 smr_val |= 0x40;
923 if (termios->c_cflag & PARENB)
924 smr_val |= 0x20;
925 if (termios->c_cflag & PARODD)
926 smr_val |= 0x30;
927 if (termios->c_cflag & CSTOPB)
928 smr_val |= 0x08;
929
930 uart_update_timeout(port, termios->c_cflag, baud);
931
932 sci_out(port, SCSMR, smr_val);
933
934 if (t > 0) {
935 if (t >= 256) {
936 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
937 t >>= 2;
938 } else
939 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
940
941 sci_out(port, SCBRR, t);
942 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
943 }
944
945 sci_init_pins(port, termios->c_cflag);
946 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
947
948 sci_out(port, SCSCR, SCSCR_INIT(port));
949
950 if ((termios->c_cflag & CREAD) != 0)
951 sci_start_rx(port, 0);
952 }
953
954 static const char *sci_type(struct uart_port *port)
955 {
956 switch (port->type) {
957 case PORT_IRDA:
958 return "irda";
959 case PORT_SCI:
960 return "sci";
961 case PORT_SCIF:
962 return "scif";
963 case PORT_SCIFA:
964 return "scifa";
965 }
966
967 return NULL;
968 }
969
970 static void sci_release_port(struct uart_port *port)
971 {
972 /* Nothing here yet .. */
973 }
974
975 static int sci_request_port(struct uart_port *port)
976 {
977 /* Nothing here yet .. */
978 return 0;
979 }
980
981 static void sci_config_port(struct uart_port *port, int flags)
982 {
983 struct sci_port *s = &sci_ports[port->line];
984
985 port->type = s->type;
986
987 if (port->flags & UPF_IOREMAP && !port->membase) {
988 #if defined(CONFIG_SUPERH64)
989 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
990 port->membase = (void __iomem *)port->mapbase;
991 #else
992 port->membase = ioremap_nocache(port->mapbase, 0x40);
993 #endif
994
995 dev_err(port->dev, "can't remap port#%d\n", port->line);
996 }
997 }
998
999 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1000 {
1001 struct sci_port *s = &sci_ports[port->line];
1002
1003 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1004 return -EINVAL;
1005 if (ser->baud_base < 2400)
1006 /* No paper tape reader for Mitch.. */
1007 return -EINVAL;
1008
1009 return 0;
1010 }
1011
1012 static struct uart_ops sci_uart_ops = {
1013 .tx_empty = sci_tx_empty,
1014 .set_mctrl = sci_set_mctrl,
1015 .get_mctrl = sci_get_mctrl,
1016 .start_tx = sci_start_tx,
1017 .stop_tx = sci_stop_tx,
1018 .stop_rx = sci_stop_rx,
1019 .enable_ms = sci_enable_ms,
1020 .break_ctl = sci_break_ctl,
1021 .startup = sci_startup,
1022 .shutdown = sci_shutdown,
1023 .set_termios = sci_set_termios,
1024 .type = sci_type,
1025 .release_port = sci_release_port,
1026 .request_port = sci_request_port,
1027 .config_port = sci_config_port,
1028 .verify_port = sci_verify_port,
1029 #ifdef CONFIG_CONSOLE_POLL
1030 .poll_get_char = sci_poll_get_char,
1031 .poll_put_char = sci_poll_put_char,
1032 #endif
1033 };
1034
1035 static void __init sci_init_ports(void)
1036 {
1037 static int first = 1;
1038 int i;
1039
1040 if (!first)
1041 return;
1042
1043 first = 0;
1044
1045 for (i = 0; i < SCI_NPORTS; i++) {
1046 sci_ports[i].port.ops = &sci_uart_ops;
1047 sci_ports[i].port.iotype = UPIO_MEM;
1048 sci_ports[i].port.line = i;
1049 sci_ports[i].port.fifosize = 1;
1050
1051 #if defined(__H8300H__) || defined(__H8300S__)
1052 #ifdef __H8300S__
1053 sci_ports[i].enable = h8300_sci_enable;
1054 sci_ports[i].disable = h8300_sci_disable;
1055 #endif
1056 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1057 #elif defined(CONFIG_HAVE_CLK)
1058 /*
1059 * XXX: We should use a proper SCI/SCIF clock
1060 */
1061 {
1062 struct clk *clk = clk_get(NULL, "module_clk");
1063 sci_ports[i].port.uartclk = clk_get_rate(clk);
1064 clk_put(clk);
1065 }
1066 #else
1067 #error "Need a valid uartclk"
1068 #endif
1069
1070 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1071 sci_ports[i].break_timer.function = sci_break_timer;
1072
1073 init_timer(&sci_ports[i].break_timer);
1074 }
1075 }
1076
1077 int __init early_sci_setup(struct uart_port *port)
1078 {
1079 if (unlikely(port->line > SCI_NPORTS))
1080 return -ENODEV;
1081
1082 sci_init_ports();
1083
1084 sci_ports[port->line].port.membase = port->membase;
1085 sci_ports[port->line].port.mapbase = port->mapbase;
1086 sci_ports[port->line].port.type = port->type;
1087
1088 return 0;
1089 }
1090
1091 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1092 /*
1093 * Print a string to the serial port trying not to disturb
1094 * any possible real use of the port...
1095 */
1096 static void serial_console_write(struct console *co, const char *s,
1097 unsigned count)
1098 {
1099 struct uart_port *port = &serial_console_port->port;
1100 unsigned short bits;
1101 int i;
1102
1103 for (i = 0; i < count; i++) {
1104 if (*s == 10)
1105 sci_poll_put_char(port, '\r');
1106
1107 sci_poll_put_char(port, *s++);
1108 }
1109
1110 /* wait until fifo is empty and last bit has been transmitted */
1111 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1112 while ((sci_in(port, SCxSR) & bits) != bits)
1113 cpu_relax();
1114 }
1115
1116 static int __init serial_console_setup(struct console *co, char *options)
1117 {
1118 struct uart_port *port;
1119 int baud = 115200;
1120 int bits = 8;
1121 int parity = 'n';
1122 int flow = 'n';
1123 int ret;
1124
1125 /*
1126 * Check whether an invalid uart number has been specified, and
1127 * if so, search for the first available port that does have
1128 * console support.
1129 */
1130 if (co->index >= SCI_NPORTS)
1131 co->index = 0;
1132
1133 serial_console_port = &sci_ports[co->index];
1134 port = &serial_console_port->port;
1135
1136 /*
1137 * Also need to check port->type, we don't actually have any
1138 * UPIO_PORT ports, but uart_report_port() handily misreports
1139 * it anyways if we don't have a port available by the time this is
1140 * called.
1141 */
1142 if (!port->type)
1143 return -ENODEV;
1144 if (!port->membase || !port->mapbase)
1145 return -ENODEV;
1146
1147 port->type = serial_console_port->type;
1148
1149 #ifdef CONFIG_HAVE_CLK
1150 if (!serial_console_port->clk)
1151 serial_console_port->clk = clk_get(NULL, "module_clk");
1152 #endif
1153
1154 if (port->flags & UPF_IOREMAP)
1155 sci_config_port(port, 0);
1156
1157 if (serial_console_port->enable)
1158 serial_console_port->enable(port);
1159
1160 if (options)
1161 uart_parse_options(options, &baud, &parity, &bits, &flow);
1162
1163 ret = uart_set_options(port, co, baud, parity, bits, flow);
1164 #if defined(__H8300H__) || defined(__H8300S__)
1165 /* disable rx interrupt */
1166 if (ret == 0)
1167 sci_stop_rx(port);
1168 #endif
1169 return ret;
1170 }
1171
1172 static struct console serial_console = {
1173 .name = "ttySC",
1174 .device = uart_console_device,
1175 .write = serial_console_write,
1176 .setup = serial_console_setup,
1177 .flags = CON_PRINTBUFFER,
1178 .index = -1,
1179 .data = &sci_uart_driver,
1180 };
1181
1182 static int __init sci_console_init(void)
1183 {
1184 sci_init_ports();
1185 register_console(&serial_console);
1186 return 0;
1187 }
1188 console_initcall(sci_console_init);
1189 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1190
1191 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1192 #define SCI_CONSOLE (&serial_console)
1193 #else
1194 #define SCI_CONSOLE 0
1195 #endif
1196
1197 static char banner[] __initdata =
1198 KERN_INFO "SuperH SCI(F) driver initialized\n";
1199
1200 static struct uart_driver sci_uart_driver = {
1201 .owner = THIS_MODULE,
1202 .driver_name = "sci",
1203 .dev_name = "ttySC",
1204 .major = SCI_MAJOR,
1205 .minor = SCI_MINOR_START,
1206 .nr = SCI_NPORTS,
1207 .cons = SCI_CONSOLE,
1208 };
1209
1210 /*
1211 * Register a set of serial devices attached to a platform device. The
1212 * list is terminated with a zero flags entry, which means we expect
1213 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1214 * remapping (such as sh64) should also set UPF_IOREMAP.
1215 */
1216 static int __devinit sci_probe(struct platform_device *dev)
1217 {
1218 struct plat_sci_port *p = dev->dev.platform_data;
1219 int i, ret = -EINVAL;
1220
1221 for (i = 0; p && p->flags != 0; p++, i++) {
1222 struct sci_port *sciport = &sci_ports[i];
1223
1224 /* Sanity check */
1225 if (unlikely(i == SCI_NPORTS)) {
1226 dev_notice(&dev->dev, "Attempting to register port "
1227 "%d when only %d are available.\n",
1228 i+1, SCI_NPORTS);
1229 dev_notice(&dev->dev, "Consider bumping "
1230 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1231 break;
1232 }
1233
1234 sciport->port.mapbase = p->mapbase;
1235
1236 if (p->mapbase && !p->membase) {
1237 if (p->flags & UPF_IOREMAP) {
1238 p->membase = ioremap_nocache(p->mapbase, 0x40);
1239 if (IS_ERR(p->membase)) {
1240 ret = PTR_ERR(p->membase);
1241 goto err_unreg;
1242 }
1243 } else {
1244 /*
1245 * For the simple (and majority of) cases
1246 * where we don't need to do any remapping,
1247 * just cast the cookie directly.
1248 */
1249 p->membase = (void __iomem *)p->mapbase;
1250 }
1251 }
1252
1253 sciport->port.membase = p->membase;
1254
1255 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1256 sciport->port.flags = p->flags;
1257 sciport->port.dev = &dev->dev;
1258
1259 sciport->type = sciport->port.type = p->type;
1260
1261 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1262
1263 uart_add_one_port(&sci_uart_driver, &sciport->port);
1264 }
1265
1266 #ifdef CONFIG_HAVE_CLK
1267 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1268 #endif
1269
1270 #ifdef CONFIG_SH_STANDARD_BIOS
1271 sh_bios_gdb_detach();
1272 #endif
1273
1274 return 0;
1275
1276 err_unreg:
1277 for (i = i - 1; i >= 0; i--)
1278 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1279
1280 return ret;
1281 }
1282
1283 static int __devexit sci_remove(struct platform_device *dev)
1284 {
1285 int i;
1286
1287 #ifdef CONFIG_HAVE_CLK
1288 cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1289 #endif
1290
1291 for (i = 0; i < SCI_NPORTS; i++)
1292 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1293
1294 return 0;
1295 }
1296
1297 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1298 {
1299 int i;
1300
1301 for (i = 0; i < SCI_NPORTS; i++) {
1302 struct sci_port *p = &sci_ports[i];
1303
1304 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1305 uart_suspend_port(&sci_uart_driver, &p->port);
1306 }
1307
1308 return 0;
1309 }
1310
1311 static int sci_resume(struct platform_device *dev)
1312 {
1313 int i;
1314
1315 for (i = 0; i < SCI_NPORTS; i++) {
1316 struct sci_port *p = &sci_ports[i];
1317
1318 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1319 uart_resume_port(&sci_uart_driver, &p->port);
1320 }
1321
1322 return 0;
1323 }
1324
1325 static struct platform_driver sci_driver = {
1326 .probe = sci_probe,
1327 .remove = __devexit_p(sci_remove),
1328 .suspend = sci_suspend,
1329 .resume = sci_resume,
1330 .driver = {
1331 .name = "sh-sci",
1332 .owner = THIS_MODULE,
1333 },
1334 };
1335
1336 static int __init sci_init(void)
1337 {
1338 int ret;
1339
1340 printk(banner);
1341
1342 sci_init_ports();
1343
1344 ret = uart_register_driver(&sci_uart_driver);
1345 if (likely(ret == 0)) {
1346 ret = platform_driver_register(&sci_driver);
1347 if (unlikely(ret))
1348 uart_unregister_driver(&sci_uart_driver);
1349 }
1350
1351 return ret;
1352 }
1353
1354 static void __exit sci_exit(void)
1355 {
1356 platform_driver_unregister(&sci_driver);
1357 uart_unregister_driver(&sci_uart_driver);
1358 }
1359
1360 module_init(sci_init);
1361 module_exit(sci_exit);
1362
1363 MODULE_LICENSE("GPL");
1364 MODULE_ALIAS("platform:sh-sci");
kernel source for telekom puls (alcatel/mediatek)