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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / s3c2410.c
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75
76 #include <asm/io.h>
77 #include <asm/irq.h>
78
79 #include <asm/hardware.h>
80 #include <asm/hardware/clock.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 #include <asm/mach-types.h>
86
87 /* structures */
88
89 struct s3c24xx_uart_info {
90 char *name;
91 unsigned int type;
92 unsigned int fifosize;
93 unsigned long rx_fifomask;
94 unsigned long rx_fifoshift;
95 unsigned long rx_fifofull;
96 unsigned long tx_fifomask;
97 unsigned long tx_fifoshift;
98 unsigned long tx_fifofull;
99
100 /* clock source control */
101
102 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
103 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
104
105 /* uart controls */
106 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
107 };
108
109 struct s3c24xx_uart_port {
110 unsigned char rx_claimed;
111 unsigned char tx_claimed;
112
113 struct s3c24xx_uart_info *info;
114 struct s3c24xx_uart_clksrc *clksrc;
115 struct clk *clk;
116 struct clk *baudclk;
117 struct uart_port port;
118 };
119
120
121 /* configuration defines */
122
123 #if 0
124 #if 1
125 /* send debug to the low-level output routines */
126
127 extern void printascii(const char *);
128
129 static void
130 s3c24xx_serial_dbg(const char *fmt, ...)
131 {
132 va_list va;
133 char buff[256];
134
135 va_start(va, fmt);
136 vsprintf(buff, fmt, va);
137 va_end(va);
138
139 printascii(buff);
140 }
141
142 #define dbg(x...) s3c24xx_serial_dbg(x)
143
144 #else
145 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
146 #endif
147 #else /* no debug */
148 #define dbg(x...) do {} while(0)
149 #endif
150
151 /* UART name and device definitions */
152
153 #define S3C24XX_SERIAL_NAME "ttySAC"
154 #define S3C24XX_SERIAL_DEVFS "tts/"
155 #define S3C24XX_SERIAL_MAJOR 204
156 #define S3C24XX_SERIAL_MINOR 64
157
158
159 /* conversion functions */
160
161 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
162 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
163
164 /* we can support 3 uarts, but not always use them */
165
166 #define NR_PORTS (3)
167
168 /* port irq numbers */
169
170 #define TX_IRQ(port) ((port)->irq + 1)
171 #define RX_IRQ(port) ((port)->irq)
172
173 /* register access controls */
174
175 #define portaddr(port, reg) ((port)->membase + (reg))
176
177 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
178 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
179
180 #define wr_regb(port, reg, val) \
181 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
182
183 #define wr_regl(port, reg, val) \
184 do { __raw_writel(val, portaddr(port, reg)); } while(0)
185
186 /* macros to change one thing to another */
187
188 #define tx_enabled(port) ((port)->unused[0])
189 #define rx_enabled(port) ((port)->unused[1])
190
191 /* flag to ignore all characters comming in */
192 #define RXSTAT_DUMMY_READ (0x10000000)
193
194 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
195 {
196 return container_of(port, struct s3c24xx_uart_port, port);
197 }
198
199 /* translate a port to the device name */
200
201 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
202 {
203 return to_platform_device(port->dev)->name;
204 }
205
206 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
207 {
208 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
209 }
210
211 static void s3c24xx_serial_rx_enable(struct uart_port *port)
212 {
213 unsigned long flags;
214 unsigned int ucon, ufcon;
215 int count = 10000;
216
217 spin_lock_irqsave(&port->lock, flags);
218
219 while (--count && !s3c24xx_serial_txempty_nofifo(port))
220 udelay(100);
221
222 ufcon = rd_regl(port, S3C2410_UFCON);
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
225
226 ucon = rd_regl(port, S3C2410_UCON);
227 ucon |= S3C2410_UCON_RXIRQMODE;
228 wr_regl(port, S3C2410_UCON, ucon);
229
230 rx_enabled(port) = 1;
231 spin_unlock_irqrestore(&port->lock, flags);
232 }
233
234 static void s3c24xx_serial_rx_disable(struct uart_port *port)
235 {
236 unsigned long flags;
237 unsigned int ucon;
238
239 spin_lock_irqsave(&port->lock, flags);
240
241 ucon = rd_regl(port, S3C2410_UCON);
242 ucon &= ~S3C2410_UCON_RXIRQMODE;
243 wr_regl(port, S3C2410_UCON, ucon);
244
245 rx_enabled(port) = 0;
246 spin_unlock_irqrestore(&port->lock, flags);
247 }
248
249 static void s3c24xx_serial_stop_tx(struct uart_port *port)
250 {
251 if (tx_enabled(port)) {
252 disable_irq(TX_IRQ(port));
253 tx_enabled(port) = 0;
254 if (port->flags & UPF_CONS_FLOW)
255 s3c24xx_serial_rx_enable(port);
256 }
257 }
258
259 static void s3c24xx_serial_start_tx(struct uart_port *port)
260 {
261 if (!tx_enabled(port)) {
262 if (port->flags & UPF_CONS_FLOW)
263 s3c24xx_serial_rx_disable(port);
264
265 enable_irq(TX_IRQ(port));
266 tx_enabled(port) = 1;
267 }
268 }
269
270
271 static void s3c24xx_serial_stop_rx(struct uart_port *port)
272 {
273 if (rx_enabled(port)) {
274 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
275 disable_irq(RX_IRQ(port));
276 rx_enabled(port) = 0;
277 }
278 }
279
280 static void s3c24xx_serial_enable_ms(struct uart_port *port)
281 {
282 }
283
284 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
285 {
286 return to_ourport(port)->info;
287 }
288
289 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
290 {
291 if (port->dev == NULL)
292 return NULL;
293
294 return (struct s3c2410_uartcfg *)port->dev->platform_data;
295 }
296
297 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
298 unsigned long ufstat)
299 {
300 struct s3c24xx_uart_info *info = ourport->info;
301
302 if (ufstat & info->rx_fifofull)
303 return info->fifosize;
304
305 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
306 }
307
308
309 /* ? - where has parity gone?? */
310 #define S3C2410_UERSTAT_PARITY (0x1000)
311
312 static irqreturn_t
313 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
314 {
315 struct s3c24xx_uart_port *ourport = dev_id;
316 struct uart_port *port = &ourport->port;
317 struct tty_struct *tty = port->info->tty;
318 unsigned int ufcon, ch, flag, ufstat, uerstat;
319 int max_count = 64;
320
321 while (max_count-- > 0) {
322 ufcon = rd_regl(port, S3C2410_UFCON);
323 ufstat = rd_regl(port, S3C2410_UFSTAT);
324
325 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
326 break;
327
328 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
329 if (tty->low_latency)
330 tty_flip_buffer_push(tty);
331
332 /*
333 * If this failed then we will throw away the
334 * bytes but must do so to clear interrupts
335 */
336 }
337
338 uerstat = rd_regl(port, S3C2410_UERSTAT);
339 ch = rd_regb(port, S3C2410_URXH);
340
341 if (port->flags & UPF_CONS_FLOW) {
342 int txe = s3c24xx_serial_txempty_nofifo(port);
343
344 if (rx_enabled(port)) {
345 if (!txe) {
346 rx_enabled(port) = 0;
347 continue;
348 }
349 } else {
350 if (txe) {
351 ufcon |= S3C2410_UFCON_RESETRX;
352 wr_regl(port, S3C2410_UFCON, ufcon);
353 rx_enabled(port) = 1;
354 goto out;
355 }
356 continue;
357 }
358 }
359
360 /* insert the character into the buffer */
361
362 flag = TTY_NORMAL;
363 port->icount.rx++;
364
365 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
366 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
367 ch, uerstat);
368
369 /* check for break */
370 if (uerstat & S3C2410_UERSTAT_BREAK) {
371 dbg("break!\n");
372 port->icount.brk++;
373 if (uart_handle_break(port))
374 goto ignore_char;
375 }
376
377 if (uerstat & S3C2410_UERSTAT_FRAME)
378 port->icount.frame++;
379 if (uerstat & S3C2410_UERSTAT_OVERRUN)
380 port->icount.overrun++;
381
382 uerstat &= port->read_status_mask;
383
384 if (uerstat & S3C2410_UERSTAT_BREAK)
385 flag = TTY_BREAK;
386 else if (uerstat & S3C2410_UERSTAT_PARITY)
387 flag = TTY_PARITY;
388 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
389 flag = TTY_FRAME;
390 }
391
392 if (uart_handle_sysrq_char(port, ch, regs))
393 goto ignore_char;
394
395 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
396
397 ignore_char:
398 continue;
399 }
400 tty_flip_buffer_push(tty);
401
402 out:
403 return IRQ_HANDLED;
404 }
405
406 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
407 {
408 struct s3c24xx_uart_port *ourport = id;
409 struct uart_port *port = &ourport->port;
410 struct circ_buf *xmit = &port->info->xmit;
411 int count = 256;
412
413 if (port->x_char) {
414 wr_regb(port, S3C2410_UTXH, port->x_char);
415 port->icount.tx++;
416 port->x_char = 0;
417 goto out;
418 }
419
420 /* if there isnt anything more to transmit, or the uart is now
421 * stopped, disable the uart and exit
422 */
423
424 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
425 s3c24xx_serial_stop_tx(port);
426 goto out;
427 }
428
429 /* try and drain the buffer... */
430
431 while (!uart_circ_empty(xmit) && count-- > 0) {
432 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
433 break;
434
435 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
436 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
437 port->icount.tx++;
438 }
439
440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
441 uart_write_wakeup(port);
442
443 if (uart_circ_empty(xmit))
444 s3c24xx_serial_stop_tx(port);
445
446 out:
447 return IRQ_HANDLED;
448 }
449
450 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
451 {
452 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
453 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
454 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
455
456 if (ufcon & S3C2410_UFCON_FIFOMODE) {
457 if ((ufstat & info->tx_fifomask) != 0 ||
458 (ufstat & info->tx_fifofull))
459 return 0;
460
461 return 1;
462 }
463
464 return s3c24xx_serial_txempty_nofifo(port);
465 }
466
467 /* no modem control lines */
468 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
469 {
470 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
471
472 if (umstat & S3C2410_UMSTAT_CTS)
473 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
474 else
475 return TIOCM_CAR | TIOCM_DSR;
476 }
477
478 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
479 {
480 /* todo - possibly remove AFC and do manual CTS */
481 }
482
483 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
484 {
485 unsigned long flags;
486 unsigned int ucon;
487
488 spin_lock_irqsave(&port->lock, flags);
489
490 ucon = rd_regl(port, S3C2410_UCON);
491
492 if (break_state)
493 ucon |= S3C2410_UCON_SBREAK;
494 else
495 ucon &= ~S3C2410_UCON_SBREAK;
496
497 wr_regl(port, S3C2410_UCON, ucon);
498
499 spin_unlock_irqrestore(&port->lock, flags);
500 }
501
502 static void s3c24xx_serial_shutdown(struct uart_port *port)
503 {
504 struct s3c24xx_uart_port *ourport = to_ourport(port);
505
506 if (ourport->tx_claimed) {
507 free_irq(TX_IRQ(port), ourport);
508 tx_enabled(port) = 0;
509 ourport->tx_claimed = 0;
510 }
511
512 if (ourport->rx_claimed) {
513 free_irq(RX_IRQ(port), ourport);
514 ourport->rx_claimed = 0;
515 rx_enabled(port) = 0;
516 }
517 }
518
519
520 static int s3c24xx_serial_startup(struct uart_port *port)
521 {
522 struct s3c24xx_uart_port *ourport = to_ourport(port);
523 int ret;
524
525 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
526 port->mapbase, port->membase);
527
528 rx_enabled(port) = 1;
529
530 ret = request_irq(RX_IRQ(port),
531 s3c24xx_serial_rx_chars, 0,
532 s3c24xx_serial_portname(port), ourport);
533
534 if (ret != 0) {
535 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
536 return ret;
537 }
538
539 ourport->rx_claimed = 1;
540
541 dbg("requesting tx irq...\n");
542
543 tx_enabled(port) = 1;
544
545 ret = request_irq(TX_IRQ(port),
546 s3c24xx_serial_tx_chars, 0,
547 s3c24xx_serial_portname(port), ourport);
548
549 if (ret) {
550 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
551 goto err;
552 }
553
554 ourport->tx_claimed = 1;
555
556 dbg("s3c24xx_serial_startup ok\n");
557
558 /* the port reset code should have done the correct
559 * register setup for the port controls */
560
561 return ret;
562
563 err:
564 s3c24xx_serial_shutdown(port);
565 return ret;
566 }
567
568 /* power power management control */
569
570 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
571 unsigned int old)
572 {
573 struct s3c24xx_uart_port *ourport = to_ourport(port);
574
575 switch (level) {
576 case 3:
577 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
578 clk_disable(ourport->baudclk);
579
580 clk_disable(ourport->clk);
581 break;
582
583 case 0:
584 clk_enable(ourport->clk);
585
586 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
587 clk_enable(ourport->baudclk);
588
589 break;
590 default:
591 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
592 }
593 }
594
595 /* baud rate calculation
596 *
597 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
598 * of different sources, including the peripheral clock ("pclk") and an
599 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
600 * with a programmable extra divisor.
601 *
602 * The following code goes through the clock sources, and calculates the
603 * baud clocks (and the resultant actual baud rates) and then tries to
604 * pick the closest one and select that.
605 *
606 */
607
608
609 #define MAX_CLKS (8)
610
611 static struct s3c24xx_uart_clksrc tmp_clksrc = {
612 .name = "pclk",
613 .min_baud = 0,
614 .max_baud = 0,
615 .divisor = 1,
616 };
617
618 static inline int
619 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
620 {
621 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
622
623 return (info->get_clksrc)(port, c);
624 }
625
626 static inline int
627 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
628 {
629 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
630
631 return (info->set_clksrc)(port, c);
632 }
633
634 struct baud_calc {
635 struct s3c24xx_uart_clksrc *clksrc;
636 unsigned int calc;
637 unsigned int quot;
638 struct clk *src;
639 };
640
641 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
642 struct uart_port *port,
643 struct s3c24xx_uart_clksrc *clksrc,
644 unsigned int baud)
645 {
646 unsigned long rate;
647
648 calc->src = clk_get(port->dev, clksrc->name);
649 if (calc->src == NULL || IS_ERR(calc->src))
650 return 0;
651
652 rate = clk_get_rate(calc->src);
653 rate /= clksrc->divisor;
654
655 calc->clksrc = clksrc;
656 calc->quot = (rate + (8 * baud)) / (16 * baud);
657 calc->calc = (rate / (calc->quot * 16));
658
659 calc->quot--;
660 return 1;
661 }
662
663 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
664 struct s3c24xx_uart_clksrc **clksrc,
665 struct clk **clk,
666 unsigned int baud)
667 {
668 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
669 struct s3c24xx_uart_clksrc *clkp;
670 struct baud_calc res[MAX_CLKS];
671 struct baud_calc *resptr, *best, *sptr;
672 int i;
673
674 clkp = cfg->clocks;
675 best = NULL;
676
677 if (cfg->clocks_size < 2) {
678 if (cfg->clocks_size == 0)
679 clkp = &tmp_clksrc;
680
681 /* check to see if we're sourcing fclk, and if so we're
682 * going to have to update the clock source
683 */
684
685 if (strcmp(clkp->name, "fclk") == 0) {
686 struct s3c24xx_uart_clksrc src;
687
688 s3c24xx_serial_getsource(port, &src);
689
690 /* check that the port already using fclk, and if
691 * not, then re-select fclk
692 */
693
694 if (strcmp(src.name, clkp->name) == 0) {
695 s3c24xx_serial_setsource(port, clkp);
696 s3c24xx_serial_getsource(port, &src);
697 }
698
699 clkp->divisor = src.divisor;
700 }
701
702 s3c24xx_serial_calcbaud(res, port, clkp, baud);
703 best = res;
704 resptr = best + 1;
705 } else {
706 resptr = res;
707
708 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
709 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
710 resptr++;
711 }
712 }
713
714 /* ok, we now need to select the best clock we found */
715
716 if (!best) {
717 unsigned int deviation = (1<<30)|((1<<30)-1);
718 int calc_deviation;
719
720 for (sptr = res; sptr < resptr; sptr++) {
721 printk(KERN_DEBUG
722 "found clk %p (%s) quot %d, calc %d\n",
723 sptr->clksrc, sptr->clksrc->name,
724 sptr->quot, sptr->calc);
725
726 calc_deviation = baud - sptr->calc;
727 if (calc_deviation < 0)
728 calc_deviation = -calc_deviation;
729
730 if (calc_deviation < deviation) {
731 best = sptr;
732 deviation = calc_deviation;
733 }
734 }
735
736 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
737 }
738
739 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
740 best->clksrc, best->clksrc->name, best->quot, best->calc);
741
742 /* store results to pass back */
743
744 *clksrc = best->clksrc;
745 *clk = best->src;
746
747 return best->quot;
748 }
749
750 static void s3c24xx_serial_set_termios(struct uart_port *port,
751 struct termios *termios,
752 struct termios *old)
753 {
754 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
755 struct s3c24xx_uart_port *ourport = to_ourport(port);
756 struct s3c24xx_uart_clksrc *clksrc;
757 struct clk *clk;
758 unsigned long flags;
759 unsigned int baud, quot;
760 unsigned int ulcon;
761 unsigned int umcon;
762
763 /*
764 * We don't support modem control lines.
765 */
766 termios->c_cflag &= ~(HUPCL | CMSPAR);
767 termios->c_cflag |= CLOCAL;
768
769 /*
770 * Ask the core to calculate the divisor for us.
771 */
772
773 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
774
775 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
776 quot = port->custom_divisor;
777 else
778 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
779
780 /* check to see if we need to change clock source */
781
782 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
783 s3c24xx_serial_setsource(port, clksrc);
784
785 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
786 clk_disable(ourport->baudclk);
787 clk_unuse(ourport->baudclk);
788 ourport->baudclk = NULL;
789 }
790
791 clk_use(clk);
792 clk_enable(clk);
793
794 ourport->clksrc = clksrc;
795 ourport->baudclk = clk;
796 }
797
798 switch (termios->c_cflag & CSIZE) {
799 case CS5:
800 dbg("config: 5bits/char\n");
801 ulcon = S3C2410_LCON_CS5;
802 break;
803 case CS6:
804 dbg("config: 6bits/char\n");
805 ulcon = S3C2410_LCON_CS6;
806 break;
807 case CS7:
808 dbg("config: 7bits/char\n");
809 ulcon = S3C2410_LCON_CS7;
810 break;
811 case CS8:
812 default:
813 dbg("config: 8bits/char\n");
814 ulcon = S3C2410_LCON_CS8;
815 break;
816 }
817
818 /* preserve original lcon IR settings */
819 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
820
821 if (termios->c_cflag & CSTOPB)
822 ulcon |= S3C2410_LCON_STOPB;
823
824 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
825
826 if (termios->c_cflag & PARENB) {
827 if (termios->c_cflag & PARODD)
828 ulcon |= S3C2410_LCON_PODD;
829 else
830 ulcon |= S3C2410_LCON_PEVEN;
831 } else {
832 ulcon |= S3C2410_LCON_PNONE;
833 }
834
835 spin_lock_irqsave(&port->lock, flags);
836
837 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
838
839 wr_regl(port, S3C2410_ULCON, ulcon);
840 wr_regl(port, S3C2410_UBRDIV, quot);
841 wr_regl(port, S3C2410_UMCON, umcon);
842
843 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
844 rd_regl(port, S3C2410_ULCON),
845 rd_regl(port, S3C2410_UCON),
846 rd_regl(port, S3C2410_UFCON));
847
848 /*
849 * Update the per-port timeout.
850 */
851 uart_update_timeout(port, termios->c_cflag, baud);
852
853 /*
854 * Which character status flags are we interested in?
855 */
856 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
857 if (termios->c_iflag & INPCK)
858 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
859
860 /*
861 * Which character status flags should we ignore?
862 */
863 port->ignore_status_mask = 0;
864 if (termios->c_iflag & IGNPAR)
865 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
866 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
867 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
868
869 /*
870 * Ignore all characters if CREAD is not set.
871 */
872 if ((termios->c_cflag & CREAD) == 0)
873 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
874
875 spin_unlock_irqrestore(&port->lock, flags);
876 }
877
878 static const char *s3c24xx_serial_type(struct uart_port *port)
879 {
880 switch (port->type) {
881 case PORT_S3C2410:
882 return "S3C2410";
883 case PORT_S3C2440:
884 return "S3C2440";
885 default:
886 return NULL;
887 }
888 }
889
890 #define MAP_SIZE (0x100)
891
892 static void s3c24xx_serial_release_port(struct uart_port *port)
893 {
894 release_mem_region(port->mapbase, MAP_SIZE);
895 }
896
897 static int s3c24xx_serial_request_port(struct uart_port *port)
898 {
899 const char *name = s3c24xx_serial_portname(port);
900 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
901 }
902
903 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
904 {
905 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
906
907 if (flags & UART_CONFIG_TYPE &&
908 s3c24xx_serial_request_port(port) == 0)
909 port->type = info->type;
910 }
911
912 /*
913 * verify the new serial_struct (for TIOCSSERIAL).
914 */
915 static int
916 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
917 {
918 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
919
920 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
921 return -EINVAL;
922
923 return 0;
924 }
925
926
927 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
928
929 static struct console s3c24xx_serial_console;
930
931 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
932 #else
933 #define S3C24XX_SERIAL_CONSOLE NULL
934 #endif
935
936 static struct uart_ops s3c24xx_serial_ops = {
937 .pm = s3c24xx_serial_pm,
938 .tx_empty = s3c24xx_serial_tx_empty,
939 .get_mctrl = s3c24xx_serial_get_mctrl,
940 .set_mctrl = s3c24xx_serial_set_mctrl,
941 .stop_tx = s3c24xx_serial_stop_tx,
942 .start_tx = s3c24xx_serial_start_tx,
943 .stop_rx = s3c24xx_serial_stop_rx,
944 .enable_ms = s3c24xx_serial_enable_ms,
945 .break_ctl = s3c24xx_serial_break_ctl,
946 .startup = s3c24xx_serial_startup,
947 .shutdown = s3c24xx_serial_shutdown,
948 .set_termios = s3c24xx_serial_set_termios,
949 .type = s3c24xx_serial_type,
950 .release_port = s3c24xx_serial_release_port,
951 .request_port = s3c24xx_serial_request_port,
952 .config_port = s3c24xx_serial_config_port,
953 .verify_port = s3c24xx_serial_verify_port,
954 };
955
956
957 static struct uart_driver s3c24xx_uart_drv = {
958 .owner = THIS_MODULE,
959 .dev_name = "s3c2410_serial",
960 .nr = 3,
961 .cons = S3C24XX_SERIAL_CONSOLE,
962 .driver_name = S3C24XX_SERIAL_NAME,
963 .devfs_name = S3C24XX_SERIAL_DEVFS,
964 .major = S3C24XX_SERIAL_MAJOR,
965 .minor = S3C24XX_SERIAL_MINOR,
966 };
967
968 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
969 [0] = {
970 .port = {
971 .lock = SPIN_LOCK_UNLOCKED,
972 .iotype = UPIO_MEM,
973 .irq = IRQ_S3CUART_RX0,
974 .uartclk = 0,
975 .fifosize = 16,
976 .ops = &s3c24xx_serial_ops,
977 .flags = UPF_BOOT_AUTOCONF,
978 .line = 0,
979 }
980 },
981 [1] = {
982 .port = {
983 .lock = SPIN_LOCK_UNLOCKED,
984 .iotype = UPIO_MEM,
985 .irq = IRQ_S3CUART_RX1,
986 .uartclk = 0,
987 .fifosize = 16,
988 .ops = &s3c24xx_serial_ops,
989 .flags = UPF_BOOT_AUTOCONF,
990 .line = 1,
991 }
992 },
993 #if NR_PORTS > 2
994
995 [2] = {
996 .port = {
997 .lock = SPIN_LOCK_UNLOCKED,
998 .iotype = UPIO_MEM,
999 .irq = IRQ_S3CUART_RX2,
1000 .uartclk = 0,
1001 .fifosize = 16,
1002 .ops = &s3c24xx_serial_ops,
1003 .flags = UPF_BOOT_AUTOCONF,
1004 .line = 2,
1005 }
1006 }
1007 #endif
1008 };
1009
1010 /* s3c24xx_serial_resetport
1011 *
1012 * wrapper to call the specific reset for this port (reset the fifos
1013 * and the settings)
1014 */
1015
1016 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1017 struct s3c2410_uartcfg *cfg)
1018 {
1019 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1020
1021 return (info->reset_port)(port, cfg);
1022 }
1023
1024 /* s3c24xx_serial_init_port
1025 *
1026 * initialise a single serial port from the platform device given
1027 */
1028
1029 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1030 struct s3c24xx_uart_info *info,
1031 struct platform_device *platdev)
1032 {
1033 struct uart_port *port = &ourport->port;
1034 struct s3c2410_uartcfg *cfg;
1035 struct resource *res;
1036
1037 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1038
1039 if (platdev == NULL)
1040 return -ENODEV;
1041
1042 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1043
1044 if (port->mapbase != 0)
1045 return 0;
1046
1047 if (cfg->hwport > 3)
1048 return -EINVAL;
1049
1050 /* setup info for port */
1051 port->dev = &platdev->dev;
1052 ourport->info = info;
1053
1054 /* copy the info in from provided structure */
1055 ourport->port.fifosize = info->fifosize;
1056
1057 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1058
1059 port->uartclk = 1;
1060
1061 if (cfg->uart_flags & UPF_CONS_FLOW) {
1062 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1063 port->flags |= UPF_CONS_FLOW;
1064 }
1065
1066 /* sort our the physical and virtual addresses for each UART */
1067
1068 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1069 if (res == NULL) {
1070 printk(KERN_ERR "failed to find memory resource for uart\n");
1071 return -EINVAL;
1072 }
1073
1074 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1075
1076 port->mapbase = res->start;
1077 port->membase = S3C24XX_VA_UART + (res->start - S3C2410_PA_UART);
1078 port->irq = platform_get_irq(platdev, 0);
1079
1080 ourport->clk = clk_get(&platdev->dev, "uart");
1081
1082 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1083 clk_use(ourport->clk);
1084
1085 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1086 port->mapbase, port->membase, port->irq, port->uartclk);
1087
1088 /* reset the fifos (and setup the uart) */
1089 s3c24xx_serial_resetport(port, cfg);
1090 return 0;
1091 }
1092
1093 /* Device driver serial port probe */
1094
1095 static int probe_index = 0;
1096
1097 int s3c24xx_serial_probe(struct device *_dev,
1098 struct s3c24xx_uart_info *info)
1099 {
1100 struct s3c24xx_uart_port *ourport;
1101 struct platform_device *dev = to_platform_device(_dev);
1102 int ret;
1103
1104 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1105
1106 ourport = &s3c24xx_serial_ports[probe_index];
1107 probe_index++;
1108
1109 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1110
1111 ret = s3c24xx_serial_init_port(ourport, info, dev);
1112 if (ret < 0)
1113 goto probe_err;
1114
1115 dbg("%s: adding port\n", __FUNCTION__);
1116 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1117 dev_set_drvdata(_dev, &ourport->port);
1118
1119 return 0;
1120
1121 probe_err:
1122 return ret;
1123 }
1124
1125 int s3c24xx_serial_remove(struct device *_dev)
1126 {
1127 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1128
1129 if (port)
1130 uart_remove_one_port(&s3c24xx_uart_drv, port);
1131
1132 return 0;
1133 }
1134
1135 /* UART power management code */
1136
1137 #ifdef CONFIG_PM
1138
1139 int s3c24xx_serial_suspend(struct device *dev, pm_message_t state, u32 level)
1140 {
1141 struct uart_port *port = s3c24xx_dev_to_port(dev);
1142
1143 if (port && level == SUSPEND_DISABLE)
1144 uart_suspend_port(&s3c24xx_uart_drv, port);
1145
1146 return 0;
1147 }
1148
1149 int s3c24xx_serial_resume(struct device *dev, u32 level)
1150 {
1151 struct uart_port *port = s3c24xx_dev_to_port(dev);
1152 struct s3c24xx_uart_port *ourport = to_ourport(port);
1153
1154 if (port && level == RESUME_ENABLE) {
1155 clk_enable(ourport->clk);
1156 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1157 clk_disable(ourport->clk);
1158
1159 uart_resume_port(&s3c24xx_uart_drv, port);
1160 }
1161
1162 return 0;
1163 }
1164
1165 #else
1166 #define s3c24xx_serial_suspend NULL
1167 #define s3c24xx_serial_resume NULL
1168 #endif
1169
1170 int s3c24xx_serial_init(struct device_driver *drv,
1171 struct s3c24xx_uart_info *info)
1172 {
1173 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1174 return driver_register(drv);
1175 }
1176
1177
1178 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1179 * port information
1180 */
1181
1182 /* cpu specific variations on the serial port support */
1183
1184 #ifdef CONFIG_CPU_S3C2400
1185
1186 static int s3c2400_serial_getsource(struct uart_port *port,
1187 struct s3c24xx_uart_clksrc *clk)
1188 {
1189 clk->divisor = 1;
1190 clk->name = "pclk";
1191
1192 return 0;
1193 }
1194
1195 static int s3c2400_serial_setsource(struct uart_port *port,
1196 struct s3c24xx_uart_clksrc *clk)
1197 {
1198 return 0;
1199 }
1200
1201 static int s3c2400_serial_resetport(struct uart_port *port,
1202 struct s3c2410_uartcfg *cfg)
1203 {
1204 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1205 port, port->mapbase, cfg);
1206
1207 wr_regl(port, S3C2410_UCON, cfg->ucon);
1208 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1209
1210 /* reset both fifos */
1211
1212 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1213 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1214
1215 return 0;
1216 }
1217
1218 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1219 .name = "Samsung S3C2400 UART",
1220 .type = PORT_S3C2400,
1221 .fifosize = 16,
1222 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1223 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1224 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1225 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1226 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1227 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1228 .get_clksrc = s3c2400_serial_getsource,
1229 .set_clksrc = s3c2400_serial_setsource,
1230 .reset_port = s3c2400_serial_resetport,
1231 };
1232
1233 static int s3c2400_serial_probe(struct device *dev)
1234 {
1235 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1236 }
1237
1238 static struct device_driver s3c2400_serial_drv = {
1239 .name = "s3c2400-uart",
1240 .bus = &platform_bus_type,
1241 .probe = s3c2400_serial_probe,
1242 .remove = s3c24xx_serial_remove,
1243 .suspend = s3c24xx_serial_suspend,
1244 .resume = s3c24xx_serial_resume,
1245 };
1246
1247 static inline int s3c2400_serial_init(void)
1248 {
1249 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1250 }
1251
1252 static inline void s3c2400_serial_exit(void)
1253 {
1254 driver_unregister(&s3c2400_serial_drv);
1255 }
1256
1257 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1258 #else
1259
1260 static inline int s3c2400_serial_init(void)
1261 {
1262 return 0;
1263 }
1264
1265 static inline void s3c2400_serial_exit(void)
1266 {
1267 }
1268
1269 #define s3c2400_uart_inf_at NULL
1270
1271 #endif /* CONFIG_CPU_S3C2400 */
1272
1273 /* S3C2410 support */
1274
1275 #ifdef CONFIG_CPU_S3C2410
1276
1277 static int s3c2410_serial_setsource(struct uart_port *port,
1278 struct s3c24xx_uart_clksrc *clk)
1279 {
1280 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1281
1282 if (strcmp(clk->name, "uclk") == 0)
1283 ucon |= S3C2410_UCON_UCLK;
1284 else
1285 ucon &= ~S3C2410_UCON_UCLK;
1286
1287 wr_regl(port, S3C2410_UCON, ucon);
1288 return 0;
1289 }
1290
1291 static int s3c2410_serial_getsource(struct uart_port *port,
1292 struct s3c24xx_uart_clksrc *clk)
1293 {
1294 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1295
1296 clk->divisor = 1;
1297 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1298
1299 return 0;
1300 }
1301
1302 static int s3c2410_serial_resetport(struct uart_port *port,
1303 struct s3c2410_uartcfg *cfg)
1304 {
1305 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1306 port, port->mapbase, cfg);
1307
1308 wr_regl(port, S3C2410_UCON, cfg->ucon);
1309 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1310
1311 /* reset both fifos */
1312
1313 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1314 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1315
1316 return 0;
1317 }
1318
1319 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1320 .name = "Samsung S3C2410 UART",
1321 .type = PORT_S3C2410,
1322 .fifosize = 16,
1323 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1324 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1325 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1326 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1327 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1328 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1329 .get_clksrc = s3c2410_serial_getsource,
1330 .set_clksrc = s3c2410_serial_setsource,
1331 .reset_port = s3c2410_serial_resetport,
1332 };
1333
1334 /* device management */
1335
1336 static int s3c2410_serial_probe(struct device *dev)
1337 {
1338 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1339 }
1340
1341 static struct device_driver s3c2410_serial_drv = {
1342 .name = "s3c2410-uart",
1343 .bus = &platform_bus_type,
1344 .probe = s3c2410_serial_probe,
1345 .remove = s3c24xx_serial_remove,
1346 .suspend = s3c24xx_serial_suspend,
1347 .resume = s3c24xx_serial_resume,
1348 };
1349
1350 static inline int s3c2410_serial_init(void)
1351 {
1352 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1353 }
1354
1355 static inline void s3c2410_serial_exit(void)
1356 {
1357 driver_unregister(&s3c2410_serial_drv);
1358 }
1359
1360 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1361 #else
1362
1363 static inline int s3c2410_serial_init(void)
1364 {
1365 return 0;
1366 }
1367
1368 static inline void s3c2410_serial_exit(void)
1369 {
1370 }
1371
1372 #define s3c2410_uart_inf_at NULL
1373
1374 #endif /* CONFIG_CPU_S3C2410 */
1375
1376 #ifdef CONFIG_CPU_S3C2440
1377
1378 static int s3c2440_serial_setsource(struct uart_port *port,
1379 struct s3c24xx_uart_clksrc *clk)
1380 {
1381 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1382
1383 // todo - proper fclk<>nonfclk switch //
1384
1385 ucon &= ~S3C2440_UCON_CLKMASK;
1386
1387 if (strcmp(clk->name, "uclk") == 0)
1388 ucon |= S3C2440_UCON_UCLK;
1389 else if (strcmp(clk->name, "pclk") == 0)
1390 ucon |= S3C2440_UCON_PCLK;
1391 else if (strcmp(clk->name, "fclk") == 0)
1392 ucon |= S3C2440_UCON_FCLK;
1393 else {
1394 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1395 return -EINVAL;
1396 }
1397
1398 wr_regl(port, S3C2410_UCON, ucon);
1399 return 0;
1400 }
1401
1402
1403 static int s3c2440_serial_getsource(struct uart_port *port,
1404 struct s3c24xx_uart_clksrc *clk)
1405 {
1406 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1407 unsigned long ucon0, ucon1, ucon2;
1408
1409 switch (ucon & S3C2440_UCON_CLKMASK) {
1410 case S3C2440_UCON_UCLK:
1411 clk->divisor = 1;
1412 clk->name = "uclk";
1413 break;
1414
1415 case S3C2440_UCON_PCLK:
1416 case S3C2440_UCON_PCLK2:
1417 clk->divisor = 1;
1418 clk->name = "pclk";
1419 break;
1420
1421 case S3C2440_UCON_FCLK:
1422 /* the fun of calculating the uart divisors on
1423 * the s3c2440 */
1424
1425 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1426 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1427 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1428
1429 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1430
1431 ucon0 &= S3C2440_UCON0_DIVMASK;
1432 ucon1 &= S3C2440_UCON1_DIVMASK;
1433 ucon2 &= S3C2440_UCON2_DIVMASK;
1434
1435 if (ucon0 != 0) {
1436 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1437 clk->divisor += 6;
1438 } else if (ucon1 != 0) {
1439 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1440 clk->divisor += 21;
1441 } else if (ucon2 != 0) {
1442 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1443 clk->divisor += 36;
1444 } else {
1445 /* manual calims 44, seems to be 9 */
1446 clk->divisor = 9;
1447 }
1448
1449 clk->name = "fclk";
1450 break;
1451 }
1452
1453 return 0;
1454 }
1455
1456 static int s3c2440_serial_resetport(struct uart_port *port,
1457 struct s3c2410_uartcfg *cfg)
1458 {
1459 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1460
1461 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1462 port, port->mapbase, cfg);
1463
1464 /* ensure we don't change the clock settings... */
1465
1466 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1467
1468 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1469 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1470
1471 /* reset both fifos */
1472
1473 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1474 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1475
1476 return 0;
1477 }
1478
1479 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1480 .name = "Samsung S3C2440 UART",
1481 .type = PORT_S3C2440,
1482 .fifosize = 64,
1483 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1484 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1485 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1486 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1487 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1488 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1489 .get_clksrc = s3c2440_serial_getsource,
1490 .set_clksrc = s3c2440_serial_setsource,
1491 .reset_port = s3c2440_serial_resetport,
1492 };
1493
1494 /* device management */
1495
1496 static int s3c2440_serial_probe(struct device *dev)
1497 {
1498 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1499 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1500 }
1501
1502 static struct device_driver s3c2440_serial_drv = {
1503 .name = "s3c2440-uart",
1504 .bus = &platform_bus_type,
1505 .probe = s3c2440_serial_probe,
1506 .remove = s3c24xx_serial_remove,
1507 .suspend = s3c24xx_serial_suspend,
1508 .resume = s3c24xx_serial_resume,
1509 };
1510
1511
1512 static inline int s3c2440_serial_init(void)
1513 {
1514 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1515 }
1516
1517 static inline void s3c2440_serial_exit(void)
1518 {
1519 driver_unregister(&s3c2440_serial_drv);
1520 }
1521
1522 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1523 #else
1524
1525 static inline int s3c2440_serial_init(void)
1526 {
1527 return 0;
1528 }
1529
1530 static inline void s3c2440_serial_exit(void)
1531 {
1532 }
1533
1534 #define s3c2440_uart_inf_at NULL
1535 #endif /* CONFIG_CPU_S3C2440 */
1536
1537 /* module initialisation code */
1538
1539 static int __init s3c24xx_serial_modinit(void)
1540 {
1541 int ret;
1542
1543 ret = uart_register_driver(&s3c24xx_uart_drv);
1544 if (ret < 0) {
1545 printk(KERN_ERR "failed to register UART driver\n");
1546 return -1;
1547 }
1548
1549 s3c2400_serial_init();
1550 s3c2410_serial_init();
1551 s3c2440_serial_init();
1552
1553 return 0;
1554 }
1555
1556 static void __exit s3c24xx_serial_modexit(void)
1557 {
1558 s3c2400_serial_exit();
1559 s3c2410_serial_exit();
1560 s3c2440_serial_exit();
1561
1562 uart_unregister_driver(&s3c24xx_uart_drv);
1563 }
1564
1565
1566 module_init(s3c24xx_serial_modinit);
1567 module_exit(s3c24xx_serial_modexit);
1568
1569 /* Console code */
1570
1571 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1572
1573 static struct uart_port *cons_uart;
1574
1575 static int
1576 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1577 {
1578 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1579 unsigned long ufstat, utrstat;
1580
1581 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1582 /* fifo mode - check ammount of data in fifo registers... */
1583
1584 ufstat = rd_regl(port, S3C2410_UFSTAT);
1585 return (ufstat & info->tx_fifofull) ? 0 : 1;
1586 }
1587
1588 /* in non-fifo mode, we go and use the tx buffer empty */
1589
1590 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1591 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1592 }
1593
1594 static void
1595 s3c24xx_serial_console_write(struct console *co, const char *s,
1596 unsigned int count)
1597 {
1598 int i;
1599 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1600
1601 for (i = 0; i < count; i++) {
1602 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1603 barrier();
1604
1605 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1606
1607 if (s[i] == '\n') {
1608 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1609 barrier();
1610
1611 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1612 }
1613 }
1614 }
1615
1616 static void __init
1617 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1618 int *parity, int *bits)
1619 {
1620 struct s3c24xx_uart_clksrc clksrc;
1621 struct clk *clk;
1622 unsigned int ulcon;
1623 unsigned int ucon;
1624 unsigned int ubrdiv;
1625 unsigned long rate;
1626
1627 ulcon = rd_regl(port, S3C2410_ULCON);
1628 ucon = rd_regl(port, S3C2410_UCON);
1629 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1630
1631 dbg("s3c24xx_serial_get_options: port=%p\n"
1632 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1633 port, ulcon, ucon, ubrdiv);
1634
1635 if ((ucon & 0xf) != 0) {
1636 /* consider the serial port configured if the tx/rx mode set */
1637
1638 switch (ulcon & S3C2410_LCON_CSMASK) {
1639 case S3C2410_LCON_CS5:
1640 *bits = 5;
1641 break;
1642 case S3C2410_LCON_CS6:
1643 *bits = 6;
1644 break;
1645 case S3C2410_LCON_CS7:
1646 *bits = 7;
1647 break;
1648 default:
1649 case S3C2410_LCON_CS8:
1650 *bits = 8;
1651 break;
1652 }
1653
1654 switch (ulcon & S3C2410_LCON_PMASK) {
1655 case S3C2410_LCON_PEVEN:
1656 *parity = 'e';
1657 break;
1658
1659 case S3C2410_LCON_PODD:
1660 *parity = 'o';
1661 break;
1662
1663 case S3C2410_LCON_PNONE:
1664 default:
1665 *parity = 'n';
1666 }
1667
1668 /* now calculate the baud rate */
1669
1670 s3c24xx_serial_getsource(port, &clksrc);
1671
1672 clk = clk_get(port->dev, clksrc.name);
1673 if (!IS_ERR(clk) && clk != NULL)
1674 rate = clk_get_rate(clk) / clksrc.divisor;
1675 else
1676 rate = 1;
1677
1678
1679 *baud = rate / ( 16 * (ubrdiv + 1));
1680 dbg("calculated baud %d\n", *baud);
1681 }
1682
1683 }
1684
1685 /* s3c24xx_serial_init_ports
1686 *
1687 * initialise the serial ports from the machine provided initialisation
1688 * data.
1689 */
1690
1691 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1692 {
1693 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1694 struct platform_device **platdev_ptr;
1695 int i;
1696
1697 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1698
1699 platdev_ptr = s3c24xx_uart_devs;
1700
1701 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1702 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1703 }
1704
1705 return 0;
1706 }
1707
1708 static int __init
1709 s3c24xx_serial_console_setup(struct console *co, char *options)
1710 {
1711 struct uart_port *port;
1712 int baud = 9600;
1713 int bits = 8;
1714 int parity = 'n';
1715 int flow = 'n';
1716
1717 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1718 co, co->index, options);
1719
1720 /* is this a valid port */
1721
1722 if (co->index == -1 || co->index >= NR_PORTS)
1723 co->index = 0;
1724
1725 port = &s3c24xx_serial_ports[co->index].port;
1726
1727 /* is the port configured? */
1728
1729 if (port->mapbase == 0x0) {
1730 co->index = 0;
1731 port = &s3c24xx_serial_ports[co->index].port;
1732 }
1733
1734 cons_uart = port;
1735
1736 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1737
1738 /*
1739 * Check whether an invalid uart number has been specified, and
1740 * if so, search for the first available port that does have
1741 * console support.
1742 */
1743 if (options)
1744 uart_parse_options(options, &baud, &parity, &bits, &flow);
1745 else
1746 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1747
1748 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1749
1750 return uart_set_options(port, co, baud, parity, bits, flow);
1751 }
1752
1753 /* s3c24xx_serial_initconsole
1754 *
1755 * initialise the console from one of the uart drivers
1756 */
1757
1758 static struct console s3c24xx_serial_console =
1759 {
1760 .name = S3C24XX_SERIAL_NAME,
1761 .device = uart_console_device,
1762 .flags = CON_PRINTBUFFER,
1763 .index = -1,
1764 .write = s3c24xx_serial_console_write,
1765 .setup = s3c24xx_serial_console_setup
1766 };
1767
1768 static int s3c24xx_serial_initconsole(void)
1769 {
1770 struct s3c24xx_uart_info *info;
1771 struct platform_device *dev = s3c24xx_uart_devs[0];
1772
1773 dbg("s3c24xx_serial_initconsole\n");
1774
1775 /* select driver based on the cpu */
1776
1777 if (dev == NULL) {
1778 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1779 return 0;
1780 }
1781
1782 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1783 info = s3c2400_uart_inf_at;
1784 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1785 info = s3c2410_uart_inf_at;
1786 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1787 info = s3c2440_uart_inf_at;
1788 } else {
1789 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1790 return 0;
1791 }
1792
1793 if (info == NULL) {
1794 printk(KERN_ERR "s3c24xx: no driver for console\n");
1795 return 0;
1796 }
1797
1798 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1799 s3c24xx_serial_init_ports(info);
1800
1801 register_console(&s3c24xx_serial_console);
1802 return 0;
1803 }
1804
1805 console_initcall(s3c24xx_serial_initconsole);
1806
1807 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1808
1809 MODULE_LICENSE("GPL");
1810 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1811 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
kernel source for telekom puls (alcatel/mediatek)