2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
26 #include <asm/byteorder.h>
31 #undef SERIAL_DEBUG_PCI
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk
{
44 int (*init
)(struct pci_dev
*dev
);
45 int (*setup
)(struct serial_private
*,
46 const struct pciserial_board
*,
47 struct uart_port
*, int);
48 void (*exit
)(struct pci_dev
*dev
);
51 #define PCI_NUM_BAR_RESOURCES 6
53 struct serial_private
{
56 void __iomem
*remapped_bar
[PCI_NUM_BAR_RESOURCES
];
57 struct pci_serial_quirk
*quirk
;
61 static void moan_device(const char *str
, struct pci_dev
*dev
)
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev
), str
, dev
->vendor
, dev
->device
,
70 dev
->subsystem_vendor
, dev
->subsystem_device
);
74 setup_port(struct serial_private
*priv
, struct uart_port
*port
,
75 int bar
, int offset
, int regshift
)
77 struct pci_dev
*dev
= priv
->dev
;
78 unsigned long base
, len
;
80 if (bar
>= PCI_NUM_BAR_RESOURCES
)
83 base
= pci_resource_start(dev
, bar
);
85 if (pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) {
86 len
= pci_resource_len(dev
, bar
);
88 if (!priv
->remapped_bar
[bar
])
89 priv
->remapped_bar
[bar
] = ioremap_nocache(base
, len
);
90 if (!priv
->remapped_bar
[bar
])
93 port
->iotype
= UPIO_MEM
;
95 port
->mapbase
= base
+ offset
;
96 port
->membase
= priv
->remapped_bar
[bar
] + offset
;
97 port
->regshift
= regshift
;
99 port
->iotype
= UPIO_PORT
;
100 port
->iobase
= base
+ offset
;
102 port
->membase
= NULL
;
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 static int addidata_apci7800_setup(struct serial_private
*priv
,
112 const struct pciserial_board
*board
,
113 struct uart_port
*port
, int idx
)
115 unsigned int bar
= 0, offset
= board
->first_offset
;
116 bar
= FL_GET_BASE(board
->flags
);
119 offset
+= idx
* board
->uart_offset
;
120 } else if ((idx
>= 2) && (idx
< 4)) {
122 offset
+= ((idx
- 2) * board
->uart_offset
);
123 } else if ((idx
>= 4) && (idx
< 6)) {
125 offset
+= ((idx
- 4) * board
->uart_offset
);
126 } else if (idx
>= 6) {
128 offset
+= ((idx
- 6) * board
->uart_offset
);
131 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
139 afavlab_setup(struct serial_private
*priv
, const struct pciserial_board
*board
,
140 struct uart_port
*port
, int idx
)
142 unsigned int bar
, offset
= board
->first_offset
;
144 bar
= FL_GET_BASE(board
->flags
);
149 offset
+= (idx
- 4) * board
->uart_offset
;
152 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
162 static int pci_hp_diva_init(struct pci_dev
*dev
)
166 switch (dev
->subsystem_device
) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1
:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME
:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE
:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2
:
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR
:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE
:
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
193 pci_hp_diva_setup(struct serial_private
*priv
,
194 const struct pciserial_board
*board
,
195 struct uart_port
*port
, int idx
)
197 unsigned int offset
= board
->first_offset
;
198 unsigned int bar
= FL_GET_BASE(board
->flags
);
200 switch (priv
->dev
->subsystem_device
) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
215 offset
+= idx
* board
->uart_offset
;
217 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
221 * Added for EKF Intel i960 serial boards
223 static int pci_inteli960ni_init(struct pci_dev
*dev
)
225 unsigned long oldval
;
227 if (!(dev
->subsystem_device
& 0x1000))
230 /* is firmware started? */
231 pci_read_config_dword(dev
, 0x44, (void *)&oldval
);
232 if (oldval
== 0x00001000L
) { /* RESET value */
233 printk(KERN_DEBUG
"Local i960 firmware missing");
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
245 static int pci_plx9050_init(struct pci_dev
*dev
)
250 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0) {
251 moan_device("no memory in bar 0", dev
);
256 if (dev
->vendor
== PCI_VENDOR_ID_PANACOM
||
257 dev
->subsystem_vendor
== PCI_SUBVENDOR_ID_EXSYS
)
260 if ((dev
->vendor
== PCI_VENDOR_ID_PLX
) &&
261 (dev
->device
== PCI_DEVICE_ID_PLX_ROMULUS
))
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
272 * enable/disable interrupts
274 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
277 writel(irq_config
, p
+ 0x4c);
280 * Read the register back to ensure that it took effect.
288 static void __devexit
pci_plx9050_exit(struct pci_dev
*dev
)
292 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0)
298 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
303 * Read the register back to ensure that it took effect.
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
313 static void __devexit
pci_ni8420_exit(struct pci_dev
*dev
)
316 unsigned long base
, len
;
317 unsigned int bar
= 0;
319 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
320 moan_device("no memory in bar", dev
);
324 base
= pci_resource_start(dev
, bar
);
325 len
= pci_resource_len(dev
, bar
);
326 p
= ioremap_nocache(base
, len
);
330 /* Disable the CPU Interrupt */
331 writel(readl(p
+ NI8420_INT_ENABLE_REG
) & ~(NI8420_INT_ENABLE_BIT
),
332 p
+ NI8420_INT_ENABLE_REG
);
338 #define MITE_IOWBSR1 0xc4
339 #define MITE_IOWCR1 0xf4
340 #define MITE_LCIMR1 0x08
341 #define MITE_LCIMR2 0x10
343 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
345 static void __devexit
pci_ni8430_exit(struct pci_dev
*dev
)
348 unsigned long base
, len
;
349 unsigned int bar
= 0;
351 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
352 moan_device("no memory in bar", dev
);
356 base
= pci_resource_start(dev
, bar
);
357 len
= pci_resource_len(dev
, bar
);
358 p
= ioremap_nocache(base
, len
);
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE
, p
+ MITE_LCIMR2
);
367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369 sbs_setup(struct serial_private
*priv
, const struct pciserial_board
*board
,
370 struct uart_port
*port
, int idx
)
372 unsigned int bar
, offset
= board
->first_offset
;
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset
+= idx
* board
->uart_offset
;
379 } else if (idx
< 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset
+= idx
* board
->uart_offset
+ 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
389 * This does initialization for PMC OCTALPRO cards:
390 * maps the device memory, resets the UARTs (needed, bc
391 * if the module is removed and inserted again, the card
392 * is in the sleep mode) and enables global interrupt.
395 /* global control register offset for SBS PMC-OctalPro */
396 #define OCT_REG_CR_OFF 0x500
398 static int sbs_init(struct pci_dev
*dev
)
402 p
= pci_ioremap_bar(dev
, 0);
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p
+ OCT_REG_CR_OFF
);
409 writeb(0x0, p
+ OCT_REG_CR_OFF
);
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p
+ OCT_REG_CR_OFF
);
419 * Disables the global interrupt of PMC-OctalPro
422 static void __devexit
sbs_exit(struct pci_dev
*dev
)
426 p
= pci_ioremap_bar(dev
, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 writeb(0, p
+ OCT_REG_CR_OFF
);
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equiped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 * Note: some SIIG cards are probed by the parport_serial object.
460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463 static int pci_siig10x_init(struct pci_dev
*dev
)
468 switch (dev
->device
& 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x
: /* 1S */
472 case PCI_DEVICE_ID_SIIG_2S_10x
: /* 2S, 2S1P */
475 default: /* 1S1P, 4S */
480 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
484 writew(readw(p
+ 0x28) & data
, p
+ 0x28);
490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493 static int pci_siig20x_init(struct pci_dev
*dev
)
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev
, 0x6f, &data
);
499 pci_write_config_byte(dev
, 0x6f, data
& 0xef);
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x
) ||
503 ((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x
)) {
504 pci_read_config_byte(dev
, 0x73, &data
);
505 pci_write_config_byte(dev
, 0x73, data
& 0xef);
510 static int pci_siig_init(struct pci_dev
*dev
)
512 unsigned int type
= dev
->device
& 0xff00;
515 return pci_siig10x_init(dev
);
516 else if (type
== 0x2000)
517 return pci_siig20x_init(dev
);
519 moan_device("Unknown SIIG card", dev
);
523 static int pci_siig_setup(struct serial_private
*priv
,
524 const struct pciserial_board
*board
,
525 struct uart_port
*port
, int idx
)
527 unsigned int bar
= FL_GET_BASE(board
->flags
) + idx
, offset
= 0;
531 offset
= (idx
- 4) * 8;
534 return setup_port(priv
, port
, bar
, offset
, 0);
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
542 static const unsigned short timedia_single_port
[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 static const unsigned short timedia_dual_port
[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 static const unsigned short timedia_quad_port
[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 static const unsigned short timedia_eight_port
[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 static const struct timedia_struct
{
568 const unsigned short *ids
;
570 { 1, timedia_single_port
},
571 { 2, timedia_dual_port
},
572 { 4, timedia_quad_port
},
573 { 8, timedia_eight_port
}
576 static int pci_timedia_init(struct pci_dev
*dev
)
578 const unsigned short *ids
;
581 for (i
= 0; i
< ARRAY_SIZE(timedia_data
); i
++) {
582 ids
= timedia_data
[i
].ids
;
583 for (j
= 0; ids
[j
]; j
++)
584 if (dev
->subsystem_device
== ids
[j
])
585 return timedia_data
[i
].num
;
591 * Timedia/SUNIX uses a mixture of BARs and offsets
592 * Ugh, this is ugly as all hell --- TYT
595 pci_timedia_setup(struct serial_private
*priv
,
596 const struct pciserial_board
*board
,
597 struct uart_port
*port
, int idx
)
599 unsigned int bar
= 0, offset
= board
->first_offset
;
606 offset
= board
->uart_offset
;
613 offset
= board
->uart_offset
;
622 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
626 * Some Titan cards are also a little weird
629 titan_400l_800l_setup(struct serial_private
*priv
,
630 const struct pciserial_board
*board
,
631 struct uart_port
*port
, int idx
)
633 unsigned int bar
, offset
= board
->first_offset
;
644 offset
= (idx
- 2) * board
->uart_offset
;
647 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
650 static int pci_xircom_init(struct pci_dev
*dev
)
656 static int pci_ni8420_init(struct pci_dev
*dev
)
659 unsigned long base
, len
;
660 unsigned int bar
= 0;
662 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
663 moan_device("no memory in bar", dev
);
667 base
= pci_resource_start(dev
, bar
);
668 len
= pci_resource_len(dev
, bar
);
669 p
= ioremap_nocache(base
, len
);
673 /* Enable CPU Interrupt */
674 writel(readl(p
+ NI8420_INT_ENABLE_REG
) | NI8420_INT_ENABLE_BIT
,
675 p
+ NI8420_INT_ENABLE_REG
);
681 #define MITE_IOWBSR1_WSIZE 0xa
682 #define MITE_IOWBSR1_WIN_OFFSET 0x800
683 #define MITE_IOWBSR1_WENAB (1 << 7)
684 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
685 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
688 static int pci_ni8430_init(struct pci_dev
*dev
)
691 unsigned long base
, len
;
693 unsigned int bar
= 0;
695 if ((pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) == 0) {
696 moan_device("no memory in bar", dev
);
700 base
= pci_resource_start(dev
, bar
);
701 len
= pci_resource_len(dev
, bar
);
702 p
= ioremap_nocache(base
, len
);
706 /* Set device window address and size in BAR0 */
707 device_window
= ((base
+ MITE_IOWBSR1_WIN_OFFSET
) & 0xffffff00)
708 | MITE_IOWBSR1_WENAB
| MITE_IOWBSR1_WSIZE
;
709 writel(device_window
, p
+ MITE_IOWBSR1
);
711 /* Set window access to go to RAMSEL IO address space */
712 writel((readl(p
+ MITE_IOWCR1
) & MITE_IOWCR1_RAMSEL_MASK
),
715 /* Enable IO Bus Interrupt 0 */
716 writel(MITE_LCIMR1_IO_IE_0
, p
+ MITE_LCIMR1
);
718 /* Enable CPU Interrupt */
719 writel(MITE_LCIMR2_SET_CPU_IE
, p
+ MITE_LCIMR2
);
725 /* UART Port Control Register */
726 #define NI8430_PORTCON 0x0f
727 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
730 pci_ni8430_setup(struct serial_private
*priv
,
731 const struct pciserial_board
*board
,
732 struct uart_port
*port
, int idx
)
735 unsigned long base
, len
;
736 unsigned int bar
, offset
= board
->first_offset
;
738 if (idx
>= board
->num_ports
)
741 bar
= FL_GET_BASE(board
->flags
);
742 offset
+= idx
* board
->uart_offset
;
744 base
= pci_resource_start(priv
->dev
, bar
);
745 len
= pci_resource_len(priv
->dev
, bar
);
746 p
= ioremap_nocache(base
, len
);
748 /* enable the transciever */
749 writeb(readb(p
+ offset
+ NI8430_PORTCON
) | NI8430_PORTCON_TXVR_ENABLE
,
750 p
+ offset
+ NI8430_PORTCON
);
754 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
758 static int pci_netmos_init(struct pci_dev
*dev
)
760 /* subdevice 0x00PS means <P> parallel, <S> serial */
761 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
763 if (dev
->device
== PCI_DEVICE_ID_NETMOS_9901
)
765 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
766 dev
->subsystem_device
== 0x0299)
775 * These chips are available with optionally one parallel port and up to
776 * two serial ports. Unfortunately they all have the same product id.
778 * Basic configuration is done over a region of 32 I/O ports. The base
779 * ioport is called INTA or INTC, depending on docs/other drivers.
781 * The region of the 32 I/O ports is configured in POSIO0R...
785 #define ITE_887x_MISCR 0x9c
786 #define ITE_887x_INTCBAR 0x78
787 #define ITE_887x_UARTBAR 0x7c
788 #define ITE_887x_PS0BAR 0x10
789 #define ITE_887x_POSIO0 0x60
792 #define ITE_887x_IOSIZE 32
793 /* I/O space size (bits 26-24; 8 bytes = 011b) */
794 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
795 /* I/O space size (bits 26-24; 32 bytes = 101b) */
796 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
797 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
798 #define ITE_887x_POSIO_SPEED (3 << 29)
799 /* enable IO_Space bit */
800 #define ITE_887x_POSIO_ENABLE (1 << 31)
802 static int pci_ite887x_init(struct pci_dev
*dev
)
804 /* inta_addr are the configuration addresses of the ITE */
805 static const short inta_addr
[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
808 struct resource
*iobase
= NULL
;
809 u32 miscr
, uartbar
, ioport
;
811 /* search for the base-ioport */
813 while (inta_addr
[i
] && iobase
== NULL
) {
814 iobase
= request_region(inta_addr
[i
], ITE_887x_IOSIZE
,
816 if (iobase
!= NULL
) {
817 /* write POSIO0R - speed | size | ioport */
818 pci_write_config_dword(dev
, ITE_887x_POSIO0
,
819 ITE_887x_POSIO_ENABLE
| ITE_887x_POSIO_SPEED
|
820 ITE_887x_POSIO_IOSIZE_32
| inta_addr
[i
]);
821 /* write INTCBAR - ioport */
822 pci_write_config_dword(dev
, ITE_887x_INTCBAR
,
824 ret
= inb(inta_addr
[i
]);
826 /* ioport connected */
829 release_region(iobase
->start
, ITE_887x_IOSIZE
);
836 printk(KERN_ERR
"ite887x: could not find iobase\n");
840 /* start of undocumented type checking (see parport_pc.c) */
841 type
= inb(iobase
->start
+ 0x18) & 0x0f;
844 case 0x2: /* ITE8871 (1P) */
845 case 0xa: /* ITE8875 (1P) */
848 case 0xe: /* ITE8872 (2S1P) */
851 case 0x6: /* ITE8873 (1S) */
854 case 0x8: /* ITE8874 (2S) */
858 moan_device("Unknown ITE887x", dev
);
862 /* configure all serial ports */
863 for (i
= 0; i
< ret
; i
++) {
864 /* read the I/O port from the device */
865 pci_read_config_dword(dev
, ITE_887x_PS0BAR
+ (0x4 * (i
+ 1)),
867 ioport
&= 0x0000FF00; /* the actual base address */
868 pci_write_config_dword(dev
, ITE_887x_POSIO0
+ (0x4 * (i
+ 1)),
869 ITE_887x_POSIO_ENABLE
| ITE_887x_POSIO_SPEED
|
870 ITE_887x_POSIO_IOSIZE_8
| ioport
);
872 /* write the ioport to the UARTBAR */
873 pci_read_config_dword(dev
, ITE_887x_UARTBAR
, &uartbar
);
874 uartbar
&= ~(0xffff << (16 * i
)); /* clear half the reg */
875 uartbar
|= (ioport
<< (16 * i
)); /* set the ioport */
876 pci_write_config_dword(dev
, ITE_887x_UARTBAR
, uartbar
);
878 /* get current config */
879 pci_read_config_dword(dev
, ITE_887x_MISCR
, &miscr
);
880 /* disable interrupts (UARTx_Routing[3:0]) */
881 miscr
&= ~(0xf << (12 - 4 * i
));
882 /* activate the UART (UARTx_En) */
883 miscr
|= 1 << (23 - i
);
884 /* write new config with activated UART */
885 pci_write_config_dword(dev
, ITE_887x_MISCR
, miscr
);
889 /* the device has no UARTs if we get here */
890 release_region(iobase
->start
, ITE_887x_IOSIZE
);
896 static void __devexit
pci_ite887x_exit(struct pci_dev
*dev
)
899 /* the ioport is bit 0-15 in POSIO0R */
900 pci_read_config_dword(dev
, ITE_887x_POSIO0
, &ioport
);
902 release_region(ioport
, ITE_887x_IOSIZE
);
906 * Oxford Semiconductor Inc.
907 * Check that device is part of the Tornado range of devices, then determine
908 * the number of ports available on the device.
910 static int pci_oxsemi_tornado_init(struct pci_dev
*dev
)
913 unsigned long deviceID
;
914 unsigned int number_uarts
= 0;
916 /* OxSemi Tornado devices are all 0xCxxx */
917 if (dev
->vendor
== PCI_VENDOR_ID_OXSEMI
&&
918 (dev
->device
& 0xF000) != 0xC000)
921 p
= pci_iomap(dev
, 0, 5);
925 deviceID
= ioread32(p
);
927 if (deviceID
== 0x07000200) {
928 number_uarts
= ioread8(p
+ 4);
930 "%d ports detected on Oxford PCI Express device\n",
938 pci_default_setup(struct serial_private
*priv
,
939 const struct pciserial_board
*board
,
940 struct uart_port
*port
, int idx
)
942 unsigned int bar
, offset
= board
->first_offset
, maxnr
;
944 bar
= FL_GET_BASE(board
->flags
);
945 if (board
->flags
& FL_BASE_BARS
)
948 offset
+= idx
* board
->uart_offset
;
950 maxnr
= (pci_resource_len(priv
->dev
, bar
) - board
->first_offset
) >>
951 (board
->reg_shift
+ 3);
953 if (board
->flags
& FL_REGION_SZ_CAP
&& idx
>= maxnr
)
956 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
959 static int skip_tx_en_setup(struct serial_private
*priv
,
960 const struct pciserial_board
*board
,
961 struct uart_port
*port
, int idx
)
963 port
->flags
|= UPF_NO_TXEN_TEST
;
964 printk(KERN_DEBUG
"serial8250: skipping TxEn test for device "
965 "[%04x:%04x] subsystem [%04x:%04x]\n",
968 priv
->dev
->subsystem_vendor
,
969 priv
->dev
->subsystem_device
);
971 return pci_default_setup(priv
, board
, port
, idx
);
974 /* This should be in linux/pci_ids.h */
975 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
976 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
977 #define PCI_DEVICE_ID_OCTPRO 0x0001
978 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
979 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
980 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
981 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
982 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
983 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
985 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
986 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
989 * Master list of serial port init/setup/exit quirks.
990 * This does not describe the general nature of the port.
991 * (ie, baud base, number and location of ports, etc)
993 * This list is ordered alphabetically by vendor then device.
994 * Specific entries must come before more generic entries.
996 static struct pci_serial_quirk pci_serial_quirks
[] __refdata
= {
998 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1001 .vendor
= PCI_VENDOR_ID_ADDIDATA_OLD
,
1002 .device
= PCI_DEVICE_ID_ADDIDATA_APCI7800
,
1003 .subvendor
= PCI_ANY_ID
,
1004 .subdevice
= PCI_ANY_ID
,
1005 .setup
= addidata_apci7800_setup
,
1008 * AFAVLAB cards - these may be called via parport_serial
1009 * It is not clear whether this applies to all products.
1012 .vendor
= PCI_VENDOR_ID_AFAVLAB
,
1013 .device
= PCI_ANY_ID
,
1014 .subvendor
= PCI_ANY_ID
,
1015 .subdevice
= PCI_ANY_ID
,
1016 .setup
= afavlab_setup
,
1022 .vendor
= PCI_VENDOR_ID_HP
,
1023 .device
= PCI_DEVICE_ID_HP_DIVA
,
1024 .subvendor
= PCI_ANY_ID
,
1025 .subdevice
= PCI_ANY_ID
,
1026 .init
= pci_hp_diva_init
,
1027 .setup
= pci_hp_diva_setup
,
1033 .vendor
= PCI_VENDOR_ID_INTEL
,
1034 .device
= PCI_DEVICE_ID_INTEL_80960_RP
,
1035 .subvendor
= 0xe4bf,
1036 .subdevice
= PCI_ANY_ID
,
1037 .init
= pci_inteli960ni_init
,
1038 .setup
= pci_default_setup
,
1041 .vendor
= PCI_VENDOR_ID_INTEL
,
1042 .device
= PCI_DEVICE_ID_INTEL_8257X_SOL
,
1043 .subvendor
= PCI_ANY_ID
,
1044 .subdevice
= PCI_ANY_ID
,
1045 .setup
= skip_tx_en_setup
,
1048 .vendor
= PCI_VENDOR_ID_INTEL
,
1049 .device
= PCI_DEVICE_ID_INTEL_82573L_SOL
,
1050 .subvendor
= PCI_ANY_ID
,
1051 .subdevice
= PCI_ANY_ID
,
1052 .setup
= skip_tx_en_setup
,
1055 .vendor
= PCI_VENDOR_ID_INTEL
,
1056 .device
= PCI_DEVICE_ID_INTEL_82573E_SOL
,
1057 .subvendor
= PCI_ANY_ID
,
1058 .subdevice
= PCI_ANY_ID
,
1059 .setup
= skip_tx_en_setup
,
1065 .vendor
= PCI_VENDOR_ID_ITE
,
1066 .device
= PCI_DEVICE_ID_ITE_8872
,
1067 .subvendor
= PCI_ANY_ID
,
1068 .subdevice
= PCI_ANY_ID
,
1069 .init
= pci_ite887x_init
,
1070 .setup
= pci_default_setup
,
1071 .exit
= __devexit_p(pci_ite887x_exit
),
1074 * National Instruments
1077 .vendor
= PCI_VENDOR_ID_NI
,
1078 .device
= PCI_DEVICE_ID_NI_PCI23216
,
1079 .subvendor
= PCI_ANY_ID
,
1080 .subdevice
= PCI_ANY_ID
,
1081 .init
= pci_ni8420_init
,
1082 .setup
= pci_default_setup
,
1083 .exit
= __devexit_p(pci_ni8420_exit
),
1086 .vendor
= PCI_VENDOR_ID_NI
,
1087 .device
= PCI_DEVICE_ID_NI_PCI2328
,
1088 .subvendor
= PCI_ANY_ID
,
1089 .subdevice
= PCI_ANY_ID
,
1090 .init
= pci_ni8420_init
,
1091 .setup
= pci_default_setup
,
1092 .exit
= __devexit_p(pci_ni8420_exit
),
1095 .vendor
= PCI_VENDOR_ID_NI
,
1096 .device
= PCI_DEVICE_ID_NI_PCI2324
,
1097 .subvendor
= PCI_ANY_ID
,
1098 .subdevice
= PCI_ANY_ID
,
1099 .init
= pci_ni8420_init
,
1100 .setup
= pci_default_setup
,
1101 .exit
= __devexit_p(pci_ni8420_exit
),
1104 .vendor
= PCI_VENDOR_ID_NI
,
1105 .device
= PCI_DEVICE_ID_NI_PCI2322
,
1106 .subvendor
= PCI_ANY_ID
,
1107 .subdevice
= PCI_ANY_ID
,
1108 .init
= pci_ni8420_init
,
1109 .setup
= pci_default_setup
,
1110 .exit
= __devexit_p(pci_ni8420_exit
),
1113 .vendor
= PCI_VENDOR_ID_NI
,
1114 .device
= PCI_DEVICE_ID_NI_PCI2324I
,
1115 .subvendor
= PCI_ANY_ID
,
1116 .subdevice
= PCI_ANY_ID
,
1117 .init
= pci_ni8420_init
,
1118 .setup
= pci_default_setup
,
1119 .exit
= __devexit_p(pci_ni8420_exit
),
1122 .vendor
= PCI_VENDOR_ID_NI
,
1123 .device
= PCI_DEVICE_ID_NI_PCI2322I
,
1124 .subvendor
= PCI_ANY_ID
,
1125 .subdevice
= PCI_ANY_ID
,
1126 .init
= pci_ni8420_init
,
1127 .setup
= pci_default_setup
,
1128 .exit
= __devexit_p(pci_ni8420_exit
),
1131 .vendor
= PCI_VENDOR_ID_NI
,
1132 .device
= PCI_DEVICE_ID_NI_PXI8420_23216
,
1133 .subvendor
= PCI_ANY_ID
,
1134 .subdevice
= PCI_ANY_ID
,
1135 .init
= pci_ni8420_init
,
1136 .setup
= pci_default_setup
,
1137 .exit
= __devexit_p(pci_ni8420_exit
),
1140 .vendor
= PCI_VENDOR_ID_NI
,
1141 .device
= PCI_DEVICE_ID_NI_PXI8420_2328
,
1142 .subvendor
= PCI_ANY_ID
,
1143 .subdevice
= PCI_ANY_ID
,
1144 .init
= pci_ni8420_init
,
1145 .setup
= pci_default_setup
,
1146 .exit
= __devexit_p(pci_ni8420_exit
),
1149 .vendor
= PCI_VENDOR_ID_NI
,
1150 .device
= PCI_DEVICE_ID_NI_PXI8420_2324
,
1151 .subvendor
= PCI_ANY_ID
,
1152 .subdevice
= PCI_ANY_ID
,
1153 .init
= pci_ni8420_init
,
1154 .setup
= pci_default_setup
,
1155 .exit
= __devexit_p(pci_ni8420_exit
),
1158 .vendor
= PCI_VENDOR_ID_NI
,
1159 .device
= PCI_DEVICE_ID_NI_PXI8420_2322
,
1160 .subvendor
= PCI_ANY_ID
,
1161 .subdevice
= PCI_ANY_ID
,
1162 .init
= pci_ni8420_init
,
1163 .setup
= pci_default_setup
,
1164 .exit
= __devexit_p(pci_ni8420_exit
),
1167 .vendor
= PCI_VENDOR_ID_NI
,
1168 .device
= PCI_DEVICE_ID_NI_PXI8422_2324
,
1169 .subvendor
= PCI_ANY_ID
,
1170 .subdevice
= PCI_ANY_ID
,
1171 .init
= pci_ni8420_init
,
1172 .setup
= pci_default_setup
,
1173 .exit
= __devexit_p(pci_ni8420_exit
),
1176 .vendor
= PCI_VENDOR_ID_NI
,
1177 .device
= PCI_DEVICE_ID_NI_PXI8422_2322
,
1178 .subvendor
= PCI_ANY_ID
,
1179 .subdevice
= PCI_ANY_ID
,
1180 .init
= pci_ni8420_init
,
1181 .setup
= pci_default_setup
,
1182 .exit
= __devexit_p(pci_ni8420_exit
),
1185 .vendor
= PCI_VENDOR_ID_NI
,
1186 .device
= PCI_ANY_ID
,
1187 .subvendor
= PCI_ANY_ID
,
1188 .subdevice
= PCI_ANY_ID
,
1189 .init
= pci_ni8430_init
,
1190 .setup
= pci_ni8430_setup
,
1191 .exit
= __devexit_p(pci_ni8430_exit
),
1197 .vendor
= PCI_VENDOR_ID_PANACOM
,
1198 .device
= PCI_DEVICE_ID_PANACOM_QUADMODEM
,
1199 .subvendor
= PCI_ANY_ID
,
1200 .subdevice
= PCI_ANY_ID
,
1201 .init
= pci_plx9050_init
,
1202 .setup
= pci_default_setup
,
1203 .exit
= __devexit_p(pci_plx9050_exit
),
1206 .vendor
= PCI_VENDOR_ID_PANACOM
,
1207 .device
= PCI_DEVICE_ID_PANACOM_DUALMODEM
,
1208 .subvendor
= PCI_ANY_ID
,
1209 .subdevice
= PCI_ANY_ID
,
1210 .init
= pci_plx9050_init
,
1211 .setup
= pci_default_setup
,
1212 .exit
= __devexit_p(pci_plx9050_exit
),
1218 .vendor
= PCI_VENDOR_ID_PLX
,
1219 .device
= PCI_DEVICE_ID_PLX_9030
,
1220 .subvendor
= PCI_SUBVENDOR_ID_PERLE
,
1221 .subdevice
= PCI_ANY_ID
,
1222 .setup
= pci_default_setup
,
1225 .vendor
= PCI_VENDOR_ID_PLX
,
1226 .device
= PCI_DEVICE_ID_PLX_9050
,
1227 .subvendor
= PCI_SUBVENDOR_ID_EXSYS
,
1228 .subdevice
= PCI_SUBDEVICE_ID_EXSYS_4055
,
1229 .init
= pci_plx9050_init
,
1230 .setup
= pci_default_setup
,
1231 .exit
= __devexit_p(pci_plx9050_exit
),
1234 .vendor
= PCI_VENDOR_ID_PLX
,
1235 .device
= PCI_DEVICE_ID_PLX_9050
,
1236 .subvendor
= PCI_SUBVENDOR_ID_KEYSPAN
,
1237 .subdevice
= PCI_SUBDEVICE_ID_KEYSPAN_SX2
,
1238 .init
= pci_plx9050_init
,
1239 .setup
= pci_default_setup
,
1240 .exit
= __devexit_p(pci_plx9050_exit
),
1243 .vendor
= PCI_VENDOR_ID_PLX
,
1244 .device
= PCI_DEVICE_ID_PLX_9050
,
1245 .subvendor
= PCI_VENDOR_ID_PLX
,
1246 .subdevice
= PCI_SUBDEVICE_ID_UNKNOWN_0x1584
,
1247 .init
= pci_plx9050_init
,
1248 .setup
= pci_default_setup
,
1249 .exit
= __devexit_p(pci_plx9050_exit
),
1252 .vendor
= PCI_VENDOR_ID_PLX
,
1253 .device
= PCI_DEVICE_ID_PLX_ROMULUS
,
1254 .subvendor
= PCI_VENDOR_ID_PLX
,
1255 .subdevice
= PCI_DEVICE_ID_PLX_ROMULUS
,
1256 .init
= pci_plx9050_init
,
1257 .setup
= pci_default_setup
,
1258 .exit
= __devexit_p(pci_plx9050_exit
),
1261 * SBS Technologies, Inc., PMC-OCTALPRO 232
1264 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
1265 .device
= PCI_DEVICE_ID_OCTPRO
,
1266 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
1267 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO232
,
1270 .exit
= __devexit_p(sbs_exit
),
1273 * SBS Technologies, Inc., PMC-OCTALPRO 422
1276 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
1277 .device
= PCI_DEVICE_ID_OCTPRO
,
1278 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
1279 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO422
,
1282 .exit
= __devexit_p(sbs_exit
),
1285 * SBS Technologies, Inc., P-Octal 232
1288 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
1289 .device
= PCI_DEVICE_ID_OCTPRO
,
1290 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
1291 .subdevice
= PCI_SUBDEVICE_ID_POCTAL232
,
1294 .exit
= __devexit_p(sbs_exit
),
1297 * SBS Technologies, Inc., P-Octal 422
1300 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
1301 .device
= PCI_DEVICE_ID_OCTPRO
,
1302 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
1303 .subdevice
= PCI_SUBDEVICE_ID_POCTAL422
,
1306 .exit
= __devexit_p(sbs_exit
),
1309 * SIIG cards - these may be called via parport_serial
1312 .vendor
= PCI_VENDOR_ID_SIIG
,
1313 .device
= PCI_ANY_ID
,
1314 .subvendor
= PCI_ANY_ID
,
1315 .subdevice
= PCI_ANY_ID
,
1316 .init
= pci_siig_init
,
1317 .setup
= pci_siig_setup
,
1323 .vendor
= PCI_VENDOR_ID_TITAN
,
1324 .device
= PCI_DEVICE_ID_TITAN_400L
,
1325 .subvendor
= PCI_ANY_ID
,
1326 .subdevice
= PCI_ANY_ID
,
1327 .setup
= titan_400l_800l_setup
,
1330 .vendor
= PCI_VENDOR_ID_TITAN
,
1331 .device
= PCI_DEVICE_ID_TITAN_800L
,
1332 .subvendor
= PCI_ANY_ID
,
1333 .subdevice
= PCI_ANY_ID
,
1334 .setup
= titan_400l_800l_setup
,
1340 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
1341 .device
= PCI_DEVICE_ID_TIMEDIA_1889
,
1342 .subvendor
= PCI_VENDOR_ID_TIMEDIA
,
1343 .subdevice
= PCI_ANY_ID
,
1344 .init
= pci_timedia_init
,
1345 .setup
= pci_timedia_setup
,
1348 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
1349 .device
= PCI_ANY_ID
,
1350 .subvendor
= PCI_ANY_ID
,
1351 .subdevice
= PCI_ANY_ID
,
1352 .setup
= pci_timedia_setup
,
1358 .vendor
= PCI_VENDOR_ID_XIRCOM
,
1359 .device
= PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
1360 .subvendor
= PCI_ANY_ID
,
1361 .subdevice
= PCI_ANY_ID
,
1362 .init
= pci_xircom_init
,
1363 .setup
= pci_default_setup
,
1366 * Netmos cards - these may be called via parport_serial
1369 .vendor
= PCI_VENDOR_ID_NETMOS
,
1370 .device
= PCI_ANY_ID
,
1371 .subvendor
= PCI_ANY_ID
,
1372 .subdevice
= PCI_ANY_ID
,
1373 .init
= pci_netmos_init
,
1374 .setup
= pci_default_setup
,
1377 * For Oxford Semiconductor and Mainpine
1380 .vendor
= PCI_VENDOR_ID_OXSEMI
,
1381 .device
= PCI_ANY_ID
,
1382 .subvendor
= PCI_ANY_ID
,
1383 .subdevice
= PCI_ANY_ID
,
1384 .init
= pci_oxsemi_tornado_init
,
1385 .setup
= pci_default_setup
,
1388 .vendor
= PCI_VENDOR_ID_MAINPINE
,
1389 .device
= PCI_ANY_ID
,
1390 .subvendor
= PCI_ANY_ID
,
1391 .subdevice
= PCI_ANY_ID
,
1392 .init
= pci_oxsemi_tornado_init
,
1393 .setup
= pci_default_setup
,
1396 * Default "match everything" terminator entry
1399 .vendor
= PCI_ANY_ID
,
1400 .device
= PCI_ANY_ID
,
1401 .subvendor
= PCI_ANY_ID
,
1402 .subdevice
= PCI_ANY_ID
,
1403 .setup
= pci_default_setup
,
1407 static inline int quirk_id_matches(u32 quirk_id
, u32 dev_id
)
1409 return quirk_id
== PCI_ANY_ID
|| quirk_id
== dev_id
;
1412 static struct pci_serial_quirk
*find_quirk(struct pci_dev
*dev
)
1414 struct pci_serial_quirk
*quirk
;
1416 for (quirk
= pci_serial_quirks
; ; quirk
++)
1417 if (quirk_id_matches(quirk
->vendor
, dev
->vendor
) &&
1418 quirk_id_matches(quirk
->device
, dev
->device
) &&
1419 quirk_id_matches(quirk
->subvendor
, dev
->subsystem_vendor
) &&
1420 quirk_id_matches(quirk
->subdevice
, dev
->subsystem_device
))
1425 static inline int get_pci_irq(struct pci_dev
*dev
,
1426 const struct pciserial_board
*board
)
1428 if (board
->flags
& FL_NOIRQ
)
1435 * This is the configuration table for all of the PCI serial boards
1436 * which we support. It is directly indexed by the pci_board_num_t enum
1437 * value, which is encoded in the pci_device_id PCI probe table's
1438 * driver_data member.
1440 * The makeup of these names are:
1441 * pbn_bn{_bt}_n_baud{_offsetinhex}
1443 * bn = PCI BAR number
1444 * bt = Index using PCI BARs
1445 * n = number of serial ports
1447 * offsetinhex = offset for each sequential port (in hex)
1449 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1451 * Please note: in theory if n = 1, _bt infix should make no difference.
1452 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1454 enum pci_board_num_t
{
1474 pbn_b0_2_1843200_200
,
1475 pbn_b0_4_1843200_200
,
1476 pbn_b0_8_1843200_200
,
1543 * Board-specific versions.
1551 pbn_oxsemi_1_4000000
,
1552 pbn_oxsemi_2_4000000
,
1553 pbn_oxsemi_4_4000000
,
1554 pbn_oxsemi_8_4000000
,
1564 pbn_exar_ibm_saturn
,
1570 pbn_ADDIDATA_PCIe_1_3906250
,
1571 pbn_ADDIDATA_PCIe_2_3906250
,
1572 pbn_ADDIDATA_PCIe_4_3906250
,
1573 pbn_ADDIDATA_PCIe_8_3906250
,
1577 * uart_offset - the space between channels
1578 * reg_shift - describes how the UART registers are mapped
1579 * to PCI memory by the card.
1580 * For example IER register on SBS, Inc. PMC-OctPro is located at
1581 * offset 0x10 from the UART base, while UART_IER is defined as 1
1582 * in include/linux/serial_reg.h,
1583 * see first lines of serial_in() and serial_out() in 8250.c
1586 static struct pciserial_board pci_boards
[] __devinitdata
= {
1590 .base_baud
= 115200,
1593 [pbn_b0_1_115200
] = {
1596 .base_baud
= 115200,
1599 [pbn_b0_2_115200
] = {
1602 .base_baud
= 115200,
1605 [pbn_b0_4_115200
] = {
1608 .base_baud
= 115200,
1611 [pbn_b0_5_115200
] = {
1614 .base_baud
= 115200,
1617 [pbn_b0_8_115200
] = {
1620 .base_baud
= 115200,
1623 [pbn_b0_1_921600
] = {
1626 .base_baud
= 921600,
1629 [pbn_b0_2_921600
] = {
1632 .base_baud
= 921600,
1635 [pbn_b0_4_921600
] = {
1638 .base_baud
= 921600,
1642 [pbn_b0_2_1130000
] = {
1645 .base_baud
= 1130000,
1649 [pbn_b0_4_1152000
] = {
1652 .base_baud
= 1152000,
1656 [pbn_b0_2_1843200
] = {
1659 .base_baud
= 1843200,
1662 [pbn_b0_4_1843200
] = {
1665 .base_baud
= 1843200,
1669 [pbn_b0_2_1843200_200
] = {
1672 .base_baud
= 1843200,
1673 .uart_offset
= 0x200,
1675 [pbn_b0_4_1843200_200
] = {
1678 .base_baud
= 1843200,
1679 .uart_offset
= 0x200,
1681 [pbn_b0_8_1843200_200
] = {
1684 .base_baud
= 1843200,
1685 .uart_offset
= 0x200,
1687 [pbn_b0_1_4000000
] = {
1690 .base_baud
= 4000000,
1694 [pbn_b0_bt_1_115200
] = {
1695 .flags
= FL_BASE0
|FL_BASE_BARS
,
1697 .base_baud
= 115200,
1700 [pbn_b0_bt_2_115200
] = {
1701 .flags
= FL_BASE0
|FL_BASE_BARS
,
1703 .base_baud
= 115200,
1706 [pbn_b0_bt_8_115200
] = {
1707 .flags
= FL_BASE0
|FL_BASE_BARS
,
1709 .base_baud
= 115200,
1713 [pbn_b0_bt_1_460800
] = {
1714 .flags
= FL_BASE0
|FL_BASE_BARS
,
1716 .base_baud
= 460800,
1719 [pbn_b0_bt_2_460800
] = {
1720 .flags
= FL_BASE0
|FL_BASE_BARS
,
1722 .base_baud
= 460800,
1725 [pbn_b0_bt_4_460800
] = {
1726 .flags
= FL_BASE0
|FL_BASE_BARS
,
1728 .base_baud
= 460800,
1732 [pbn_b0_bt_1_921600
] = {
1733 .flags
= FL_BASE0
|FL_BASE_BARS
,
1735 .base_baud
= 921600,
1738 [pbn_b0_bt_2_921600
] = {
1739 .flags
= FL_BASE0
|FL_BASE_BARS
,
1741 .base_baud
= 921600,
1744 [pbn_b0_bt_4_921600
] = {
1745 .flags
= FL_BASE0
|FL_BASE_BARS
,
1747 .base_baud
= 921600,
1750 [pbn_b0_bt_8_921600
] = {
1751 .flags
= FL_BASE0
|FL_BASE_BARS
,
1753 .base_baud
= 921600,
1757 [pbn_b1_1_115200
] = {
1760 .base_baud
= 115200,
1763 [pbn_b1_2_115200
] = {
1766 .base_baud
= 115200,
1769 [pbn_b1_4_115200
] = {
1772 .base_baud
= 115200,
1775 [pbn_b1_8_115200
] = {
1778 .base_baud
= 115200,
1781 [pbn_b1_16_115200
] = {
1784 .base_baud
= 115200,
1788 [pbn_b1_1_921600
] = {
1791 .base_baud
= 921600,
1794 [pbn_b1_2_921600
] = {
1797 .base_baud
= 921600,
1800 [pbn_b1_4_921600
] = {
1803 .base_baud
= 921600,
1806 [pbn_b1_8_921600
] = {
1809 .base_baud
= 921600,
1812 [pbn_b1_2_1250000
] = {
1815 .base_baud
= 1250000,
1819 [pbn_b1_bt_1_115200
] = {
1820 .flags
= FL_BASE1
|FL_BASE_BARS
,
1822 .base_baud
= 115200,
1825 [pbn_b1_bt_2_115200
] = {
1826 .flags
= FL_BASE1
|FL_BASE_BARS
,
1828 .base_baud
= 115200,
1831 [pbn_b1_bt_4_115200
] = {
1832 .flags
= FL_BASE1
|FL_BASE_BARS
,
1834 .base_baud
= 115200,
1838 [pbn_b1_bt_2_921600
] = {
1839 .flags
= FL_BASE1
|FL_BASE_BARS
,
1841 .base_baud
= 921600,
1845 [pbn_b1_1_1382400
] = {
1848 .base_baud
= 1382400,
1851 [pbn_b1_2_1382400
] = {
1854 .base_baud
= 1382400,
1857 [pbn_b1_4_1382400
] = {
1860 .base_baud
= 1382400,
1863 [pbn_b1_8_1382400
] = {
1866 .base_baud
= 1382400,
1870 [pbn_b2_1_115200
] = {
1873 .base_baud
= 115200,
1876 [pbn_b2_2_115200
] = {
1879 .base_baud
= 115200,
1882 [pbn_b2_4_115200
] = {
1885 .base_baud
= 115200,
1888 [pbn_b2_8_115200
] = {
1891 .base_baud
= 115200,
1895 [pbn_b2_1_460800
] = {
1898 .base_baud
= 460800,
1901 [pbn_b2_4_460800
] = {
1904 .base_baud
= 460800,
1907 [pbn_b2_8_460800
] = {
1910 .base_baud
= 460800,
1913 [pbn_b2_16_460800
] = {
1916 .base_baud
= 460800,
1920 [pbn_b2_1_921600
] = {
1923 .base_baud
= 921600,
1926 [pbn_b2_4_921600
] = {
1929 .base_baud
= 921600,
1932 [pbn_b2_8_921600
] = {
1935 .base_baud
= 921600,
1939 [pbn_b2_bt_1_115200
] = {
1940 .flags
= FL_BASE2
|FL_BASE_BARS
,
1942 .base_baud
= 115200,
1945 [pbn_b2_bt_2_115200
] = {
1946 .flags
= FL_BASE2
|FL_BASE_BARS
,
1948 .base_baud
= 115200,
1951 [pbn_b2_bt_4_115200
] = {
1952 .flags
= FL_BASE2
|FL_BASE_BARS
,
1954 .base_baud
= 115200,
1958 [pbn_b2_bt_2_921600
] = {
1959 .flags
= FL_BASE2
|FL_BASE_BARS
,
1961 .base_baud
= 921600,
1964 [pbn_b2_bt_4_921600
] = {
1965 .flags
= FL_BASE2
|FL_BASE_BARS
,
1967 .base_baud
= 921600,
1971 [pbn_b3_2_115200
] = {
1974 .base_baud
= 115200,
1977 [pbn_b3_4_115200
] = {
1980 .base_baud
= 115200,
1983 [pbn_b3_8_115200
] = {
1986 .base_baud
= 115200,
1991 * Entries following this are board-specific.
2000 .base_baud
= 921600,
2001 .uart_offset
= 0x400,
2005 .flags
= FL_BASE2
|FL_BASE_BARS
,
2007 .base_baud
= 921600,
2008 .uart_offset
= 0x400,
2012 .flags
= FL_BASE2
|FL_BASE_BARS
,
2014 .base_baud
= 921600,
2015 .uart_offset
= 0x400,
2019 [pbn_exsys_4055
] = {
2022 .base_baud
= 115200,
2026 /* I think this entry is broken - the first_offset looks wrong --rmk */
2027 [pbn_plx_romulus
] = {
2030 .base_baud
= 921600,
2031 .uart_offset
= 8 << 2,
2033 .first_offset
= 0x03,
2037 * This board uses the size of PCI Base region 0 to
2038 * signal now many ports are available
2041 .flags
= FL_BASE0
|FL_REGION_SZ_CAP
,
2043 .base_baud
= 115200,
2046 [pbn_oxsemi_1_4000000
] = {
2049 .base_baud
= 4000000,
2050 .uart_offset
= 0x200,
2051 .first_offset
= 0x1000,
2053 [pbn_oxsemi_2_4000000
] = {
2056 .base_baud
= 4000000,
2057 .uart_offset
= 0x200,
2058 .first_offset
= 0x1000,
2060 [pbn_oxsemi_4_4000000
] = {
2063 .base_baud
= 4000000,
2064 .uart_offset
= 0x200,
2065 .first_offset
= 0x1000,
2067 [pbn_oxsemi_8_4000000
] = {
2070 .base_baud
= 4000000,
2071 .uart_offset
= 0x200,
2072 .first_offset
= 0x1000,
2077 * EKF addition for i960 Boards form EKF with serial port.
2080 [pbn_intel_i960
] = {
2083 .base_baud
= 921600,
2084 .uart_offset
= 8 << 2,
2086 .first_offset
= 0x10000,
2089 .flags
= FL_BASE0
|FL_NOIRQ
,
2091 .base_baud
= 458333,
2094 .first_offset
= 0x20178,
2098 * Computone - uses IOMEM.
2100 [pbn_computone_4
] = {
2103 .base_baud
= 921600,
2104 .uart_offset
= 0x40,
2106 .first_offset
= 0x200,
2108 [pbn_computone_6
] = {
2111 .base_baud
= 921600,
2112 .uart_offset
= 0x40,
2114 .first_offset
= 0x200,
2116 [pbn_computone_8
] = {
2119 .base_baud
= 921600,
2120 .uart_offset
= 0x40,
2122 .first_offset
= 0x200,
2127 .base_baud
= 460800,
2132 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2133 * Only basic 16550A support.
2134 * XR17C15[24] are not tested, but they should work.
2136 [pbn_exar_XR17C152
] = {
2139 .base_baud
= 921600,
2140 .uart_offset
= 0x200,
2142 [pbn_exar_XR17C154
] = {
2145 .base_baud
= 921600,
2146 .uart_offset
= 0x200,
2148 [pbn_exar_XR17C158
] = {
2151 .base_baud
= 921600,
2152 .uart_offset
= 0x200,
2154 [pbn_exar_ibm_saturn
] = {
2157 .base_baud
= 921600,
2158 .uart_offset
= 0x200,
2162 * PA Semi PWRficient PA6T-1682M on-chip UART
2164 [pbn_pasemi_1682M
] = {
2167 .base_baud
= 8333333,
2170 * National Instruments 843x
2175 .base_baud
= 3686400,
2176 .uart_offset
= 0x10,
2177 .first_offset
= 0x800,
2182 .base_baud
= 3686400,
2183 .uart_offset
= 0x10,
2184 .first_offset
= 0x800,
2189 .base_baud
= 3686400,
2190 .uart_offset
= 0x10,
2191 .first_offset
= 0x800,
2196 .base_baud
= 3686400,
2197 .uart_offset
= 0x10,
2198 .first_offset
= 0x800,
2201 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2203 [pbn_ADDIDATA_PCIe_1_3906250
] = {
2206 .base_baud
= 3906250,
2207 .uart_offset
= 0x200,
2208 .first_offset
= 0x1000,
2210 [pbn_ADDIDATA_PCIe_2_3906250
] = {
2213 .base_baud
= 3906250,
2214 .uart_offset
= 0x200,
2215 .first_offset
= 0x1000,
2217 [pbn_ADDIDATA_PCIe_4_3906250
] = {
2220 .base_baud
= 3906250,
2221 .uart_offset
= 0x200,
2222 .first_offset
= 0x1000,
2224 [pbn_ADDIDATA_PCIe_8_3906250
] = {
2227 .base_baud
= 3906250,
2228 .uart_offset
= 0x200,
2229 .first_offset
= 0x1000,
2233 static const struct pci_device_id softmodem_blacklist
[] = {
2234 { PCI_VDEVICE(AL
, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2238 * Given a complete unknown PCI device, try to use some heuristics to
2239 * guess what the configuration might be, based on the pitiful PCI
2240 * serial specs. Returns 0 on success, 1 on failure.
2242 static int __devinit
2243 serial_pci_guess_board(struct pci_dev
*dev
, struct pciserial_board
*board
)
2245 const struct pci_device_id
*blacklist
;
2246 int num_iomem
, num_port
, first_port
= -1, i
;
2249 * If it is not a communications device or the programming
2250 * interface is greater than 6, give up.
2252 * (Should we try to make guesses for multiport serial devices
2255 if ((((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL
) &&
2256 ((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM
)) ||
2257 (dev
->class & 0xff) > 6)
2261 * Do not access blacklisted devices that are known not to
2262 * feature serial ports.
2264 for (blacklist
= softmodem_blacklist
;
2265 blacklist
< softmodem_blacklist
+ ARRAY_SIZE(softmodem_blacklist
);
2267 if (dev
->vendor
== blacklist
->vendor
&&
2268 dev
->device
== blacklist
->device
)
2272 num_iomem
= num_port
= 0;
2273 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
2274 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
) {
2276 if (first_port
== -1)
2279 if (pci_resource_flags(dev
, i
) & IORESOURCE_MEM
)
2284 * If there is 1 or 0 iomem regions, and exactly one port,
2285 * use it. We guess the number of ports based on the IO
2288 if (num_iomem
<= 1 && num_port
== 1) {
2289 board
->flags
= first_port
;
2290 board
->num_ports
= pci_resource_len(dev
, first_port
) / 8;
2295 * Now guess if we've got a board which indexes by BARs.
2296 * Each IO BAR should be 8 bytes, and they should follow
2301 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
2302 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
&&
2303 pci_resource_len(dev
, i
) == 8 &&
2304 (first_port
== -1 || (first_port
+ num_port
) == i
)) {
2306 if (first_port
== -1)
2312 board
->flags
= first_port
| FL_BASE_BARS
;
2313 board
->num_ports
= num_port
;
2321 serial_pci_matches(const struct pciserial_board
*board
,
2322 const struct pciserial_board
*guessed
)
2325 board
->num_ports
== guessed
->num_ports
&&
2326 board
->base_baud
== guessed
->base_baud
&&
2327 board
->uart_offset
== guessed
->uart_offset
&&
2328 board
->reg_shift
== guessed
->reg_shift
&&
2329 board
->first_offset
== guessed
->first_offset
;
2332 struct serial_private
*
2333 pciserial_init_ports(struct pci_dev
*dev
, const struct pciserial_board
*board
)
2335 struct uart_port serial_port
;
2336 struct serial_private
*priv
;
2337 struct pci_serial_quirk
*quirk
;
2338 int rc
, nr_ports
, i
;
2340 nr_ports
= board
->num_ports
;
2343 * Find an init and setup quirks.
2345 quirk
= find_quirk(dev
);
2348 * Run the new-style initialization function.
2349 * The initialization function returns:
2351 * 0 - use board->num_ports
2352 * >0 - number of ports
2355 rc
= quirk
->init(dev
);
2364 priv
= kzalloc(sizeof(struct serial_private
) +
2365 sizeof(unsigned int) * nr_ports
,
2368 priv
= ERR_PTR(-ENOMEM
);
2373 priv
->quirk
= quirk
;
2375 memset(&serial_port
, 0, sizeof(struct uart_port
));
2376 serial_port
.flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
| UPF_SHARE_IRQ
;
2377 serial_port
.uartclk
= board
->base_baud
* 16;
2378 serial_port
.irq
= get_pci_irq(dev
, board
);
2379 serial_port
.dev
= &dev
->dev
;
2381 for (i
= 0; i
< nr_ports
; i
++) {
2382 if (quirk
->setup(priv
, board
, &serial_port
, i
))
2385 #ifdef SERIAL_DEBUG_PCI
2386 printk(KERN_DEBUG
"Setup PCI port: port %lx, irq %d, type %d\n",
2387 serial_port
.iobase
, serial_port
.irq
, serial_port
.iotype
);
2390 priv
->line
[i
] = serial8250_register_port(&serial_port
);
2391 if (priv
->line
[i
] < 0) {
2392 printk(KERN_WARNING
"Couldn't register serial port %s: %d\n", pci_name(dev
), priv
->line
[i
]);
2405 EXPORT_SYMBOL_GPL(pciserial_init_ports
);
2407 void pciserial_remove_ports(struct serial_private
*priv
)
2409 struct pci_serial_quirk
*quirk
;
2412 for (i
= 0; i
< priv
->nr
; i
++)
2413 serial8250_unregister_port(priv
->line
[i
]);
2415 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
2416 if (priv
->remapped_bar
[i
])
2417 iounmap(priv
->remapped_bar
[i
]);
2418 priv
->remapped_bar
[i
] = NULL
;
2422 * Find the exit quirks.
2424 quirk
= find_quirk(priv
->dev
);
2426 quirk
->exit(priv
->dev
);
2430 EXPORT_SYMBOL_GPL(pciserial_remove_ports
);
2432 void pciserial_suspend_ports(struct serial_private
*priv
)
2436 for (i
= 0; i
< priv
->nr
; i
++)
2437 if (priv
->line
[i
] >= 0)
2438 serial8250_suspend_port(priv
->line
[i
]);
2440 EXPORT_SYMBOL_GPL(pciserial_suspend_ports
);
2442 void pciserial_resume_ports(struct serial_private
*priv
)
2447 * Ensure that the board is correctly configured.
2449 if (priv
->quirk
->init
)
2450 priv
->quirk
->init(priv
->dev
);
2452 for (i
= 0; i
< priv
->nr
; i
++)
2453 if (priv
->line
[i
] >= 0)
2454 serial8250_resume_port(priv
->line
[i
]);
2456 EXPORT_SYMBOL_GPL(pciserial_resume_ports
);
2459 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2460 * to the arrangement of serial ports on a PCI card.
2462 static int __devinit
2463 pciserial_init_one(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
2465 struct serial_private
*priv
;
2466 const struct pciserial_board
*board
;
2467 struct pciserial_board tmp
;
2470 if (ent
->driver_data
>= ARRAY_SIZE(pci_boards
)) {
2471 printk(KERN_ERR
"pci_init_one: invalid driver_data: %ld\n",
2476 board
= &pci_boards
[ent
->driver_data
];
2478 rc
= pci_enable_device(dev
);
2482 if (ent
->driver_data
== pbn_default
) {
2484 * Use a copy of the pci_board entry for this;
2485 * avoid changing entries in the table.
2487 memcpy(&tmp
, board
, sizeof(struct pciserial_board
));
2491 * We matched one of our class entries. Try to
2492 * determine the parameters of this board.
2494 rc
= serial_pci_guess_board(dev
, &tmp
);
2499 * We matched an explicit entry. If we are able to
2500 * detect this boards settings with our heuristic,
2501 * then we no longer need this entry.
2503 memcpy(&tmp
, &pci_boards
[pbn_default
],
2504 sizeof(struct pciserial_board
));
2505 rc
= serial_pci_guess_board(dev
, &tmp
);
2506 if (rc
== 0 && serial_pci_matches(board
, &tmp
))
2507 moan_device("Redundant entry in serial pci_table.",
2511 priv
= pciserial_init_ports(dev
, board
);
2512 if (!IS_ERR(priv
)) {
2513 pci_set_drvdata(dev
, priv
);
2520 pci_disable_device(dev
);
2524 static void __devexit
pciserial_remove_one(struct pci_dev
*dev
)
2526 struct serial_private
*priv
= pci_get_drvdata(dev
);
2528 pci_set_drvdata(dev
, NULL
);
2530 pciserial_remove_ports(priv
);
2532 pci_disable_device(dev
);
2536 static int pciserial_suspend_one(struct pci_dev
*dev
, pm_message_t state
)
2538 struct serial_private
*priv
= pci_get_drvdata(dev
);
2541 pciserial_suspend_ports(priv
);
2543 pci_save_state(dev
);
2544 pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2548 static int pciserial_resume_one(struct pci_dev
*dev
)
2551 struct serial_private
*priv
= pci_get_drvdata(dev
);
2553 pci_set_power_state(dev
, PCI_D0
);
2554 pci_restore_state(dev
);
2558 * The device may have been disabled. Re-enable it.
2560 err
= pci_enable_device(dev
);
2561 /* FIXME: We cannot simply error out here */
2563 printk(KERN_ERR
"pciserial: Unable to re-enable ports, trying to continue.\n");
2564 pciserial_resume_ports(priv
);
2570 static struct pci_device_id serial_pci_tbl
[] = {
2571 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2572 { PCI_VENDOR_ID_ADVANTECH
, PCI_DEVICE_ID_ADVANTECH_PCI3620
,
2573 PCI_DEVICE_ID_ADVANTECH_PCI3620
, 0x0001, 0, 0,
2575 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
2576 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2577 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
2579 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
2580 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2581 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
2583 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
2584 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2585 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
2587 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2588 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2589 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
2591 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2592 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2593 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
2595 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2596 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2597 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
2599 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2600 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2601 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485
, 0, 0,
2603 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2604 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2605 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4
, 0, 0,
2607 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2608 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2609 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485
, 0, 0,
2611 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2612 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2613 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2
, 0, 0,
2615 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2616 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2617 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485
, 0, 0,
2619 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2620 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2621 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6
, 0, 0,
2623 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2624 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2625 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1
, 0, 0,
2627 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2628 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2629 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1
, 0, 0,
2631 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2632 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2633 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ
, 0, 0,
2635 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2636 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2637 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2
, 0, 0,
2639 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2640 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2641 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4
, 0, 0,
2643 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2644 PCI_VENDOR_ID_AFAVLAB
,
2645 PCI_SUBDEVICE_ID_AFAVLAB_P061
, 0, 0,
2647 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2648 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2649 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232
, 0, 0,
2650 pbn_b0_2_1843200_200
},
2651 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2652 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2653 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232
, 0, 0,
2654 pbn_b0_4_1843200_200
},
2655 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2656 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2657 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232
, 0, 0,
2658 pbn_b0_8_1843200_200
},
2659 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2660 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2661 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1
, 0, 0,
2662 pbn_b0_2_1843200_200
},
2663 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2664 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2665 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2
, 0, 0,
2666 pbn_b0_4_1843200_200
},
2667 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2668 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2669 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4
, 0, 0,
2670 pbn_b0_8_1843200_200
},
2671 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2672 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2673 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2
, 0, 0,
2674 pbn_b0_2_1843200_200
},
2675 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2676 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2677 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4
, 0, 0,
2678 pbn_b0_4_1843200_200
},
2679 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2680 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2681 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8
, 0, 0,
2682 pbn_b0_8_1843200_200
},
2683 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2684 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2685 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485
, 0, 0,
2686 pbn_b0_2_1843200_200
},
2687 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2688 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2689 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485
, 0, 0,
2690 pbn_b0_4_1843200_200
},
2691 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2692 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2693 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485
, 0, 0,
2694 pbn_b0_8_1843200_200
},
2695 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2696 PCI_VENDOR_ID_IBM
, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT
,
2697 0, 0, pbn_exar_ibm_saturn
},
2699 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_U530
,
2700 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2701 pbn_b2_bt_1_115200
},
2702 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM2
,
2703 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2704 pbn_b2_bt_2_115200
},
2705 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM422
,
2706 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2707 pbn_b2_bt_4_115200
},
2708 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM232
,
2709 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2710 pbn_b2_bt_2_115200
},
2711 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM4
,
2712 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2713 pbn_b2_bt_4_115200
},
2714 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM8
,
2715 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2717 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_7803
,
2718 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2720 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM8
,
2721 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2724 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_GTEK_SERIAL2
,
2725 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2726 pbn_b2_bt_2_115200
},
2727 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM200
,
2728 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2729 pbn_b2_bt_2_921600
},
2731 * VScom SPCOM800, from sl@s.pl
2733 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM800
,
2734 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2736 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_1077
,
2737 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2739 /* Unknown card - subdevice 0x1584 */
2740 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2742 PCI_SUBDEVICE_ID_UNKNOWN_0x1584
, 0, 0,
2744 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2745 PCI_SUBVENDOR_ID_KEYSPAN
,
2746 PCI_SUBDEVICE_ID_KEYSPAN_SX2
, 0, 0,
2748 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_QUADMODEM
,
2749 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2751 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_DUALMODEM
,
2752 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2754 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
2755 PCI_VENDOR_ID_ESDGMBH
,
2756 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4
, 0, 0,
2758 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2759 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2760 PCI_SUBDEVICE_ID_CHASE_PCIFAST4
, 0, 0,
2762 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2763 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2764 PCI_SUBDEVICE_ID_CHASE_PCIFAST8
, 0, 0,
2766 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2767 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2768 PCI_SUBDEVICE_ID_CHASE_PCIFAST16
, 0, 0,
2770 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2771 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2772 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC
, 0, 0,
2774 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2775 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
2776 PCI_SUBDEVICE_ID_CHASE_PCIRAS4
, 0, 0,
2778 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2779 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
2780 PCI_SUBDEVICE_ID_CHASE_PCIRAS8
, 0, 0,
2782 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2783 PCI_SUBVENDOR_ID_EXSYS
,
2784 PCI_SUBDEVICE_ID_EXSYS_4055
, 0, 0,
2787 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2790 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_ROMULUS
,
2791 0x10b5, 0x106a, 0, 0,
2793 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSC100
,
2794 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2796 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC100
,
2797 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2799 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100D
,
2800 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2802 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100M
,
2803 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2805 { PCI_VENDOR_ID_SPECIALIX
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2806 PCI_VENDOR_ID_SPECIALIX
, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4
,
2809 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2810 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL
,
2815 * The below card is a little controversial since it is the
2816 * subject of a PCI vendor/device ID clash. (See
2817 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2818 * For now just used the hex ID 0x950a.
2820 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
2821 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL
, 0, 0,
2823 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
2824 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2826 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_C950
,
2827 PCI_VENDOR_ID_OXSEMI
, PCI_SUBDEVICE_ID_OXSEMI_C950
, 0, 0,
2829 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2830 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2832 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI952
,
2833 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2834 pbn_b0_bt_2_921600
},
2837 * Oxford Semiconductor Inc. Tornado PCI express device range.
2839 { PCI_VENDOR_ID_OXSEMI
, 0xc101, /* OXPCIe952 1 Legacy UART */
2840 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2842 { PCI_VENDOR_ID_OXSEMI
, 0xc105, /* OXPCIe952 1 Legacy UART */
2843 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2845 { PCI_VENDOR_ID_OXSEMI
, 0xc11b, /* OXPCIe952 1 Native UART */
2846 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2847 pbn_oxsemi_1_4000000
},
2848 { PCI_VENDOR_ID_OXSEMI
, 0xc11f, /* OXPCIe952 1 Native UART */
2849 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2850 pbn_oxsemi_1_4000000
},
2851 { PCI_VENDOR_ID_OXSEMI
, 0xc120, /* OXPCIe952 1 Legacy UART */
2852 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2854 { PCI_VENDOR_ID_OXSEMI
, 0xc124, /* OXPCIe952 1 Legacy UART */
2855 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2857 { PCI_VENDOR_ID_OXSEMI
, 0xc138, /* OXPCIe952 1 Native UART */
2858 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2859 pbn_oxsemi_1_4000000
},
2860 { PCI_VENDOR_ID_OXSEMI
, 0xc13d, /* OXPCIe952 1 Native UART */
2861 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2862 pbn_oxsemi_1_4000000
},
2863 { PCI_VENDOR_ID_OXSEMI
, 0xc140, /* OXPCIe952 1 Legacy UART */
2864 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2866 { PCI_VENDOR_ID_OXSEMI
, 0xc141, /* OXPCIe952 1 Legacy UART */
2867 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2869 { PCI_VENDOR_ID_OXSEMI
, 0xc144, /* OXPCIe952 1 Legacy UART */
2870 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2872 { PCI_VENDOR_ID_OXSEMI
, 0xc145, /* OXPCIe952 1 Legacy UART */
2873 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2875 { PCI_VENDOR_ID_OXSEMI
, 0xc158, /* OXPCIe952 2 Native UART */
2876 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2877 pbn_oxsemi_2_4000000
},
2878 { PCI_VENDOR_ID_OXSEMI
, 0xc15d, /* OXPCIe952 2 Native UART */
2879 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2880 pbn_oxsemi_2_4000000
},
2881 { PCI_VENDOR_ID_OXSEMI
, 0xc208, /* OXPCIe954 4 Native UART */
2882 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2883 pbn_oxsemi_4_4000000
},
2884 { PCI_VENDOR_ID_OXSEMI
, 0xc20d, /* OXPCIe954 4 Native UART */
2885 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2886 pbn_oxsemi_4_4000000
},
2887 { PCI_VENDOR_ID_OXSEMI
, 0xc308, /* OXPCIe958 8 Native UART */
2888 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2889 pbn_oxsemi_8_4000000
},
2890 { PCI_VENDOR_ID_OXSEMI
, 0xc30d, /* OXPCIe958 8 Native UART */
2891 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2892 pbn_oxsemi_8_4000000
},
2893 { PCI_VENDOR_ID_OXSEMI
, 0xc40b, /* OXPCIe200 1 Native UART */
2894 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2895 pbn_oxsemi_1_4000000
},
2896 { PCI_VENDOR_ID_OXSEMI
, 0xc40f, /* OXPCIe200 1 Native UART */
2897 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2898 pbn_oxsemi_1_4000000
},
2899 { PCI_VENDOR_ID_OXSEMI
, 0xc41b, /* OXPCIe200 1 Native UART */
2900 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2901 pbn_oxsemi_1_4000000
},
2902 { PCI_VENDOR_ID_OXSEMI
, 0xc41f, /* OXPCIe200 1 Native UART */
2903 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2904 pbn_oxsemi_1_4000000
},
2905 { PCI_VENDOR_ID_OXSEMI
, 0xc42b, /* OXPCIe200 1 Native UART */
2906 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2907 pbn_oxsemi_1_4000000
},
2908 { PCI_VENDOR_ID_OXSEMI
, 0xc42f, /* OXPCIe200 1 Native UART */
2909 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2910 pbn_oxsemi_1_4000000
},
2911 { PCI_VENDOR_ID_OXSEMI
, 0xc43b, /* OXPCIe200 1 Native UART */
2912 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2913 pbn_oxsemi_1_4000000
},
2914 { PCI_VENDOR_ID_OXSEMI
, 0xc43f, /* OXPCIe200 1 Native UART */
2915 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2916 pbn_oxsemi_1_4000000
},
2917 { PCI_VENDOR_ID_OXSEMI
, 0xc44b, /* OXPCIe200 1 Native UART */
2918 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2919 pbn_oxsemi_1_4000000
},
2920 { PCI_VENDOR_ID_OXSEMI
, 0xc44f, /* OXPCIe200 1 Native UART */
2921 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2922 pbn_oxsemi_1_4000000
},
2923 { PCI_VENDOR_ID_OXSEMI
, 0xc45b, /* OXPCIe200 1 Native UART */
2924 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2925 pbn_oxsemi_1_4000000
},
2926 { PCI_VENDOR_ID_OXSEMI
, 0xc45f, /* OXPCIe200 1 Native UART */
2927 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2928 pbn_oxsemi_1_4000000
},
2929 { PCI_VENDOR_ID_OXSEMI
, 0xc46b, /* OXPCIe200 1 Native UART */
2930 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2931 pbn_oxsemi_1_4000000
},
2932 { PCI_VENDOR_ID_OXSEMI
, 0xc46f, /* OXPCIe200 1 Native UART */
2933 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2934 pbn_oxsemi_1_4000000
},
2935 { PCI_VENDOR_ID_OXSEMI
, 0xc47b, /* OXPCIe200 1 Native UART */
2936 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2937 pbn_oxsemi_1_4000000
},
2938 { PCI_VENDOR_ID_OXSEMI
, 0xc47f, /* OXPCIe200 1 Native UART */
2939 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2940 pbn_oxsemi_1_4000000
},
2941 { PCI_VENDOR_ID_OXSEMI
, 0xc48b, /* OXPCIe200 1 Native UART */
2942 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2943 pbn_oxsemi_1_4000000
},
2944 { PCI_VENDOR_ID_OXSEMI
, 0xc48f, /* OXPCIe200 1 Native UART */
2945 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2946 pbn_oxsemi_1_4000000
},
2947 { PCI_VENDOR_ID_OXSEMI
, 0xc49b, /* OXPCIe200 1 Native UART */
2948 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2949 pbn_oxsemi_1_4000000
},
2950 { PCI_VENDOR_ID_OXSEMI
, 0xc49f, /* OXPCIe200 1 Native UART */
2951 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2952 pbn_oxsemi_1_4000000
},
2953 { PCI_VENDOR_ID_OXSEMI
, 0xc4ab, /* OXPCIe200 1 Native UART */
2954 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2955 pbn_oxsemi_1_4000000
},
2956 { PCI_VENDOR_ID_OXSEMI
, 0xc4af, /* OXPCIe200 1 Native UART */
2957 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2958 pbn_oxsemi_1_4000000
},
2959 { PCI_VENDOR_ID_OXSEMI
, 0xc4bb, /* OXPCIe200 1 Native UART */
2960 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2961 pbn_oxsemi_1_4000000
},
2962 { PCI_VENDOR_ID_OXSEMI
, 0xc4bf, /* OXPCIe200 1 Native UART */
2963 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2964 pbn_oxsemi_1_4000000
},
2965 { PCI_VENDOR_ID_OXSEMI
, 0xc4cb, /* OXPCIe200 1 Native UART */
2966 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2967 pbn_oxsemi_1_4000000
},
2968 { PCI_VENDOR_ID_OXSEMI
, 0xc4cf, /* OXPCIe200 1 Native UART */
2969 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2970 pbn_oxsemi_1_4000000
},
2972 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2974 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2975 PCI_VENDOR_ID_MAINPINE
, 0x4001, 0, 0,
2976 pbn_oxsemi_1_4000000
},
2977 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2978 PCI_VENDOR_ID_MAINPINE
, 0x4002, 0, 0,
2979 pbn_oxsemi_2_4000000
},
2980 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2981 PCI_VENDOR_ID_MAINPINE
, 0x4004, 0, 0,
2982 pbn_oxsemi_4_4000000
},
2983 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2984 PCI_VENDOR_ID_MAINPINE
, 0x4008, 0, 0,
2985 pbn_oxsemi_8_4000000
},
2987 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2988 * from skokodyn@yahoo.com
2990 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2991 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO232
, 0, 0,
2993 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2994 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO422
, 0, 0,
2996 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2997 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL232
, 0, 0,
2999 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
3000 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL422
, 0, 0,
3004 * Digitan DS560-558, from jimd@esoft.com
3006 { PCI_VENDOR_ID_ATT
, PCI_DEVICE_ID_ATT_VENUS_MODEM
,
3007 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3011 * Titan Electronic cards
3012 * The 400L and 800L have a custom setup quirk.
3014 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100
,
3015 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3017 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200
,
3018 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3020 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400
,
3021 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3023 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800B
,
3024 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3026 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100L
,
3027 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3029 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200L
,
3030 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3031 pbn_b1_bt_2_921600
},
3032 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400L
,
3033 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3034 pbn_b0_bt_4_921600
},
3035 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800L
,
3036 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3037 pbn_b0_bt_8_921600
},
3039 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_550
,
3040 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3042 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_650
,
3043 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3045 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_850
,
3046 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3048 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_550
,
3049 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3050 pbn_b2_bt_2_921600
},
3051 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_650
,
3052 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3053 pbn_b2_bt_2_921600
},
3054 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_850
,
3055 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3056 pbn_b2_bt_2_921600
},
3057 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_550
,
3058 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3059 pbn_b2_bt_4_921600
},
3060 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_650
,
3061 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3062 pbn_b2_bt_4_921600
},
3063 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_850
,
3064 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3065 pbn_b2_bt_4_921600
},
3066 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_550
,
3067 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3069 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_650
,
3070 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3072 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_850
,
3073 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3075 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_550
,
3076 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3077 pbn_b0_bt_2_921600
},
3078 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_650
,
3079 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3080 pbn_b0_bt_2_921600
},
3081 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_850
,
3082 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3083 pbn_b0_bt_2_921600
},
3084 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_550
,
3085 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3086 pbn_b0_bt_4_921600
},
3087 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_650
,
3088 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3089 pbn_b0_bt_4_921600
},
3090 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_850
,
3091 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3092 pbn_b0_bt_4_921600
},
3093 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_550
,
3094 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3095 pbn_b0_bt_8_921600
},
3096 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_650
,
3097 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3098 pbn_b0_bt_8_921600
},
3099 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_850
,
3100 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3101 pbn_b0_bt_8_921600
},
3104 * Computone devices submitted by Doug McNash dmcnash@computone.com
3106 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
3107 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG4
,
3108 0, 0, pbn_computone_4
},
3109 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
3110 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG8
,
3111 0, 0, pbn_computone_8
},
3112 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
3113 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG6
,
3114 0, 0, pbn_computone_6
},
3116 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI95N
,
3117 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3119 { PCI_VENDOR_ID_TIMEDIA
, PCI_DEVICE_ID_TIMEDIA_1889
,
3120 PCI_VENDOR_ID_TIMEDIA
, PCI_ANY_ID
, 0, 0,
3121 pbn_b0_bt_1_921600
},
3124 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3126 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P028
,
3127 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3128 pbn_b0_bt_8_115200
},
3129 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P030
,
3130 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3131 pbn_b0_bt_8_115200
},
3133 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_DSERIAL
,
3134 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3135 pbn_b0_bt_2_115200
},
3136 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_A
,
3137 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3138 pbn_b0_bt_2_115200
},
3139 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_B
,
3140 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3141 pbn_b0_bt_2_115200
},
3142 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_A
,
3143 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3144 pbn_b0_bt_4_460800
},
3145 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_B
,
3146 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3147 pbn_b0_bt_4_460800
},
3148 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_PLUS
,
3149 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3150 pbn_b0_bt_2_460800
},
3151 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_A
,
3152 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3153 pbn_b0_bt_2_460800
},
3154 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_B
,
3155 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3156 pbn_b0_bt_2_460800
},
3157 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_SSERIAL
,
3158 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3159 pbn_b0_bt_1_115200
},
3160 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_650
,
3161 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3162 pbn_b0_bt_1_460800
},
3165 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3166 * Cards are identified by their subsystem vendor IDs, which
3167 * (in hex) match the model number.
3169 * Note that JC140x are RS422/485 cards which require ox950
3170 * ACR = 0x10, and as such are not currently fully supported.
3172 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF0
,
3173 0x1204, 0x0004, 0, 0,
3175 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF0
,
3176 0x1208, 0x0004, 0, 0,
3178 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3179 0x1402, 0x0002, 0, 0,
3180 pbn_b0_2_921600 }, */
3181 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3182 0x1404, 0x0004, 0, 0,
3183 pbn_b0_4_921600 }, */
3184 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF1
,
3185 0x1208, 0x0004, 0, 0,
3189 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3191 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RAC4
,
3192 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3196 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3198 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RACIII
,
3199 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3203 * RAStel 2 port modem, gerg@moreton.com.au
3205 { PCI_VENDOR_ID_MORETON
, PCI_DEVICE_ID_RASTEL_2PORT
,
3206 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3207 pbn_b2_bt_2_115200
},
3210 * EKF addition for i960 Boards form EKF with serial port
3212 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80960_RP
,
3213 0xE4BF, PCI_ANY_ID
, 0, 0,
3217 * Xircom Cardbus/Ethernet combos
3219 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
3220 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3223 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3225 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_RBM56G
,
3226 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3230 * Untested PCI modems, sent in from various folks...
3234 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3236 { PCI_VENDOR_ID_ROCKWELL
, 0x1004,
3237 0x1048, 0x1500, 0, 0,
3240 { PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
,
3247 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
3248 PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_RMP3
, 0, 0,
3250 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
3251 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3253 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_AUX
,
3254 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3257 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM2
,
3258 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3260 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM4
,
3261 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3263 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM8
,
3264 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3268 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3270 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
3271 PCI_ANY_ID
, PCI_ANY_ID
,
3273 0, pbn_exar_XR17C152
},
3274 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
3275 PCI_ANY_ID
, PCI_ANY_ID
,
3277 0, pbn_exar_XR17C154
},
3278 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
3279 PCI_ANY_ID
, PCI_ANY_ID
,
3281 0, pbn_exar_XR17C158
},
3284 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3286 { PCI_VENDOR_ID_TOPIC
, PCI_DEVICE_ID_TOPIC_TP560
,
3287 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3292 { PCI_VENDOR_ID_ITE
, PCI_DEVICE_ID_ITE_8872
,
3293 PCI_ANY_ID
, PCI_ANY_ID
,
3295 pbn_b1_bt_1_115200
},
3300 { PCI_VENDOR_ID_INTASHIELD
, PCI_DEVICE_ID_INTASHIELD_IS200
,
3301 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, /* 135a.0811 */
3306 { PCI_VENDOR_ID_INTASHIELD
, PCI_DEVICE_ID_INTASHIELD_IS400
,
3307 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, /* 135a.0dc0 */
3310 * Perle PCI-RAS cards
3312 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
3313 PCI_SUBVENDOR_ID_PERLE
, PCI_SUBDEVICE_ID_PCI_RAS4
,
3314 0, 0, pbn_b2_4_921600
},
3315 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
3316 PCI_SUBVENDOR_ID_PERLE
, PCI_SUBDEVICE_ID_PCI_RAS8
,
3317 0, 0, pbn_b2_8_921600
},
3320 * Mainpine series cards: Fairly standard layout but fools
3321 * parts of the autodetect in some cases and uses otherwise
3322 * unmatched communications subclasses in the PCI Express case
3325 { /* RockForceDUO */
3326 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3327 PCI_VENDOR_ID_MAINPINE
, 0x0200,
3328 0, 0, pbn_b0_2_115200
},
3329 { /* RockForceQUATRO */
3330 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3331 PCI_VENDOR_ID_MAINPINE
, 0x0300,
3332 0, 0, pbn_b0_4_115200
},
3333 { /* RockForceDUO+ */
3334 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3335 PCI_VENDOR_ID_MAINPINE
, 0x0400,
3336 0, 0, pbn_b0_2_115200
},
3337 { /* RockForceQUATRO+ */
3338 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3339 PCI_VENDOR_ID_MAINPINE
, 0x0500,
3340 0, 0, pbn_b0_4_115200
},
3342 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3343 PCI_VENDOR_ID_MAINPINE
, 0x0600,
3344 0, 0, pbn_b0_2_115200
},
3346 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3347 PCI_VENDOR_ID_MAINPINE
, 0x0700,
3348 0, 0, pbn_b0_4_115200
},
3349 { /* RockForceOCTO+ */
3350 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3351 PCI_VENDOR_ID_MAINPINE
, 0x0800,
3352 0, 0, pbn_b0_8_115200
},
3353 { /* RockForceDUO+ */
3354 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3355 PCI_VENDOR_ID_MAINPINE
, 0x0C00,
3356 0, 0, pbn_b0_2_115200
},
3357 { /* RockForceQUARTRO+ */
3358 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3359 PCI_VENDOR_ID_MAINPINE
, 0x0D00,
3360 0, 0, pbn_b0_4_115200
},
3361 { /* RockForceOCTO+ */
3362 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3363 PCI_VENDOR_ID_MAINPINE
, 0x1D00,
3364 0, 0, pbn_b0_8_115200
},
3366 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3367 PCI_VENDOR_ID_MAINPINE
, 0x2000,
3368 0, 0, pbn_b0_1_115200
},
3370 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3371 PCI_VENDOR_ID_MAINPINE
, 0x2100,
3372 0, 0, pbn_b0_1_115200
},
3374 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3375 PCI_VENDOR_ID_MAINPINE
, 0x2200,
3376 0, 0, pbn_b0_2_115200
},
3378 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3379 PCI_VENDOR_ID_MAINPINE
, 0x2300,
3380 0, 0, pbn_b0_2_115200
},
3382 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3383 PCI_VENDOR_ID_MAINPINE
, 0x2400,
3384 0, 0, pbn_b0_4_115200
},
3386 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3387 PCI_VENDOR_ID_MAINPINE
, 0x2500,
3388 0, 0, pbn_b0_4_115200
},
3390 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3391 PCI_VENDOR_ID_MAINPINE
, 0x2600,
3392 0, 0, pbn_b0_8_115200
},
3394 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3395 PCI_VENDOR_ID_MAINPINE
, 0x2700,
3396 0, 0, pbn_b0_8_115200
},
3397 { /* IQ Express D1 */
3398 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3399 PCI_VENDOR_ID_MAINPINE
, 0x3000,
3400 0, 0, pbn_b0_1_115200
},
3401 { /* IQ Express F1 */
3402 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3403 PCI_VENDOR_ID_MAINPINE
, 0x3100,
3404 0, 0, pbn_b0_1_115200
},
3405 { /* IQ Express D2 */
3406 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3407 PCI_VENDOR_ID_MAINPINE
, 0x3200,
3408 0, 0, pbn_b0_2_115200
},
3409 { /* IQ Express F2 */
3410 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3411 PCI_VENDOR_ID_MAINPINE
, 0x3300,
3412 0, 0, pbn_b0_2_115200
},
3413 { /* IQ Express D4 */
3414 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3415 PCI_VENDOR_ID_MAINPINE
, 0x3400,
3416 0, 0, pbn_b0_4_115200
},
3417 { /* IQ Express F4 */
3418 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3419 PCI_VENDOR_ID_MAINPINE
, 0x3500,
3420 0, 0, pbn_b0_4_115200
},
3421 { /* IQ Express D8 */
3422 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3423 PCI_VENDOR_ID_MAINPINE
, 0x3C00,
3424 0, 0, pbn_b0_8_115200
},
3425 { /* IQ Express F8 */
3426 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3427 PCI_VENDOR_ID_MAINPINE
, 0x3D00,
3428 0, 0, pbn_b0_8_115200
},
3432 * PA Semi PA6T-1682M on-chip UART
3434 { PCI_VENDOR_ID_PASEMI
, 0xa004,
3435 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3439 * National Instruments
3441 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI23216
,
3442 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3444 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2328
,
3445 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3447 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2324
,
3448 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3449 pbn_b1_bt_4_115200
},
3450 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2322
,
3451 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3452 pbn_b1_bt_2_115200
},
3453 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2324I
,
3454 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3455 pbn_b1_bt_4_115200
},
3456 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI2322I
,
3457 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3458 pbn_b1_bt_2_115200
},
3459 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_23216
,
3460 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3462 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_2328
,
3463 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3465 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_2324
,
3466 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3467 pbn_b1_bt_4_115200
},
3468 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8420_2322
,
3469 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3470 pbn_b1_bt_2_115200
},
3471 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8422_2324
,
3472 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3473 pbn_b1_bt_4_115200
},
3474 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8422_2322
,
3475 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3476 pbn_b1_bt_2_115200
},
3477 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_2322
,
3478 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3480 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_2322
,
3481 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3483 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_2324
,
3484 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3486 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_2324
,
3487 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3489 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_2328
,
3490 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3492 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_2328
,
3493 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3495 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8430_23216
,
3496 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3498 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8430_23216
,
3499 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3501 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8432_2322
,
3502 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3504 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8432_2322
,
3505 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3507 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PXI8432_2324
,
3508 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3510 { PCI_VENDOR_ID_NI
, PCI_DEVICE_ID_NI_PCI8432_2324
,
3511 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3515 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3517 { PCI_VENDOR_ID_ADDIDATA
,
3518 PCI_DEVICE_ID_ADDIDATA_APCI7500
,
3525 { PCI_VENDOR_ID_ADDIDATA
,
3526 PCI_DEVICE_ID_ADDIDATA_APCI7420
,
3533 { PCI_VENDOR_ID_ADDIDATA
,
3534 PCI_DEVICE_ID_ADDIDATA_APCI7300
,
3541 { PCI_VENDOR_ID_ADDIDATA_OLD
,
3542 PCI_DEVICE_ID_ADDIDATA_APCI7800
,
3549 { PCI_VENDOR_ID_ADDIDATA
,
3550 PCI_DEVICE_ID_ADDIDATA_APCI7500_2
,
3557 { PCI_VENDOR_ID_ADDIDATA
,
3558 PCI_DEVICE_ID_ADDIDATA_APCI7420_2
,
3565 { PCI_VENDOR_ID_ADDIDATA
,
3566 PCI_DEVICE_ID_ADDIDATA_APCI7300_2
,
3573 { PCI_VENDOR_ID_ADDIDATA
,
3574 PCI_DEVICE_ID_ADDIDATA_APCI7500_3
,
3581 { PCI_VENDOR_ID_ADDIDATA
,
3582 PCI_DEVICE_ID_ADDIDATA_APCI7420_3
,
3589 { PCI_VENDOR_ID_ADDIDATA
,
3590 PCI_DEVICE_ID_ADDIDATA_APCI7300_3
,
3597 { PCI_VENDOR_ID_ADDIDATA
,
3598 PCI_DEVICE_ID_ADDIDATA_APCI7800_3
,
3605 { PCI_VENDOR_ID_ADDIDATA
,
3606 PCI_DEVICE_ID_ADDIDATA_APCIe7500
,
3611 pbn_ADDIDATA_PCIe_4_3906250
},
3613 { PCI_VENDOR_ID_ADDIDATA
,
3614 PCI_DEVICE_ID_ADDIDATA_APCIe7420
,
3619 pbn_ADDIDATA_PCIe_2_3906250
},
3621 { PCI_VENDOR_ID_ADDIDATA
,
3622 PCI_DEVICE_ID_ADDIDATA_APCIe7300
,
3627 pbn_ADDIDATA_PCIe_1_3906250
},
3629 { PCI_VENDOR_ID_ADDIDATA
,
3630 PCI_DEVICE_ID_ADDIDATA_APCIe7800
,
3635 pbn_ADDIDATA_PCIe_8_3906250
},
3637 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9835
,
3638 PCI_VENDOR_ID_IBM
, 0x0299,
3639 0, 0, pbn_b0_bt_2_115200
},
3641 { PCI_VENDOR_ID_NETMOS
, PCI_DEVICE_ID_NETMOS_9901
,
3643 0, 0, pbn_b0_1_115200
},
3646 * These entries match devices with class COMMUNICATION_SERIAL,
3647 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3649 { PCI_ANY_ID
, PCI_ANY_ID
,
3650 PCI_ANY_ID
, PCI_ANY_ID
,
3651 PCI_CLASS_COMMUNICATION_SERIAL
<< 8,
3652 0xffff00, pbn_default
},
3653 { PCI_ANY_ID
, PCI_ANY_ID
,
3654 PCI_ANY_ID
, PCI_ANY_ID
,
3655 PCI_CLASS_COMMUNICATION_MODEM
<< 8,
3656 0xffff00, pbn_default
},
3657 { PCI_ANY_ID
, PCI_ANY_ID
,
3658 PCI_ANY_ID
, PCI_ANY_ID
,
3659 PCI_CLASS_COMMUNICATION_MULTISERIAL
<< 8,
3660 0xffff00, pbn_default
},
3664 static struct pci_driver serial_pci_driver
= {
3666 .probe
= pciserial_init_one
,
3667 .remove
= __devexit_p(pciserial_remove_one
),
3669 .suspend
= pciserial_suspend_one
,
3670 .resume
= pciserial_resume_one
,
3672 .id_table
= serial_pci_tbl
,
3675 static int __init
serial8250_pci_init(void)
3677 return pci_register_driver(&serial_pci_driver
);
3680 static void __exit
serial8250_pci_exit(void)
3682 pci_unregister_driver(&serial_pci_driver
);
3685 module_init(serial8250_pci_init
);
3686 module_exit(serial8250_pci_exit
);
3688 MODULE_LICENSE("GPL");
3689 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3690 MODULE_DEVICE_TABLE(pci
, serial_pci_tbl
);