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[PATCH] pcmcia: new suspend core
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_sx4.c
1 /*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include <asm/io.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_sx4"
49 #define DRV_VERSION "0.8"
50
51
52 enum {
53 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
54
55 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
56 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
59
60 PDC_20621_SEQCTL = 0x400,
61 PDC_20621_SEQMASK = 0x480,
62 PDC_20621_GENERAL_CTL = 0x484,
63 PDC_20621_PAGE_SIZE = (32 * 1024),
64
65 /* chosen, not constant, values; we design our own DIMM mem map */
66 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
67 PDC_20621_DIMM_BASE = 0x00200000,
68 PDC_20621_DIMM_DATA = (64 * 1024),
69 PDC_DIMM_DATA_STEP = (256 * 1024),
70 PDC_DIMM_WINDOW_STEP = (8 * 1024),
71 PDC_DIMM_HOST_PRD = (6 * 1024),
72 PDC_DIMM_HOST_PKT = (128 * 0),
73 PDC_DIMM_HPKT_PRD = (128 * 1),
74 PDC_DIMM_ATA_PKT = (128 * 2),
75 PDC_DIMM_APKT_PRD = (128 * 3),
76 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
77 PDC_PAGE_WINDOW = 0x40,
78 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
79 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
80 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
81
82 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
83
84 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
85 (1<<23),
86
87 board_20621 = 0, /* FastTrak S150 SX4 */
88
89 PDC_RESET = (1 << 11), /* HDMA reset */
90
91 PDC_MAX_HDMA = 32,
92 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
93
94 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
95 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
96 PDC_MAX_DIMM_MODULE = 0x02,
97 PDC_I2C_CONTROL_OFFSET = 0x48,
98 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
99 PDC_DIMM0_CONTROL_OFFSET = 0x80,
100 PDC_DIMM1_CONTROL_OFFSET = 0x84,
101 PDC_SDRAM_CONTROL_OFFSET = 0x88,
102 PDC_I2C_WRITE = 0x00000000,
103 PDC_I2C_READ = 0x00000040,
104 PDC_I2C_START = 0x00000080,
105 PDC_I2C_MASK_INT = 0x00000020,
106 PDC_I2C_COMPLETE = 0x00010000,
107 PDC_I2C_NO_ACK = 0x00100000,
108 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
109 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
110 PDC_DIMM_SPD_ROW_NUM = 3,
111 PDC_DIMM_SPD_COLUMN_NUM = 4,
112 PDC_DIMM_SPD_MODULE_ROW = 5,
113 PDC_DIMM_SPD_TYPE = 11,
114 PDC_DIMM_SPD_FRESH_RATE = 12,
115 PDC_DIMM_SPD_BANK_NUM = 17,
116 PDC_DIMM_SPD_CAS_LATENCY = 18,
117 PDC_DIMM_SPD_ATTRIBUTE = 21,
118 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
119 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
120 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
121 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
122 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
123 PDC_CTL_STATUS = 0x08,
124 PDC_DIMM_WINDOW_CTLR = 0x0C,
125 PDC_TIME_CONTROL = 0x3C,
126 PDC_TIME_PERIOD = 0x40,
127 PDC_TIME_COUNTER = 0x44,
128 PDC_GENERAL_CTLR = 0x484,
129 PCI_PLL_INIT = 0x8A531824,
130 PCI_X_TCOUNT = 0xEE1E5CFF
131 };
132
133
134 struct pdc_port_priv {
135 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
136 u8 *pkt;
137 dma_addr_t pkt_dma;
138 };
139
140 struct pdc_host_priv {
141 void __iomem *dimm_mmio;
142
143 unsigned int doing_hdma;
144 unsigned int hdma_prod;
145 unsigned int hdma_cons;
146 struct {
147 struct ata_queued_cmd *qc;
148 unsigned int seq;
149 unsigned long pkt_ofs;
150 } hdma[32];
151 };
152
153
154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
156 static void pdc_eng_timeout(struct ata_port *ap);
157 static void pdc_20621_phy_reset (struct ata_port *ap);
158 static int pdc_port_start(struct ata_port *ap);
159 static void pdc_port_stop(struct ata_port *ap);
160 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
161 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
163 static void pdc20621_host_stop(struct ata_host_set *host_set);
164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
165 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
167 u32 device, u32 subaddr, u32 *pdata);
168 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
170 #ifdef ATA_VERBOSE_DEBUG
171 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
172 void *psource, u32 offset, u32 size);
173 #endif
174 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
175 void *psource, u32 offset, u32 size);
176 static void pdc20621_irq_clear(struct ata_port *ap);
177 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
178
179
180 static struct scsi_host_template pdc_sata_sht = {
181 .module = THIS_MODULE,
182 .name = DRV_NAME,
183 .ioctl = ata_scsi_ioctl,
184 .queuecommand = ata_scsi_queuecmd,
185 .eh_strategy_handler = ata_scsi_error,
186 .can_queue = ATA_DEF_QUEUE,
187 .this_id = ATA_SHT_THIS_ID,
188 .sg_tablesize = LIBATA_MAX_PRD,
189 .max_sectors = ATA_MAX_SECTORS,
190 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
191 .emulated = ATA_SHT_EMULATED,
192 .use_clustering = ATA_SHT_USE_CLUSTERING,
193 .proc_name = DRV_NAME,
194 .dma_boundary = ATA_DMA_BOUNDARY,
195 .slave_configure = ata_scsi_slave_config,
196 .bios_param = ata_std_bios_param,
197 .ordered_flush = 1,
198 };
199
200 static const struct ata_port_operations pdc_20621_ops = {
201 .port_disable = ata_port_disable,
202 .tf_load = pdc_tf_load_mmio,
203 .tf_read = ata_tf_read,
204 .check_status = ata_check_status,
205 .exec_command = pdc_exec_command_mmio,
206 .dev_select = ata_std_dev_select,
207 .phy_reset = pdc_20621_phy_reset,
208 .qc_prep = pdc20621_qc_prep,
209 .qc_issue = pdc20621_qc_issue_prot,
210 .eng_timeout = pdc_eng_timeout,
211 .irq_handler = pdc20621_interrupt,
212 .irq_clear = pdc20621_irq_clear,
213 .port_start = pdc_port_start,
214 .port_stop = pdc_port_stop,
215 .host_stop = pdc20621_host_stop,
216 };
217
218 static const struct ata_port_info pdc_port_info[] = {
219 /* board_20621 */
220 {
221 .sht = &pdc_sata_sht,
222 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
223 ATA_FLAG_SRST | ATA_FLAG_MMIO |
224 ATA_FLAG_NO_ATAPI,
225 .pio_mask = 0x1f, /* pio0-4 */
226 .mwdma_mask = 0x07, /* mwdma0-2 */
227 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
228 .port_ops = &pdc_20621_ops,
229 },
230
231 };
232
233 static const struct pci_device_id pdc_sata_pci_tbl[] = {
234 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
235 board_20621 },
236 { } /* terminate list */
237 };
238
239
240 static struct pci_driver pdc_sata_pci_driver = {
241 .name = DRV_NAME,
242 .id_table = pdc_sata_pci_tbl,
243 .probe = pdc_sata_init_one,
244 .remove = ata_pci_remove_one,
245 };
246
247
248 static void pdc20621_host_stop(struct ata_host_set *host_set)
249 {
250 struct pci_dev *pdev = to_pci_dev(host_set->dev);
251 struct pdc_host_priv *hpriv = host_set->private_data;
252 void __iomem *dimm_mmio = hpriv->dimm_mmio;
253
254 pci_iounmap(pdev, dimm_mmio);
255 kfree(hpriv);
256
257 pci_iounmap(pdev, host_set->mmio_base);
258 }
259
260 static int pdc_port_start(struct ata_port *ap)
261 {
262 struct device *dev = ap->host_set->dev;
263 struct pdc_port_priv *pp;
264 int rc;
265
266 rc = ata_port_start(ap);
267 if (rc)
268 return rc;
269
270 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
271 if (!pp) {
272 rc = -ENOMEM;
273 goto err_out;
274 }
275 memset(pp, 0, sizeof(*pp));
276
277 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
278 if (!pp->pkt) {
279 rc = -ENOMEM;
280 goto err_out_kfree;
281 }
282
283 ap->private_data = pp;
284
285 return 0;
286
287 err_out_kfree:
288 kfree(pp);
289 err_out:
290 ata_port_stop(ap);
291 return rc;
292 }
293
294
295 static void pdc_port_stop(struct ata_port *ap)
296 {
297 struct device *dev = ap->host_set->dev;
298 struct pdc_port_priv *pp = ap->private_data;
299
300 ap->private_data = NULL;
301 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
302 kfree(pp);
303 ata_port_stop(ap);
304 }
305
306
307 static void pdc_20621_phy_reset (struct ata_port *ap)
308 {
309 VPRINTK("ENTER\n");
310 ap->cbl = ATA_CBL_SATA;
311 ata_port_probe(ap);
312 ata_bus_reset(ap);
313 }
314
315 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
316 unsigned int portno,
317 unsigned int total_len)
318 {
319 u32 addr;
320 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
321 u32 *buf32 = (u32 *) buf;
322
323 /* output ATA packet S/G table */
324 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
325 (PDC_DIMM_DATA_STEP * portno);
326 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
327 buf32[dw] = cpu_to_le32(addr);
328 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
329
330 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
331 PDC_20621_DIMM_BASE +
332 (PDC_DIMM_WINDOW_STEP * portno) +
333 PDC_DIMM_APKT_PRD,
334 buf32[dw], buf32[dw + 1]);
335 }
336
337 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
338 unsigned int portno,
339 unsigned int total_len)
340 {
341 u32 addr;
342 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
343 u32 *buf32 = (u32 *) buf;
344
345 /* output Host DMA packet S/G table */
346 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
347 (PDC_DIMM_DATA_STEP * portno);
348
349 buf32[dw] = cpu_to_le32(addr);
350 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
351
352 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
353 PDC_20621_DIMM_BASE +
354 (PDC_DIMM_WINDOW_STEP * portno) +
355 PDC_DIMM_HPKT_PRD,
356 buf32[dw], buf32[dw + 1]);
357 }
358
359 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
360 unsigned int devno, u8 *buf,
361 unsigned int portno)
362 {
363 unsigned int i, dw;
364 u32 *buf32 = (u32 *) buf;
365 u8 dev_reg;
366
367 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
368 (PDC_DIMM_WINDOW_STEP * portno) +
369 PDC_DIMM_APKT_PRD;
370 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
371
372 i = PDC_DIMM_ATA_PKT;
373
374 /*
375 * Set up ATA packet
376 */
377 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
378 buf[i++] = PDC_PKT_READ;
379 else if (tf->protocol == ATA_PROT_NODATA)
380 buf[i++] = PDC_PKT_NODATA;
381 else
382 buf[i++] = 0;
383 buf[i++] = 0; /* reserved */
384 buf[i++] = portno + 1; /* seq. id */
385 buf[i++] = 0xff; /* delay seq. id */
386
387 /* dimm dma S/G, and next-pkt */
388 dw = i >> 2;
389 if (tf->protocol == ATA_PROT_NODATA)
390 buf32[dw] = 0;
391 else
392 buf32[dw] = cpu_to_le32(dimm_sg);
393 buf32[dw + 1] = 0;
394 i += 8;
395
396 if (devno == 0)
397 dev_reg = ATA_DEVICE_OBS;
398 else
399 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
400
401 /* select device */
402 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
403 buf[i++] = dev_reg;
404
405 /* device control register */
406 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
407 buf[i++] = tf->ctl;
408
409 return i;
410 }
411
412 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
413 unsigned int portno)
414 {
415 unsigned int dw;
416 u32 tmp, *buf32 = (u32 *) buf;
417
418 unsigned int host_sg = PDC_20621_DIMM_BASE +
419 (PDC_DIMM_WINDOW_STEP * portno) +
420 PDC_DIMM_HOST_PRD;
421 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
422 (PDC_DIMM_WINDOW_STEP * portno) +
423 PDC_DIMM_HPKT_PRD;
424 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
425 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
426
427 dw = PDC_DIMM_HOST_PKT >> 2;
428
429 /*
430 * Set up Host DMA packet
431 */
432 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
433 tmp = PDC_PKT_READ;
434 else
435 tmp = 0;
436 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
437 tmp |= (0xff << 24); /* delay seq. id */
438 buf32[dw + 0] = cpu_to_le32(tmp);
439 buf32[dw + 1] = cpu_to_le32(host_sg);
440 buf32[dw + 2] = cpu_to_le32(dimm_sg);
441 buf32[dw + 3] = 0;
442
443 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
444 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
445 PDC_DIMM_HOST_PKT,
446 buf32[dw + 0],
447 buf32[dw + 1],
448 buf32[dw + 2],
449 buf32[dw + 3]);
450 }
451
452 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
453 {
454 struct scatterlist *sg;
455 struct ata_port *ap = qc->ap;
456 struct pdc_port_priv *pp = ap->private_data;
457 void __iomem *mmio = ap->host_set->mmio_base;
458 struct pdc_host_priv *hpriv = ap->host_set->private_data;
459 void __iomem *dimm_mmio = hpriv->dimm_mmio;
460 unsigned int portno = ap->port_no;
461 unsigned int i, idx, total_len = 0, sgt_len;
462 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
463
464 assert(qc->flags & ATA_QCFLAG_DMAMAP);
465
466 VPRINTK("ata%u: ENTER\n", ap->id);
467
468 /* hard-code chip #0 */
469 mmio += PDC_CHIP0_OFS;
470
471 /*
472 * Build S/G table
473 */
474 idx = 0;
475 ata_for_each_sg(sg, qc) {
476 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
477 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
478 total_len += sg_dma_len(sg);
479 }
480 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
481 sgt_len = idx * 4;
482
483 /*
484 * Build ATA, host DMA packets
485 */
486 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
487 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
488
489 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
490 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
491
492 if (qc->tf.flags & ATA_TFLAG_LBA48)
493 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
494 else
495 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
496
497 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
498
499 /* copy three S/G tables and two packets to DIMM MMIO window */
500 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
501 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
502 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
503 PDC_DIMM_HOST_PRD,
504 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
505
506 /* force host FIFO dump */
507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
508
509 readl(dimm_mmio); /* MMIO PCI posting flush */
510
511 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
512 }
513
514 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
515 {
516 struct ata_port *ap = qc->ap;
517 struct pdc_port_priv *pp = ap->private_data;
518 void __iomem *mmio = ap->host_set->mmio_base;
519 struct pdc_host_priv *hpriv = ap->host_set->private_data;
520 void __iomem *dimm_mmio = hpriv->dimm_mmio;
521 unsigned int portno = ap->port_no;
522 unsigned int i;
523
524 VPRINTK("ata%u: ENTER\n", ap->id);
525
526 /* hard-code chip #0 */
527 mmio += PDC_CHIP0_OFS;
528
529 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
530
531 if (qc->tf.flags & ATA_TFLAG_LBA48)
532 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
533 else
534 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
535
536 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
537
538 /* copy three S/G tables and two packets to DIMM MMIO window */
539 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
540 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
541
542 /* force host FIFO dump */
543 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
544
545 readl(dimm_mmio); /* MMIO PCI posting flush */
546
547 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
548 }
549
550 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
551 {
552 switch (qc->tf.protocol) {
553 case ATA_PROT_DMA:
554 pdc20621_dma_prep(qc);
555 break;
556 case ATA_PROT_NODATA:
557 pdc20621_nodata_prep(qc);
558 break;
559 default:
560 break;
561 }
562 }
563
564 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
565 unsigned int seq,
566 u32 pkt_ofs)
567 {
568 struct ata_port *ap = qc->ap;
569 struct ata_host_set *host_set = ap->host_set;
570 void __iomem *mmio = host_set->mmio_base;
571
572 /* hard-code chip #0 */
573 mmio += PDC_CHIP0_OFS;
574
575 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
576 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
577
578 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
579 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
580 }
581
582 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
583 unsigned int seq,
584 u32 pkt_ofs)
585 {
586 struct ata_port *ap = qc->ap;
587 struct pdc_host_priv *pp = ap->host_set->private_data;
588 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
589
590 if (!pp->doing_hdma) {
591 __pdc20621_push_hdma(qc, seq, pkt_ofs);
592 pp->doing_hdma = 1;
593 return;
594 }
595
596 pp->hdma[idx].qc = qc;
597 pp->hdma[idx].seq = seq;
598 pp->hdma[idx].pkt_ofs = pkt_ofs;
599 pp->hdma_prod++;
600 }
601
602 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
603 {
604 struct ata_port *ap = qc->ap;
605 struct pdc_host_priv *pp = ap->host_set->private_data;
606 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
607
608 /* if nothing on queue, we're done */
609 if (pp->hdma_prod == pp->hdma_cons) {
610 pp->doing_hdma = 0;
611 return;
612 }
613
614 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
615 pp->hdma[idx].pkt_ofs);
616 pp->hdma_cons++;
617 }
618
619 #ifdef ATA_VERBOSE_DEBUG
620 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
621 {
622 struct ata_port *ap = qc->ap;
623 unsigned int port_no = ap->port_no;
624 struct pdc_host_priv *hpriv = ap->host_set->private_data;
625 void *dimm_mmio = hpriv->dimm_mmio;
626
627 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
628 dimm_mmio += PDC_DIMM_HOST_PKT;
629
630 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
631 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
632 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
633 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
634 }
635 #else
636 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
637 #endif /* ATA_VERBOSE_DEBUG */
638
639 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
640 {
641 struct ata_port *ap = qc->ap;
642 struct ata_host_set *host_set = ap->host_set;
643 unsigned int port_no = ap->port_no;
644 void __iomem *mmio = host_set->mmio_base;
645 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
646 u8 seq = (u8) (port_no + 1);
647 unsigned int port_ofs;
648
649 /* hard-code chip #0 */
650 mmio += PDC_CHIP0_OFS;
651
652 VPRINTK("ata%u: ENTER\n", ap->id);
653
654 wmb(); /* flush PRD, pkt writes */
655
656 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
657
658 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
659 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
660 seq += 4;
661
662 pdc20621_dump_hdma(qc);
663 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
664 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
665 port_ofs + PDC_DIMM_HOST_PKT,
666 port_ofs + PDC_DIMM_HOST_PKT,
667 seq);
668 } else {
669 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
670 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
671
672 writel(port_ofs + PDC_DIMM_ATA_PKT,
673 (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
674 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
675 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
676 port_ofs + PDC_DIMM_ATA_PKT,
677 port_ofs + PDC_DIMM_ATA_PKT,
678 seq);
679 }
680 }
681
682 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
683 {
684 switch (qc->tf.protocol) {
685 case ATA_PROT_DMA:
686 case ATA_PROT_NODATA:
687 pdc20621_packet_start(qc);
688 return 0;
689
690 case ATA_PROT_ATAPI_DMA:
691 BUG();
692 break;
693
694 default:
695 break;
696 }
697
698 return ata_qc_issue_prot(qc);
699 }
700
701 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
702 struct ata_queued_cmd *qc,
703 unsigned int doing_hdma,
704 void __iomem *mmio)
705 {
706 unsigned int port_no = ap->port_no;
707 unsigned int port_ofs =
708 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
709 u8 status;
710 unsigned int handled = 0;
711
712 VPRINTK("ENTER\n");
713
714 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
715 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
716
717 /* step two - DMA from DIMM to host */
718 if (doing_hdma) {
719 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
720 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
721 /* get drive status; clear intr; complete txn */
722 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
723 ata_qc_complete(qc);
724 pdc20621_pop_hdma(qc);
725 }
726
727 /* step one - exec ATA command */
728 else {
729 u8 seq = (u8) (port_no + 1 + 4);
730 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
731 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
732
733 /* submit hdma pkt */
734 pdc20621_dump_hdma(qc);
735 pdc20621_push_hdma(qc, seq,
736 port_ofs + PDC_DIMM_HOST_PKT);
737 }
738 handled = 1;
739
740 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
741
742 /* step one - DMA from host to DIMM */
743 if (doing_hdma) {
744 u8 seq = (u8) (port_no + 1);
745 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
746 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
747
748 /* submit ata pkt */
749 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
750 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
751 writel(port_ofs + PDC_DIMM_ATA_PKT,
752 (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
753 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
754 }
755
756 /* step two - execute ATA command */
757 else {
758 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
759 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
760 /* get drive status; clear intr; complete txn */
761 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
762 ata_qc_complete(qc);
763 pdc20621_pop_hdma(qc);
764 }
765 handled = 1;
766
767 /* command completion, but no data xfer */
768 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
769
770 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
771 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
772 qc->err_mask |= ac_err_mask(status);
773 ata_qc_complete(qc);
774 handled = 1;
775
776 } else {
777 ap->stats.idle_irq++;
778 }
779
780 return handled;
781 }
782
783 static void pdc20621_irq_clear(struct ata_port *ap)
784 {
785 struct ata_host_set *host_set = ap->host_set;
786 void __iomem *mmio = host_set->mmio_base;
787
788 mmio += PDC_CHIP0_OFS;
789
790 readl(mmio + PDC_20621_SEQMASK);
791 }
792
793 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
794 {
795 struct ata_host_set *host_set = dev_instance;
796 struct ata_port *ap;
797 u32 mask = 0;
798 unsigned int i, tmp, port_no;
799 unsigned int handled = 0;
800 void __iomem *mmio_base;
801
802 VPRINTK("ENTER\n");
803
804 if (!host_set || !host_set->mmio_base) {
805 VPRINTK("QUICK EXIT\n");
806 return IRQ_NONE;
807 }
808
809 mmio_base = host_set->mmio_base;
810
811 /* reading should also clear interrupts */
812 mmio_base += PDC_CHIP0_OFS;
813 mask = readl(mmio_base + PDC_20621_SEQMASK);
814 VPRINTK("mask == 0x%x\n", mask);
815
816 if (mask == 0xffffffff) {
817 VPRINTK("QUICK EXIT 2\n");
818 return IRQ_NONE;
819 }
820 mask &= 0xffff; /* only 16 tags possible */
821 if (!mask) {
822 VPRINTK("QUICK EXIT 3\n");
823 return IRQ_NONE;
824 }
825
826 spin_lock(&host_set->lock);
827
828 for (i = 1; i < 9; i++) {
829 port_no = i - 1;
830 if (port_no > 3)
831 port_no -= 4;
832 if (port_no >= host_set->n_ports)
833 ap = NULL;
834 else
835 ap = host_set->ports[port_no];
836 tmp = mask & (1 << i);
837 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
838 if (tmp && ap &&
839 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
840 struct ata_queued_cmd *qc;
841
842 qc = ata_qc_from_tag(ap, ap->active_tag);
843 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
844 handled += pdc20621_host_intr(ap, qc, (i > 4),
845 mmio_base);
846 }
847 }
848
849 spin_unlock(&host_set->lock);
850
851 VPRINTK("mask == 0x%x\n", mask);
852
853 VPRINTK("EXIT\n");
854
855 return IRQ_RETVAL(handled);
856 }
857
858 static void pdc_eng_timeout(struct ata_port *ap)
859 {
860 u8 drv_stat;
861 struct ata_host_set *host_set = ap->host_set;
862 struct ata_queued_cmd *qc;
863 unsigned long flags;
864
865 DPRINTK("ENTER\n");
866
867 spin_lock_irqsave(&host_set->lock, flags);
868
869 qc = ata_qc_from_tag(ap, ap->active_tag);
870 if (!qc) {
871 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
872 ap->id);
873 goto out;
874 }
875
876 /* hack alert! We cannot use the supplied completion
877 * function from inside the ->eh_strategy_handler() thread.
878 * libata is the only user of ->eh_strategy_handler() in
879 * any kernel, so the default scsi_done() assumes it is
880 * not being called from the SCSI EH.
881 */
882 qc->scsidone = scsi_finish_command;
883
884 switch (qc->tf.protocol) {
885 case ATA_PROT_DMA:
886 case ATA_PROT_NODATA:
887 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
888 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
889 ata_qc_complete(qc);
890 break;
891
892 default:
893 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
894
895 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
896 ap->id, qc->tf.command, drv_stat);
897
898 qc->err_mask |= ac_err_mask(drv_stat);
899 ata_qc_complete(qc);
900 break;
901 }
902
903 out:
904 spin_unlock_irqrestore(&host_set->lock, flags);
905 DPRINTK("EXIT\n");
906 }
907
908 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
909 {
910 WARN_ON (tf->protocol == ATA_PROT_DMA ||
911 tf->protocol == ATA_PROT_NODATA);
912 ata_tf_load(ap, tf);
913 }
914
915
916 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
917 {
918 WARN_ON (tf->protocol == ATA_PROT_DMA ||
919 tf->protocol == ATA_PROT_NODATA);
920 ata_exec_command(ap, tf);
921 }
922
923
924 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
925 {
926 port->cmd_addr = base;
927 port->data_addr = base;
928 port->feature_addr =
929 port->error_addr = base + 0x4;
930 port->nsect_addr = base + 0x8;
931 port->lbal_addr = base + 0xc;
932 port->lbam_addr = base + 0x10;
933 port->lbah_addr = base + 0x14;
934 port->device_addr = base + 0x18;
935 port->command_addr =
936 port->status_addr = base + 0x1c;
937 port->altstatus_addr =
938 port->ctl_addr = base + 0x38;
939 }
940
941
942 #ifdef ATA_VERBOSE_DEBUG
943 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
944 u32 offset, u32 size)
945 {
946 u32 window_size;
947 u16 idx;
948 u8 page_mask;
949 long dist;
950 void __iomem *mmio = pe->mmio_base;
951 struct pdc_host_priv *hpriv = pe->private_data;
952 void __iomem *dimm_mmio = hpriv->dimm_mmio;
953
954 /* hard-code chip #0 */
955 mmio += PDC_CHIP0_OFS;
956
957 page_mask = 0x00;
958 window_size = 0x2000 * 4; /* 32K byte uchar size */
959 idx = (u16) (offset / window_size);
960
961 writel(0x01, mmio + PDC_GENERAL_CTLR);
962 readl(mmio + PDC_GENERAL_CTLR);
963 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
964 readl(mmio + PDC_DIMM_WINDOW_CTLR);
965
966 offset -= (idx * window_size);
967 idx++;
968 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
969 (long) (window_size - offset);
970 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
971 dist);
972
973 psource += dist;
974 size -= dist;
975 for (; (long) size >= (long) window_size ;) {
976 writel(0x01, mmio + PDC_GENERAL_CTLR);
977 readl(mmio + PDC_GENERAL_CTLR);
978 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
979 readl(mmio + PDC_DIMM_WINDOW_CTLR);
980 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
981 window_size / 4);
982 psource += window_size;
983 size -= window_size;
984 idx ++;
985 }
986
987 if (size) {
988 writel(0x01, mmio + PDC_GENERAL_CTLR);
989 readl(mmio + PDC_GENERAL_CTLR);
990 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
991 readl(mmio + PDC_DIMM_WINDOW_CTLR);
992 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
993 size / 4);
994 }
995 }
996 #endif
997
998
999 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
1000 u32 offset, u32 size)
1001 {
1002 u32 window_size;
1003 u16 idx;
1004 u8 page_mask;
1005 long dist;
1006 void __iomem *mmio = pe->mmio_base;
1007 struct pdc_host_priv *hpriv = pe->private_data;
1008 void __iomem *dimm_mmio = hpriv->dimm_mmio;
1009
1010 /* hard-code chip #0 */
1011 mmio += PDC_CHIP0_OFS;
1012
1013 page_mask = 0x00;
1014 window_size = 0x2000 * 4; /* 32K byte uchar size */
1015 idx = (u16) (offset / window_size);
1016
1017 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1018 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1019 offset -= (idx * window_size);
1020 idx++;
1021 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1022 (long) (window_size - offset);
1023 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1024 writel(0x01, mmio + PDC_GENERAL_CTLR);
1025 readl(mmio + PDC_GENERAL_CTLR);
1026
1027 psource += dist;
1028 size -= dist;
1029 for (; (long) size >= (long) window_size ;) {
1030 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1031 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1032 memcpy_toio(dimm_mmio, psource, window_size / 4);
1033 writel(0x01, mmio + PDC_GENERAL_CTLR);
1034 readl(mmio + PDC_GENERAL_CTLR);
1035 psource += window_size;
1036 size -= window_size;
1037 idx ++;
1038 }
1039
1040 if (size) {
1041 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1042 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1043 memcpy_toio(dimm_mmio, psource, size / 4);
1044 writel(0x01, mmio + PDC_GENERAL_CTLR);
1045 readl(mmio + PDC_GENERAL_CTLR);
1046 }
1047 }
1048
1049
1050 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1051 u32 subaddr, u32 *pdata)
1052 {
1053 void __iomem *mmio = pe->mmio_base;
1054 u32 i2creg = 0;
1055 u32 status;
1056 u32 count =0;
1057
1058 /* hard-code chip #0 */
1059 mmio += PDC_CHIP0_OFS;
1060
1061 i2creg |= device << 24;
1062 i2creg |= subaddr << 16;
1063
1064 /* Set the device and subaddress */
1065 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1066 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1067
1068 /* Write Control to perform read operation, mask int */
1069 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1070 mmio + PDC_I2C_CONTROL_OFFSET);
1071
1072 for (count = 0; count <= 1000; count ++) {
1073 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1074 if (status & PDC_I2C_COMPLETE) {
1075 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1076 break;
1077 } else if (count == 1000)
1078 return 0;
1079 }
1080
1081 *pdata = (status >> 8) & 0x000000ff;
1082 return 1;
1083 }
1084
1085
1086 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1087 {
1088 u32 data=0 ;
1089 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1090 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1091 if (data == 100)
1092 return 100;
1093 } else
1094 return 0;
1095
1096 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1097 if(data <= 0x75)
1098 return 133;
1099 } else
1100 return 0;
1101
1102 return 0;
1103 }
1104
1105
1106 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1107 {
1108 u32 spd0[50];
1109 u32 data = 0;
1110 int size, i;
1111 u8 bdimmsize;
1112 void __iomem *mmio = pe->mmio_base;
1113 static const struct {
1114 unsigned int reg;
1115 unsigned int ofs;
1116 } pdc_i2c_read_data [] = {
1117 { PDC_DIMM_SPD_TYPE, 11 },
1118 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1119 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1120 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1121 { PDC_DIMM_SPD_ROW_NUM, 3 },
1122 { PDC_DIMM_SPD_BANK_NUM, 17 },
1123 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1124 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1125 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1126 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1127 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1128 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1129 };
1130
1131 /* hard-code chip #0 */
1132 mmio += PDC_CHIP0_OFS;
1133
1134 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1135 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1136 pdc_i2c_read_data[i].reg,
1137 &spd0[pdc_i2c_read_data[i].ofs]);
1138
1139 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1140 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1141 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1142 data |= (((((spd0[29] > spd0[28])
1143 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1144 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1145
1146 if (spd0[18] & 0x08)
1147 data |= ((0x03) << 14);
1148 else if (spd0[18] & 0x04)
1149 data |= ((0x02) << 14);
1150 else if (spd0[18] & 0x01)
1151 data |= ((0x01) << 14);
1152 else
1153 data |= (0 << 14);
1154
1155 /*
1156 Calculate the size of bDIMMSize (power of 2) and
1157 merge the DIMM size by program start/end address.
1158 */
1159
1160 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1161 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1162 data |= (((size / 16) - 1) << 16);
1163 data |= (0 << 23);
1164 data |= 8;
1165 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1166 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1167 return size;
1168 }
1169
1170
1171 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1172 {
1173 u32 data, spd0;
1174 int error, i;
1175 void __iomem *mmio = pe->mmio_base;
1176
1177 /* hard-code chip #0 */
1178 mmio += PDC_CHIP0_OFS;
1179
1180 /*
1181 Set To Default : DIMM Module Global Control Register (0x022259F1)
1182 DIMM Arbitration Disable (bit 20)
1183 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1184 Refresh Enable (bit 17)
1185 */
1186
1187 data = 0x022259F1;
1188 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1189 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1190
1191 /* Turn on for ECC */
1192 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1193 PDC_DIMM_SPD_TYPE, &spd0);
1194 if (spd0 == 0x02) {
1195 data |= (0x01 << 16);
1196 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1197 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1198 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1199 }
1200
1201 /* DIMM Initialization Select/Enable (bit 18/19) */
1202 data &= (~(1<<18));
1203 data |= (1<<19);
1204 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1205
1206 error = 1;
1207 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1208 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1209 if (!(data & (1<<19))) {
1210 error = 0;
1211 break;
1212 }
1213 msleep(i*100);
1214 }
1215 return error;
1216 }
1217
1218
1219 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1220 {
1221 int speed, size, length;
1222 u32 addr,spd0,pci_status;
1223 u32 tmp=0;
1224 u32 time_period=0;
1225 u32 tcount=0;
1226 u32 ticks=0;
1227 u32 clock=0;
1228 u32 fparam=0;
1229 void __iomem *mmio = pe->mmio_base;
1230
1231 /* hard-code chip #0 */
1232 mmio += PDC_CHIP0_OFS;
1233
1234 /* Initialize PLL based upon PCI Bus Frequency */
1235
1236 /* Initialize Time Period Register */
1237 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1238 time_period = readl(mmio + PDC_TIME_PERIOD);
1239 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1240
1241 /* Enable timer */
1242 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1243 readl(mmio + PDC_TIME_CONTROL);
1244
1245 /* Wait 3 seconds */
1246 msleep(3000);
1247
1248 /*
1249 When timer is enabled, counter is decreased every internal
1250 clock cycle.
1251 */
1252
1253 tcount = readl(mmio + PDC_TIME_COUNTER);
1254 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1255
1256 /*
1257 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1258 register should be >= (0xffffffff - 3x10^8).
1259 */
1260 if(tcount >= PCI_X_TCOUNT) {
1261 ticks = (time_period - tcount);
1262 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1263
1264 clock = (ticks / 300000);
1265 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1266
1267 clock = (clock * 33);
1268 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1269
1270 /* PLL F Param (bit 22:16) */
1271 fparam = (1400000 / clock) - 2;
1272 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1273
1274 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1275 pci_status = (0x8a001824 | (fparam << 16));
1276 } else
1277 pci_status = PCI_PLL_INIT;
1278
1279 /* Initialize PLL. */
1280 VPRINTK("pci_status: 0x%x\n", pci_status);
1281 writel(pci_status, mmio + PDC_CTL_STATUS);
1282 readl(mmio + PDC_CTL_STATUS);
1283
1284 /*
1285 Read SPD of DIMM by I2C interface,
1286 and program the DIMM Module Controller.
1287 */
1288 if (!(speed = pdc20621_detect_dimm(pe))) {
1289 printk(KERN_ERR "Detect Local DIMM Fail\n");
1290 return 1; /* DIMM error */
1291 }
1292 VPRINTK("Local DIMM Speed = %d\n", speed);
1293
1294 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1295 size = pdc20621_prog_dimm0(pe);
1296 VPRINTK("Local DIMM Size = %dMB\n",size);
1297
1298 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1299 if (pdc20621_prog_dimm_global(pe)) {
1300 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1301 return 1;
1302 }
1303
1304 #ifdef ATA_VERBOSE_DEBUG
1305 {
1306 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1307 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1308 '1','.','1','0',
1309 '9','8','0','3','1','6','1','2',0,0};
1310 u8 test_parttern2[40] = {0};
1311
1312 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1313 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1314
1315 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1316 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1317 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1318 test_parttern2[1], &(test_parttern2[2]));
1319 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1320 40);
1321 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1322 test_parttern2[1], &(test_parttern2[2]));
1323
1324 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1325 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1326 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1327 test_parttern2[1], &(test_parttern2[2]));
1328 }
1329 #endif
1330
1331 /* ECC initiliazation. */
1332
1333 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1334 PDC_DIMM_SPD_TYPE, &spd0);
1335 if (spd0 == 0x02) {
1336 VPRINTK("Start ECC initialization\n");
1337 addr = 0;
1338 length = size * 1024 * 1024;
1339 while (addr < length) {
1340 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1341 sizeof(u32));
1342 addr += sizeof(u32);
1343 }
1344 VPRINTK("Finish ECC initialization\n");
1345 }
1346 return 0;
1347 }
1348
1349
1350 static void pdc_20621_init(struct ata_probe_ent *pe)
1351 {
1352 u32 tmp;
1353 void __iomem *mmio = pe->mmio_base;
1354
1355 /* hard-code chip #0 */
1356 mmio += PDC_CHIP0_OFS;
1357
1358 /*
1359 * Select page 0x40 for our 32k DIMM window
1360 */
1361 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1362 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1363 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1364
1365 /*
1366 * Reset Host DMA
1367 */
1368 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1369 tmp |= PDC_RESET;
1370 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1371 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1372
1373 udelay(10);
1374
1375 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1376 tmp &= ~PDC_RESET;
1377 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1378 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1379 }
1380
1381 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1382 {
1383 static int printed_version;
1384 struct ata_probe_ent *probe_ent = NULL;
1385 unsigned long base;
1386 void __iomem *mmio_base;
1387 void __iomem *dimm_mmio = NULL;
1388 struct pdc_host_priv *hpriv = NULL;
1389 unsigned int board_idx = (unsigned int) ent->driver_data;
1390 int pci_dev_busy = 0;
1391 int rc;
1392
1393 if (!printed_version++)
1394 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1395
1396 /*
1397 * If this driver happens to only be useful on Apple's K2, then
1398 * we should check that here as it has a normal Serverworks ID
1399 */
1400 rc = pci_enable_device(pdev);
1401 if (rc)
1402 return rc;
1403
1404 rc = pci_request_regions(pdev, DRV_NAME);
1405 if (rc) {
1406 pci_dev_busy = 1;
1407 goto err_out;
1408 }
1409
1410 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1411 if (rc)
1412 goto err_out_regions;
1413 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1414 if (rc)
1415 goto err_out_regions;
1416
1417 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1418 if (probe_ent == NULL) {
1419 rc = -ENOMEM;
1420 goto err_out_regions;
1421 }
1422
1423 memset(probe_ent, 0, sizeof(*probe_ent));
1424 probe_ent->dev = pci_dev_to_dev(pdev);
1425 INIT_LIST_HEAD(&probe_ent->node);
1426
1427 mmio_base = pci_iomap(pdev, 3, 0);
1428 if (mmio_base == NULL) {
1429 rc = -ENOMEM;
1430 goto err_out_free_ent;
1431 }
1432 base = (unsigned long) mmio_base;
1433
1434 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1435 if (!hpriv) {
1436 rc = -ENOMEM;
1437 goto err_out_iounmap;
1438 }
1439 memset(hpriv, 0, sizeof(*hpriv));
1440
1441 dimm_mmio = pci_iomap(pdev, 4, 0);
1442 if (!dimm_mmio) {
1443 kfree(hpriv);
1444 rc = -ENOMEM;
1445 goto err_out_iounmap;
1446 }
1447
1448 hpriv->dimm_mmio = dimm_mmio;
1449
1450 probe_ent->sht = pdc_port_info[board_idx].sht;
1451 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1452 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1453 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1454 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1455 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1456
1457 probe_ent->irq = pdev->irq;
1458 probe_ent->irq_flags = SA_SHIRQ;
1459 probe_ent->mmio_base = mmio_base;
1460
1461 probe_ent->private_data = hpriv;
1462 base += PDC_CHIP0_OFS;
1463
1464 probe_ent->n_ports = 4;
1465 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1466 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1467 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1468 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1469
1470 pci_set_master(pdev);
1471
1472 /* initialize adapter */
1473 /* initialize local dimm */
1474 if (pdc20621_dimm_init(probe_ent)) {
1475 rc = -ENOMEM;
1476 goto err_out_iounmap_dimm;
1477 }
1478 pdc_20621_init(probe_ent);
1479
1480 /* FIXME: check ata_device_add return value */
1481 ata_device_add(probe_ent);
1482 kfree(probe_ent);
1483
1484 return 0;
1485
1486 err_out_iounmap_dimm: /* only get to this label if 20621 */
1487 kfree(hpriv);
1488 pci_iounmap(pdev, dimm_mmio);
1489 err_out_iounmap:
1490 pci_iounmap(pdev, mmio_base);
1491 err_out_free_ent:
1492 kfree(probe_ent);
1493 err_out_regions:
1494 pci_release_regions(pdev);
1495 err_out:
1496 if (!pci_dev_busy)
1497 pci_disable_device(pdev);
1498 return rc;
1499 }
1500
1501
1502 static int __init pdc_sata_init(void)
1503 {
1504 return pci_module_init(&pdc_sata_pci_driver);
1505 }
1506
1507
1508 static void __exit pdc_sata_exit(void)
1509 {
1510 pci_unregister_driver(&pdc_sata_pci_driver);
1511 }
1512
1513
1514 MODULE_AUTHOR("Jeff Garzik");
1515 MODULE_DESCRIPTION("Promise SATA low-level driver");
1516 MODULE_LICENSE("GPL");
1517 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1518 MODULE_VERSION(DRV_VERSION);
1519
1520 module_init(pdc_sata_init);
1521 module_exit(pdc_sata_exit);
kernel source for telekom puls (alcatel/mediatek)