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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_sil24.c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
14 *
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
22 * later version.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/device.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_cmnd.h>
41 #include <linux/libata.h>
42 #include <asm/io.h>
43
44 #define DRV_NAME "sata_sil24"
45 #define DRV_VERSION "0.22" /* Silicon Image's preview driver was 0.10 */
46
47 /*
48 * Port request block (PRB) 32 bytes
49 */
50 struct sil24_prb {
51 u16 ctrl;
52 u16 prot;
53 u32 rx_cnt;
54 u8 fis[6 * 4];
55 };
56
57 /*
58 * Scatter gather entry (SGE) 16 bytes
59 */
60 struct sil24_sge {
61 u64 addr;
62 u32 cnt;
63 u32 flags;
64 };
65
66 /*
67 * Port multiplier
68 */
69 struct sil24_port_multiplier {
70 u32 diag;
71 u32 sactive;
72 };
73
74 enum {
75 /*
76 * Global controller registers (128 bytes @ BAR0)
77 */
78 /* 32 bit regs */
79 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
80 HOST_CTRL = 0x40,
81 HOST_IRQ_STAT = 0x44,
82 HOST_PHY_CFG = 0x48,
83 HOST_BIST_CTRL = 0x50,
84 HOST_BIST_PTRN = 0x54,
85 HOST_BIST_STAT = 0x58,
86 HOST_MEM_BIST_STAT = 0x5c,
87 HOST_FLASH_CMD = 0x70,
88 /* 8 bit regs */
89 HOST_FLASH_DATA = 0x74,
90 HOST_TRANSITION_DETECT = 0x75,
91 HOST_GPIO_CTRL = 0x76,
92 HOST_I2C_ADDR = 0x78, /* 32 bit */
93 HOST_I2C_DATA = 0x7c,
94 HOST_I2C_XFER_CNT = 0x7e,
95 HOST_I2C_CTRL = 0x7f,
96
97 /* HOST_SLOT_STAT bits */
98 HOST_SSTAT_ATTN = (1 << 31),
99
100 /*
101 * Port registers
102 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
103 */
104 PORT_REGS_SIZE = 0x2000,
105 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
106
107 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
108 /* 32 bit regs */
109 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
110 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
111 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
112 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
113 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
114 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
115 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
116 PORT_CMD_ERR = 0x1024, /* command error number */
117 PORT_FIS_CFG = 0x1028,
118 PORT_FIFO_THRES = 0x102c,
119 /* 16 bit regs */
120 PORT_DECODE_ERR_CNT = 0x1040,
121 PORT_DECODE_ERR_THRESH = 0x1042,
122 PORT_CRC_ERR_CNT = 0x1044,
123 PORT_CRC_ERR_THRESH = 0x1046,
124 PORT_HSHK_ERR_CNT = 0x1048,
125 PORT_HSHK_ERR_THRESH = 0x104a,
126 /* 32 bit regs */
127 PORT_PHY_CFG = 0x1050,
128 PORT_SLOT_STAT = 0x1800,
129 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
130 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
131 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
132 PORT_SCONTROL = 0x1f00,
133 PORT_SSTATUS = 0x1f04,
134 PORT_SERROR = 0x1f08,
135 PORT_SACTIVE = 0x1f0c,
136
137 /* PORT_CTRL_STAT bits */
138 PORT_CS_PORT_RST = (1 << 0), /* port reset */
139 PORT_CS_DEV_RST = (1 << 1), /* device reset */
140 PORT_CS_INIT = (1 << 2), /* port initialize */
141 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
142 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
143 PORT_CS_RESUME = (1 << 6), /* port resume */
144 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
145 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
146 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
147
148 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
149 /* bits[11:0] are masked */
150 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
151 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
152 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
153 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
154 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
155 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
156 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
157 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
158
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
163
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
167
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
191
192 /* bits of PRB control field */
193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
198
199 /* PRB protocol field */
200 PRB_PROT_PACKET = (1 << 0),
201 PRB_PROT_TCQ = (1 << 1),
202 PRB_PROT_NCQ = (1 << 2),
203 PRB_PROT_READ = (1 << 3),
204 PRB_PROT_WRITE = (1 << 4),
205 PRB_PROT_TRANSPARENT = (1 << 5),
206
207 /*
208 * Other constants
209 */
210 SGE_TRM = (1 << 31), /* Last SGE in chain */
211 SGE_LNK = (1 << 30), /* linked list
212 Points to SGT, not SGE */
213 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
214 data address ignored */
215
216 /* board id */
217 BID_SIL3124 = 0,
218 BID_SIL3132 = 1,
219 BID_SIL3131 = 2,
220
221 IRQ_STAT_4PORTS = 0xf,
222 };
223
224 struct sil24_cmd_block {
225 struct sil24_prb prb;
226 struct sil24_sge sge[LIBATA_MAX_PRD];
227 };
228
229 /*
230 * ap->private_data
231 *
232 * The preview driver always returned 0 for status. We emulate it
233 * here from the previous interrupt.
234 */
235 struct sil24_port_priv {
236 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
237 dma_addr_t cmd_block_dma; /* DMA base addr for them */
238 struct ata_taskfile tf; /* Cached taskfile registers */
239 };
240
241 /* ap->host_set->private_data */
242 struct sil24_host_priv {
243 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
244 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
245 };
246
247 static u8 sil24_check_status(struct ata_port *ap);
248 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
249 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
250 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
251 static void sil24_phy_reset(struct ata_port *ap);
252 static void sil24_qc_prep(struct ata_queued_cmd *qc);
253 static int sil24_qc_issue(struct ata_queued_cmd *qc);
254 static void sil24_irq_clear(struct ata_port *ap);
255 static void sil24_eng_timeout(struct ata_port *ap);
256 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
257 static int sil24_port_start(struct ata_port *ap);
258 static void sil24_port_stop(struct ata_port *ap);
259 static void sil24_host_stop(struct ata_host_set *host_set);
260 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
261
262 static const struct pci_device_id sil24_pci_tbl[] = {
263 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
264 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
265 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
266 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
267 { } /* terminate list */
268 };
269
270 static struct pci_driver sil24_pci_driver = {
271 .name = DRV_NAME,
272 .id_table = sil24_pci_tbl,
273 .probe = sil24_init_one,
274 .remove = ata_pci_remove_one, /* safe? */
275 };
276
277 static struct scsi_host_template sil24_sht = {
278 .module = THIS_MODULE,
279 .name = DRV_NAME,
280 .ioctl = ata_scsi_ioctl,
281 .queuecommand = ata_scsi_queuecmd,
282 .eh_strategy_handler = ata_scsi_error,
283 .can_queue = ATA_DEF_QUEUE,
284 .this_id = ATA_SHT_THIS_ID,
285 .sg_tablesize = LIBATA_MAX_PRD,
286 .max_sectors = ATA_MAX_SECTORS,
287 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
288 .emulated = ATA_SHT_EMULATED,
289 .use_clustering = ATA_SHT_USE_CLUSTERING,
290 .proc_name = DRV_NAME,
291 .dma_boundary = ATA_DMA_BOUNDARY,
292 .slave_configure = ata_scsi_slave_config,
293 .bios_param = ata_std_bios_param,
294 .ordered_flush = 1, /* NCQ not supported yet */
295 };
296
297 static const struct ata_port_operations sil24_ops = {
298 .port_disable = ata_port_disable,
299
300 .check_status = sil24_check_status,
301 .check_altstatus = sil24_check_status,
302 .dev_select = ata_noop_dev_select,
303
304 .tf_read = sil24_tf_read,
305
306 .phy_reset = sil24_phy_reset,
307
308 .qc_prep = sil24_qc_prep,
309 .qc_issue = sil24_qc_issue,
310
311 .eng_timeout = sil24_eng_timeout,
312
313 .irq_handler = sil24_interrupt,
314 .irq_clear = sil24_irq_clear,
315
316 .scr_read = sil24_scr_read,
317 .scr_write = sil24_scr_write,
318
319 .port_start = sil24_port_start,
320 .port_stop = sil24_port_stop,
321 .host_stop = sil24_host_stop,
322 };
323
324 /*
325 * Use bits 30-31 of host_flags to encode available port numbers.
326 * Current maxium is 4.
327 */
328 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
329 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
330
331 static struct ata_port_info sil24_port_info[] = {
332 /* sil_3124 */
333 {
334 .sht = &sil24_sht,
335 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
336 ATA_FLAG_SRST | ATA_FLAG_MMIO |
337 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4),
338 .pio_mask = 0x1f, /* pio0-4 */
339 .mwdma_mask = 0x07, /* mwdma0-2 */
340 .udma_mask = 0x3f, /* udma0-5 */
341 .port_ops = &sil24_ops,
342 },
343 /* sil_3132 */
344 {
345 .sht = &sil24_sht,
346 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
347 ATA_FLAG_SRST | ATA_FLAG_MMIO |
348 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2),
349 .pio_mask = 0x1f, /* pio0-4 */
350 .mwdma_mask = 0x07, /* mwdma0-2 */
351 .udma_mask = 0x3f, /* udma0-5 */
352 .port_ops = &sil24_ops,
353 },
354 /* sil_3131/sil_3531 */
355 {
356 .sht = &sil24_sht,
357 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
358 ATA_FLAG_SRST | ATA_FLAG_MMIO |
359 ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1),
360 .pio_mask = 0x1f, /* pio0-4 */
361 .mwdma_mask = 0x07, /* mwdma0-2 */
362 .udma_mask = 0x3f, /* udma0-5 */
363 .port_ops = &sil24_ops,
364 },
365 };
366
367 static inline void sil24_update_tf(struct ata_port *ap)
368 {
369 struct sil24_port_priv *pp = ap->private_data;
370 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
371 struct sil24_prb __iomem *prb = port;
372 u8 fis[6 * 4];
373
374 memcpy_fromio(fis, prb->fis, 6 * 4);
375 ata_tf_from_fis(fis, &pp->tf);
376 }
377
378 static u8 sil24_check_status(struct ata_port *ap)
379 {
380 struct sil24_port_priv *pp = ap->private_data;
381 return pp->tf.command;
382 }
383
384 static int sil24_scr_map[] = {
385 [SCR_CONTROL] = 0,
386 [SCR_STATUS] = 1,
387 [SCR_ERROR] = 2,
388 [SCR_ACTIVE] = 3,
389 };
390
391 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
392 {
393 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
394 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
395 void __iomem *addr;
396 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
397 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
398 }
399 return 0xffffffffU;
400 }
401
402 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
403 {
404 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
405 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
406 void __iomem *addr;
407 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
408 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
409 }
410 }
411
412 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
413 {
414 struct sil24_port_priv *pp = ap->private_data;
415 *tf = pp->tf;
416 }
417
418 static int sil24_issue_SRST(struct ata_port *ap)
419 {
420 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
421 struct sil24_port_priv *pp = ap->private_data;
422 struct sil24_prb *prb = &pp->cmd_block[0].prb;
423 dma_addr_t paddr = pp->cmd_block_dma;
424 u32 irq_enable, irq_stat;
425 int cnt;
426
427 /* temporarily turn off IRQs during SRST */
428 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
429 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
430
431 /*
432 * XXX: Not sure whether the following sleep is needed or not.
433 * The original driver had it. So....
434 */
435 msleep(10);
436
437 prb->ctrl = PRB_CTRL_SRST;
438 prb->fis[1] = 0; /* no PM yet */
439
440 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
441
442 for (cnt = 0; cnt < 100; cnt++) {
443 irq_stat = readl(port + PORT_IRQ_STAT);
444 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
445
446 irq_stat >>= PORT_IRQ_RAW_SHIFT;
447 if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR))
448 break;
449
450 msleep(1);
451 }
452
453 /* restore IRQs */
454 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
455
456 if (!(irq_stat & PORT_IRQ_COMPLETE))
457 return -1;
458
459 /* update TF */
460 sil24_update_tf(ap);
461 return 0;
462 }
463
464 static void sil24_phy_reset(struct ata_port *ap)
465 {
466 struct sil24_port_priv *pp = ap->private_data;
467
468 __sata_phy_reset(ap);
469 if (ap->flags & ATA_FLAG_PORT_DISABLED)
470 return;
471
472 if (sil24_issue_SRST(ap) < 0) {
473 printk(KERN_ERR DRV_NAME
474 " ata%u: SRST failed, disabling port\n", ap->id);
475 ap->ops->port_disable(ap);
476 return;
477 }
478
479 ap->device->class = ata_dev_classify(&pp->tf);
480
481 /* No ATAPI yet */
482 if (ap->device->class == ATA_DEV_ATAPI)
483 ap->ops->port_disable(ap);
484 }
485
486 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
487 struct sil24_cmd_block *cb)
488 {
489 struct sil24_sge *sge = cb->sge;
490 struct scatterlist *sg;
491 unsigned int idx = 0;
492
493 ata_for_each_sg(sg, qc) {
494 sge->addr = cpu_to_le64(sg_dma_address(sg));
495 sge->cnt = cpu_to_le32(sg_dma_len(sg));
496 if (ata_sg_is_last(sg, qc))
497 sge->flags = cpu_to_le32(SGE_TRM);
498 else
499 sge->flags = 0;
500
501 sge++;
502 idx++;
503 }
504 }
505
506 static void sil24_qc_prep(struct ata_queued_cmd *qc)
507 {
508 struct ata_port *ap = qc->ap;
509 struct sil24_port_priv *pp = ap->private_data;
510 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
511 struct sil24_prb *prb = &cb->prb;
512
513 switch (qc->tf.protocol) {
514 case ATA_PROT_PIO:
515 case ATA_PROT_DMA:
516 case ATA_PROT_NODATA:
517 break;
518 default:
519 /* ATAPI isn't supported yet */
520 BUG();
521 }
522
523 ata_tf_to_fis(&qc->tf, prb->fis, 0);
524
525 if (qc->flags & ATA_QCFLAG_DMAMAP)
526 sil24_fill_sg(qc, cb);
527 }
528
529 static int sil24_qc_issue(struct ata_queued_cmd *qc)
530 {
531 struct ata_port *ap = qc->ap;
532 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
533 struct sil24_port_priv *pp = ap->private_data;
534 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
535
536 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
537 return 0;
538 }
539
540 static void sil24_irq_clear(struct ata_port *ap)
541 {
542 /* unused */
543 }
544
545 static int __sil24_restart_controller(void __iomem *port)
546 {
547 u32 tmp;
548 int cnt;
549
550 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
551
552 /* Max ~10ms */
553 for (cnt = 0; cnt < 10000; cnt++) {
554 tmp = readl(port + PORT_CTRL_STAT);
555 if (tmp & PORT_CS_RDY)
556 return 0;
557 udelay(1);
558 }
559
560 return -1;
561 }
562
563 static void sil24_restart_controller(struct ata_port *ap)
564 {
565 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
566 printk(KERN_ERR DRV_NAME
567 " ata%u: failed to restart controller\n", ap->id);
568 }
569
570 static int __sil24_reset_controller(void __iomem *port)
571 {
572 int cnt;
573 u32 tmp;
574
575 /* Reset controller state. Is this correct? */
576 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
577 readl(port + PORT_CTRL_STAT); /* sync */
578
579 /* Max ~100ms */
580 for (cnt = 0; cnt < 1000; cnt++) {
581 udelay(100);
582 tmp = readl(port + PORT_CTRL_STAT);
583 if (!(tmp & PORT_CS_DEV_RST))
584 break;
585 }
586
587 if (tmp & PORT_CS_DEV_RST)
588 return -1;
589
590 if (tmp & PORT_CS_RDY)
591 return 0;
592
593 return __sil24_restart_controller(port);
594 }
595
596 static void sil24_reset_controller(struct ata_port *ap)
597 {
598 printk(KERN_NOTICE DRV_NAME
599 " ata%u: resetting controller...\n", ap->id);
600 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
601 printk(KERN_ERR DRV_NAME
602 " ata%u: failed to reset controller\n", ap->id);
603 }
604
605 static void sil24_eng_timeout(struct ata_port *ap)
606 {
607 struct ata_queued_cmd *qc;
608
609 qc = ata_qc_from_tag(ap, ap->active_tag);
610 if (!qc) {
611 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
612 ap->id);
613 return;
614 }
615
616 /*
617 * hack alert! We cannot use the supplied completion
618 * function from inside the ->eh_strategy_handler() thread.
619 * libata is the only user of ->eh_strategy_handler() in
620 * any kernel, so the default scsi_done() assumes it is
621 * not being called from the SCSI EH.
622 */
623 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
624 qc->scsidone = scsi_finish_command;
625 ata_qc_complete(qc, AC_ERR_OTHER);
626
627 sil24_reset_controller(ap);
628 }
629
630 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
631 {
632 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
633 struct sil24_port_priv *pp = ap->private_data;
634 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
635 u32 irq_stat, cmd_err, sstatus, serror;
636 unsigned int err_mask;
637
638 irq_stat = readl(port + PORT_IRQ_STAT);
639 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
640
641 if (!(irq_stat & PORT_IRQ_ERROR)) {
642 /* ignore non-completion, non-error irqs for now */
643 printk(KERN_WARNING DRV_NAME
644 "ata%u: non-error exception irq (irq_stat %x)\n",
645 ap->id, irq_stat);
646 return;
647 }
648
649 cmd_err = readl(port + PORT_CMD_ERR);
650 sstatus = readl(port + PORT_SSTATUS);
651 serror = readl(port + PORT_SERROR);
652 if (serror)
653 writel(serror, port + PORT_SERROR);
654
655 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
656 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
657 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
658
659 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
660 /*
661 * Device is reporting error, tf registers are valid.
662 */
663 sil24_update_tf(ap);
664 err_mask = ac_err_mask(pp->tf.command);
665 sil24_restart_controller(ap);
666 } else {
667 /*
668 * Other errors. libata currently doesn't have any
669 * mechanism to report these errors. Just turn on
670 * ATA_ERR.
671 */
672 err_mask = AC_ERR_OTHER;
673 sil24_reset_controller(ap);
674 }
675
676 if (qc)
677 ata_qc_complete(qc, err_mask);
678 }
679
680 static inline void sil24_host_intr(struct ata_port *ap)
681 {
682 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
683 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
684 u32 slot_stat;
685
686 slot_stat = readl(port + PORT_SLOT_STAT);
687 if (!(slot_stat & HOST_SSTAT_ATTN)) {
688 struct sil24_port_priv *pp = ap->private_data;
689 /*
690 * !HOST_SSAT_ATTN guarantees successful completion,
691 * so reading back tf registers is unnecessary for
692 * most commands. TODO: read tf registers for
693 * commands which require these values on successful
694 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
695 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
696 */
697 sil24_update_tf(ap);
698
699 if (qc)
700 ata_qc_complete(qc, ac_err_mask(pp->tf.command));
701 } else
702 sil24_error_intr(ap, slot_stat);
703 }
704
705 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
706 {
707 struct ata_host_set *host_set = dev_instance;
708 struct sil24_host_priv *hpriv = host_set->private_data;
709 unsigned handled = 0;
710 u32 status;
711 int i;
712
713 status = readl(hpriv->host_base + HOST_IRQ_STAT);
714
715 if (status == 0xffffffff) {
716 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
717 "PCI fault or device removal?\n");
718 goto out;
719 }
720
721 if (!(status & IRQ_STAT_4PORTS))
722 goto out;
723
724 spin_lock(&host_set->lock);
725
726 for (i = 0; i < host_set->n_ports; i++)
727 if (status & (1 << i)) {
728 struct ata_port *ap = host_set->ports[i];
729 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
730 sil24_host_intr(host_set->ports[i]);
731 handled++;
732 } else
733 printk(KERN_ERR DRV_NAME
734 ": interrupt from disabled port %d\n", i);
735 }
736
737 spin_unlock(&host_set->lock);
738 out:
739 return IRQ_RETVAL(handled);
740 }
741
742 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
743 {
744 const size_t cb_size = sizeof(*pp->cmd_block);
745
746 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
747 }
748
749 static int sil24_port_start(struct ata_port *ap)
750 {
751 struct device *dev = ap->host_set->dev;
752 struct sil24_port_priv *pp;
753 struct sil24_cmd_block *cb;
754 size_t cb_size = sizeof(*cb);
755 dma_addr_t cb_dma;
756 int rc = -ENOMEM;
757
758 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
759 if (!pp)
760 goto err_out;
761
762 pp->tf.command = ATA_DRDY;
763
764 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
765 if (!cb)
766 goto err_out_pp;
767 memset(cb, 0, cb_size);
768
769 rc = ata_pad_alloc(ap, dev);
770 if (rc)
771 goto err_out_pad;
772
773 pp->cmd_block = cb;
774 pp->cmd_block_dma = cb_dma;
775
776 ap->private_data = pp;
777
778 return 0;
779
780 err_out_pad:
781 sil24_cblk_free(pp, dev);
782 err_out_pp:
783 kfree(pp);
784 err_out:
785 return rc;
786 }
787
788 static void sil24_port_stop(struct ata_port *ap)
789 {
790 struct device *dev = ap->host_set->dev;
791 struct sil24_port_priv *pp = ap->private_data;
792
793 sil24_cblk_free(pp, dev);
794 ata_pad_free(ap, dev);
795 kfree(pp);
796 }
797
798 static void sil24_host_stop(struct ata_host_set *host_set)
799 {
800 struct sil24_host_priv *hpriv = host_set->private_data;
801
802 iounmap(hpriv->host_base);
803 iounmap(hpriv->port_base);
804 kfree(hpriv);
805 }
806
807 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
808 {
809 static int printed_version = 0;
810 unsigned int board_id = (unsigned int)ent->driver_data;
811 struct ata_port_info *pinfo = &sil24_port_info[board_id];
812 struct ata_probe_ent *probe_ent = NULL;
813 struct sil24_host_priv *hpriv = NULL;
814 void __iomem *host_base = NULL;
815 void __iomem *port_base = NULL;
816 int i, rc;
817
818 if (!printed_version++)
819 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
820
821 rc = pci_enable_device(pdev);
822 if (rc)
823 return rc;
824
825 rc = pci_request_regions(pdev, DRV_NAME);
826 if (rc)
827 goto out_disable;
828
829 rc = -ENOMEM;
830 /* ioremap mmio registers */
831 host_base = ioremap(pci_resource_start(pdev, 0),
832 pci_resource_len(pdev, 0));
833 if (!host_base)
834 goto out_free;
835 port_base = ioremap(pci_resource_start(pdev, 2),
836 pci_resource_len(pdev, 2));
837 if (!port_base)
838 goto out_free;
839
840 /* allocate & init probe_ent and hpriv */
841 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
842 if (!probe_ent)
843 goto out_free;
844
845 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
846 if (!hpriv)
847 goto out_free;
848
849 memset(probe_ent, 0, sizeof(*probe_ent));
850 probe_ent->dev = pci_dev_to_dev(pdev);
851 INIT_LIST_HEAD(&probe_ent->node);
852
853 probe_ent->sht = pinfo->sht;
854 probe_ent->host_flags = pinfo->host_flags;
855 probe_ent->pio_mask = pinfo->pio_mask;
856 probe_ent->udma_mask = pinfo->udma_mask;
857 probe_ent->port_ops = pinfo->port_ops;
858 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
859
860 probe_ent->irq = pdev->irq;
861 probe_ent->irq_flags = SA_SHIRQ;
862 probe_ent->mmio_base = port_base;
863 probe_ent->private_data = hpriv;
864
865 memset(hpriv, 0, sizeof(*hpriv));
866 hpriv->host_base = host_base;
867 hpriv->port_base = port_base;
868
869 /*
870 * Configure the device
871 */
872 /*
873 * FIXME: This device is certainly 64-bit capable. We just
874 * don't know how to use it. After fixing 32bit activation in
875 * this function, enable 64bit masks here.
876 */
877 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
878 if (rc) {
879 dev_printk(KERN_ERR, &pdev->dev,
880 "32-bit DMA enable failed\n");
881 goto out_free;
882 }
883 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
884 if (rc) {
885 dev_printk(KERN_ERR, &pdev->dev,
886 "32-bit consistent DMA enable failed\n");
887 goto out_free;
888 }
889
890 /* GPIO off */
891 writel(0, host_base + HOST_FLASH_CMD);
892
893 /* Mask interrupts during initialization */
894 writel(0, host_base + HOST_CTRL);
895
896 for (i = 0; i < probe_ent->n_ports; i++) {
897 void __iomem *port = port_base + i * PORT_REGS_SIZE;
898 unsigned long portu = (unsigned long)port;
899 u32 tmp;
900 int cnt;
901
902 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
903 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
904
905 ata_std_ports(&probe_ent->port[i]);
906
907 /* Initial PHY setting */
908 writel(0x20c, port + PORT_PHY_CFG);
909
910 /* Clear port RST */
911 tmp = readl(port + PORT_CTRL_STAT);
912 if (tmp & PORT_CS_PORT_RST) {
913 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
914 readl(port + PORT_CTRL_STAT); /* sync */
915 for (cnt = 0; cnt < 10; cnt++) {
916 msleep(10);
917 tmp = readl(port + PORT_CTRL_STAT);
918 if (!(tmp & PORT_CS_PORT_RST))
919 break;
920 }
921 if (tmp & PORT_CS_PORT_RST)
922 dev_printk(KERN_ERR, &pdev->dev,
923 "failed to clear port RST\n");
924 }
925
926 /* Zero error counters. */
927 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
928 writel(0x8000, port + PORT_CRC_ERR_THRESH);
929 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
930 writel(0x0000, port + PORT_DECODE_ERR_CNT);
931 writel(0x0000, port + PORT_CRC_ERR_CNT);
932 writel(0x0000, port + PORT_HSHK_ERR_CNT);
933
934 /* FIXME: 32bit activation? */
935 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
936 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
937
938 /* Configure interrupts */
939 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
940 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
941 port + PORT_IRQ_ENABLE_SET);
942
943 /* Clear interrupts */
944 writel(0x0fff0fff, port + PORT_IRQ_STAT);
945 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
946
947 /* Clear port multiplier enable and resume bits */
948 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
949
950 /* Reset itself */
951 if (__sil24_reset_controller(port))
952 dev_printk(KERN_ERR, &pdev->dev,
953 "failed to reset controller\n");
954 }
955
956 /* Turn on interrupts */
957 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
958
959 pci_set_master(pdev);
960
961 /* FIXME: check ata_device_add return value */
962 ata_device_add(probe_ent);
963
964 kfree(probe_ent);
965 return 0;
966
967 out_free:
968 if (host_base)
969 iounmap(host_base);
970 if (port_base)
971 iounmap(port_base);
972 kfree(probe_ent);
973 kfree(hpriv);
974 pci_release_regions(pdev);
975 out_disable:
976 pci_disable_device(pdev);
977 return rc;
978 }
979
980 static int __init sil24_init(void)
981 {
982 return pci_module_init(&sil24_pci_driver);
983 }
984
985 static void __exit sil24_exit(void)
986 {
987 pci_unregister_driver(&sil24_pci_driver);
988 }
989
990 MODULE_AUTHOR("Tejun Heo");
991 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
992 MODULE_LICENSE("GPL");
993 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
994
995 module_init(sil24_init);
996 module_exit(sil24_exit);
kernel source for telekom puls (alcatel/mediatek)