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[PATCH] libata: kill ata_dev_reread_id()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_sil.c
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "0.9"
50
51 enum {
52 SIL_FLAG_MOD15WRITE = (1 << 30),
53
54 sil_3112 = 0,
55 sil_3112_m15w = 1,
56 sil_3114 = 2,
57
58 SIL_FIFO_R0 = 0x40,
59 SIL_FIFO_W0 = 0x41,
60 SIL_FIFO_R1 = 0x44,
61 SIL_FIFO_W1 = 0x45,
62 SIL_FIFO_R2 = 0x240,
63 SIL_FIFO_W2 = 0x241,
64 SIL_FIFO_R3 = 0x244,
65 SIL_FIFO_W3 = 0x245,
66
67 SIL_SYSCFG = 0x48,
68 SIL_MASK_IDE0_INT = (1 << 22),
69 SIL_MASK_IDE1_INT = (1 << 23),
70 SIL_MASK_IDE2_INT = (1 << 24),
71 SIL_MASK_IDE3_INT = (1 << 25),
72 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
73 SIL_MASK_4PORT = SIL_MASK_2PORT |
74 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
75
76 SIL_IDE2_BMDMA = 0x200,
77
78 SIL_INTR_STEERING = (1 << 1),
79 SIL_QUIRK_MOD15WRITE = (1 << 0),
80 SIL_QUIRK_UDMA5MAX = (1 << 1),
81 };
82
83 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
85 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
86 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
87 static void sil_post_set_mode (struct ata_port *ap);
88
89
90 static const struct pci_device_id sil_pci_tbl[] = {
91 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
92 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
93 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
94 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
95 { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
96 { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
97 { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
98 { } /* terminate list */
99 };
100
101
102 /* TODO firmware versions should be added - eric */
103 static const struct sil_drivelist {
104 const char * product;
105 unsigned int quirk;
106 } sil_blacklist [] = {
107 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
108 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
109 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
110 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
111 { "ST380013AS", SIL_QUIRK_MOD15WRITE },
112 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
113 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
114 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
115 { "ST3120026AS", SIL_QUIRK_MOD15WRITE },
116 { "ST3200822AS", SIL_QUIRK_MOD15WRITE },
117 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
118 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
119 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
120 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
121 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
122 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
123 { }
124 };
125
126 static struct pci_driver sil_pci_driver = {
127 .name = DRV_NAME,
128 .id_table = sil_pci_tbl,
129 .probe = sil_init_one,
130 .remove = ata_pci_remove_one,
131 };
132
133 static struct scsi_host_template sil_sht = {
134 .module = THIS_MODULE,
135 .name = DRV_NAME,
136 .ioctl = ata_scsi_ioctl,
137 .queuecommand = ata_scsi_queuecmd,
138 .eh_timed_out = ata_scsi_timed_out,
139 .eh_strategy_handler = ata_scsi_error,
140 .can_queue = ATA_DEF_QUEUE,
141 .this_id = ATA_SHT_THIS_ID,
142 .sg_tablesize = LIBATA_MAX_PRD,
143 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
144 .emulated = ATA_SHT_EMULATED,
145 .use_clustering = ATA_SHT_USE_CLUSTERING,
146 .proc_name = DRV_NAME,
147 .dma_boundary = ATA_DMA_BOUNDARY,
148 .slave_configure = ata_scsi_slave_config,
149 .bios_param = ata_std_bios_param,
150 };
151
152 static const struct ata_port_operations sil_ops = {
153 .port_disable = ata_port_disable,
154 .dev_config = sil_dev_config,
155 .tf_load = ata_tf_load,
156 .tf_read = ata_tf_read,
157 .check_status = ata_check_status,
158 .exec_command = ata_exec_command,
159 .dev_select = ata_std_dev_select,
160 .probe_reset = ata_std_probe_reset,
161 .post_set_mode = sil_post_set_mode,
162 .bmdma_setup = ata_bmdma_setup,
163 .bmdma_start = ata_bmdma_start,
164 .bmdma_stop = ata_bmdma_stop,
165 .bmdma_status = ata_bmdma_status,
166 .qc_prep = ata_qc_prep,
167 .qc_issue = ata_qc_issue_prot,
168 .eng_timeout = ata_eng_timeout,
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
171 .scr_read = sil_scr_read,
172 .scr_write = sil_scr_write,
173 .port_start = ata_port_start,
174 .port_stop = ata_port_stop,
175 .host_stop = ata_pci_host_stop,
176 };
177
178 static const struct ata_port_info sil_port_info[] = {
179 /* sil_3112 */
180 {
181 .sht = &sil_sht,
182 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
183 ATA_FLAG_MMIO,
184 .pio_mask = 0x1f, /* pio0-4 */
185 .mwdma_mask = 0x07, /* mwdma0-2 */
186 .udma_mask = 0x3f, /* udma0-5 */
187 .port_ops = &sil_ops,
188 }, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
189 {
190 .sht = &sil_sht,
191 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | SIL_FLAG_MOD15WRITE,
193 .pio_mask = 0x1f, /* pio0-4 */
194 .mwdma_mask = 0x07, /* mwdma0-2 */
195 .udma_mask = 0x3f, /* udma0-5 */
196 .port_ops = &sil_ops,
197 }, /* sil_3114 */
198 {
199 .sht = &sil_sht,
200 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
201 ATA_FLAG_MMIO,
202 .pio_mask = 0x1f, /* pio0-4 */
203 .mwdma_mask = 0x07, /* mwdma0-2 */
204 .udma_mask = 0x3f, /* udma0-5 */
205 .port_ops = &sil_ops,
206 },
207 };
208
209 /* per-port register offsets */
210 /* TODO: we can probably calculate rather than use a table */
211 static const struct {
212 unsigned long tf; /* ATA taskfile register block */
213 unsigned long ctl; /* ATA control/altstatus register block */
214 unsigned long bmdma; /* DMA register block */
215 unsigned long scr; /* SATA control register block */
216 unsigned long sien; /* SATA Interrupt Enable register */
217 unsigned long xfer_mode;/* data transfer mode register */
218 } sil_port[] = {
219 /* port 0 ... */
220 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
221 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
222 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
223 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
224 /* ... port 3 */
225 };
226
227 MODULE_AUTHOR("Jeff Garzik");
228 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
229 MODULE_LICENSE("GPL");
230 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
231 MODULE_VERSION(DRV_VERSION);
232
233 static int slow_down = 0;
234 module_param(slow_down, int, 0444);
235 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
236
237
238 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
239 {
240 u8 cache_line = 0;
241 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
242 return cache_line;
243 }
244
245 static void sil_post_set_mode (struct ata_port *ap)
246 {
247 struct ata_host_set *host_set = ap->host_set;
248 struct ata_device *dev;
249 void __iomem *addr =
250 host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
251 u32 tmp, dev_mode[2];
252 unsigned int i;
253
254 for (i = 0; i < 2; i++) {
255 dev = &ap->device[i];
256 if (!ata_dev_present(dev))
257 dev_mode[i] = 0; /* PIO0/1/2 */
258 else if (dev->flags & ATA_DFLAG_PIO)
259 dev_mode[i] = 1; /* PIO3/4 */
260 else
261 dev_mode[i] = 3; /* UDMA */
262 /* value 2 indicates MDMA */
263 }
264
265 tmp = readl(addr);
266 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
267 tmp |= dev_mode[0];
268 tmp |= (dev_mode[1] << 4);
269 writel(tmp, addr);
270 readl(addr); /* flush */
271 }
272
273 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
274 {
275 unsigned long offset = ap->ioaddr.scr_addr;
276
277 switch (sc_reg) {
278 case SCR_STATUS:
279 return offset + 4;
280 case SCR_ERROR:
281 return offset + 8;
282 case SCR_CONTROL:
283 return offset;
284 default:
285 /* do nothing */
286 break;
287 }
288
289 return 0;
290 }
291
292 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
293 {
294 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
295 if (mmio)
296 return readl(mmio);
297 return 0xffffffffU;
298 }
299
300 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
301 {
302 void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
303 if (mmio)
304 writel(val, mmio);
305 }
306
307 /**
308 * sil_dev_config - Apply device/host-specific errata fixups
309 * @ap: Port containing device to be examined
310 * @dev: Device to be examined
311 *
312 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
313 * device is known to be present, this function is called.
314 * We apply two errata fixups which are specific to Silicon Image,
315 * a Seagate and a Maxtor fixup.
316 *
317 * For certain Seagate devices, we must limit the maximum sectors
318 * to under 8K.
319 *
320 * For certain Maxtor devices, we must not program the drive
321 * beyond udma5.
322 *
323 * Both fixups are unfairly pessimistic. As soon as I get more
324 * information on these errata, I will create a more exhaustive
325 * list, and apply the fixups to only the specific
326 * devices/hosts/firmwares that need it.
327 *
328 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
329 * The Maxtor quirk is in the blacklist, but I'm keeping the original
330 * pessimistic fix for the following reasons...
331 * - There seems to be less info on it, only one device gleaned off the
332 * Windows driver, maybe only one is affected. More info would be greatly
333 * appreciated.
334 * - But then again UDMA5 is hardly anything to complain about
335 */
336 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
337 {
338 unsigned int n, quirks = 0;
339 unsigned char model_num[41];
340
341 ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
342
343 for (n = 0; sil_blacklist[n].product; n++)
344 if (!strcmp(sil_blacklist[n].product, model_num)) {
345 quirks = sil_blacklist[n].quirk;
346 break;
347 }
348
349 /* limit requests to 15 sectors */
350 if (slow_down ||
351 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
352 (quirks & SIL_QUIRK_MOD15WRITE))) {
353 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix (mod15write workaround)\n",
354 ap->id, dev->devno);
355 dev->max_sectors = 15;
356 return;
357 }
358
359 /* limit to udma5 */
360 if (quirks & SIL_QUIRK_UDMA5MAX) {
361 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
362 ap->id, dev->devno, model_num);
363 ap->udma_mask &= ATA_UDMA5;
364 return;
365 }
366 }
367
368 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
369 {
370 static int printed_version;
371 struct ata_probe_ent *probe_ent = NULL;
372 unsigned long base;
373 void __iomem *mmio_base;
374 int rc;
375 unsigned int i;
376 int pci_dev_busy = 0;
377 u32 tmp, irq_mask;
378 u8 cls;
379
380 if (!printed_version++)
381 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
382
383 /*
384 * If this driver happens to only be useful on Apple's K2, then
385 * we should check that here as it has a normal Serverworks ID
386 */
387 rc = pci_enable_device(pdev);
388 if (rc)
389 return rc;
390
391 rc = pci_request_regions(pdev, DRV_NAME);
392 if (rc) {
393 pci_dev_busy = 1;
394 goto err_out;
395 }
396
397 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
398 if (rc)
399 goto err_out_regions;
400 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
401 if (rc)
402 goto err_out_regions;
403
404 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
405 if (probe_ent == NULL) {
406 rc = -ENOMEM;
407 goto err_out_regions;
408 }
409
410 memset(probe_ent, 0, sizeof(*probe_ent));
411 INIT_LIST_HEAD(&probe_ent->node);
412 probe_ent->dev = pci_dev_to_dev(pdev);
413 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
414 probe_ent->sht = sil_port_info[ent->driver_data].sht;
415 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
416 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
417 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
418 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
419 probe_ent->irq = pdev->irq;
420 probe_ent->irq_flags = SA_SHIRQ;
421 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
422
423 mmio_base = pci_iomap(pdev, 5, 0);
424 if (mmio_base == NULL) {
425 rc = -ENOMEM;
426 goto err_out_free_ent;
427 }
428
429 probe_ent->mmio_base = mmio_base;
430
431 base = (unsigned long) mmio_base;
432
433 for (i = 0; i < probe_ent->n_ports; i++) {
434 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
435 probe_ent->port[i].altstatus_addr =
436 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
437 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
438 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
439 ata_std_ports(&probe_ent->port[i]);
440 }
441
442 /* Initialize FIFO PCI bus arbitration */
443 cls = sil_get_device_cache_line(pdev);
444 if (cls) {
445 cls >>= 3;
446 cls++; /* cls = (line_size/8)+1 */
447 writeb(cls, mmio_base + SIL_FIFO_R0);
448 writeb(cls, mmio_base + SIL_FIFO_W0);
449 writeb(cls, mmio_base + SIL_FIFO_R1);
450 writeb(cls, mmio_base + SIL_FIFO_W1);
451 if (ent->driver_data == sil_3114) {
452 writeb(cls, mmio_base + SIL_FIFO_R2);
453 writeb(cls, mmio_base + SIL_FIFO_W2);
454 writeb(cls, mmio_base + SIL_FIFO_R3);
455 writeb(cls, mmio_base + SIL_FIFO_W3);
456 }
457 } else
458 dev_printk(KERN_WARNING, &pdev->dev,
459 "cache line size not set. Driver may not function\n");
460
461 if (ent->driver_data == sil_3114) {
462 irq_mask = SIL_MASK_4PORT;
463
464 /* flip the magic "make 4 ports work" bit */
465 tmp = readl(mmio_base + SIL_IDE2_BMDMA);
466 if ((tmp & SIL_INTR_STEERING) == 0)
467 writel(tmp | SIL_INTR_STEERING,
468 mmio_base + SIL_IDE2_BMDMA);
469
470 } else {
471 irq_mask = SIL_MASK_2PORT;
472 }
473
474 /* make sure IDE0/1/2/3 interrupts are not masked */
475 tmp = readl(mmio_base + SIL_SYSCFG);
476 if (tmp & irq_mask) {
477 tmp &= ~irq_mask;
478 writel(tmp, mmio_base + SIL_SYSCFG);
479 readl(mmio_base + SIL_SYSCFG); /* flush */
480 }
481
482 /* mask all SATA phy-related interrupts */
483 /* TODO: unmask bit 6 (SError N bit) for hotplug */
484 for (i = 0; i < probe_ent->n_ports; i++)
485 writel(0, mmio_base + sil_port[i].sien);
486
487 pci_set_master(pdev);
488
489 /* FIXME: check ata_device_add return value */
490 ata_device_add(probe_ent);
491 kfree(probe_ent);
492
493 return 0;
494
495 err_out_free_ent:
496 kfree(probe_ent);
497 err_out_regions:
498 pci_release_regions(pdev);
499 err_out:
500 if (!pci_dev_busy)
501 pci_disable_device(pdev);
502 return rc;
503 }
504
505 static int __init sil_init(void)
506 {
507 return pci_module_init(&sil_pci_driver);
508 }
509
510 static void __exit sil_exit(void)
511 {
512 pci_unregister_driver(&sil_pci_driver);
513 }
514
515
516 module_init(sil_init);
517 module_exit(sil_exit);
kernel source for telekom puls (alcatel/mediatek)