2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #include "sata_promise.h"
42 #define DRV_NAME "sata_promise"
43 #define DRV_VERSION "1.01"
47 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
48 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
49 PDC_TBG_MODE
= 0x41, /* TBG mode */
50 PDC_FLASH_CTL
= 0x44, /* Flash control register */
51 PDC_PCI_CTL
= 0x48, /* PCI control and status register */
52 PDC_GLOBAL_CTL
= 0x48, /* Global control/status (per port) */
53 PDC_CTLSTAT
= 0x60, /* IDE control and status (per port) */
54 PDC_SATA_PLUG_CSR
= 0x6C, /* SATA Plug control/status reg */
55 PDC_SLEW_CTL
= 0x470, /* slew rate control reg */
57 PDC_ERR_MASK
= (1<<19) | (1<<20) | (1<<21) | (1<<22) |
58 (1<<8) | (1<<9) | (1<<10),
60 board_2037x
= 0, /* FastTrak S150 TX2plus */
61 board_20319
= 1, /* FastTrak S150 TX4 */
62 board_20619
= 2, /* FastTrak TX4000 */
64 PDC_HAS_PATA
= (1 << 1), /* PDC20375 has PATA */
66 PDC_RESET
= (1 << 11), /* HDMA reset */
70 struct pdc_port_priv
{
75 static u32
pdc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
76 static void pdc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
77 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
78 static irqreturn_t
pdc_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
79 static void pdc_eng_timeout(struct ata_port
*ap
);
80 static int pdc_port_start(struct ata_port
*ap
);
81 static void pdc_port_stop(struct ata_port
*ap
);
82 static void pdc_phy_reset(struct ata_port
*ap
);
83 static void pdc_qc_prep(struct ata_queued_cmd
*qc
);
84 static void pdc_tf_load_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
);
85 static void pdc_exec_command_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
);
86 static void pdc_irq_clear(struct ata_port
*ap
);
87 static int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
);
89 static Scsi_Host_Template pdc_ata_sht
= {
90 .module
= THIS_MODULE
,
92 .ioctl
= ata_scsi_ioctl
,
93 .queuecommand
= ata_scsi_queuecmd
,
94 .eh_strategy_handler
= ata_scsi_error
,
95 .can_queue
= ATA_DEF_QUEUE
,
96 .this_id
= ATA_SHT_THIS_ID
,
97 .sg_tablesize
= LIBATA_MAX_PRD
,
98 .max_sectors
= ATA_MAX_SECTORS
,
99 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
100 .emulated
= ATA_SHT_EMULATED
,
101 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
102 .proc_name
= DRV_NAME
,
103 .dma_boundary
= ATA_DMA_BOUNDARY
,
104 .slave_configure
= ata_scsi_slave_config
,
105 .bios_param
= ata_std_bios_param
,
109 static struct ata_port_operations pdc_ata_ops
= {
110 .port_disable
= ata_port_disable
,
111 .tf_load
= pdc_tf_load_mmio
,
112 .tf_read
= ata_tf_read
,
113 .check_status
= ata_check_status
,
114 .exec_command
= pdc_exec_command_mmio
,
115 .dev_select
= ata_std_dev_select
,
116 .phy_reset
= pdc_phy_reset
,
117 .qc_prep
= pdc_qc_prep
,
118 .qc_issue
= pdc_qc_issue_prot
,
119 .eng_timeout
= pdc_eng_timeout
,
120 .irq_handler
= pdc_interrupt
,
121 .irq_clear
= pdc_irq_clear
,
122 .scr_read
= pdc_sata_scr_read
,
123 .scr_write
= pdc_sata_scr_write
,
124 .port_start
= pdc_port_start
,
125 .port_stop
= pdc_port_stop
,
128 static struct ata_port_info pdc_port_info
[] = {
132 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
133 ATA_FLAG_SRST
| ATA_FLAG_MMIO
,
134 .pio_mask
= 0x1f, /* pio0-4 */
135 .mwdma_mask
= 0x07, /* mwdma0-2 */
136 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
137 .port_ops
= &pdc_ata_ops
,
143 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
144 ATA_FLAG_SRST
| ATA_FLAG_MMIO
,
145 .pio_mask
= 0x1f, /* pio0-4 */
146 .mwdma_mask
= 0x07, /* mwdma0-2 */
147 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
148 .port_ops
= &pdc_ata_ops
,
154 .host_flags
= ATA_FLAG_NO_LEGACY
| ATA_FLAG_SRST
|
155 ATA_FLAG_MMIO
| ATA_FLAG_SLAVE_POSS
,
156 .pio_mask
= 0x1f, /* pio0-4 */
157 .mwdma_mask
= 0x07, /* mwdma0-2 */
158 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
159 .port_ops
= &pdc_ata_ops
,
163 static struct pci_device_id pdc_ata_pci_tbl
[] = {
164 { PCI_VENDOR_ID_PROMISE
, 0x3371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
166 { PCI_VENDOR_ID_PROMISE
, 0x3373, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
168 { PCI_VENDOR_ID_PROMISE
, 0x3375, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
170 { PCI_VENDOR_ID_PROMISE
, 0x3376, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
172 { PCI_VENDOR_ID_PROMISE
, 0x3574, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
174 { PCI_VENDOR_ID_PROMISE
, 0x3d75, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
177 { PCI_VENDOR_ID_PROMISE
, 0x3318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
179 { PCI_VENDOR_ID_PROMISE
, 0x3319, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
181 { PCI_VENDOR_ID_PROMISE
, 0x3d18, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
184 { PCI_VENDOR_ID_PROMISE
, 0x6629, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
187 { } /* terminate list */
191 static struct pci_driver pdc_ata_pci_driver
= {
193 .id_table
= pdc_ata_pci_tbl
,
194 .probe
= pdc_ata_init_one
,
195 .remove
= ata_pci_remove_one
,
199 static int pdc_port_start(struct ata_port
*ap
)
201 struct device
*dev
= ap
->host_set
->dev
;
202 struct pdc_port_priv
*pp
;
205 rc
= ata_port_start(ap
);
209 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
214 memset(pp
, 0, sizeof(*pp
));
216 pp
->pkt
= dma_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
222 ap
->private_data
= pp
;
234 static void pdc_port_stop(struct ata_port
*ap
)
236 struct device
*dev
= ap
->host_set
->dev
;
237 struct pdc_port_priv
*pp
= ap
->private_data
;
239 ap
->private_data
= NULL
;
240 dma_free_coherent(dev
, 128, pp
->pkt
, pp
->pkt_dma
);
246 static void pdc_reset_port(struct ata_port
*ap
)
248 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
+ PDC_CTLSTAT
;
252 for (i
= 11; i
> 0; i
--) {
265 readl(mmio
); /* flush */
268 static void pdc_phy_reset(struct ata_port
*ap
)
274 static u32
pdc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
276 if (sc_reg
> SCR_CONTROL
)
278 return readl((void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
282 static void pdc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
,
285 if (sc_reg
> SCR_CONTROL
)
287 writel(val
, (void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
290 static void pdc_qc_prep(struct ata_queued_cmd
*qc
)
292 struct pdc_port_priv
*pp
= qc
->ap
->private_data
;
297 switch (qc
->tf
.protocol
) {
302 case ATA_PROT_NODATA
:
303 i
= pdc_pkt_header(&qc
->tf
, qc
->ap
->prd_dma
,
304 qc
->dev
->devno
, pp
->pkt
);
306 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
307 i
= pdc_prep_lba48(&qc
->tf
, pp
->pkt
, i
);
309 i
= pdc_prep_lba28(&qc
->tf
, pp
->pkt
, i
);
311 pdc_pkt_footer(&qc
->tf
, pp
->pkt
, i
);
319 static void pdc_eng_timeout(struct ata_port
*ap
)
322 struct ata_queued_cmd
*qc
;
326 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
328 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
333 /* hack alert! We cannot use the supplied completion
334 * function from inside the ->eh_strategy_handler() thread.
335 * libata is the only user of ->eh_strategy_handler() in
336 * any kernel, so the default scsi_done() assumes it is
337 * not being called from the SCSI EH.
339 qc
->scsidone
= scsi_finish_command
;
341 switch (qc
->tf
.protocol
) {
343 case ATA_PROT_NODATA
:
344 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
345 ata_qc_complete(qc
, ata_wait_idle(ap
) | ATA_ERR
);
349 drv_stat
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
351 printk(KERN_ERR
"ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
352 ap
->id
, qc
->tf
.command
, drv_stat
);
354 ata_qc_complete(qc
, drv_stat
);
362 static inline unsigned int pdc_host_intr( struct ata_port
*ap
,
363 struct ata_queued_cmd
*qc
)
366 unsigned int handled
= 0, have_err
= 0;
368 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
+ PDC_GLOBAL_CTL
;
371 if (tmp
& PDC_ERR_MASK
) {
376 switch (qc
->tf
.protocol
) {
378 case ATA_PROT_NODATA
:
379 status
= ata_wait_idle(ap
);
382 ata_qc_complete(qc
, status
);
387 ap
->stats
.idle_irq
++;
394 static void pdc_irq_clear(struct ata_port
*ap
)
396 struct ata_host_set
*host_set
= ap
->host_set
;
397 void *mmio
= host_set
->mmio_base
;
399 readl(mmio
+ PDC_INT_SEQMASK
);
402 static irqreturn_t
pdc_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
404 struct ata_host_set
*host_set
= dev_instance
;
408 unsigned int handled
= 0;
413 if (!host_set
|| !host_set
->mmio_base
) {
414 VPRINTK("QUICK EXIT\n");
418 mmio_base
= host_set
->mmio_base
;
420 /* reading should also clear interrupts */
421 mask
= readl(mmio_base
+ PDC_INT_SEQMASK
);
423 if (mask
== 0xffffffff) {
424 VPRINTK("QUICK EXIT 2\n");
427 mask
&= 0xffff; /* only 16 tags possible */
429 VPRINTK("QUICK EXIT 3\n");
433 spin_lock(&host_set
->lock
);
435 writel(mask
, mmio_base
+ PDC_INT_SEQMASK
);
437 for (i
= 0; i
< host_set
->n_ports
; i
++) {
438 VPRINTK("port %u\n", i
);
439 ap
= host_set
->ports
[i
];
440 tmp
= mask
& (1 << (i
+ 1));
441 if (tmp
&& ap
&& (!(ap
->flags
& ATA_FLAG_PORT_DISABLED
))) {
442 struct ata_queued_cmd
*qc
;
444 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
445 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
)))
446 handled
+= pdc_host_intr(ap
, qc
);
450 spin_unlock(&host_set
->lock
);
454 return IRQ_RETVAL(handled
);
457 static inline void pdc_packet_start(struct ata_queued_cmd
*qc
)
459 struct ata_port
*ap
= qc
->ap
;
460 struct pdc_port_priv
*pp
= ap
->private_data
;
461 unsigned int port_no
= ap
->port_no
;
462 u8 seq
= (u8
) (port_no
+ 1);
464 VPRINTK("ENTER, ap %p\n", ap
);
466 writel(0x00000001, ap
->host_set
->mmio_base
+ (seq
* 4));
467 readl(ap
->host_set
->mmio_base
+ (seq
* 4)); /* flush */
470 wmb(); /* flush PRD, pkt writes */
471 writel(pp
->pkt_dma
, (void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
472 readl((void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
); /* flush */
475 static int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
)
477 switch (qc
->tf
.protocol
) {
479 case ATA_PROT_NODATA
:
480 pdc_packet_start(qc
);
483 case ATA_PROT_ATAPI_DMA
:
491 return ata_qc_issue_prot(qc
);
494 static void pdc_tf_load_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
)
496 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
497 tf
->protocol
== ATA_PROT_NODATA
);
502 static void pdc_exec_command_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
)
504 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
505 tf
->protocol
== ATA_PROT_NODATA
);
506 ata_exec_command(ap
, tf
);
510 static void pdc_ata_setup_port(struct ata_ioports
*port
, unsigned long base
)
512 port
->cmd_addr
= base
;
513 port
->data_addr
= base
;
515 port
->error_addr
= base
+ 0x4;
516 port
->nsect_addr
= base
+ 0x8;
517 port
->lbal_addr
= base
+ 0xc;
518 port
->lbam_addr
= base
+ 0x10;
519 port
->lbah_addr
= base
+ 0x14;
520 port
->device_addr
= base
+ 0x18;
522 port
->status_addr
= base
+ 0x1c;
523 port
->altstatus_addr
=
524 port
->ctl_addr
= base
+ 0x38;
528 static void pdc_host_init(unsigned int chip_id
, struct ata_probe_ent
*pe
)
530 void *mmio
= pe
->mmio_base
;
534 * Except for the hotplug stuff, this is voodoo from the
535 * Promise driver. Label this entire section
536 * "TODO: figure out why we do this"
539 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
540 tmp
= readl(mmio
+ PDC_FLASH_CTL
);
541 tmp
|= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
542 writel(tmp
, mmio
+ PDC_FLASH_CTL
);
544 /* clear plug/unplug flags for all ports */
545 tmp
= readl(mmio
+ PDC_SATA_PLUG_CSR
);
546 writel(tmp
| 0xff, mmio
+ PDC_SATA_PLUG_CSR
);
548 /* mask plug/unplug ints */
549 tmp
= readl(mmio
+ PDC_SATA_PLUG_CSR
);
550 writel(tmp
| 0xff0000, mmio
+ PDC_SATA_PLUG_CSR
);
552 /* reduce TBG clock to 133 Mhz. */
553 tmp
= readl(mmio
+ PDC_TBG_MODE
);
554 tmp
&= ~0x30000; /* clear bit 17, 16*/
555 tmp
|= 0x10000; /* set bit 17:16 = 0:1 */
556 writel(tmp
, mmio
+ PDC_TBG_MODE
);
558 readl(mmio
+ PDC_TBG_MODE
); /* flush */
561 /* adjust slew rate control register. */
562 tmp
= readl(mmio
+ PDC_SLEW_CTL
);
563 tmp
&= 0xFFFFF03F; /* clear bit 11 ~ 6 */
564 tmp
|= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
565 writel(tmp
, mmio
+ PDC_SLEW_CTL
);
568 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
570 static int printed_version
;
571 struct ata_probe_ent
*probe_ent
= NULL
;
574 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
575 int pci_dev_busy
= 0;
578 if (!printed_version
++)
579 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
582 * If this driver happens to only be useful on Apple's K2, then
583 * we should check that here as it has a normal Serverworks ID
585 rc
= pci_enable_device(pdev
);
589 rc
= pci_request_regions(pdev
, DRV_NAME
);
595 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
597 goto err_out_regions
;
598 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
600 goto err_out_regions
;
602 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
603 if (probe_ent
== NULL
) {
605 goto err_out_regions
;
608 memset(probe_ent
, 0, sizeof(*probe_ent
));
609 probe_ent
->dev
= pci_dev_to_dev(pdev
);
610 INIT_LIST_HEAD(&probe_ent
->node
);
612 mmio_base
= ioremap(pci_resource_start(pdev
, 3),
613 pci_resource_len(pdev
, 3));
614 if (mmio_base
== NULL
) {
616 goto err_out_free_ent
;
618 base
= (unsigned long) mmio_base
;
620 probe_ent
->sht
= pdc_port_info
[board_idx
].sht
;
621 probe_ent
->host_flags
= pdc_port_info
[board_idx
].host_flags
;
622 probe_ent
->pio_mask
= pdc_port_info
[board_idx
].pio_mask
;
623 probe_ent
->mwdma_mask
= pdc_port_info
[board_idx
].mwdma_mask
;
624 probe_ent
->udma_mask
= pdc_port_info
[board_idx
].udma_mask
;
625 probe_ent
->port_ops
= pdc_port_info
[board_idx
].port_ops
;
627 probe_ent
->irq
= pdev
->irq
;
628 probe_ent
->irq_flags
= SA_SHIRQ
;
629 probe_ent
->mmio_base
= mmio_base
;
631 pdc_ata_setup_port(&probe_ent
->port
[0], base
+ 0x200);
632 pdc_ata_setup_port(&probe_ent
->port
[1], base
+ 0x280);
634 probe_ent
->port
[0].scr_addr
= base
+ 0x400;
635 probe_ent
->port
[1].scr_addr
= base
+ 0x500;
637 /* notice 4-port boards */
640 probe_ent
->n_ports
= 4;
642 pdc_ata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
643 pdc_ata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
645 probe_ent
->port
[2].scr_addr
= base
+ 0x600;
646 probe_ent
->port
[3].scr_addr
= base
+ 0x700;
649 probe_ent
->n_ports
= 2;
652 probe_ent
->n_ports
= 4;
654 pdc_ata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
655 pdc_ata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
657 probe_ent
->port
[2].scr_addr
= base
+ 0x600;
658 probe_ent
->port
[3].scr_addr
= base
+ 0x700;
665 pci_set_master(pdev
);
667 /* initialize adapter */
668 pdc_host_init(board_idx
, probe_ent
);
670 /* FIXME: check ata_device_add return value */
671 ata_device_add(probe_ent
);
679 pci_release_regions(pdev
);
682 pci_disable_device(pdev
);
687 static int __init
pdc_ata_init(void)
689 return pci_module_init(&pdc_ata_pci_driver
);
693 static void __exit
pdc_ata_exit(void)
695 pci_unregister_driver(&pdc_ata_pci_driver
);
699 MODULE_AUTHOR("Jeff Garzik");
700 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
701 MODULE_LICENSE("GPL");
702 MODULE_DEVICE_TABLE(pci
, pdc_ata_pci_tbl
);
703 MODULE_VERSION(DRV_VERSION
);
705 module_init(pdc_ata_init
);
706 module_exit(pdc_ata_exit
);