2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.03"
53 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE
= 0x41, /* TBG mode */
56 PDC_FLASH_CTL
= 0x44, /* Flash control register */
57 PDC_PCI_CTL
= 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL
= 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT
= 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR
= 0x6C, /* SATA Plug control/status reg */
61 PDC_SLEW_CTL
= 0x470, /* slew rate control reg */
63 PDC_ERR_MASK
= (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
66 board_2037x
= 0, /* FastTrak S150 TX2plus */
67 board_20319
= 1, /* FastTrak S150 TX4 */
68 board_20619
= 2, /* FastTrak TX4000 */
70 PDC_HAS_PATA
= (1 << 1), /* PDC20375 has PATA */
72 PDC_RESET
= (1 << 11), /* HDMA reset */
74 PDC_COMMON_FLAGS
= ATA_FLAG_NO_LEGACY
| ATA_FLAG_SRST
|
75 ATA_FLAG_MMIO
| ATA_FLAG_NO_ATAPI
,
79 struct pdc_port_priv
{
84 static u32
pdc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
85 static void pdc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
86 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
87 static irqreturn_t
pdc_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
88 static void pdc_eng_timeout(struct ata_port
*ap
);
89 static int pdc_port_start(struct ata_port
*ap
);
90 static void pdc_port_stop(struct ata_port
*ap
);
91 static void pdc_pata_phy_reset(struct ata_port
*ap
);
92 static void pdc_sata_phy_reset(struct ata_port
*ap
);
93 static void pdc_qc_prep(struct ata_queued_cmd
*qc
);
94 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
95 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
);
96 static void pdc_irq_clear(struct ata_port
*ap
);
97 static int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
);
100 static struct scsi_host_template pdc_ata_sht
= {
101 .module
= THIS_MODULE
,
103 .ioctl
= ata_scsi_ioctl
,
104 .queuecommand
= ata_scsi_queuecmd
,
105 .eh_strategy_handler
= ata_scsi_error
,
106 .can_queue
= ATA_DEF_QUEUE
,
107 .this_id
= ATA_SHT_THIS_ID
,
108 .sg_tablesize
= LIBATA_MAX_PRD
,
109 .max_sectors
= ATA_MAX_SECTORS
,
110 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
111 .emulated
= ATA_SHT_EMULATED
,
112 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
113 .proc_name
= DRV_NAME
,
114 .dma_boundary
= ATA_DMA_BOUNDARY
,
115 .slave_configure
= ata_scsi_slave_config
,
116 .bios_param
= ata_std_bios_param
,
120 static const struct ata_port_operations pdc_sata_ops
= {
121 .port_disable
= ata_port_disable
,
122 .tf_load
= pdc_tf_load_mmio
,
123 .tf_read
= ata_tf_read
,
124 .check_status
= ata_check_status
,
125 .exec_command
= pdc_exec_command_mmio
,
126 .dev_select
= ata_std_dev_select
,
128 .phy_reset
= pdc_sata_phy_reset
,
130 .qc_prep
= pdc_qc_prep
,
131 .qc_issue
= pdc_qc_issue_prot
,
132 .eng_timeout
= pdc_eng_timeout
,
133 .irq_handler
= pdc_interrupt
,
134 .irq_clear
= pdc_irq_clear
,
136 .scr_read
= pdc_sata_scr_read
,
137 .scr_write
= pdc_sata_scr_write
,
138 .port_start
= pdc_port_start
,
139 .port_stop
= pdc_port_stop
,
140 .host_stop
= ata_pci_host_stop
,
143 static const struct ata_port_operations pdc_pata_ops
= {
144 .port_disable
= ata_port_disable
,
145 .tf_load
= pdc_tf_load_mmio
,
146 .tf_read
= ata_tf_read
,
147 .check_status
= ata_check_status
,
148 .exec_command
= pdc_exec_command_mmio
,
149 .dev_select
= ata_std_dev_select
,
151 .phy_reset
= pdc_pata_phy_reset
,
153 .qc_prep
= pdc_qc_prep
,
154 .qc_issue
= pdc_qc_issue_prot
,
155 .eng_timeout
= pdc_eng_timeout
,
156 .irq_handler
= pdc_interrupt
,
157 .irq_clear
= pdc_irq_clear
,
159 .port_start
= pdc_port_start
,
160 .port_stop
= pdc_port_stop
,
161 .host_stop
= ata_pci_host_stop
,
164 static const struct ata_port_info pdc_port_info
[] = {
168 .host_flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
,
169 .pio_mask
= 0x1f, /* pio0-4 */
170 .mwdma_mask
= 0x07, /* mwdma0-2 */
171 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
172 .port_ops
= &pdc_sata_ops
,
178 .host_flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SATA
,
179 .pio_mask
= 0x1f, /* pio0-4 */
180 .mwdma_mask
= 0x07, /* mwdma0-2 */
181 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
182 .port_ops
= &pdc_sata_ops
,
188 .host_flags
= PDC_COMMON_FLAGS
| ATA_FLAG_SLAVE_POSS
,
189 .pio_mask
= 0x1f, /* pio0-4 */
190 .mwdma_mask
= 0x07, /* mwdma0-2 */
191 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
192 .port_ops
= &pdc_pata_ops
,
196 static const struct pci_device_id pdc_ata_pci_tbl
[] = {
197 { PCI_VENDOR_ID_PROMISE
, 0x3371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
199 { PCI_VENDOR_ID_PROMISE
, 0x3570, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
201 { PCI_VENDOR_ID_PROMISE
, 0x3571, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
203 { PCI_VENDOR_ID_PROMISE
, 0x3373, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
205 { PCI_VENDOR_ID_PROMISE
, 0x3375, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
207 { PCI_VENDOR_ID_PROMISE
, 0x3376, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
209 { PCI_VENDOR_ID_PROMISE
, 0x3574, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
211 { PCI_VENDOR_ID_PROMISE
, 0x3d75, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
213 { PCI_VENDOR_ID_PROMISE
, 0x3d73, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
216 { PCI_VENDOR_ID_PROMISE
, 0x3318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
218 { PCI_VENDOR_ID_PROMISE
, 0x3319, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
220 { PCI_VENDOR_ID_PROMISE
, 0x3519, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
222 { PCI_VENDOR_ID_PROMISE
, 0x3d17, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
224 { PCI_VENDOR_ID_PROMISE
, 0x3d18, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
227 { PCI_VENDOR_ID_PROMISE
, 0x6629, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
230 { } /* terminate list */
234 static struct pci_driver pdc_ata_pci_driver
= {
236 .id_table
= pdc_ata_pci_tbl
,
237 .probe
= pdc_ata_init_one
,
238 .remove
= ata_pci_remove_one
,
242 static int pdc_port_start(struct ata_port
*ap
)
244 struct device
*dev
= ap
->host_set
->dev
;
245 struct pdc_port_priv
*pp
;
248 rc
= ata_port_start(ap
);
252 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
257 memset(pp
, 0, sizeof(*pp
));
259 pp
->pkt
= dma_alloc_coherent(dev
, 128, &pp
->pkt_dma
, GFP_KERNEL
);
265 ap
->private_data
= pp
;
277 static void pdc_port_stop(struct ata_port
*ap
)
279 struct device
*dev
= ap
->host_set
->dev
;
280 struct pdc_port_priv
*pp
= ap
->private_data
;
282 ap
->private_data
= NULL
;
283 dma_free_coherent(dev
, 128, pp
->pkt
, pp
->pkt_dma
);
289 static void pdc_reset_port(struct ata_port
*ap
)
291 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_CTLSTAT
;
295 for (i
= 11; i
> 0; i
--) {
308 readl(mmio
); /* flush */
311 static void pdc_sata_phy_reset(struct ata_port
*ap
)
317 static void pdc_pata_phy_reset(struct ata_port
*ap
)
319 /* FIXME: add cable detect. Don't assume 40-pin cable */
320 ap
->cbl
= ATA_CBL_PATA40
;
321 ap
->udma_mask
&= ATA_UDMA_MASK_40C
;
328 static u32
pdc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
330 if (sc_reg
> SCR_CONTROL
)
332 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
336 static void pdc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
,
339 if (sc_reg
> SCR_CONTROL
)
341 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
344 static void pdc_qc_prep(struct ata_queued_cmd
*qc
)
346 struct pdc_port_priv
*pp
= qc
->ap
->private_data
;
351 switch (qc
->tf
.protocol
) {
356 case ATA_PROT_NODATA
:
357 i
= pdc_pkt_header(&qc
->tf
, qc
->ap
->prd_dma
,
358 qc
->dev
->devno
, pp
->pkt
);
360 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
361 i
= pdc_prep_lba48(&qc
->tf
, pp
->pkt
, i
);
363 i
= pdc_prep_lba28(&qc
->tf
, pp
->pkt
, i
);
365 pdc_pkt_footer(&qc
->tf
, pp
->pkt
, i
);
373 static void pdc_eng_timeout(struct ata_port
*ap
)
375 struct ata_host_set
*host_set
= ap
->host_set
;
377 struct ata_queued_cmd
*qc
;
382 spin_lock_irqsave(&host_set
->lock
, flags
);
384 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
386 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
391 /* hack alert! We cannot use the supplied completion
392 * function from inside the ->eh_strategy_handler() thread.
393 * libata is the only user of ->eh_strategy_handler() in
394 * any kernel, so the default scsi_done() assumes it is
395 * not being called from the SCSI EH.
397 qc
->scsidone
= scsi_finish_command
;
399 switch (qc
->tf
.protocol
) {
401 case ATA_PROT_NODATA
:
402 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
403 drv_stat
= ata_wait_idle(ap
);
404 qc
->err_mask
|= __ac_err_mask(drv_stat
);
409 drv_stat
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
411 printk(KERN_ERR
"ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
412 ap
->id
, qc
->tf
.command
, drv_stat
);
414 qc
->err_mask
|= ac_err_mask(drv_stat
);
420 spin_unlock_irqrestore(&host_set
->lock
, flags
);
424 static inline unsigned int pdc_host_intr( struct ata_port
*ap
,
425 struct ata_queued_cmd
*qc
)
427 unsigned int handled
= 0;
429 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_GLOBAL_CTL
;
432 if (tmp
& PDC_ERR_MASK
) {
433 qc
->err_mask
|= AC_ERR_DEV
;
437 switch (qc
->tf
.protocol
) {
439 case ATA_PROT_NODATA
:
440 qc
->err_mask
|= ac_err_mask(ata_wait_idle(ap
));
446 ap
->stats
.idle_irq
++;
453 static void pdc_irq_clear(struct ata_port
*ap
)
455 struct ata_host_set
*host_set
= ap
->host_set
;
456 void __iomem
*mmio
= host_set
->mmio_base
;
458 readl(mmio
+ PDC_INT_SEQMASK
);
461 static irqreturn_t
pdc_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
463 struct ata_host_set
*host_set
= dev_instance
;
467 unsigned int handled
= 0;
468 void __iomem
*mmio_base
;
472 if (!host_set
|| !host_set
->mmio_base
) {
473 VPRINTK("QUICK EXIT\n");
477 mmio_base
= host_set
->mmio_base
;
479 /* reading should also clear interrupts */
480 mask
= readl(mmio_base
+ PDC_INT_SEQMASK
);
482 if (mask
== 0xffffffff) {
483 VPRINTK("QUICK EXIT 2\n");
486 mask
&= 0xffff; /* only 16 tags possible */
488 VPRINTK("QUICK EXIT 3\n");
492 spin_lock(&host_set
->lock
);
494 writel(mask
, mmio_base
+ PDC_INT_SEQMASK
);
496 for (i
= 0; i
< host_set
->n_ports
; i
++) {
497 VPRINTK("port %u\n", i
);
498 ap
= host_set
->ports
[i
];
499 tmp
= mask
& (1 << (i
+ 1));
501 !(ap
->flags
& (ATA_FLAG_PORT_DISABLED
| ATA_FLAG_NOINTR
))) {
502 struct ata_queued_cmd
*qc
;
504 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
505 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
)))
506 handled
+= pdc_host_intr(ap
, qc
);
510 spin_unlock(&host_set
->lock
);
514 return IRQ_RETVAL(handled
);
517 static inline void pdc_packet_start(struct ata_queued_cmd
*qc
)
519 struct ata_port
*ap
= qc
->ap
;
520 struct pdc_port_priv
*pp
= ap
->private_data
;
521 unsigned int port_no
= ap
->port_no
;
522 u8 seq
= (u8
) (port_no
+ 1);
524 VPRINTK("ENTER, ap %p\n", ap
);
526 writel(0x00000001, ap
->host_set
->mmio_base
+ (seq
* 4));
527 readl(ap
->host_set
->mmio_base
+ (seq
* 4)); /* flush */
530 wmb(); /* flush PRD, pkt writes */
531 writel(pp
->pkt_dma
, (void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
532 readl((void __iomem
*) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
); /* flush */
535 static int pdc_qc_issue_prot(struct ata_queued_cmd
*qc
)
537 switch (qc
->tf
.protocol
) {
539 case ATA_PROT_NODATA
:
540 pdc_packet_start(qc
);
543 case ATA_PROT_ATAPI_DMA
:
551 return ata_qc_issue_prot(qc
);
554 static void pdc_tf_load_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
556 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
557 tf
->protocol
== ATA_PROT_NODATA
);
562 static void pdc_exec_command_mmio(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
564 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
565 tf
->protocol
== ATA_PROT_NODATA
);
566 ata_exec_command(ap
, tf
);
570 static void pdc_ata_setup_port(struct ata_ioports
*port
, unsigned long base
)
572 port
->cmd_addr
= base
;
573 port
->data_addr
= base
;
575 port
->error_addr
= base
+ 0x4;
576 port
->nsect_addr
= base
+ 0x8;
577 port
->lbal_addr
= base
+ 0xc;
578 port
->lbam_addr
= base
+ 0x10;
579 port
->lbah_addr
= base
+ 0x14;
580 port
->device_addr
= base
+ 0x18;
582 port
->status_addr
= base
+ 0x1c;
583 port
->altstatus_addr
=
584 port
->ctl_addr
= base
+ 0x38;
588 static void pdc_host_init(unsigned int chip_id
, struct ata_probe_ent
*pe
)
590 void __iomem
*mmio
= pe
->mmio_base
;
594 * Except for the hotplug stuff, this is voodoo from the
595 * Promise driver. Label this entire section
596 * "TODO: figure out why we do this"
599 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
600 tmp
= readl(mmio
+ PDC_FLASH_CTL
);
601 tmp
|= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
602 writel(tmp
, mmio
+ PDC_FLASH_CTL
);
604 /* clear plug/unplug flags for all ports */
605 tmp
= readl(mmio
+ PDC_SATA_PLUG_CSR
);
606 writel(tmp
| 0xff, mmio
+ PDC_SATA_PLUG_CSR
);
608 /* mask plug/unplug ints */
609 tmp
= readl(mmio
+ PDC_SATA_PLUG_CSR
);
610 writel(tmp
| 0xff0000, mmio
+ PDC_SATA_PLUG_CSR
);
612 /* reduce TBG clock to 133 Mhz. */
613 tmp
= readl(mmio
+ PDC_TBG_MODE
);
614 tmp
&= ~0x30000; /* clear bit 17, 16*/
615 tmp
|= 0x10000; /* set bit 17:16 = 0:1 */
616 writel(tmp
, mmio
+ PDC_TBG_MODE
);
618 readl(mmio
+ PDC_TBG_MODE
); /* flush */
621 /* adjust slew rate control register. */
622 tmp
= readl(mmio
+ PDC_SLEW_CTL
);
623 tmp
&= 0xFFFFF03F; /* clear bit 11 ~ 6 */
624 tmp
|= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
625 writel(tmp
, mmio
+ PDC_SLEW_CTL
);
628 static int pdc_ata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
630 static int printed_version
;
631 struct ata_probe_ent
*probe_ent
= NULL
;
633 void __iomem
*mmio_base
;
634 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
635 int pci_dev_busy
= 0;
638 if (!printed_version
++)
639 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
642 * If this driver happens to only be useful on Apple's K2, then
643 * we should check that here as it has a normal Serverworks ID
645 rc
= pci_enable_device(pdev
);
649 rc
= pci_request_regions(pdev
, DRV_NAME
);
655 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
657 goto err_out_regions
;
658 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
660 goto err_out_regions
;
662 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
663 if (probe_ent
== NULL
) {
665 goto err_out_regions
;
668 memset(probe_ent
, 0, sizeof(*probe_ent
));
669 probe_ent
->dev
= pci_dev_to_dev(pdev
);
670 INIT_LIST_HEAD(&probe_ent
->node
);
672 mmio_base
= pci_iomap(pdev
, 3, 0);
673 if (mmio_base
== NULL
) {
675 goto err_out_free_ent
;
677 base
= (unsigned long) mmio_base
;
679 probe_ent
->sht
= pdc_port_info
[board_idx
].sht
;
680 probe_ent
->host_flags
= pdc_port_info
[board_idx
].host_flags
;
681 probe_ent
->pio_mask
= pdc_port_info
[board_idx
].pio_mask
;
682 probe_ent
->mwdma_mask
= pdc_port_info
[board_idx
].mwdma_mask
;
683 probe_ent
->udma_mask
= pdc_port_info
[board_idx
].udma_mask
;
684 probe_ent
->port_ops
= pdc_port_info
[board_idx
].port_ops
;
686 probe_ent
->irq
= pdev
->irq
;
687 probe_ent
->irq_flags
= SA_SHIRQ
;
688 probe_ent
->mmio_base
= mmio_base
;
690 pdc_ata_setup_port(&probe_ent
->port
[0], base
+ 0x200);
691 pdc_ata_setup_port(&probe_ent
->port
[1], base
+ 0x280);
693 probe_ent
->port
[0].scr_addr
= base
+ 0x400;
694 probe_ent
->port
[1].scr_addr
= base
+ 0x500;
696 /* notice 4-port boards */
699 probe_ent
->n_ports
= 4;
701 pdc_ata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
702 pdc_ata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
704 probe_ent
->port
[2].scr_addr
= base
+ 0x600;
705 probe_ent
->port
[3].scr_addr
= base
+ 0x700;
708 probe_ent
->n_ports
= 2;
711 probe_ent
->n_ports
= 4;
713 pdc_ata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
714 pdc_ata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
716 probe_ent
->port
[2].scr_addr
= base
+ 0x600;
717 probe_ent
->port
[3].scr_addr
= base
+ 0x700;
724 pci_set_master(pdev
);
726 /* initialize adapter */
727 pdc_host_init(board_idx
, probe_ent
);
729 /* FIXME: check ata_device_add return value */
730 ata_device_add(probe_ent
);
738 pci_release_regions(pdev
);
741 pci_disable_device(pdev
);
746 static int __init
pdc_ata_init(void)
748 return pci_module_init(&pdc_ata_pci_driver
);
752 static void __exit
pdc_ata_exit(void)
754 pci_unregister_driver(&pdc_ata_pci_driver
);
758 MODULE_AUTHOR("Jeff Garzik");
759 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
760 MODULE_LICENSE("GPL");
761 MODULE_DEVICE_TABLE(pci
, pdc_ata_pci_tbl
);
762 MODULE_VERSION(DRV_VERSION
);
764 module_init(pdc_ata_init
);
765 module_exit(pdc_ata_exit
);