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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
100
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
112
113 int ql2xmaxqdepth = MAX_Q_DEPTH;
114 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115 MODULE_PARM_DESC(ql2xmaxqdepth,
116 "Maximum queue depth to set for each LUN. "
117 "Default is 32.");
118
119 int ql2xenabledif = 2;
120 module_param(ql2xenabledif, int, S_IRUGO);
121 MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
125
126 int ql2xenablehba_err_chk = 2;
127 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128 MODULE_PARM_DESC(ql2xenablehba_err_chk,
129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
134
135 int ql2xiidmaenable=1;
136 module_param(ql2xiidmaenable, int, S_IRUGO);
137 MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
141 int ql2xmaxqueues = 1;
142 module_param(ql2xmaxqueues, int, S_IRUGO);
143 MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
147
148 int ql2xmultique_tag;
149 module_param(ql2xmultique_tag, int, S_IRUGO);
150 MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
154
155 int ql2xfwloadbin;
156 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
157 MODULE_PARM_DESC(ql2xfwloadbin,
158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
164 int ql2xetsenable;
165 module_param(ql2xetsenable, int, S_IRUGO);
166 MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
170 int ql2xdbwr = 1;
171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xdbwr,
173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
176
177 int ql2xtargetreset = 1;
178 module_param(ql2xtargetreset, int, S_IRUGO);
179 MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
183 int ql2xgffidenable;
184 module_param(ql2xgffidenable, int, S_IRUGO);
185 MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
188
189 int ql2xasynctmfenable;
190 module_param(ql2xasynctmfenable, int, S_IRUGO);
191 MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
194
195 int ql2xdontresethba;
196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
197 MODULE_PARM_DESC(ql2xdontresethba,
198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
201
202 uint ql2xmaxlun = MAX_LUNS;
203 module_param(ql2xmaxlun, uint, S_IRUGO);
204 MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
208 int ql2xmdcapmask = 0x1F;
209 module_param(ql2xmdcapmask, int, S_IRUGO);
210 MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
213
214 int ql2xmdenable = 1;
215 module_param(ql2xmdenable, int, S_IRUGO);
216 MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
220
221 /*
222 * SCSI host template entry points
223 */
224 static int qla2xxx_slave_configure(struct scsi_device * device);
225 static int qla2xxx_slave_alloc(struct scsi_device *);
226 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227 static void qla2xxx_scan_start(struct Scsi_Host *);
228 static void qla2xxx_slave_destroy(struct scsi_device *);
229 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
230 static int qla2xxx_eh_abort(struct scsi_cmnd *);
231 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
232 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
233 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
235
236 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
237 static int qla2x00_change_queue_type(struct scsi_device *, int);
238 static void qla2x00_free_device(scsi_qla_host_t *);
239
240 struct scsi_host_template qla2xxx_driver_template = {
241 .module = THIS_MODULE,
242 .name = QLA2XXX_DRIVER_NAME,
243 .queuecommand = qla2xxx_queuecommand,
244
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
250
251 .slave_configure = qla2xxx_slave_configure,
252
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
259 .this_id = -1,
260 .cmd_per_lun = 3,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
263
264 .max_sectors = 0xFFFF,
265 .shost_attrs = qla2x00_host_attrs,
266
267 .supported_mode = MODE_INITIATOR,
268 };
269
270 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
271 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
272
273 /* TODO Convert to inlines
274 *
275 * Timer routines
276 */
277
278 __inline__ void
279 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
280 {
281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
287 }
288
289 static inline void
290 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
291 {
292 /* Currently used for 82XX only. */
293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
296 return;
297 }
298
299 mod_timer(&vha->timer, jiffies + interval * HZ);
300 }
301
302 static __inline__ void
303 qla2x00_stop_timer(scsi_qla_host_t *vha)
304 {
305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
307 }
308
309 static int qla2x00_do_dpc(void *data);
310
311 static void qla2x00_rst_aen(scsi_qla_host_t *);
312
313 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
315 static void qla2x00_free_fw_dump(struct qla_hw_data *);
316 static void qla2x00_mem_free(struct qla_hw_data *);
317
318 /* -------------------------------------------------------------------------- */
319 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
320 struct rsp_que *rsp)
321 {
322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
324 GFP_KERNEL);
325 if (!ha->req_q_map) {
326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
328 goto fail_req_map;
329 }
330
331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
332 GFP_KERNEL);
333 if (!ha->rsp_q_map) {
334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
336 goto fail_rsp_map;
337 }
338 /*
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
341 */
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
346 return 1;
347
348 fail_rsp_map:
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
351 fail_req_map:
352 return -ENOMEM;
353 }
354
355 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
356 {
357 if (IS_QLAFX00(ha)) {
358 if (req && req->ring_fx00)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length_fx00 + 1) * sizeof(request_t),
361 req->ring_fx00, req->dma_fx00);
362 } else if (req && req->ring)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length + 1) * sizeof(request_t),
365 req->ring, req->dma);
366
367 if (req)
368 kfree(req->outstanding_cmds);
369
370 kfree(req);
371 req = NULL;
372 }
373
374 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
375 {
376 if (IS_QLAFX00(ha)) {
377 if (rsp && rsp->ring)
378 dma_free_coherent(&ha->pdev->dev,
379 (rsp->length_fx00 + 1) * sizeof(request_t),
380 rsp->ring_fx00, rsp->dma_fx00);
381 } else if (rsp && rsp->ring) {
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length + 1) * sizeof(response_t),
384 rsp->ring, rsp->dma);
385 }
386 kfree(rsp);
387 rsp = NULL;
388 }
389
390 static void qla2x00_free_queues(struct qla_hw_data *ha)
391 {
392 struct req_que *req;
393 struct rsp_que *rsp;
394 int cnt;
395
396 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
397 req = ha->req_q_map[cnt];
398 qla2x00_free_req_que(ha, req);
399 }
400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
402
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 rsp = ha->rsp_q_map[cnt];
405 qla2x00_free_rsp_que(ha, rsp);
406 }
407 kfree(ha->rsp_q_map);
408 ha->rsp_q_map = NULL;
409 }
410
411 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
412 {
413 uint16_t options = 0;
414 int ques, req, ret;
415 struct qla_hw_data *ha = vha->hw;
416
417 if (!(ha->fw_attributes & BIT_6)) {
418 ql_log(ql_log_warn, vha, 0x00d8,
419 "Firmware is not multi-queue capable.\n");
420 goto fail;
421 }
422 if (ql2xmultique_tag) {
423 /* create a request queue for IO */
424 options |= BIT_7;
425 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
426 QLA_DEFAULT_QUE_QOS);
427 if (!req) {
428 ql_log(ql_log_warn, vha, 0x00e0,
429 "Failed to create request queue.\n");
430 goto fail;
431 }
432 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
433 vha->req = ha->req_q_map[req];
434 options |= BIT_1;
435 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
436 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
437 if (!ret) {
438 ql_log(ql_log_warn, vha, 0x00e8,
439 "Failed to create response queue.\n");
440 goto fail2;
441 }
442 }
443 ha->flags.cpu_affinity_enabled = 1;
444 ql_dbg(ql_dbg_multiq, vha, 0xc007,
445 "CPU affinity mode enalbed, "
446 "no. of response queues:%d no. of request queues:%d.\n",
447 ha->max_rsp_queues, ha->max_req_queues);
448 ql_dbg(ql_dbg_init, vha, 0x00e9,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 }
453 return 0;
454 fail2:
455 qla25xx_delete_queues(vha);
456 destroy_workqueue(ha->wq);
457 ha->wq = NULL;
458 vha->req = ha->req_q_map[0];
459 fail:
460 ha->mqenable = 0;
461 kfree(ha->req_q_map);
462 kfree(ha->rsp_q_map);
463 ha->max_req_queues = ha->max_rsp_queues = 1;
464 return 1;
465 }
466
467 static char *
468 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
469 {
470 struct qla_hw_data *ha = vha->hw;
471 static char *pci_bus_modes[] = {
472 "33", "66", "100", "133",
473 };
474 uint16_t pci_bus;
475
476 strcpy(str, "PCI");
477 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
478 if (pci_bus) {
479 strcat(str, "-X (");
480 strcat(str, pci_bus_modes[pci_bus]);
481 } else {
482 pci_bus = (ha->pci_attr & BIT_8) >> 8;
483 strcat(str, " (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 }
486 strcat(str, " MHz)");
487
488 return (str);
489 }
490
491 static char *
492 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
493 {
494 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
495 struct qla_hw_data *ha = vha->hw;
496 uint32_t pci_bus;
497
498 if (pci_is_pcie(ha->pdev)) {
499 char lwstr[6];
500 uint32_t lstat, lspeed, lwidth;
501
502 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
503 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
504 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
505
506 strcpy(str, "PCIe (");
507 switch (lspeed) {
508 case 1:
509 strcat(str, "2.5GT/s ");
510 break;
511 case 2:
512 strcat(str, "5.0GT/s ");
513 break;
514 case 3:
515 strcat(str, "8.0GT/s ");
516 break;
517 default:
518 strcat(str, "<unknown> ");
519 break;
520 }
521 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
522 strcat(str, lwstr);
523
524 return str;
525 }
526
527 strcpy(str, "PCI");
528 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
529 if (pci_bus == 0 || pci_bus == 8) {
530 strcat(str, " (");
531 strcat(str, pci_bus_modes[pci_bus >> 3]);
532 } else {
533 strcat(str, "-X ");
534 if (pci_bus & BIT_2)
535 strcat(str, "Mode 2");
536 else
537 strcat(str, "Mode 1");
538 strcat(str, " (");
539 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
540 }
541 strcat(str, " MHz)");
542
543 return str;
544 }
545
546 static char *
547 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
548 {
549 char un_str[10];
550 struct qla_hw_data *ha = vha->hw;
551
552 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
553 ha->fw_minor_version,
554 ha->fw_subminor_version);
555
556 if (ha->fw_attributes & BIT_9) {
557 strcat(str, "FLX");
558 return (str);
559 }
560
561 switch (ha->fw_attributes & 0xFF) {
562 case 0x7:
563 strcat(str, "EF");
564 break;
565 case 0x17:
566 strcat(str, "TP");
567 break;
568 case 0x37:
569 strcat(str, "IP");
570 break;
571 case 0x77:
572 strcat(str, "VI");
573 break;
574 default:
575 sprintf(un_str, "(%x)", ha->fw_attributes);
576 strcat(str, un_str);
577 break;
578 }
579 if (ha->fw_attributes & 0x100)
580 strcat(str, "X");
581
582 return (str);
583 }
584
585 static char *
586 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
587 {
588 struct qla_hw_data *ha = vha->hw;
589
590 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
591 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
592 return str;
593 }
594
595 void
596 qla2x00_sp_free_dma(void *vha, void *ptr)
597 {
598 srb_t *sp = (srb_t *)ptr;
599 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
600 struct qla_hw_data *ha = sp->fcport->vha->hw;
601 void *ctx = GET_CMD_CTX_SP(sp);
602
603 if (sp->flags & SRB_DMA_VALID) {
604 scsi_dma_unmap(cmd);
605 sp->flags &= ~SRB_DMA_VALID;
606 }
607
608 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
609 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
610 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
611 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
612 }
613
614 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
615 /* List assured to be having elements */
616 qla2x00_clean_dsd_pool(ha, sp);
617 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
618 }
619
620 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
621 dma_pool_free(ha->dl_dma_pool, ctx,
622 ((struct crc_context *)ctx)->crc_ctx_dma);
623 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
624 }
625
626 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
627 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
628
629 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
630 ctx1->fcp_cmnd_dma);
631 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
632 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
633 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
634 mempool_free(ctx1, ha->ctx_mempool);
635 ctx1 = NULL;
636 }
637
638 CMD_SP(cmd) = NULL;
639 qla2x00_rel_sp(sp->fcport->vha, sp);
640 }
641
642 static void
643 qla2x00_sp_compl(void *data, void *ptr, int res)
644 {
645 struct qla_hw_data *ha = (struct qla_hw_data *)data;
646 srb_t *sp = (srb_t *)ptr;
647 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
648
649 cmd->result = res;
650
651 if (atomic_read(&sp->ref_count) == 0) {
652 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
653 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
654 sp, GET_CMD_SP(sp));
655 if (ql2xextended_error_logging & ql_dbg_io)
656 BUG();
657 return;
658 }
659 if (!atomic_dec_and_test(&sp->ref_count))
660 return;
661
662 qla2x00_sp_free_dma(ha, sp);
663 cmd->scsi_done(cmd);
664 }
665
666 /* If we are SP1 here, we need to still take and release the host_lock as SP1
667 * does not have the changes necessary to avoid taking host->host_lock.
668 */
669 static int
670 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
671 {
672 scsi_qla_host_t *vha = shost_priv(host);
673 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
674 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
675 struct qla_hw_data *ha = vha->hw;
676 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
677 srb_t *sp;
678 int rval;
679
680 if (ha->flags.eeh_busy) {
681 if (ha->flags.pci_channel_io_perm_failure) {
682 ql_dbg(ql_dbg_aer, vha, 0x9010,
683 "PCI Channel IO permanent failure, exiting "
684 "cmd=%p.\n", cmd);
685 cmd->result = DID_NO_CONNECT << 16;
686 } else {
687 ql_dbg(ql_dbg_aer, vha, 0x9011,
688 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
689 cmd->result = DID_REQUEUE << 16;
690 }
691 goto qc24_fail_command;
692 }
693
694 rval = fc_remote_port_chkready(rport);
695 if (rval) {
696 cmd->result = rval;
697 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
698 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
699 cmd, rval);
700 goto qc24_fail_command;
701 }
702
703 if (!vha->flags.difdix_supported &&
704 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
705 ql_dbg(ql_dbg_io, vha, 0x3004,
706 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
707 cmd);
708 cmd->result = DID_NO_CONNECT << 16;
709 goto qc24_fail_command;
710 }
711
712 if (!fcport) {
713 cmd->result = DID_NO_CONNECT << 16;
714 goto qc24_fail_command;
715 }
716
717 if (atomic_read(&fcport->state) != FCS_ONLINE) {
718 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
719 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
720 ql_dbg(ql_dbg_io, vha, 0x3005,
721 "Returning DNC, fcport_state=%d loop_state=%d.\n",
722 atomic_read(&fcport->state),
723 atomic_read(&base_vha->loop_state));
724 cmd->result = DID_NO_CONNECT << 16;
725 goto qc24_fail_command;
726 }
727 goto qc24_target_busy;
728 }
729
730 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
731 if (!sp) {
732 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
733 goto qc24_host_busy;
734 }
735
736 sp->u.scmd.cmd = cmd;
737 sp->type = SRB_SCSI_CMD;
738 atomic_set(&sp->ref_count, 1);
739 CMD_SP(cmd) = (void *)sp;
740 sp->free = qla2x00_sp_free_dma;
741 sp->done = qla2x00_sp_compl;
742
743 rval = ha->isp_ops->start_scsi(sp);
744 if (rval != QLA_SUCCESS) {
745 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
746 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
747 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
748 goto qc24_host_busy_free_sp;
749 }
750
751 return 0;
752
753 qc24_host_busy_free_sp:
754 qla2x00_sp_free_dma(ha, sp);
755
756 qc24_host_busy:
757 return SCSI_MLQUEUE_HOST_BUSY;
758
759 qc24_target_busy:
760 return SCSI_MLQUEUE_TARGET_BUSY;
761
762 qc24_fail_command:
763 cmd->scsi_done(cmd);
764
765 return 0;
766 }
767
768 /*
769 * qla2x00_eh_wait_on_command
770 * Waits for the command to be returned by the Firmware for some
771 * max time.
772 *
773 * Input:
774 * cmd = Scsi Command to wait on.
775 *
776 * Return:
777 * Not Found : 0
778 * Found : 1
779 */
780 static int
781 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
782 {
783 #define ABORT_POLLING_PERIOD 1000
784 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
785 unsigned long wait_iter = ABORT_WAIT_ITER;
786 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
787 struct qla_hw_data *ha = vha->hw;
788 int ret = QLA_SUCCESS;
789
790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
791 ql_dbg(ql_dbg_taskm, vha, 0x8005,
792 "Return:eh_wait.\n");
793 return ret;
794 }
795
796 while (CMD_SP(cmd) && wait_iter--) {
797 msleep(ABORT_POLLING_PERIOD);
798 }
799 if (CMD_SP(cmd))
800 ret = QLA_FUNCTION_FAILED;
801
802 return ret;
803 }
804
805 /*
806 * qla2x00_wait_for_hba_online
807 * Wait till the HBA is online after going through
808 * <= MAX_RETRIES_OF_ISP_ABORT or
809 * finally HBA is disabled ie marked offline
810 *
811 * Input:
812 * ha - pointer to host adapter structure
813 *
814 * Note:
815 * Does context switching-Release SPIN_LOCK
816 * (if any) before calling this routine.
817 *
818 * Return:
819 * Success (Adapter is online) : 0
820 * Failed (Adapter is offline/disabled) : 1
821 */
822 int
823 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
824 {
825 int return_status;
826 unsigned long wait_online;
827 struct qla_hw_data *ha = vha->hw;
828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
829
830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
834 ha->dpc_active) && time_before(jiffies, wait_online)) {
835
836 msleep(1000);
837 }
838 if (base_vha->flags.online)
839 return_status = QLA_SUCCESS;
840 else
841 return_status = QLA_FUNCTION_FAILED;
842
843 return (return_status);
844 }
845
846 /*
847 * qla2x00_wait_for_reset_ready
848 * Wait till the HBA is online after going through
849 * <= MAX_RETRIES_OF_ISP_ABORT or
850 * finally HBA is disabled ie marked offline or flash
851 * operations are in progress.
852 *
853 * Input:
854 * ha - pointer to host adapter structure
855 *
856 * Note:
857 * Does context switching-Release SPIN_LOCK
858 * (if any) before calling this routine.
859 *
860 * Return:
861 * Success (Adapter is online/no flash ops) : 0
862 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
863 */
864 static int
865 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
866 {
867 int return_status;
868 unsigned long wait_online;
869 struct qla_hw_data *ha = vha->hw;
870 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
871
872 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
873 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
874 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
875 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
876 ha->optrom_state != QLA_SWAITING ||
877 ha->dpc_active) && time_before(jiffies, wait_online))
878 msleep(1000);
879
880 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
881 return_status = QLA_SUCCESS;
882 else
883 return_status = QLA_FUNCTION_FAILED;
884
885 ql_dbg(ql_dbg_taskm, vha, 0x8019,
886 "%s return status=%d.\n", __func__, return_status);
887
888 return return_status;
889 }
890
891 int
892 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
893 {
894 int return_status;
895 unsigned long wait_reset;
896 struct qla_hw_data *ha = vha->hw;
897 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
898
899 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
900 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
901 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
902 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
903 ha->dpc_active) && time_before(jiffies, wait_reset)) {
904
905 msleep(1000);
906
907 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
908 ha->flags.chip_reset_done)
909 break;
910 }
911 if (ha->flags.chip_reset_done)
912 return_status = QLA_SUCCESS;
913 else
914 return_status = QLA_FUNCTION_FAILED;
915
916 return return_status;
917 }
918
919 static void
920 sp_get(struct srb *sp)
921 {
922 atomic_inc(&sp->ref_count);
923 }
924
925 /**************************************************************************
926 * qla2xxx_eh_abort
927 *
928 * Description:
929 * The abort function will abort the specified command.
930 *
931 * Input:
932 * cmd = Linux SCSI command packet to be aborted.
933 *
934 * Returns:
935 * Either SUCCESS or FAILED.
936 *
937 * Note:
938 * Only return FAILED if command not returned by firmware.
939 **************************************************************************/
940 static int
941 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
942 {
943 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
944 srb_t *sp;
945 int ret;
946 unsigned int id, lun;
947 unsigned long flags;
948 int wait = 0;
949 struct qla_hw_data *ha = vha->hw;
950
951 if (!CMD_SP(cmd))
952 return SUCCESS;
953
954 ret = fc_block_scsi_eh(cmd);
955 if (ret != 0)
956 return ret;
957 ret = SUCCESS;
958
959 id = cmd->device->id;
960 lun = cmd->device->lun;
961
962 spin_lock_irqsave(&ha->hardware_lock, flags);
963 sp = (srb_t *) CMD_SP(cmd);
964 if (!sp) {
965 spin_unlock_irqrestore(&ha->hardware_lock, flags);
966 return SUCCESS;
967 }
968
969 ql_dbg(ql_dbg_taskm, vha, 0x8002,
970 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
971 vha->host_no, id, lun, sp, cmd);
972
973 /* Get a reference to the sp and drop the lock.*/
974 sp_get(sp);
975
976 spin_unlock_irqrestore(&ha->hardware_lock, flags);
977 if (ha->isp_ops->abort_command(sp)) {
978 ret = FAILED;
979 ql_dbg(ql_dbg_taskm, vha, 0x8003,
980 "Abort command mbx failed cmd=%p.\n", cmd);
981 } else {
982 ql_dbg(ql_dbg_taskm, vha, 0x8004,
983 "Abort command mbx success cmd=%p.\n", cmd);
984 wait = 1;
985 }
986
987 spin_lock_irqsave(&ha->hardware_lock, flags);
988 sp->done(ha, sp, 0);
989 spin_unlock_irqrestore(&ha->hardware_lock, flags);
990
991 /* Did the command return during mailbox execution? */
992 if (ret == FAILED && !CMD_SP(cmd))
993 ret = SUCCESS;
994
995 /* Wait for the command to be returned. */
996 if (wait) {
997 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
998 ql_log(ql_log_warn, vha, 0x8006,
999 "Abort handler timed out cmd=%p.\n", cmd);
1000 ret = FAILED;
1001 }
1002 }
1003
1004 ql_log(ql_log_info, vha, 0x801c,
1005 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1006 vha->host_no, id, lun, wait, ret);
1007
1008 return ret;
1009 }
1010
1011 int
1012 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1013 unsigned int l, enum nexus_wait_type type)
1014 {
1015 int cnt, match, status;
1016 unsigned long flags;
1017 struct qla_hw_data *ha = vha->hw;
1018 struct req_que *req;
1019 srb_t *sp;
1020 struct scsi_cmnd *cmd;
1021
1022 status = QLA_SUCCESS;
1023
1024 spin_lock_irqsave(&ha->hardware_lock, flags);
1025 req = vha->req;
1026 for (cnt = 1; status == QLA_SUCCESS &&
1027 cnt < req->num_outstanding_cmds; cnt++) {
1028 sp = req->outstanding_cmds[cnt];
1029 if (!sp)
1030 continue;
1031 if (sp->type != SRB_SCSI_CMD)
1032 continue;
1033 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1034 continue;
1035 match = 0;
1036 cmd = GET_CMD_SP(sp);
1037 switch (type) {
1038 case WAIT_HOST:
1039 match = 1;
1040 break;
1041 case WAIT_TARGET:
1042 match = cmd->device->id == t;
1043 break;
1044 case WAIT_LUN:
1045 match = (cmd->device->id == t &&
1046 cmd->device->lun == l);
1047 break;
1048 }
1049 if (!match)
1050 continue;
1051
1052 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1053 status = qla2x00_eh_wait_on_command(cmd);
1054 spin_lock_irqsave(&ha->hardware_lock, flags);
1055 }
1056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1057
1058 return status;
1059 }
1060
1061 static char *reset_errors[] = {
1062 "HBA not online",
1063 "HBA not ready",
1064 "Task management failed",
1065 "Waiting for command completions",
1066 };
1067
1068 static int
1069 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1070 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1071 {
1072 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1073 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1074 int err;
1075
1076 if (!fcport) {
1077 return FAILED;
1078 }
1079
1080 err = fc_block_scsi_eh(cmd);
1081 if (err != 0)
1082 return err;
1083
1084 ql_log(ql_log_info, vha, 0x8009,
1085 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
1086 cmd->device->id, cmd->device->lun, cmd);
1087
1088 err = 0;
1089 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1090 ql_log(ql_log_warn, vha, 0x800a,
1091 "Wait for hba online failed for cmd=%p.\n", cmd);
1092 goto eh_reset_failed;
1093 }
1094 err = 2;
1095 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1096 != QLA_SUCCESS) {
1097 ql_log(ql_log_warn, vha, 0x800c,
1098 "do_reset failed for cmd=%p.\n", cmd);
1099 goto eh_reset_failed;
1100 }
1101 err = 3;
1102 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1103 cmd->device->lun, type) != QLA_SUCCESS) {
1104 ql_log(ql_log_warn, vha, 0x800d,
1105 "wait for pending cmds failed for cmd=%p.\n", cmd);
1106 goto eh_reset_failed;
1107 }
1108
1109 ql_log(ql_log_info, vha, 0x800e,
1110 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1111 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1112
1113 return SUCCESS;
1114
1115 eh_reset_failed:
1116 ql_log(ql_log_info, vha, 0x800f,
1117 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1118 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1119 cmd);
1120 return FAILED;
1121 }
1122
1123 static int
1124 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1125 {
1126 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1127 struct qla_hw_data *ha = vha->hw;
1128
1129 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1130 ha->isp_ops->lun_reset);
1131 }
1132
1133 static int
1134 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1135 {
1136 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1137 struct qla_hw_data *ha = vha->hw;
1138
1139 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1140 ha->isp_ops->target_reset);
1141 }
1142
1143 /**************************************************************************
1144 * qla2xxx_eh_bus_reset
1145 *
1146 * Description:
1147 * The bus reset function will reset the bus and abort any executing
1148 * commands.
1149 *
1150 * Input:
1151 * cmd = Linux SCSI command packet of the command that cause the
1152 * bus reset.
1153 *
1154 * Returns:
1155 * SUCCESS/FAILURE (defined as macro in scsi.h).
1156 *
1157 **************************************************************************/
1158 static int
1159 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1160 {
1161 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1162 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1163 int ret = FAILED;
1164 unsigned int id, lun;
1165
1166 id = cmd->device->id;
1167 lun = cmd->device->lun;
1168
1169 if (!fcport) {
1170 return ret;
1171 }
1172
1173 ret = fc_block_scsi_eh(cmd);
1174 if (ret != 0)
1175 return ret;
1176 ret = FAILED;
1177
1178 ql_log(ql_log_info, vha, 0x8012,
1179 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1180
1181 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1182 ql_log(ql_log_fatal, vha, 0x8013,
1183 "Wait for hba online failed board disabled.\n");
1184 goto eh_bus_reset_done;
1185 }
1186
1187 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1188 ret = SUCCESS;
1189
1190 if (ret == FAILED)
1191 goto eh_bus_reset_done;
1192
1193 /* Flush outstanding commands. */
1194 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1195 QLA_SUCCESS) {
1196 ql_log(ql_log_warn, vha, 0x8014,
1197 "Wait for pending commands failed.\n");
1198 ret = FAILED;
1199 }
1200
1201 eh_bus_reset_done:
1202 ql_log(ql_log_warn, vha, 0x802b,
1203 "BUS RESET %s nexus=%ld:%d:%d.\n",
1204 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1205
1206 return ret;
1207 }
1208
1209 /**************************************************************************
1210 * qla2xxx_eh_host_reset
1211 *
1212 * Description:
1213 * The reset function will reset the Adapter.
1214 *
1215 * Input:
1216 * cmd = Linux SCSI command packet of the command that cause the
1217 * adapter reset.
1218 *
1219 * Returns:
1220 * Either SUCCESS or FAILED.
1221 *
1222 * Note:
1223 **************************************************************************/
1224 static int
1225 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1226 {
1227 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1228 struct qla_hw_data *ha = vha->hw;
1229 int ret = FAILED;
1230 unsigned int id, lun;
1231 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1232
1233 id = cmd->device->id;
1234 lun = cmd->device->lun;
1235
1236 ql_log(ql_log_info, vha, 0x8018,
1237 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1238
1239 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
1240 goto eh_host_reset_lock;
1241
1242 if (vha != base_vha) {
1243 if (qla2x00_vp_abort_isp(vha))
1244 goto eh_host_reset_lock;
1245 } else {
1246 if (IS_P3P_TYPE(vha->hw)) {
1247 if (!qla82xx_fcoe_ctx_reset(vha)) {
1248 /* Ctx reset success */
1249 ret = SUCCESS;
1250 goto eh_host_reset_lock;
1251 }
1252 /* fall thru if ctx reset failed */
1253 }
1254 if (ha->wq)
1255 flush_workqueue(ha->wq);
1256
1257 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1258 if (ha->isp_ops->abort_isp(base_vha)) {
1259 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1260 /* failed. schedule dpc to try */
1261 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1262
1263 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1264 ql_log(ql_log_warn, vha, 0x802a,
1265 "wait for hba online failed.\n");
1266 goto eh_host_reset_lock;
1267 }
1268 }
1269 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1270 }
1271
1272 /* Waiting for command to be returned to OS.*/
1273 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1274 QLA_SUCCESS)
1275 ret = SUCCESS;
1276
1277 eh_host_reset_lock:
1278 ql_log(ql_log_info, vha, 0x8017,
1279 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1280 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1281
1282 return ret;
1283 }
1284
1285 /*
1286 * qla2x00_loop_reset
1287 * Issue loop reset.
1288 *
1289 * Input:
1290 * ha = adapter block pointer.
1291 *
1292 * Returns:
1293 * 0 = success
1294 */
1295 int
1296 qla2x00_loop_reset(scsi_qla_host_t *vha)
1297 {
1298 int ret;
1299 struct fc_port *fcport;
1300 struct qla_hw_data *ha = vha->hw;
1301
1302 if (IS_QLAFX00(ha)) {
1303 return qlafx00_loop_reset(vha);
1304 }
1305
1306 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1307 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1308 if (fcport->port_type != FCT_TARGET)
1309 continue;
1310
1311 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1312 if (ret != QLA_SUCCESS) {
1313 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1314 "Bus Reset failed: Reset=%d "
1315 "d_id=%x.\n", ret, fcport->d_id.b24);
1316 }
1317 }
1318 }
1319
1320
1321 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1322 atomic_set(&vha->loop_state, LOOP_DOWN);
1323 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1324 qla2x00_mark_all_devices_lost(vha, 0);
1325 ret = qla2x00_full_login_lip(vha);
1326 if (ret != QLA_SUCCESS) {
1327 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1328 "full_login_lip=%d.\n", ret);
1329 }
1330 }
1331
1332 if (ha->flags.enable_lip_reset) {
1333 ret = qla2x00_lip_reset(vha);
1334 if (ret != QLA_SUCCESS)
1335 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1336 "lip_reset failed (%d).\n", ret);
1337 }
1338
1339 /* Issue marker command only when we are going to start the I/O */
1340 vha->marker_needed = 1;
1341
1342 return QLA_SUCCESS;
1343 }
1344
1345 void
1346 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1347 {
1348 int que, cnt;
1349 unsigned long flags;
1350 srb_t *sp;
1351 struct qla_hw_data *ha = vha->hw;
1352 struct req_que *req;
1353
1354 spin_lock_irqsave(&ha->hardware_lock, flags);
1355 for (que = 0; que < ha->max_req_queues; que++) {
1356 req = ha->req_q_map[que];
1357 if (!req)
1358 continue;
1359 if (!req->outstanding_cmds)
1360 continue;
1361 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1362 sp = req->outstanding_cmds[cnt];
1363 if (sp) {
1364 req->outstanding_cmds[cnt] = NULL;
1365 sp->done(vha, sp, res);
1366 }
1367 }
1368 }
1369 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1370 }
1371
1372 static int
1373 qla2xxx_slave_alloc(struct scsi_device *sdev)
1374 {
1375 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1376
1377 if (!rport || fc_remote_port_chkready(rport))
1378 return -ENXIO;
1379
1380 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1381
1382 return 0;
1383 }
1384
1385 static int
1386 qla2xxx_slave_configure(struct scsi_device *sdev)
1387 {
1388 scsi_qla_host_t *vha = shost_priv(sdev->host);
1389 struct req_que *req = vha->req;
1390
1391 if (IS_T10_PI_CAPABLE(vha->hw))
1392 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1393
1394 if (sdev->tagged_supported)
1395 scsi_activate_tcq(sdev, req->max_q_depth);
1396 else
1397 scsi_deactivate_tcq(sdev, req->max_q_depth);
1398 return 0;
1399 }
1400
1401 static void
1402 qla2xxx_slave_destroy(struct scsi_device *sdev)
1403 {
1404 sdev->hostdata = NULL;
1405 }
1406
1407 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1408 {
1409 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1410
1411 if (!scsi_track_queue_full(sdev, qdepth))
1412 return;
1413
1414 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1415 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1416 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1417 }
1418
1419 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1420 {
1421 fc_port_t *fcport = sdev->hostdata;
1422 struct scsi_qla_host *vha = fcport->vha;
1423 struct req_que *req = NULL;
1424
1425 req = vha->req;
1426 if (!req)
1427 return;
1428
1429 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1430 return;
1431
1432 if (sdev->ordered_tags)
1433 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1434 else
1435 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1436
1437 ql_dbg(ql_dbg_io, vha, 0x302a,
1438 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1439 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1440 }
1441
1442 static int
1443 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1444 {
1445 switch (reason) {
1446 case SCSI_QDEPTH_DEFAULT:
1447 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1448 break;
1449 case SCSI_QDEPTH_QFULL:
1450 qla2x00_handle_queue_full(sdev, qdepth);
1451 break;
1452 case SCSI_QDEPTH_RAMP_UP:
1453 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1454 break;
1455 default:
1456 return -EOPNOTSUPP;
1457 }
1458
1459 return sdev->queue_depth;
1460 }
1461
1462 static int
1463 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1464 {
1465 if (sdev->tagged_supported) {
1466 scsi_set_tag_type(sdev, tag_type);
1467 if (tag_type)
1468 scsi_activate_tcq(sdev, sdev->queue_depth);
1469 else
1470 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1471 } else
1472 tag_type = 0;
1473
1474 return tag_type;
1475 }
1476
1477 static void
1478 qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1479 {
1480 scsi_qla_host_t *vp;
1481 struct Scsi_Host *shost;
1482 struct scsi_device *sdev;
1483 struct qla_hw_data *ha = vha->hw;
1484 unsigned long flags;
1485
1486 ha->host_last_rampdown_time = jiffies;
1487
1488 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1489 return;
1490
1491 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1492 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1493 else
1494 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1495
1496 /*
1497 * Geometrically ramp down the queue depth for all devices on this
1498 * adapter
1499 */
1500 spin_lock_irqsave(&ha->vport_slock, flags);
1501 list_for_each_entry(vp, &ha->vp_list, list) {
1502 shost = vp->host;
1503 shost_for_each_device(sdev, shost) {
1504 if (sdev->queue_depth > shost->cmd_per_lun) {
1505 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1506 continue;
1507 ql_dbg(ql_dbg_io, vp, 0x3031,
1508 "%ld:%d:%d: Ramping down queue depth to %d",
1509 vp->host_no, sdev->id, sdev->lun,
1510 ha->cfg_lun_q_depth);
1511 qla2x00_change_queue_depth(sdev,
1512 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1513 }
1514 }
1515 }
1516 spin_unlock_irqrestore(&ha->vport_slock, flags);
1517
1518 return;
1519 }
1520
1521 static void
1522 qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1523 {
1524 scsi_qla_host_t *vp;
1525 struct Scsi_Host *shost;
1526 struct scsi_device *sdev;
1527 struct qla_hw_data *ha = vha->hw;
1528 unsigned long flags;
1529
1530 ha->host_last_rampup_time = jiffies;
1531 ha->cfg_lun_q_depth++;
1532
1533 /*
1534 * Linearly ramp up the queue depth for all devices on this
1535 * adapter
1536 */
1537 spin_lock_irqsave(&ha->vport_slock, flags);
1538 list_for_each_entry(vp, &ha->vp_list, list) {
1539 shost = vp->host;
1540 shost_for_each_device(sdev, shost) {
1541 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1542 continue;
1543 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1544 SCSI_QDEPTH_RAMP_UP);
1545 }
1546 }
1547 spin_unlock_irqrestore(&ha->vport_slock, flags);
1548
1549 return;
1550 }
1551
1552 /**
1553 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1554 * @ha: HA context
1555 *
1556 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1557 * supported addressing method.
1558 */
1559 static void
1560 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1561 {
1562 /* Assume a 32bit DMA mask. */
1563 ha->flags.enable_64bit_addressing = 0;
1564
1565 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1566 /* Any upper-dword bits set? */
1567 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1568 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1569 /* Ok, a 64bit DMA mask is applicable. */
1570 ha->flags.enable_64bit_addressing = 1;
1571 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1572 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1573 return;
1574 }
1575 }
1576
1577 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1578 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1579 }
1580
1581 static void
1582 qla2x00_enable_intrs(struct qla_hw_data *ha)
1583 {
1584 unsigned long flags = 0;
1585 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1586
1587 spin_lock_irqsave(&ha->hardware_lock, flags);
1588 ha->interrupts_on = 1;
1589 /* enable risc and host interrupts */
1590 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1591 RD_REG_WORD(&reg->ictrl);
1592 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1593
1594 }
1595
1596 static void
1597 qla2x00_disable_intrs(struct qla_hw_data *ha)
1598 {
1599 unsigned long flags = 0;
1600 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1601
1602 spin_lock_irqsave(&ha->hardware_lock, flags);
1603 ha->interrupts_on = 0;
1604 /* disable risc and host interrupts */
1605 WRT_REG_WORD(&reg->ictrl, 0);
1606 RD_REG_WORD(&reg->ictrl);
1607 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1608 }
1609
1610 static void
1611 qla24xx_enable_intrs(struct qla_hw_data *ha)
1612 {
1613 unsigned long flags = 0;
1614 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1615
1616 spin_lock_irqsave(&ha->hardware_lock, flags);
1617 ha->interrupts_on = 1;
1618 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1619 RD_REG_DWORD(&reg->ictrl);
1620 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1621 }
1622
1623 static void
1624 qla24xx_disable_intrs(struct qla_hw_data *ha)
1625 {
1626 unsigned long flags = 0;
1627 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1628
1629 if (IS_NOPOLLING_TYPE(ha))
1630 return;
1631 spin_lock_irqsave(&ha->hardware_lock, flags);
1632 ha->interrupts_on = 0;
1633 WRT_REG_DWORD(&reg->ictrl, 0);
1634 RD_REG_DWORD(&reg->ictrl);
1635 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1636 }
1637
1638 static int
1639 qla2x00_iospace_config(struct qla_hw_data *ha)
1640 {
1641 resource_size_t pio;
1642 uint16_t msix;
1643 int cpus;
1644
1645 if (pci_request_selected_regions(ha->pdev, ha->bars,
1646 QLA2XXX_DRIVER_NAME)) {
1647 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1648 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1649 pci_name(ha->pdev));
1650 goto iospace_error_exit;
1651 }
1652 if (!(ha->bars & 1))
1653 goto skip_pio;
1654
1655 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1656 pio = pci_resource_start(ha->pdev, 0);
1657 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1658 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1659 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1660 "Invalid pci I/O region size (%s).\n",
1661 pci_name(ha->pdev));
1662 pio = 0;
1663 }
1664 } else {
1665 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1666 "Region #0 no a PIO resource (%s).\n",
1667 pci_name(ha->pdev));
1668 pio = 0;
1669 }
1670 ha->pio_address = pio;
1671 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1672 "PIO address=%llu.\n",
1673 (unsigned long long)ha->pio_address);
1674
1675 skip_pio:
1676 /* Use MMIO operations for all accesses. */
1677 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1679 "Region #1 not an MMIO resource (%s), aborting.\n",
1680 pci_name(ha->pdev));
1681 goto iospace_error_exit;
1682 }
1683 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1684 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1685 "Invalid PCI mem region size (%s), aborting.\n",
1686 pci_name(ha->pdev));
1687 goto iospace_error_exit;
1688 }
1689
1690 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1691 if (!ha->iobase) {
1692 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1693 "Cannot remap MMIO (%s), aborting.\n",
1694 pci_name(ha->pdev));
1695 goto iospace_error_exit;
1696 }
1697
1698 /* Determine queue resources */
1699 ha->max_req_queues = ha->max_rsp_queues = 1;
1700 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1701 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1702 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1703 goto mqiobase_exit;
1704
1705 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1706 pci_resource_len(ha->pdev, 3));
1707 if (ha->mqiobase) {
1708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1709 "MQIO Base=%p.\n", ha->mqiobase);
1710 /* Read MSIX vector size of the board */
1711 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1712 ha->msix_count = msix;
1713 /* Max queues are bounded by available msix vectors */
1714 /* queue 0 uses two msix vectors */
1715 if (ql2xmultique_tag) {
1716 cpus = num_online_cpus();
1717 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1718 (cpus + 1) : (ha->msix_count - 1);
1719 ha->max_req_queues = 2;
1720 } else if (ql2xmaxqueues > 1) {
1721 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1722 QLA_MQ_SIZE : ql2xmaxqueues;
1723 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1724 "QoS mode set, max no of request queues:%d.\n",
1725 ha->max_req_queues);
1726 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1727 "QoS mode set, max no of request queues:%d.\n",
1728 ha->max_req_queues);
1729 }
1730 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1731 "MSI-X vector count: %d.\n", msix);
1732 } else
1733 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1734 "BAR 3 not enabled.\n");
1735
1736 mqiobase_exit:
1737 ha->msix_count = ha->max_rsp_queues + 1;
1738 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1739 "MSIX Count:%d.\n", ha->msix_count);
1740 return (0);
1741
1742 iospace_error_exit:
1743 return (-ENOMEM);
1744 }
1745
1746
1747 static int
1748 qla83xx_iospace_config(struct qla_hw_data *ha)
1749 {
1750 uint16_t msix;
1751 int cpus;
1752
1753 if (pci_request_selected_regions(ha->pdev, ha->bars,
1754 QLA2XXX_DRIVER_NAME)) {
1755 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1756 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1757 pci_name(ha->pdev));
1758
1759 goto iospace_error_exit;
1760 }
1761
1762 /* Use MMIO operations for all accesses. */
1763 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1764 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1765 "Invalid pci I/O region size (%s).\n",
1766 pci_name(ha->pdev));
1767 goto iospace_error_exit;
1768 }
1769 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1770 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1771 "Invalid PCI mem region size (%s), aborting\n",
1772 pci_name(ha->pdev));
1773 goto iospace_error_exit;
1774 }
1775
1776 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1777 if (!ha->iobase) {
1778 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1779 "Cannot remap MMIO (%s), aborting.\n",
1780 pci_name(ha->pdev));
1781 goto iospace_error_exit;
1782 }
1783
1784 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1785 /* 83XX 26XX always use MQ type access for queues
1786 * - mbar 2, a.k.a region 4 */
1787 ha->max_req_queues = ha->max_rsp_queues = 1;
1788 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1789 pci_resource_len(ha->pdev, 4));
1790
1791 if (!ha->mqiobase) {
1792 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1793 "BAR2/region4 not enabled\n");
1794 goto mqiobase_exit;
1795 }
1796
1797 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1798 pci_resource_len(ha->pdev, 2));
1799 if (ha->msixbase) {
1800 /* Read MSIX vector size of the board */
1801 pci_read_config_word(ha->pdev,
1802 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1803 ha->msix_count = msix;
1804 /* Max queues are bounded by available msix vectors */
1805 /* queue 0 uses two msix vectors */
1806 if (ql2xmultique_tag) {
1807 cpus = num_online_cpus();
1808 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1809 (cpus + 1) : (ha->msix_count - 1);
1810 ha->max_req_queues = 2;
1811 } else if (ql2xmaxqueues > 1) {
1812 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1813 QLA_MQ_SIZE : ql2xmaxqueues;
1814 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1815 "QoS mode set, max no of request queues:%d.\n",
1816 ha->max_req_queues);
1817 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1818 "QoS mode set, max no of request queues:%d.\n",
1819 ha->max_req_queues);
1820 }
1821 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1822 "MSI-X vector count: %d.\n", msix);
1823 } else
1824 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1825 "BAR 1 not enabled.\n");
1826
1827 mqiobase_exit:
1828 ha->msix_count = ha->max_rsp_queues + 1;
1829
1830 qlt_83xx_iospace_config(ha);
1831
1832 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1833 "MSIX Count:%d.\n", ha->msix_count);
1834 return 0;
1835
1836 iospace_error_exit:
1837 return -ENOMEM;
1838 }
1839
1840 static struct isp_operations qla2100_isp_ops = {
1841 .pci_config = qla2100_pci_config,
1842 .reset_chip = qla2x00_reset_chip,
1843 .chip_diag = qla2x00_chip_diag,
1844 .config_rings = qla2x00_config_rings,
1845 .reset_adapter = qla2x00_reset_adapter,
1846 .nvram_config = qla2x00_nvram_config,
1847 .update_fw_options = qla2x00_update_fw_options,
1848 .load_risc = qla2x00_load_risc,
1849 .pci_info_str = qla2x00_pci_info_str,
1850 .fw_version_str = qla2x00_fw_version_str,
1851 .intr_handler = qla2100_intr_handler,
1852 .enable_intrs = qla2x00_enable_intrs,
1853 .disable_intrs = qla2x00_disable_intrs,
1854 .abort_command = qla2x00_abort_command,
1855 .target_reset = qla2x00_abort_target,
1856 .lun_reset = qla2x00_lun_reset,
1857 .fabric_login = qla2x00_login_fabric,
1858 .fabric_logout = qla2x00_fabric_logout,
1859 .calc_req_entries = qla2x00_calc_iocbs_32,
1860 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1861 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1862 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1863 .read_nvram = qla2x00_read_nvram_data,
1864 .write_nvram = qla2x00_write_nvram_data,
1865 .fw_dump = qla2100_fw_dump,
1866 .beacon_on = NULL,
1867 .beacon_off = NULL,
1868 .beacon_blink = NULL,
1869 .read_optrom = qla2x00_read_optrom_data,
1870 .write_optrom = qla2x00_write_optrom_data,
1871 .get_flash_version = qla2x00_get_flash_version,
1872 .start_scsi = qla2x00_start_scsi,
1873 .abort_isp = qla2x00_abort_isp,
1874 .iospace_config = qla2x00_iospace_config,
1875 .initialize_adapter = qla2x00_initialize_adapter,
1876 };
1877
1878 static struct isp_operations qla2300_isp_ops = {
1879 .pci_config = qla2300_pci_config,
1880 .reset_chip = qla2x00_reset_chip,
1881 .chip_diag = qla2x00_chip_diag,
1882 .config_rings = qla2x00_config_rings,
1883 .reset_adapter = qla2x00_reset_adapter,
1884 .nvram_config = qla2x00_nvram_config,
1885 .update_fw_options = qla2x00_update_fw_options,
1886 .load_risc = qla2x00_load_risc,
1887 .pci_info_str = qla2x00_pci_info_str,
1888 .fw_version_str = qla2x00_fw_version_str,
1889 .intr_handler = qla2300_intr_handler,
1890 .enable_intrs = qla2x00_enable_intrs,
1891 .disable_intrs = qla2x00_disable_intrs,
1892 .abort_command = qla2x00_abort_command,
1893 .target_reset = qla2x00_abort_target,
1894 .lun_reset = qla2x00_lun_reset,
1895 .fabric_login = qla2x00_login_fabric,
1896 .fabric_logout = qla2x00_fabric_logout,
1897 .calc_req_entries = qla2x00_calc_iocbs_32,
1898 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1899 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1900 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1901 .read_nvram = qla2x00_read_nvram_data,
1902 .write_nvram = qla2x00_write_nvram_data,
1903 .fw_dump = qla2300_fw_dump,
1904 .beacon_on = qla2x00_beacon_on,
1905 .beacon_off = qla2x00_beacon_off,
1906 .beacon_blink = qla2x00_beacon_blink,
1907 .read_optrom = qla2x00_read_optrom_data,
1908 .write_optrom = qla2x00_write_optrom_data,
1909 .get_flash_version = qla2x00_get_flash_version,
1910 .start_scsi = qla2x00_start_scsi,
1911 .abort_isp = qla2x00_abort_isp,
1912 .iospace_config = qla2x00_iospace_config,
1913 .initialize_adapter = qla2x00_initialize_adapter,
1914 };
1915
1916 static struct isp_operations qla24xx_isp_ops = {
1917 .pci_config = qla24xx_pci_config,
1918 .reset_chip = qla24xx_reset_chip,
1919 .chip_diag = qla24xx_chip_diag,
1920 .config_rings = qla24xx_config_rings,
1921 .reset_adapter = qla24xx_reset_adapter,
1922 .nvram_config = qla24xx_nvram_config,
1923 .update_fw_options = qla24xx_update_fw_options,
1924 .load_risc = qla24xx_load_risc,
1925 .pci_info_str = qla24xx_pci_info_str,
1926 .fw_version_str = qla24xx_fw_version_str,
1927 .intr_handler = qla24xx_intr_handler,
1928 .enable_intrs = qla24xx_enable_intrs,
1929 .disable_intrs = qla24xx_disable_intrs,
1930 .abort_command = qla24xx_abort_command,
1931 .target_reset = qla24xx_abort_target,
1932 .lun_reset = qla24xx_lun_reset,
1933 .fabric_login = qla24xx_login_fabric,
1934 .fabric_logout = qla24xx_fabric_logout,
1935 .calc_req_entries = NULL,
1936 .build_iocbs = NULL,
1937 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1938 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1939 .read_nvram = qla24xx_read_nvram_data,
1940 .write_nvram = qla24xx_write_nvram_data,
1941 .fw_dump = qla24xx_fw_dump,
1942 .beacon_on = qla24xx_beacon_on,
1943 .beacon_off = qla24xx_beacon_off,
1944 .beacon_blink = qla24xx_beacon_blink,
1945 .read_optrom = qla24xx_read_optrom_data,
1946 .write_optrom = qla24xx_write_optrom_data,
1947 .get_flash_version = qla24xx_get_flash_version,
1948 .start_scsi = qla24xx_start_scsi,
1949 .abort_isp = qla2x00_abort_isp,
1950 .iospace_config = qla2x00_iospace_config,
1951 .initialize_adapter = qla2x00_initialize_adapter,
1952 };
1953
1954 static struct isp_operations qla25xx_isp_ops = {
1955 .pci_config = qla25xx_pci_config,
1956 .reset_chip = qla24xx_reset_chip,
1957 .chip_diag = qla24xx_chip_diag,
1958 .config_rings = qla24xx_config_rings,
1959 .reset_adapter = qla24xx_reset_adapter,
1960 .nvram_config = qla24xx_nvram_config,
1961 .update_fw_options = qla24xx_update_fw_options,
1962 .load_risc = qla24xx_load_risc,
1963 .pci_info_str = qla24xx_pci_info_str,
1964 .fw_version_str = qla24xx_fw_version_str,
1965 .intr_handler = qla24xx_intr_handler,
1966 .enable_intrs = qla24xx_enable_intrs,
1967 .disable_intrs = qla24xx_disable_intrs,
1968 .abort_command = qla24xx_abort_command,
1969 .target_reset = qla24xx_abort_target,
1970 .lun_reset = qla24xx_lun_reset,
1971 .fabric_login = qla24xx_login_fabric,
1972 .fabric_logout = qla24xx_fabric_logout,
1973 .calc_req_entries = NULL,
1974 .build_iocbs = NULL,
1975 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1976 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1977 .read_nvram = qla25xx_read_nvram_data,
1978 .write_nvram = qla25xx_write_nvram_data,
1979 .fw_dump = qla25xx_fw_dump,
1980 .beacon_on = qla24xx_beacon_on,
1981 .beacon_off = qla24xx_beacon_off,
1982 .beacon_blink = qla24xx_beacon_blink,
1983 .read_optrom = qla25xx_read_optrom_data,
1984 .write_optrom = qla24xx_write_optrom_data,
1985 .get_flash_version = qla24xx_get_flash_version,
1986 .start_scsi = qla24xx_dif_start_scsi,
1987 .abort_isp = qla2x00_abort_isp,
1988 .iospace_config = qla2x00_iospace_config,
1989 .initialize_adapter = qla2x00_initialize_adapter,
1990 };
1991
1992 static struct isp_operations qla81xx_isp_ops = {
1993 .pci_config = qla25xx_pci_config,
1994 .reset_chip = qla24xx_reset_chip,
1995 .chip_diag = qla24xx_chip_diag,
1996 .config_rings = qla24xx_config_rings,
1997 .reset_adapter = qla24xx_reset_adapter,
1998 .nvram_config = qla81xx_nvram_config,
1999 .update_fw_options = qla81xx_update_fw_options,
2000 .load_risc = qla81xx_load_risc,
2001 .pci_info_str = qla24xx_pci_info_str,
2002 .fw_version_str = qla24xx_fw_version_str,
2003 .intr_handler = qla24xx_intr_handler,
2004 .enable_intrs = qla24xx_enable_intrs,
2005 .disable_intrs = qla24xx_disable_intrs,
2006 .abort_command = qla24xx_abort_command,
2007 .target_reset = qla24xx_abort_target,
2008 .lun_reset = qla24xx_lun_reset,
2009 .fabric_login = qla24xx_login_fabric,
2010 .fabric_logout = qla24xx_fabric_logout,
2011 .calc_req_entries = NULL,
2012 .build_iocbs = NULL,
2013 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2014 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2015 .read_nvram = NULL,
2016 .write_nvram = NULL,
2017 .fw_dump = qla81xx_fw_dump,
2018 .beacon_on = qla24xx_beacon_on,
2019 .beacon_off = qla24xx_beacon_off,
2020 .beacon_blink = qla83xx_beacon_blink,
2021 .read_optrom = qla25xx_read_optrom_data,
2022 .write_optrom = qla24xx_write_optrom_data,
2023 .get_flash_version = qla24xx_get_flash_version,
2024 .start_scsi = qla24xx_dif_start_scsi,
2025 .abort_isp = qla2x00_abort_isp,
2026 .iospace_config = qla2x00_iospace_config,
2027 .initialize_adapter = qla2x00_initialize_adapter,
2028 };
2029
2030 static struct isp_operations qla82xx_isp_ops = {
2031 .pci_config = qla82xx_pci_config,
2032 .reset_chip = qla82xx_reset_chip,
2033 .chip_diag = qla24xx_chip_diag,
2034 .config_rings = qla82xx_config_rings,
2035 .reset_adapter = qla24xx_reset_adapter,
2036 .nvram_config = qla81xx_nvram_config,
2037 .update_fw_options = qla24xx_update_fw_options,
2038 .load_risc = qla82xx_load_risc,
2039 .pci_info_str = qla24xx_pci_info_str,
2040 .fw_version_str = qla24xx_fw_version_str,
2041 .intr_handler = qla82xx_intr_handler,
2042 .enable_intrs = qla82xx_enable_intrs,
2043 .disable_intrs = qla82xx_disable_intrs,
2044 .abort_command = qla24xx_abort_command,
2045 .target_reset = qla24xx_abort_target,
2046 .lun_reset = qla24xx_lun_reset,
2047 .fabric_login = qla24xx_login_fabric,
2048 .fabric_logout = qla24xx_fabric_logout,
2049 .calc_req_entries = NULL,
2050 .build_iocbs = NULL,
2051 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2052 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2053 .read_nvram = qla24xx_read_nvram_data,
2054 .write_nvram = qla24xx_write_nvram_data,
2055 .fw_dump = qla24xx_fw_dump,
2056 .beacon_on = qla82xx_beacon_on,
2057 .beacon_off = qla82xx_beacon_off,
2058 .beacon_blink = NULL,
2059 .read_optrom = qla82xx_read_optrom_data,
2060 .write_optrom = qla82xx_write_optrom_data,
2061 .get_flash_version = qla82xx_get_flash_version,
2062 .start_scsi = qla82xx_start_scsi,
2063 .abort_isp = qla82xx_abort_isp,
2064 .iospace_config = qla82xx_iospace_config,
2065 .initialize_adapter = qla2x00_initialize_adapter,
2066 };
2067
2068 static struct isp_operations qla8044_isp_ops = {
2069 .pci_config = qla82xx_pci_config,
2070 .reset_chip = qla82xx_reset_chip,
2071 .chip_diag = qla24xx_chip_diag,
2072 .config_rings = qla82xx_config_rings,
2073 .reset_adapter = qla24xx_reset_adapter,
2074 .nvram_config = qla81xx_nvram_config,
2075 .update_fw_options = qla24xx_update_fw_options,
2076 .load_risc = qla82xx_load_risc,
2077 .pci_info_str = qla24xx_pci_info_str,
2078 .fw_version_str = qla24xx_fw_version_str,
2079 .intr_handler = qla8044_intr_handler,
2080 .enable_intrs = qla82xx_enable_intrs,
2081 .disable_intrs = qla82xx_disable_intrs,
2082 .abort_command = qla24xx_abort_command,
2083 .target_reset = qla24xx_abort_target,
2084 .lun_reset = qla24xx_lun_reset,
2085 .fabric_login = qla24xx_login_fabric,
2086 .fabric_logout = qla24xx_fabric_logout,
2087 .calc_req_entries = NULL,
2088 .build_iocbs = NULL,
2089 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2090 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2091 .read_nvram = NULL,
2092 .write_nvram = NULL,
2093 .fw_dump = qla24xx_fw_dump,
2094 .beacon_on = qla82xx_beacon_on,
2095 .beacon_off = qla82xx_beacon_off,
2096 .beacon_blink = NULL,
2097 .read_optrom = qla82xx_read_optrom_data,
2098 .write_optrom = qla8044_write_optrom_data,
2099 .get_flash_version = qla82xx_get_flash_version,
2100 .start_scsi = qla82xx_start_scsi,
2101 .abort_isp = qla8044_abort_isp,
2102 .iospace_config = qla82xx_iospace_config,
2103 .initialize_adapter = qla2x00_initialize_adapter,
2104 };
2105
2106 static struct isp_operations qla83xx_isp_ops = {
2107 .pci_config = qla25xx_pci_config,
2108 .reset_chip = qla24xx_reset_chip,
2109 .chip_diag = qla24xx_chip_diag,
2110 .config_rings = qla24xx_config_rings,
2111 .reset_adapter = qla24xx_reset_adapter,
2112 .nvram_config = qla81xx_nvram_config,
2113 .update_fw_options = qla81xx_update_fw_options,
2114 .load_risc = qla81xx_load_risc,
2115 .pci_info_str = qla24xx_pci_info_str,
2116 .fw_version_str = qla24xx_fw_version_str,
2117 .intr_handler = qla24xx_intr_handler,
2118 .enable_intrs = qla24xx_enable_intrs,
2119 .disable_intrs = qla24xx_disable_intrs,
2120 .abort_command = qla24xx_abort_command,
2121 .target_reset = qla24xx_abort_target,
2122 .lun_reset = qla24xx_lun_reset,
2123 .fabric_login = qla24xx_login_fabric,
2124 .fabric_logout = qla24xx_fabric_logout,
2125 .calc_req_entries = NULL,
2126 .build_iocbs = NULL,
2127 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2128 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2129 .read_nvram = NULL,
2130 .write_nvram = NULL,
2131 .fw_dump = qla83xx_fw_dump,
2132 .beacon_on = qla24xx_beacon_on,
2133 .beacon_off = qla24xx_beacon_off,
2134 .beacon_blink = qla83xx_beacon_blink,
2135 .read_optrom = qla25xx_read_optrom_data,
2136 .write_optrom = qla24xx_write_optrom_data,
2137 .get_flash_version = qla24xx_get_flash_version,
2138 .start_scsi = qla24xx_dif_start_scsi,
2139 .abort_isp = qla2x00_abort_isp,
2140 .iospace_config = qla83xx_iospace_config,
2141 .initialize_adapter = qla2x00_initialize_adapter,
2142 };
2143
2144 static struct isp_operations qlafx00_isp_ops = {
2145 .pci_config = qlafx00_pci_config,
2146 .reset_chip = qlafx00_soft_reset,
2147 .chip_diag = qlafx00_chip_diag,
2148 .config_rings = qlafx00_config_rings,
2149 .reset_adapter = qlafx00_soft_reset,
2150 .nvram_config = NULL,
2151 .update_fw_options = NULL,
2152 .load_risc = NULL,
2153 .pci_info_str = qlafx00_pci_info_str,
2154 .fw_version_str = qlafx00_fw_version_str,
2155 .intr_handler = qlafx00_intr_handler,
2156 .enable_intrs = qlafx00_enable_intrs,
2157 .disable_intrs = qlafx00_disable_intrs,
2158 .abort_command = qlafx00_abort_command,
2159 .target_reset = qlafx00_abort_target,
2160 .lun_reset = qlafx00_lun_reset,
2161 .fabric_login = NULL,
2162 .fabric_logout = NULL,
2163 .calc_req_entries = NULL,
2164 .build_iocbs = NULL,
2165 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2166 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2167 .read_nvram = qla24xx_read_nvram_data,
2168 .write_nvram = qla24xx_write_nvram_data,
2169 .fw_dump = NULL,
2170 .beacon_on = qla24xx_beacon_on,
2171 .beacon_off = qla24xx_beacon_off,
2172 .beacon_blink = NULL,
2173 .read_optrom = qla24xx_read_optrom_data,
2174 .write_optrom = qla24xx_write_optrom_data,
2175 .get_flash_version = qla24xx_get_flash_version,
2176 .start_scsi = qlafx00_start_scsi,
2177 .abort_isp = qlafx00_abort_isp,
2178 .iospace_config = qlafx00_iospace_config,
2179 .initialize_adapter = qlafx00_initialize_adapter,
2180 };
2181
2182 static inline void
2183 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2184 {
2185 ha->device_type = DT_EXTENDED_IDS;
2186 switch (ha->pdev->device) {
2187 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2188 ha->device_type |= DT_ISP2100;
2189 ha->device_type &= ~DT_EXTENDED_IDS;
2190 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2191 break;
2192 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2193 ha->device_type |= DT_ISP2200;
2194 ha->device_type &= ~DT_EXTENDED_IDS;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2196 break;
2197 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2198 ha->device_type |= DT_ISP2300;
2199 ha->device_type |= DT_ZIO_SUPPORTED;
2200 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2201 break;
2202 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2203 ha->device_type |= DT_ISP2312;
2204 ha->device_type |= DT_ZIO_SUPPORTED;
2205 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2206 break;
2207 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2208 ha->device_type |= DT_ISP2322;
2209 ha->device_type |= DT_ZIO_SUPPORTED;
2210 if (ha->pdev->subsystem_vendor == 0x1028 &&
2211 ha->pdev->subsystem_device == 0x0170)
2212 ha->device_type |= DT_OEM_001;
2213 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2214 break;
2215 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2216 ha->device_type |= DT_ISP6312;
2217 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2218 break;
2219 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2220 ha->device_type |= DT_ISP6322;
2221 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2222 break;
2223 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2224 ha->device_type |= DT_ISP2422;
2225 ha->device_type |= DT_ZIO_SUPPORTED;
2226 ha->device_type |= DT_FWI2;
2227 ha->device_type |= DT_IIDMA;
2228 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2229 break;
2230 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2231 ha->device_type |= DT_ISP2432;
2232 ha->device_type |= DT_ZIO_SUPPORTED;
2233 ha->device_type |= DT_FWI2;
2234 ha->device_type |= DT_IIDMA;
2235 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2236 break;
2237 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2238 ha->device_type |= DT_ISP8432;
2239 ha->device_type |= DT_ZIO_SUPPORTED;
2240 ha->device_type |= DT_FWI2;
2241 ha->device_type |= DT_IIDMA;
2242 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2243 break;
2244 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2245 ha->device_type |= DT_ISP5422;
2246 ha->device_type |= DT_FWI2;
2247 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2248 break;
2249 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2250 ha->device_type |= DT_ISP5432;
2251 ha->device_type |= DT_FWI2;
2252 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2253 break;
2254 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2255 ha->device_type |= DT_ISP2532;
2256 ha->device_type |= DT_ZIO_SUPPORTED;
2257 ha->device_type |= DT_FWI2;
2258 ha->device_type |= DT_IIDMA;
2259 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2260 break;
2261 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2262 ha->device_type |= DT_ISP8001;
2263 ha->device_type |= DT_ZIO_SUPPORTED;
2264 ha->device_type |= DT_FWI2;
2265 ha->device_type |= DT_IIDMA;
2266 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2267 break;
2268 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2269 ha->device_type |= DT_ISP8021;
2270 ha->device_type |= DT_ZIO_SUPPORTED;
2271 ha->device_type |= DT_FWI2;
2272 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2273 /* Initialize 82XX ISP flags */
2274 qla82xx_init_flags(ha);
2275 break;
2276 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2277 ha->device_type |= DT_ISP8044;
2278 ha->device_type |= DT_ZIO_SUPPORTED;
2279 ha->device_type |= DT_FWI2;
2280 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2281 /* Initialize 82XX ISP flags */
2282 qla82xx_init_flags(ha);
2283 break;
2284 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2285 ha->device_type |= DT_ISP2031;
2286 ha->device_type |= DT_ZIO_SUPPORTED;
2287 ha->device_type |= DT_FWI2;
2288 ha->device_type |= DT_IIDMA;
2289 ha->device_type |= DT_T10_PI;
2290 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2291 break;
2292 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2293 ha->device_type |= DT_ISP8031;
2294 ha->device_type |= DT_ZIO_SUPPORTED;
2295 ha->device_type |= DT_FWI2;
2296 ha->device_type |= DT_IIDMA;
2297 ha->device_type |= DT_T10_PI;
2298 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2299 break;
2300 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2301 ha->device_type |= DT_ISPFX00;
2302 break;
2303 }
2304
2305 if (IS_QLA82XX(ha))
2306 ha->port_no = !(ha->portnum & 1);
2307 else
2308 /* Get adapter physical port no from interrupt pin register. */
2309 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2310
2311 if (ha->port_no & 1)
2312 ha->flags.port0 = 1;
2313 else
2314 ha->flags.port0 = 0;
2315 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2316 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2317 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
2318 }
2319
2320 static void
2321 qla2xxx_scan_start(struct Scsi_Host *shost)
2322 {
2323 scsi_qla_host_t *vha = shost_priv(shost);
2324
2325 if (vha->hw->flags.running_gold_fw)
2326 return;
2327
2328 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2329 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2330 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2331 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2332 }
2333
2334 static int
2335 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2336 {
2337 scsi_qla_host_t *vha = shost_priv(shost);
2338
2339 if (!vha->host)
2340 return 1;
2341 if (time > vha->hw->loop_reset_delay * HZ)
2342 return 1;
2343
2344 return atomic_read(&vha->loop_state) == LOOP_READY;
2345 }
2346
2347 /*
2348 * PCI driver interface
2349 */
2350 static int
2351 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2352 {
2353 int ret = -ENODEV;
2354 struct Scsi_Host *host;
2355 scsi_qla_host_t *base_vha = NULL;
2356 struct qla_hw_data *ha;
2357 char pci_info[30];
2358 char fw_str[30], wq_name[30];
2359 struct scsi_host_template *sht;
2360 int bars, mem_only = 0;
2361 uint16_t req_length = 0, rsp_length = 0;
2362 struct req_que *req = NULL;
2363 struct rsp_que *rsp = NULL;
2364 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2365 sht = &qla2xxx_driver_template;
2366 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2367 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2368 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2369 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2370 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2371 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2372 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2373 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2374 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2375 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2376 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2377 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) {
2378 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2379 mem_only = 1;
2380 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2381 "Mem only adapter.\n");
2382 }
2383 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2384 "Bars=%d.\n", bars);
2385
2386 if (mem_only) {
2387 if (pci_enable_device_mem(pdev))
2388 goto probe_out;
2389 } else {
2390 if (pci_enable_device(pdev))
2391 goto probe_out;
2392 }
2393
2394 /* This may fail but that's ok */
2395 pci_enable_pcie_error_reporting(pdev);
2396
2397 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2398 if (!ha) {
2399 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2400 "Unable to allocate memory for ha.\n");
2401 goto probe_out;
2402 }
2403 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2404 "Memory allocated for ha=%p.\n", ha);
2405 ha->pdev = pdev;
2406 ha->tgt.enable_class_2 = ql2xenableclass2;
2407
2408 /* Clear our data area */
2409 ha->bars = bars;
2410 ha->mem_only = mem_only;
2411 spin_lock_init(&ha->hardware_lock);
2412 spin_lock_init(&ha->vport_slock);
2413 mutex_init(&ha->selflogin_lock);
2414
2415 /* Set ISP-type information. */
2416 qla2x00_set_isp_flags(ha);
2417
2418 /* Set EEH reset type to fundamental if required by hba */
2419 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2420 IS_QLA83XX(ha))
2421 pdev->needs_freset = 1;
2422
2423 ha->prev_topology = 0;
2424 ha->init_cb_size = sizeof(init_cb_t);
2425 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2426 ha->optrom_size = OPTROM_SIZE_2300;
2427 ha->cfg_lun_q_depth = ql2xmaxqdepth;
2428
2429 /* Assign ISP specific operations. */
2430 if (IS_QLA2100(ha)) {
2431 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2432 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2433 req_length = REQUEST_ENTRY_CNT_2100;
2434 rsp_length = RESPONSE_ENTRY_CNT_2100;
2435 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2436 ha->gid_list_info_size = 4;
2437 ha->flash_conf_off = ~0;
2438 ha->flash_data_off = ~0;
2439 ha->nvram_conf_off = ~0;
2440 ha->nvram_data_off = ~0;
2441 ha->isp_ops = &qla2100_isp_ops;
2442 } else if (IS_QLA2200(ha)) {
2443 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2444 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2445 req_length = REQUEST_ENTRY_CNT_2200;
2446 rsp_length = RESPONSE_ENTRY_CNT_2100;
2447 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2448 ha->gid_list_info_size = 4;
2449 ha->flash_conf_off = ~0;
2450 ha->flash_data_off = ~0;
2451 ha->nvram_conf_off = ~0;
2452 ha->nvram_data_off = ~0;
2453 ha->isp_ops = &qla2100_isp_ops;
2454 } else if (IS_QLA23XX(ha)) {
2455 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2456 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2457 req_length = REQUEST_ENTRY_CNT_2200;
2458 rsp_length = RESPONSE_ENTRY_CNT_2300;
2459 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2460 ha->gid_list_info_size = 6;
2461 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2462 ha->optrom_size = OPTROM_SIZE_2322;
2463 ha->flash_conf_off = ~0;
2464 ha->flash_data_off = ~0;
2465 ha->nvram_conf_off = ~0;
2466 ha->nvram_data_off = ~0;
2467 ha->isp_ops = &qla2300_isp_ops;
2468 } else if (IS_QLA24XX_TYPE(ha)) {
2469 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2470 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2471 req_length = REQUEST_ENTRY_CNT_24XX;
2472 rsp_length = RESPONSE_ENTRY_CNT_2300;
2473 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2474 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2475 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2476 ha->gid_list_info_size = 8;
2477 ha->optrom_size = OPTROM_SIZE_24XX;
2478 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2479 ha->isp_ops = &qla24xx_isp_ops;
2480 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2481 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2482 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2483 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2484 } else if (IS_QLA25XX(ha)) {
2485 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2486 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2487 req_length = REQUEST_ENTRY_CNT_24XX;
2488 rsp_length = RESPONSE_ENTRY_CNT_2300;
2489 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2490 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2491 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2492 ha->gid_list_info_size = 8;
2493 ha->optrom_size = OPTROM_SIZE_25XX;
2494 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2495 ha->isp_ops = &qla25xx_isp_ops;
2496 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2497 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2498 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2499 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2500 } else if (IS_QLA81XX(ha)) {
2501 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2502 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2503 req_length = REQUEST_ENTRY_CNT_24XX;
2504 rsp_length = RESPONSE_ENTRY_CNT_2300;
2505 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2506 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2507 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2508 ha->gid_list_info_size = 8;
2509 ha->optrom_size = OPTROM_SIZE_81XX;
2510 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2511 ha->isp_ops = &qla81xx_isp_ops;
2512 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2513 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2514 ha->nvram_conf_off = ~0;
2515 ha->nvram_data_off = ~0;
2516 } else if (IS_QLA82XX(ha)) {
2517 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2518 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2519 req_length = REQUEST_ENTRY_CNT_82XX;
2520 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2521 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2522 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2523 ha->gid_list_info_size = 8;
2524 ha->optrom_size = OPTROM_SIZE_82XX;
2525 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2526 ha->isp_ops = &qla82xx_isp_ops;
2527 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2528 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2529 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2530 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2531 } else if (IS_QLA8044(ha)) {
2532 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2533 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2534 req_length = REQUEST_ENTRY_CNT_82XX;
2535 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2536 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2537 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2538 ha->gid_list_info_size = 8;
2539 ha->optrom_size = OPTROM_SIZE_83XX;
2540 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2541 ha->isp_ops = &qla8044_isp_ops;
2542 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2543 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2544 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2545 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2546 } else if (IS_QLA83XX(ha)) {
2547 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2548 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2549 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2550 req_length = REQUEST_ENTRY_CNT_24XX;
2551 rsp_length = RESPONSE_ENTRY_CNT_2300;
2552 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2553 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2554 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2555 ha->gid_list_info_size = 8;
2556 ha->optrom_size = OPTROM_SIZE_83XX;
2557 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2558 ha->isp_ops = &qla83xx_isp_ops;
2559 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2560 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2561 ha->nvram_conf_off = ~0;
2562 ha->nvram_data_off = ~0;
2563 } else if (IS_QLAFX00(ha)) {
2564 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2565 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2566 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2567 req_length = REQUEST_ENTRY_CNT_FX00;
2568 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2569 ha->init_cb_size = sizeof(struct init_cb_fx);
2570 ha->isp_ops = &qlafx00_isp_ops;
2571 ha->port_down_retry_count = 30; /* default value */
2572 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2573 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2574 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2575 ha->mr.fw_hbt_en = 1;
2576 }
2577
2578 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2579 "mbx_count=%d, req_length=%d, "
2580 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2581 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2582 "max_fibre_devices=%d.\n",
2583 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2584 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2585 ha->nvram_npiv_size, ha->max_fibre_devices);
2586 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2587 "isp_ops=%p, flash_conf_off=%d, "
2588 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2589 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2590 ha->nvram_conf_off, ha->nvram_data_off);
2591
2592 /* Configure PCI I/O space */
2593 ret = ha->isp_ops->iospace_config(ha);
2594 if (ret)
2595 goto iospace_config_failed;
2596
2597 ql_log_pci(ql_log_info, pdev, 0x001d,
2598 "Found an ISP%04X irq %d iobase 0x%p.\n",
2599 pdev->device, pdev->irq, ha->iobase);
2600 mutex_init(&ha->vport_lock);
2601 init_completion(&ha->mbx_cmd_comp);
2602 complete(&ha->mbx_cmd_comp);
2603 init_completion(&ha->mbx_intr_comp);
2604 init_completion(&ha->dcbx_comp);
2605 init_completion(&ha->lb_portup_comp);
2606
2607 set_bit(0, (unsigned long *) ha->vp_idx_map);
2608
2609 qla2x00_config_dma_addressing(ha);
2610 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2611 "64 Bit addressing is %s.\n",
2612 ha->flags.enable_64bit_addressing ? "enable" :
2613 "disable");
2614 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2615 if (!ret) {
2616 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2617 "Failed to allocate memory for adapter, aborting.\n");
2618
2619 goto probe_hw_failed;
2620 }
2621
2622 req->max_q_depth = MAX_Q_DEPTH;
2623 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2624 req->max_q_depth = ql2xmaxqdepth;
2625
2626
2627 base_vha = qla2x00_create_host(sht, ha);
2628 if (!base_vha) {
2629 ret = -ENOMEM;
2630 qla2x00_mem_free(ha);
2631 qla2x00_free_req_que(ha, req);
2632 qla2x00_free_rsp_que(ha, rsp);
2633 goto probe_hw_failed;
2634 }
2635
2636 pci_set_drvdata(pdev, base_vha);
2637
2638 host = base_vha->host;
2639 base_vha->req = req;
2640 if (IS_QLAFX00(ha))
2641 host->can_queue = 1024;
2642 else
2643 host->can_queue = req->length + 128;
2644 if (IS_QLA2XXX_MIDTYPE(ha))
2645 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2646 else
2647 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2648 base_vha->vp_idx;
2649
2650 /* Setup fcport template structure. */
2651 ha->mr.fcport.vha = base_vha;
2652 ha->mr.fcport.port_type = FCT_UNKNOWN;
2653 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2654 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2655 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2656 ha->mr.fcport.scan_state = 1;
2657
2658 /* Set the SG table size based on ISP type */
2659 if (!IS_FWI2_CAPABLE(ha)) {
2660 if (IS_QLA2100(ha))
2661 host->sg_tablesize = 32;
2662 } else {
2663 if (!IS_QLA82XX(ha))
2664 host->sg_tablesize = QLA_SG_ALL;
2665 }
2666 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2667 "can_queue=%d, req=%p, "
2668 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2669 host->can_queue, base_vha->req,
2670 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2671 host->max_id = ha->max_fibre_devices;
2672 host->cmd_per_lun = 3;
2673 host->unique_id = host->host_no;
2674 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2675 host->max_cmd_len = 32;
2676 else
2677 host->max_cmd_len = MAX_CMDSZ;
2678 host->max_channel = MAX_BUSES - 1;
2679 host->max_lun = ql2xmaxlun;
2680 host->transportt = qla2xxx_transport_template;
2681 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2682
2683 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2684 "max_id=%d this_id=%d "
2685 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2686 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
2687 host->this_id, host->cmd_per_lun, host->unique_id,
2688 host->max_cmd_len, host->max_channel, host->max_lun,
2689 host->transportt, sht->vendor_id);
2690
2691 que_init:
2692 /* Alloc arrays of request and response ring ptrs */
2693 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2694 ql_log(ql_log_fatal, base_vha, 0x003d,
2695 "Failed to allocate memory for queue pointers..."
2696 "aborting.\n");
2697 goto probe_init_failed;
2698 }
2699
2700 qlt_probe_one_stage1(base_vha, ha);
2701
2702 /* Set up the irqs */
2703 ret = qla2x00_request_irqs(ha, rsp);
2704 if (ret)
2705 goto probe_init_failed;
2706
2707 pci_save_state(pdev);
2708
2709 /* Assign back pointers */
2710 rsp->req = req;
2711 req->rsp = rsp;
2712
2713 if (IS_QLAFX00(ha)) {
2714 ha->rsp_q_map[0] = rsp;
2715 ha->req_q_map[0] = req;
2716 set_bit(0, ha->req_qid_map);
2717 set_bit(0, ha->rsp_qid_map);
2718 }
2719
2720 /* FWI2-capable only. */
2721 req->req_q_in = &ha->iobase->isp24.req_q_in;
2722 req->req_q_out = &ha->iobase->isp24.req_q_out;
2723 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2724 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2725 if (ha->mqenable || IS_QLA83XX(ha)) {
2726 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2727 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2728 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2729 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2730 }
2731
2732 if (IS_QLAFX00(ha)) {
2733 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2734 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2735 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2736 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2737 }
2738
2739 if (IS_P3P_TYPE(ha)) {
2740 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2741 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2742 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2743 }
2744
2745 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2746 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2747 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2748 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2749 "req->req_q_in=%p req->req_q_out=%p "
2750 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2751 req->req_q_in, req->req_q_out,
2752 rsp->rsp_q_in, rsp->rsp_q_out);
2753 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2754 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2755 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2756 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2757 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2758 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2759
2760 if (ha->isp_ops->initialize_adapter(base_vha)) {
2761 ql_log(ql_log_fatal, base_vha, 0x00d6,
2762 "Failed to initialize adapter - Adapter flags %x.\n",
2763 base_vha->device_flags);
2764
2765 if (IS_QLA82XX(ha)) {
2766 qla82xx_idc_lock(ha);
2767 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2768 QLA8XXX_DEV_FAILED);
2769 qla82xx_idc_unlock(ha);
2770 ql_log(ql_log_fatal, base_vha, 0x00d7,
2771 "HW State: FAILED.\n");
2772 } else if (IS_QLA8044(ha)) {
2773 qla8044_idc_lock(ha);
2774 qla8044_wr_direct(base_vha,
2775 QLA8044_CRB_DEV_STATE_INDEX,
2776 QLA8XXX_DEV_FAILED);
2777 qla8044_idc_unlock(ha);
2778 ql_log(ql_log_fatal, base_vha, 0x0150,
2779 "HW State: FAILED.\n");
2780 }
2781
2782 ret = -ENODEV;
2783 goto probe_failed;
2784 }
2785
2786 if (ha->mqenable) {
2787 if (qla25xx_setup_mode(base_vha)) {
2788 ql_log(ql_log_warn, base_vha, 0x00ec,
2789 "Failed to create queues, falling back to single queue mode.\n");
2790 goto que_init;
2791 }
2792 }
2793
2794 if (ha->flags.running_gold_fw)
2795 goto skip_dpc;
2796
2797 /*
2798 * Startup the kernel thread for this host adapter
2799 */
2800 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2801 "%s_dpc", base_vha->host_str);
2802 if (IS_ERR(ha->dpc_thread)) {
2803 ql_log(ql_log_fatal, base_vha, 0x00ed,
2804 "Failed to start DPC thread.\n");
2805 ret = PTR_ERR(ha->dpc_thread);
2806 goto probe_failed;
2807 }
2808 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2809 "DPC thread started successfully.\n");
2810
2811 /*
2812 * If we're not coming up in initiator mode, we might sit for
2813 * a while without waking up the dpc thread, which leads to a
2814 * stuck process warning. So just kick the dpc once here and
2815 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2816 */
2817 qla2xxx_wake_dpc(base_vha);
2818
2819 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2820 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2821 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2822 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2823
2824 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2825 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2826 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2827 INIT_WORK(&ha->idc_state_handler,
2828 qla83xx_idc_state_handler_work);
2829 INIT_WORK(&ha->nic_core_unrecoverable,
2830 qla83xx_nic_core_unrecoverable_work);
2831 }
2832
2833 skip_dpc:
2834 list_add_tail(&base_vha->list, &ha->vp_list);
2835 base_vha->host->irq = ha->pdev->irq;
2836
2837 /* Initialized the timer */
2838 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2839 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2840 "Started qla2x00_timer with "
2841 "interval=%d.\n", WATCH_INTERVAL);
2842 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2843 "Detected hba at address=%p.\n",
2844 ha);
2845
2846 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2847 if (ha->fw_attributes & BIT_4) {
2848 int prot = 0, guard;
2849 base_vha->flags.difdix_supported = 1;
2850 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2851 "Registering for DIF/DIX type 1 and 3 protection.\n");
2852 if (ql2xenabledif == 1)
2853 prot = SHOST_DIX_TYPE0_PROTECTION;
2854 scsi_host_set_prot(host,
2855 prot | SHOST_DIF_TYPE1_PROTECTION
2856 | SHOST_DIF_TYPE2_PROTECTION
2857 | SHOST_DIF_TYPE3_PROTECTION
2858 | SHOST_DIX_TYPE1_PROTECTION
2859 | SHOST_DIX_TYPE2_PROTECTION
2860 | SHOST_DIX_TYPE3_PROTECTION);
2861
2862 guard = SHOST_DIX_GUARD_CRC;
2863
2864 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2865 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2866 guard |= SHOST_DIX_GUARD_IP;
2867
2868 scsi_host_set_guard(host, guard);
2869 } else
2870 base_vha->flags.difdix_supported = 0;
2871 }
2872
2873 ha->isp_ops->enable_intrs(ha);
2874
2875 if (IS_QLAFX00(ha)) {
2876 ret = qlafx00_fx_disc(base_vha,
2877 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2878 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2879 QLA_SG_ALL : 128;
2880 }
2881
2882 ret = scsi_add_host(host, &pdev->dev);
2883 if (ret)
2884 goto probe_failed;
2885
2886 base_vha->flags.init_done = 1;
2887 base_vha->flags.online = 1;
2888
2889 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2890 "Init done and hba is online.\n");
2891
2892 if (qla_ini_mode_enabled(base_vha))
2893 scsi_scan_host(host);
2894 else
2895 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2896 "skipping scsi_scan_host() for non-initiator port\n");
2897
2898 qla2x00_alloc_sysfs_attr(base_vha);
2899
2900 if (IS_QLAFX00(ha)) {
2901 ret = qlafx00_fx_disc(base_vha,
2902 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2903
2904 /* Register system information */
2905 ret = qlafx00_fx_disc(base_vha,
2906 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2907 }
2908
2909 qla2x00_init_host_attr(base_vha);
2910
2911 qla2x00_dfs_setup(base_vha);
2912
2913 ql_log(ql_log_info, base_vha, 0x00fb,
2914 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2915 ql_log(ql_log_info, base_vha, 0x00fc,
2916 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2917 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2918 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2919 base_vha->host_no,
2920 ha->isp_ops->fw_version_str(base_vha, fw_str));
2921
2922 qlt_add_target(ha, base_vha);
2923
2924 return 0;
2925
2926 probe_init_failed:
2927 qla2x00_free_req_que(ha, req);
2928 ha->req_q_map[0] = NULL;
2929 clear_bit(0, ha->req_qid_map);
2930 qla2x00_free_rsp_que(ha, rsp);
2931 ha->rsp_q_map[0] = NULL;
2932 clear_bit(0, ha->rsp_qid_map);
2933 ha->max_req_queues = ha->max_rsp_queues = 0;
2934
2935 probe_failed:
2936 if (base_vha->timer_active)
2937 qla2x00_stop_timer(base_vha);
2938 base_vha->flags.online = 0;
2939 if (ha->dpc_thread) {
2940 struct task_struct *t = ha->dpc_thread;
2941
2942 ha->dpc_thread = NULL;
2943 kthread_stop(t);
2944 }
2945
2946 qla2x00_free_device(base_vha);
2947
2948 scsi_host_put(base_vha->host);
2949
2950 probe_hw_failed:
2951 if (IS_QLA82XX(ha)) {
2952 qla82xx_idc_lock(ha);
2953 qla82xx_clear_drv_active(ha);
2954 qla82xx_idc_unlock(ha);
2955 }
2956 if (IS_QLA8044(ha)) {
2957 qla8044_idc_lock(ha);
2958 qla8044_clear_drv_active(base_vha);
2959 qla8044_idc_unlock(ha);
2960 }
2961 iospace_config_failed:
2962 if (IS_P3P_TYPE(ha)) {
2963 if (!ha->nx_pcibase)
2964 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2965 if (!ql2xdbwr)
2966 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2967 } else {
2968 if (ha->iobase)
2969 iounmap(ha->iobase);
2970 if (ha->cregbase)
2971 iounmap(ha->cregbase);
2972 }
2973 pci_release_selected_regions(ha->pdev, ha->bars);
2974 kfree(ha);
2975 ha = NULL;
2976
2977 probe_out:
2978 pci_disable_device(pdev);
2979 return ret;
2980 }
2981
2982 static void
2983 qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2984 {
2985 struct qla_hw_data *ha = vha->hw;
2986 struct task_struct *t = ha->dpc_thread;
2987
2988 if (ha->dpc_thread == NULL)
2989 return;
2990 /*
2991 * qla2xxx_wake_dpc checks for ->dpc_thread
2992 * so we need to zero it out.
2993 */
2994 ha->dpc_thread = NULL;
2995 kthread_stop(t);
2996 }
2997
2998 static void
2999 qla2x00_shutdown(struct pci_dev *pdev)
3000 {
3001 scsi_qla_host_t *vha;
3002 struct qla_hw_data *ha;
3003
3004 if (!atomic_read(&pdev->enable_cnt))
3005 return;
3006
3007 vha = pci_get_drvdata(pdev);
3008 ha = vha->hw;
3009
3010 /* Notify ISPFX00 firmware */
3011 if (IS_QLAFX00(ha))
3012 qlafx00_driver_shutdown(vha, 20);
3013
3014 /* Turn-off FCE trace */
3015 if (ha->flags.fce_enabled) {
3016 qla2x00_disable_fce_trace(vha, NULL, NULL);
3017 ha->flags.fce_enabled = 0;
3018 }
3019
3020 /* Turn-off EFT trace */
3021 if (ha->eft)
3022 qla2x00_disable_eft_trace(vha);
3023
3024 /* Stop currently executing firmware. */
3025 qla2x00_try_to_stop_firmware(vha);
3026
3027 /* Turn adapter off line */
3028 vha->flags.online = 0;
3029
3030 /* turn-off interrupts on the card */
3031 if (ha->interrupts_on) {
3032 vha->flags.init_done = 0;
3033 ha->isp_ops->disable_intrs(ha);
3034 }
3035
3036 qla2x00_free_irqs(vha);
3037
3038 qla2x00_free_fw_dump(ha);
3039 }
3040
3041 static void
3042 qla2x00_remove_one(struct pci_dev *pdev)
3043 {
3044 scsi_qla_host_t *base_vha, *vha;
3045 struct qla_hw_data *ha;
3046 unsigned long flags;
3047
3048 /*
3049 * If the PCI device is disabled that means that probe failed and any
3050 * resources should be have cleaned up on probe exit.
3051 */
3052 if (!atomic_read(&pdev->enable_cnt))
3053 return;
3054
3055 base_vha = pci_get_drvdata(pdev);
3056 ha = base_vha->hw;
3057
3058 ha->flags.host_shutting_down = 1;
3059
3060 set_bit(UNLOADING, &base_vha->dpc_flags);
3061 if (IS_QLAFX00(ha))
3062 qlafx00_driver_shutdown(base_vha, 20);
3063
3064 mutex_lock(&ha->vport_lock);
3065 while (ha->cur_vport_count) {
3066 spin_lock_irqsave(&ha->vport_slock, flags);
3067
3068 BUG_ON(base_vha->list.next == &ha->vp_list);
3069 /* This assumes first entry in ha->vp_list is always base vha */
3070 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3071 scsi_host_get(vha->host);
3072
3073 spin_unlock_irqrestore(&ha->vport_slock, flags);
3074 mutex_unlock(&ha->vport_lock);
3075
3076 fc_vport_terminate(vha->fc_vport);
3077 scsi_host_put(vha->host);
3078
3079 mutex_lock(&ha->vport_lock);
3080 }
3081 mutex_unlock(&ha->vport_lock);
3082
3083 if (IS_QLA8031(ha)) {
3084 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3085 "Clearing fcoe driver presence.\n");
3086 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3087 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3088 "Error while clearing DRV-Presence.\n");
3089 }
3090
3091 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3092
3093 qla2x00_dfs_remove(base_vha);
3094
3095 qla84xx_put_chip(base_vha);
3096
3097 /* Disable timer */
3098 if (base_vha->timer_active)
3099 qla2x00_stop_timer(base_vha);
3100
3101 base_vha->flags.online = 0;
3102
3103 /* Flush the work queue and remove it */
3104 if (ha->wq) {
3105 flush_workqueue(ha->wq);
3106 destroy_workqueue(ha->wq);
3107 ha->wq = NULL;
3108 }
3109
3110 /* Cancel all work and destroy DPC workqueues */
3111 if (ha->dpc_lp_wq) {
3112 cancel_work_sync(&ha->idc_aen);
3113 destroy_workqueue(ha->dpc_lp_wq);
3114 ha->dpc_lp_wq = NULL;
3115 }
3116
3117 if (ha->dpc_hp_wq) {
3118 cancel_work_sync(&ha->nic_core_reset);
3119 cancel_work_sync(&ha->idc_state_handler);
3120 cancel_work_sync(&ha->nic_core_unrecoverable);
3121 destroy_workqueue(ha->dpc_hp_wq);
3122 ha->dpc_hp_wq = NULL;
3123 }
3124
3125 /* Kill the kernel thread for this host */
3126 if (ha->dpc_thread) {
3127 struct task_struct *t = ha->dpc_thread;
3128
3129 /*
3130 * qla2xxx_wake_dpc checks for ->dpc_thread
3131 * so we need to zero it out.
3132 */
3133 ha->dpc_thread = NULL;
3134 kthread_stop(t);
3135 }
3136 qlt_remove_target(ha, base_vha);
3137
3138 qla2x00_free_sysfs_attr(base_vha);
3139
3140 fc_remove_host(base_vha->host);
3141
3142 scsi_remove_host(base_vha->host);
3143
3144 qla2x00_free_device(base_vha);
3145
3146 scsi_host_put(base_vha->host);
3147
3148 if (IS_QLA8044(ha)) {
3149 qla8044_idc_lock(ha);
3150 qla8044_clear_drv_active(base_vha);
3151 qla8044_idc_unlock(ha);
3152 }
3153 if (IS_QLA82XX(ha)) {
3154 qla82xx_idc_lock(ha);
3155 qla82xx_clear_drv_active(ha);
3156 qla82xx_idc_unlock(ha);
3157
3158 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3159 if (!ql2xdbwr)
3160 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3161 } else {
3162 if (ha->iobase)
3163 iounmap(ha->iobase);
3164
3165 if (ha->cregbase)
3166 iounmap(ha->cregbase);
3167
3168 if (ha->mqiobase)
3169 iounmap(ha->mqiobase);
3170
3171 if (IS_QLA83XX(ha) && ha->msixbase)
3172 iounmap(ha->msixbase);
3173 }
3174
3175 pci_release_selected_regions(ha->pdev, ha->bars);
3176 kfree(ha);
3177 ha = NULL;
3178
3179 pci_disable_pcie_error_reporting(pdev);
3180
3181 pci_disable_device(pdev);
3182 }
3183
3184 static void
3185 qla2x00_free_device(scsi_qla_host_t *vha)
3186 {
3187 struct qla_hw_data *ha = vha->hw;
3188
3189 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3190
3191 /* Disable timer */
3192 if (vha->timer_active)
3193 qla2x00_stop_timer(vha);
3194
3195 qla2x00_stop_dpc_thread(vha);
3196
3197 qla25xx_delete_queues(vha);
3198 if (ha->flags.fce_enabled)
3199 qla2x00_disable_fce_trace(vha, NULL, NULL);
3200
3201 if (ha->eft)
3202 qla2x00_disable_eft_trace(vha);
3203
3204 /* Stop currently executing firmware. */
3205 qla2x00_try_to_stop_firmware(vha);
3206
3207 vha->flags.online = 0;
3208
3209 /* turn-off interrupts on the card */
3210 if (ha->interrupts_on) {
3211 vha->flags.init_done = 0;
3212 ha->isp_ops->disable_intrs(ha);
3213 }
3214
3215 qla2x00_free_irqs(vha);
3216
3217 qla2x00_free_fcports(vha);
3218
3219 qla2x00_mem_free(ha);
3220
3221 qla82xx_md_free(vha);
3222
3223 qla2x00_free_queues(ha);
3224 }
3225
3226 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3227 {
3228 fc_port_t *fcport, *tfcport;
3229
3230 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3231 list_del(&fcport->list);
3232 qla2x00_clear_loop_id(fcport);
3233 kfree(fcport);
3234 fcport = NULL;
3235 }
3236 }
3237
3238 static inline void
3239 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3240 int defer)
3241 {
3242 struct fc_rport *rport;
3243 scsi_qla_host_t *base_vha;
3244 unsigned long flags;
3245
3246 if (!fcport->rport)
3247 return;
3248
3249 rport = fcport->rport;
3250 if (defer) {
3251 base_vha = pci_get_drvdata(vha->hw->pdev);
3252 spin_lock_irqsave(vha->host->host_lock, flags);
3253 fcport->drport = rport;
3254 spin_unlock_irqrestore(vha->host->host_lock, flags);
3255 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3256 qla2xxx_wake_dpc(base_vha);
3257 } else {
3258 fc_remote_port_delete(rport);
3259 qlt_fc_port_deleted(vha, fcport);
3260 }
3261 }
3262
3263 /*
3264 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3265 *
3266 * Input: ha = adapter block pointer. fcport = port structure pointer.
3267 *
3268 * Return: None.
3269 *
3270 * Context:
3271 */
3272 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3273 int do_login, int defer)
3274 {
3275 if (IS_QLAFX00(vha->hw)) {
3276 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3277 qla2x00_schedule_rport_del(vha, fcport, defer);
3278 return;
3279 }
3280
3281 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3282 vha->vp_idx == fcport->vha->vp_idx) {
3283 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3284 qla2x00_schedule_rport_del(vha, fcport, defer);
3285 }
3286 /*
3287 * We may need to retry the login, so don't change the state of the
3288 * port but do the retries.
3289 */
3290 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3291 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3292
3293 if (!do_login)
3294 return;
3295
3296 if (fcport->login_retry == 0) {
3297 fcport->login_retry = vha->hw->login_retry_count;
3298 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3299
3300 ql_dbg(ql_dbg_disc, vha, 0x2067,
3301 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3302 fcport->port_name, fcport->loop_id, fcport->login_retry);
3303 }
3304 }
3305
3306 /*
3307 * qla2x00_mark_all_devices_lost
3308 * Updates fcport state when device goes offline.
3309 *
3310 * Input:
3311 * ha = adapter block pointer.
3312 * fcport = port structure pointer.
3313 *
3314 * Return:
3315 * None.
3316 *
3317 * Context:
3318 */
3319 void
3320 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3321 {
3322 fc_port_t *fcport;
3323
3324 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3325 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3326 continue;
3327
3328 /*
3329 * No point in marking the device as lost, if the device is
3330 * already DEAD.
3331 */
3332 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3333 continue;
3334 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3335 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3336 if (defer)
3337 qla2x00_schedule_rport_del(vha, fcport, defer);
3338 else if (vha->vp_idx == fcport->vha->vp_idx)
3339 qla2x00_schedule_rport_del(vha, fcport, defer);
3340 }
3341 }
3342 }
3343
3344 /*
3345 * qla2x00_mem_alloc
3346 * Allocates adapter memory.
3347 *
3348 * Returns:
3349 * 0 = success.
3350 * !0 = failure.
3351 */
3352 static int
3353 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3354 struct req_que **req, struct rsp_que **rsp)
3355 {
3356 char name[16];
3357
3358 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3359 &ha->init_cb_dma, GFP_KERNEL);
3360 if (!ha->init_cb)
3361 goto fail;
3362
3363 if (qlt_mem_alloc(ha) < 0)
3364 goto fail_free_init_cb;
3365
3366 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3367 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3368 if (!ha->gid_list)
3369 goto fail_free_tgt_mem;
3370
3371 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3372 if (!ha->srb_mempool)
3373 goto fail_free_gid_list;
3374
3375 if (IS_P3P_TYPE(ha)) {
3376 /* Allocate cache for CT6 Ctx. */
3377 if (!ctx_cachep) {
3378 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3379 sizeof(struct ct6_dsd), 0,
3380 SLAB_HWCACHE_ALIGN, NULL);
3381 if (!ctx_cachep)
3382 goto fail_free_gid_list;
3383 }
3384 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3385 ctx_cachep);
3386 if (!ha->ctx_mempool)
3387 goto fail_free_srb_mempool;
3388 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3389 "ctx_cachep=%p ctx_mempool=%p.\n",
3390 ctx_cachep, ha->ctx_mempool);
3391 }
3392
3393 /* Get memory for cached NVRAM */
3394 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3395 if (!ha->nvram)
3396 goto fail_free_ctx_mempool;
3397
3398 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3399 ha->pdev->device);
3400 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3401 DMA_POOL_SIZE, 8, 0);
3402 if (!ha->s_dma_pool)
3403 goto fail_free_nvram;
3404
3405 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3406 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3407 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3408
3409 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3410 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3411 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3412 if (!ha->dl_dma_pool) {
3413 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3414 "Failed to allocate memory for dl_dma_pool.\n");
3415 goto fail_s_dma_pool;
3416 }
3417
3418 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3419 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3420 if (!ha->fcp_cmnd_dma_pool) {
3421 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3422 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3423 goto fail_dl_dma_pool;
3424 }
3425 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3426 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3427 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3428 }
3429
3430 /* Allocate memory for SNS commands */
3431 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3432 /* Get consistent memory allocated for SNS commands */
3433 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3434 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3435 if (!ha->sns_cmd)
3436 goto fail_dma_pool;
3437 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3438 "sns_cmd: %p.\n", ha->sns_cmd);
3439 } else {
3440 /* Get consistent memory allocated for MS IOCB */
3441 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3442 &ha->ms_iocb_dma);
3443 if (!ha->ms_iocb)
3444 goto fail_dma_pool;
3445 /* Get consistent memory allocated for CT SNS commands */
3446 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3447 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3448 if (!ha->ct_sns)
3449 goto fail_free_ms_iocb;
3450 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3451 "ms_iocb=%p ct_sns=%p.\n",
3452 ha->ms_iocb, ha->ct_sns);
3453 }
3454
3455 /* Allocate memory for request ring */
3456 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3457 if (!*req) {
3458 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3459 "Failed to allocate memory for req.\n");
3460 goto fail_req;
3461 }
3462 (*req)->length = req_len;
3463 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3464 ((*req)->length + 1) * sizeof(request_t),
3465 &(*req)->dma, GFP_KERNEL);
3466 if (!(*req)->ring) {
3467 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3468 "Failed to allocate memory for req_ring.\n");
3469 goto fail_req_ring;
3470 }
3471 /* Allocate memory for response ring */
3472 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3473 if (!*rsp) {
3474 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3475 "Failed to allocate memory for rsp.\n");
3476 goto fail_rsp;
3477 }
3478 (*rsp)->hw = ha;
3479 (*rsp)->length = rsp_len;
3480 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3481 ((*rsp)->length + 1) * sizeof(response_t),
3482 &(*rsp)->dma, GFP_KERNEL);
3483 if (!(*rsp)->ring) {
3484 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3485 "Failed to allocate memory for rsp_ring.\n");
3486 goto fail_rsp_ring;
3487 }
3488 (*req)->rsp = *rsp;
3489 (*rsp)->req = *req;
3490 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3491 "req=%p req->length=%d req->ring=%p rsp=%p "
3492 "rsp->length=%d rsp->ring=%p.\n",
3493 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3494 (*rsp)->ring);
3495 /* Allocate memory for NVRAM data for vports */
3496 if (ha->nvram_npiv_size) {
3497 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3498 ha->nvram_npiv_size, GFP_KERNEL);
3499 if (!ha->npiv_info) {
3500 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3501 "Failed to allocate memory for npiv_info.\n");
3502 goto fail_npiv_info;
3503 }
3504 } else
3505 ha->npiv_info = NULL;
3506
3507 /* Get consistent memory allocated for EX-INIT-CB. */
3508 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
3509 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3510 &ha->ex_init_cb_dma);
3511 if (!ha->ex_init_cb)
3512 goto fail_ex_init_cb;
3513 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3514 "ex_init_cb=%p.\n", ha->ex_init_cb);
3515 }
3516
3517 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3518
3519 /* Get consistent memory allocated for Async Port-Database. */
3520 if (!IS_FWI2_CAPABLE(ha)) {
3521 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3522 &ha->async_pd_dma);
3523 if (!ha->async_pd)
3524 goto fail_async_pd;
3525 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3526 "async_pd=%p.\n", ha->async_pd);
3527 }
3528
3529 INIT_LIST_HEAD(&ha->vp_list);
3530
3531 /* Allocate memory for our loop_id bitmap */
3532 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3533 GFP_KERNEL);
3534 if (!ha->loop_id_map)
3535 goto fail_async_pd;
3536 else {
3537 qla2x00_set_reserved_loop_ids(ha);
3538 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3539 "loop_id_map=%p. \n", ha->loop_id_map);
3540 }
3541
3542 return 1;
3543
3544 fail_async_pd:
3545 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3546 fail_ex_init_cb:
3547 kfree(ha->npiv_info);
3548 fail_npiv_info:
3549 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3550 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3551 (*rsp)->ring = NULL;
3552 (*rsp)->dma = 0;
3553 fail_rsp_ring:
3554 kfree(*rsp);
3555 fail_rsp:
3556 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3557 sizeof(request_t), (*req)->ring, (*req)->dma);
3558 (*req)->ring = NULL;
3559 (*req)->dma = 0;
3560 fail_req_ring:
3561 kfree(*req);
3562 fail_req:
3563 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3564 ha->ct_sns, ha->ct_sns_dma);
3565 ha->ct_sns = NULL;
3566 ha->ct_sns_dma = 0;
3567 fail_free_ms_iocb:
3568 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3569 ha->ms_iocb = NULL;
3570 ha->ms_iocb_dma = 0;
3571 fail_dma_pool:
3572 if (IS_QLA82XX(ha) || ql2xenabledif) {
3573 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3574 ha->fcp_cmnd_dma_pool = NULL;
3575 }
3576 fail_dl_dma_pool:
3577 if (IS_QLA82XX(ha) || ql2xenabledif) {
3578 dma_pool_destroy(ha->dl_dma_pool);
3579 ha->dl_dma_pool = NULL;
3580 }
3581 fail_s_dma_pool:
3582 dma_pool_destroy(ha->s_dma_pool);
3583 ha->s_dma_pool = NULL;
3584 fail_free_nvram:
3585 kfree(ha->nvram);
3586 ha->nvram = NULL;
3587 fail_free_ctx_mempool:
3588 mempool_destroy(ha->ctx_mempool);
3589 ha->ctx_mempool = NULL;
3590 fail_free_srb_mempool:
3591 mempool_destroy(ha->srb_mempool);
3592 ha->srb_mempool = NULL;
3593 fail_free_gid_list:
3594 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3595 ha->gid_list,
3596 ha->gid_list_dma);
3597 ha->gid_list = NULL;
3598 ha->gid_list_dma = 0;
3599 fail_free_tgt_mem:
3600 qlt_mem_free(ha);
3601 fail_free_init_cb:
3602 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3603 ha->init_cb_dma);
3604 ha->init_cb = NULL;
3605 ha->init_cb_dma = 0;
3606 fail:
3607 ql_log(ql_log_fatal, NULL, 0x0030,
3608 "Memory allocation failure.\n");
3609 return -ENOMEM;
3610 }
3611
3612 /*
3613 * qla2x00_free_fw_dump
3614 * Frees fw dump stuff.
3615 *
3616 * Input:
3617 * ha = adapter block pointer
3618 */
3619 static void
3620 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3621 {
3622 if (ha->fce)
3623 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
3624 ha->fce_dma);
3625
3626 if (ha->fw_dump) {
3627 if (ha->eft)
3628 dma_free_coherent(&ha->pdev->dev,
3629 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
3630 vfree(ha->fw_dump);
3631 }
3632 ha->fce = NULL;
3633 ha->fce_dma = 0;
3634 ha->eft = NULL;
3635 ha->eft_dma = 0;
3636 ha->fw_dump = NULL;
3637 ha->fw_dumped = 0;
3638 ha->fw_dump_reading = 0;
3639 }
3640
3641 /*
3642 * qla2x00_mem_free
3643 * Frees all adapter allocated memory.
3644 *
3645 * Input:
3646 * ha = adapter block pointer.
3647 */
3648 static void
3649 qla2x00_mem_free(struct qla_hw_data *ha)
3650 {
3651 qla2x00_free_fw_dump(ha);
3652
3653 if (ha->mctp_dump)
3654 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3655 ha->mctp_dump_dma);
3656
3657 if (ha->srb_mempool)
3658 mempool_destroy(ha->srb_mempool);
3659
3660 if (ha->dcbx_tlv)
3661 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3662 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3663
3664 if (ha->xgmac_data)
3665 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3666 ha->xgmac_data, ha->xgmac_data_dma);
3667
3668 if (ha->sns_cmd)
3669 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3670 ha->sns_cmd, ha->sns_cmd_dma);
3671
3672 if (ha->ct_sns)
3673 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3674 ha->ct_sns, ha->ct_sns_dma);
3675
3676 if (ha->sfp_data)
3677 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3678
3679 if (ha->ms_iocb)
3680 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3681
3682 if (ha->ex_init_cb)
3683 dma_pool_free(ha->s_dma_pool,
3684 ha->ex_init_cb, ha->ex_init_cb_dma);
3685
3686 if (ha->async_pd)
3687 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3688
3689 if (ha->s_dma_pool)
3690 dma_pool_destroy(ha->s_dma_pool);
3691
3692 if (ha->gid_list)
3693 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3694 ha->gid_list, ha->gid_list_dma);
3695
3696 if (IS_QLA82XX(ha)) {
3697 if (!list_empty(&ha->gbl_dsd_list)) {
3698 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3699
3700 /* clean up allocated prev pool */
3701 list_for_each_entry_safe(dsd_ptr,
3702 tdsd_ptr, &ha->gbl_dsd_list, list) {
3703 dma_pool_free(ha->dl_dma_pool,
3704 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3705 list_del(&dsd_ptr->list);
3706 kfree(dsd_ptr);
3707 }
3708 }
3709 }
3710
3711 if (ha->dl_dma_pool)
3712 dma_pool_destroy(ha->dl_dma_pool);
3713
3714 if (ha->fcp_cmnd_dma_pool)
3715 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3716
3717 if (ha->ctx_mempool)
3718 mempool_destroy(ha->ctx_mempool);
3719
3720 qlt_mem_free(ha);
3721
3722 if (ha->init_cb)
3723 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3724 ha->init_cb, ha->init_cb_dma);
3725 vfree(ha->optrom_buffer);
3726 kfree(ha->nvram);
3727 kfree(ha->npiv_info);
3728 kfree(ha->swl);
3729 kfree(ha->loop_id_map);
3730
3731 ha->srb_mempool = NULL;
3732 ha->ctx_mempool = NULL;
3733 ha->sns_cmd = NULL;
3734 ha->sns_cmd_dma = 0;
3735 ha->ct_sns = NULL;
3736 ha->ct_sns_dma = 0;
3737 ha->ms_iocb = NULL;
3738 ha->ms_iocb_dma = 0;
3739 ha->init_cb = NULL;
3740 ha->init_cb_dma = 0;
3741 ha->ex_init_cb = NULL;
3742 ha->ex_init_cb_dma = 0;
3743 ha->async_pd = NULL;
3744 ha->async_pd_dma = 0;
3745
3746 ha->s_dma_pool = NULL;
3747 ha->dl_dma_pool = NULL;
3748 ha->fcp_cmnd_dma_pool = NULL;
3749
3750 ha->gid_list = NULL;
3751 ha->gid_list_dma = 0;
3752
3753 ha->tgt.atio_ring = NULL;
3754 ha->tgt.atio_dma = 0;
3755 ha->tgt.tgt_vp_map = NULL;
3756 }
3757
3758 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3759 struct qla_hw_data *ha)
3760 {
3761 struct Scsi_Host *host;
3762 struct scsi_qla_host *vha = NULL;
3763
3764 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3765 if (host == NULL) {
3766 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3767 "Failed to allocate host from the scsi layer, aborting.\n");
3768 goto fail;
3769 }
3770
3771 /* Clear our data area */
3772 vha = shost_priv(host);
3773 memset(vha, 0, sizeof(scsi_qla_host_t));
3774
3775 vha->host = host;
3776 vha->host_no = host->host_no;
3777 vha->hw = ha;
3778
3779 INIT_LIST_HEAD(&vha->vp_fcports);
3780 INIT_LIST_HEAD(&vha->work_list);
3781 INIT_LIST_HEAD(&vha->list);
3782
3783 spin_lock_init(&vha->work_lock);
3784
3785 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3786 ql_dbg(ql_dbg_init, vha, 0x0041,
3787 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3788 vha->host, vha->hw, vha,
3789 dev_name(&(ha->pdev->dev)));
3790
3791 return vha;
3792
3793 fail:
3794 return vha;
3795 }
3796
3797 static struct qla_work_evt *
3798 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3799 {
3800 struct qla_work_evt *e;
3801 uint8_t bail;
3802
3803 QLA_VHA_MARK_BUSY(vha, bail);
3804 if (bail)
3805 return NULL;
3806
3807 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3808 if (!e) {
3809 QLA_VHA_MARK_NOT_BUSY(vha);
3810 return NULL;
3811 }
3812
3813 INIT_LIST_HEAD(&e->list);
3814 e->type = type;
3815 e->flags = QLA_EVT_FLAG_FREE;
3816 return e;
3817 }
3818
3819 static int
3820 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3821 {
3822 unsigned long flags;
3823
3824 spin_lock_irqsave(&vha->work_lock, flags);
3825 list_add_tail(&e->list, &vha->work_list);
3826 spin_unlock_irqrestore(&vha->work_lock, flags);
3827 qla2xxx_wake_dpc(vha);
3828
3829 return QLA_SUCCESS;
3830 }
3831
3832 int
3833 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3834 u32 data)
3835 {
3836 struct qla_work_evt *e;
3837
3838 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3839 if (!e)
3840 return QLA_FUNCTION_FAILED;
3841
3842 e->u.aen.code = code;
3843 e->u.aen.data = data;
3844 return qla2x00_post_work(vha, e);
3845 }
3846
3847 int
3848 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3849 {
3850 struct qla_work_evt *e;
3851
3852 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3853 if (!e)
3854 return QLA_FUNCTION_FAILED;
3855
3856 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3857 return qla2x00_post_work(vha, e);
3858 }
3859
3860 #define qla2x00_post_async_work(name, type) \
3861 int qla2x00_post_async_##name##_work( \
3862 struct scsi_qla_host *vha, \
3863 fc_port_t *fcport, uint16_t *data) \
3864 { \
3865 struct qla_work_evt *e; \
3866 \
3867 e = qla2x00_alloc_work(vha, type); \
3868 if (!e) \
3869 return QLA_FUNCTION_FAILED; \
3870 \
3871 e->u.logio.fcport = fcport; \
3872 if (data) { \
3873 e->u.logio.data[0] = data[0]; \
3874 e->u.logio.data[1] = data[1]; \
3875 } \
3876 return qla2x00_post_work(vha, e); \
3877 }
3878
3879 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3880 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3881 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3882 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3883 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3884 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3885
3886 int
3887 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3888 {
3889 struct qla_work_evt *e;
3890
3891 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3892 if (!e)
3893 return QLA_FUNCTION_FAILED;
3894
3895 e->u.uevent.code = code;
3896 return qla2x00_post_work(vha, e);
3897 }
3898
3899 static void
3900 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3901 {
3902 char event_string[40];
3903 char *envp[] = { event_string, NULL };
3904
3905 switch (code) {
3906 case QLA_UEVENT_CODE_FW_DUMP:
3907 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3908 vha->host_no);
3909 break;
3910 default:
3911 /* do nothing */
3912 break;
3913 }
3914 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3915 }
3916
3917 int
3918 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3919 uint32_t *data, int cnt)
3920 {
3921 struct qla_work_evt *e;
3922
3923 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3924 if (!e)
3925 return QLA_FUNCTION_FAILED;
3926
3927 e->u.aenfx.evtcode = evtcode;
3928 e->u.aenfx.count = cnt;
3929 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3930 return qla2x00_post_work(vha, e);
3931 }
3932
3933 void
3934 qla2x00_do_work(struct scsi_qla_host *vha)
3935 {
3936 struct qla_work_evt *e, *tmp;
3937 unsigned long flags;
3938 LIST_HEAD(work);
3939
3940 spin_lock_irqsave(&vha->work_lock, flags);
3941 list_splice_init(&vha->work_list, &work);
3942 spin_unlock_irqrestore(&vha->work_lock, flags);
3943
3944 list_for_each_entry_safe(e, tmp, &work, list) {
3945 list_del_init(&e->list);
3946
3947 switch (e->type) {
3948 case QLA_EVT_AEN:
3949 fc_host_post_event(vha->host, fc_get_event_number(),
3950 e->u.aen.code, e->u.aen.data);
3951 break;
3952 case QLA_EVT_IDC_ACK:
3953 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3954 break;
3955 case QLA_EVT_ASYNC_LOGIN:
3956 qla2x00_async_login(vha, e->u.logio.fcport,
3957 e->u.logio.data);
3958 break;
3959 case QLA_EVT_ASYNC_LOGIN_DONE:
3960 qla2x00_async_login_done(vha, e->u.logio.fcport,
3961 e->u.logio.data);
3962 break;
3963 case QLA_EVT_ASYNC_LOGOUT:
3964 qla2x00_async_logout(vha, e->u.logio.fcport);
3965 break;
3966 case QLA_EVT_ASYNC_LOGOUT_DONE:
3967 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3968 e->u.logio.data);
3969 break;
3970 case QLA_EVT_ASYNC_ADISC:
3971 qla2x00_async_adisc(vha, e->u.logio.fcport,
3972 e->u.logio.data);
3973 break;
3974 case QLA_EVT_ASYNC_ADISC_DONE:
3975 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3976 e->u.logio.data);
3977 break;
3978 case QLA_EVT_UEVENT:
3979 qla2x00_uevent_emit(vha, e->u.uevent.code);
3980 break;
3981 case QLA_EVT_AENFX:
3982 qlafx00_process_aen(vha, e);
3983 break;
3984 }
3985 if (e->flags & QLA_EVT_FLAG_FREE)
3986 kfree(e);
3987
3988 /* For each work completed decrement vha ref count */
3989 QLA_VHA_MARK_NOT_BUSY(vha);
3990 }
3991 }
3992
3993 /* Relogins all the fcports of a vport
3994 * Context: dpc thread
3995 */
3996 void qla2x00_relogin(struct scsi_qla_host *vha)
3997 {
3998 fc_port_t *fcport;
3999 int status;
4000 uint16_t next_loopid = 0;
4001 struct qla_hw_data *ha = vha->hw;
4002 uint16_t data[2];
4003
4004 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4005 /*
4006 * If the port is not ONLINE then try to login
4007 * to it if we haven't run out of retries.
4008 */
4009 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4010 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4011 fcport->login_retry--;
4012 if (fcport->flags & FCF_FABRIC_DEVICE) {
4013 if (fcport->flags & FCF_FCP2_DEVICE)
4014 ha->isp_ops->fabric_logout(vha,
4015 fcport->loop_id,
4016 fcport->d_id.b.domain,
4017 fcport->d_id.b.area,
4018 fcport->d_id.b.al_pa);
4019
4020 if (fcport->loop_id == FC_NO_LOOP_ID) {
4021 fcport->loop_id = next_loopid =
4022 ha->min_external_loopid;
4023 status = qla2x00_find_new_loop_id(
4024 vha, fcport);
4025 if (status != QLA_SUCCESS) {
4026 /* Ran out of IDs to use */
4027 break;
4028 }
4029 }
4030
4031 if (IS_ALOGIO_CAPABLE(ha)) {
4032 fcport->flags |= FCF_ASYNC_SENT;
4033 data[0] = 0;
4034 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4035 status = qla2x00_post_async_login_work(
4036 vha, fcport, data);
4037 if (status == QLA_SUCCESS)
4038 continue;
4039 /* Attempt a retry. */
4040 status = 1;
4041 } else {
4042 status = qla2x00_fabric_login(vha,
4043 fcport, &next_loopid);
4044 if (status == QLA_SUCCESS) {
4045 int status2;
4046 uint8_t opts;
4047
4048 opts = 0;
4049 if (fcport->flags &
4050 FCF_FCP2_DEVICE)
4051 opts |= BIT_1;
4052 status2 =
4053 qla2x00_get_port_database(
4054 vha, fcport, opts);
4055 if (status2 != QLA_SUCCESS)
4056 status = 1;
4057 }
4058 }
4059 } else
4060 status = qla2x00_local_device_login(vha,
4061 fcport);
4062
4063 if (status == QLA_SUCCESS) {
4064 fcport->old_loop_id = fcport->loop_id;
4065
4066 ql_dbg(ql_dbg_disc, vha, 0x2003,
4067 "Port login OK: logged in ID 0x%x.\n",
4068 fcport->loop_id);
4069
4070 qla2x00_update_fcport(vha, fcport);
4071
4072 } else if (status == 1) {
4073 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4074 /* retry the login again */
4075 ql_dbg(ql_dbg_disc, vha, 0x2007,
4076 "Retrying %d login again loop_id 0x%x.\n",
4077 fcport->login_retry, fcport->loop_id);
4078 } else {
4079 fcport->login_retry = 0;
4080 }
4081
4082 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4083 qla2x00_clear_loop_id(fcport);
4084 }
4085 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4086 break;
4087 }
4088 }
4089
4090 /* Schedule work on any of the dpc-workqueues */
4091 void
4092 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4093 {
4094 struct qla_hw_data *ha = base_vha->hw;
4095
4096 switch (work_code) {
4097 case MBA_IDC_AEN: /* 0x8200 */
4098 if (ha->dpc_lp_wq)
4099 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4100 break;
4101
4102 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4103 if (!ha->flags.nic_core_reset_hdlr_active) {
4104 if (ha->dpc_hp_wq)
4105 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4106 } else
4107 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4108 "NIC Core reset is already active. Skip "
4109 "scheduling it again.\n");
4110 break;
4111 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4112 if (ha->dpc_hp_wq)
4113 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4114 break;
4115 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4116 if (ha->dpc_hp_wq)
4117 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4118 break;
4119 default:
4120 ql_log(ql_log_warn, base_vha, 0xb05f,
4121 "Unknow work-code=0x%x.\n", work_code);
4122 }
4123
4124 return;
4125 }
4126
4127 /* Work: Perform NIC Core Unrecoverable state handling */
4128 void
4129 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4130 {
4131 struct qla_hw_data *ha =
4132 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4133 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4134 uint32_t dev_state = 0;
4135
4136 qla83xx_idc_lock(base_vha, 0);
4137 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4138 qla83xx_reset_ownership(base_vha);
4139 if (ha->flags.nic_core_reset_owner) {
4140 ha->flags.nic_core_reset_owner = 0;
4141 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4142 QLA8XXX_DEV_FAILED);
4143 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4144 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4145 }
4146 qla83xx_idc_unlock(base_vha, 0);
4147 }
4148
4149 /* Work: Execute IDC state handler */
4150 void
4151 qla83xx_idc_state_handler_work(struct work_struct *work)
4152 {
4153 struct qla_hw_data *ha =
4154 container_of(work, struct qla_hw_data, idc_state_handler);
4155 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4156 uint32_t dev_state = 0;
4157
4158 qla83xx_idc_lock(base_vha, 0);
4159 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4160 if (dev_state == QLA8XXX_DEV_FAILED ||
4161 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4162 qla83xx_idc_state_handler(base_vha);
4163 qla83xx_idc_unlock(base_vha, 0);
4164 }
4165
4166 static int
4167 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4168 {
4169 int rval = QLA_SUCCESS;
4170 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4171 uint32_t heart_beat_counter1, heart_beat_counter2;
4172
4173 do {
4174 if (time_after(jiffies, heart_beat_wait)) {
4175 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4176 "Nic Core f/w is not alive.\n");
4177 rval = QLA_FUNCTION_FAILED;
4178 break;
4179 }
4180
4181 qla83xx_idc_lock(base_vha, 0);
4182 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4183 &heart_beat_counter1);
4184 qla83xx_idc_unlock(base_vha, 0);
4185 msleep(100);
4186 qla83xx_idc_lock(base_vha, 0);
4187 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4188 &heart_beat_counter2);
4189 qla83xx_idc_unlock(base_vha, 0);
4190 } while (heart_beat_counter1 == heart_beat_counter2);
4191
4192 return rval;
4193 }
4194
4195 /* Work: Perform NIC Core Reset handling */
4196 void
4197 qla83xx_nic_core_reset_work(struct work_struct *work)
4198 {
4199 struct qla_hw_data *ha =
4200 container_of(work, struct qla_hw_data, nic_core_reset);
4201 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4202 uint32_t dev_state = 0;
4203
4204 if (IS_QLA2031(ha)) {
4205 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4206 ql_log(ql_log_warn, base_vha, 0xb081,
4207 "Failed to dump mctp\n");
4208 return;
4209 }
4210
4211 if (!ha->flags.nic_core_reset_hdlr_active) {
4212 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4213 qla83xx_idc_lock(base_vha, 0);
4214 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4215 &dev_state);
4216 qla83xx_idc_unlock(base_vha, 0);
4217 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4218 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4219 "Nic Core f/w is alive.\n");
4220 return;
4221 }
4222 }
4223
4224 ha->flags.nic_core_reset_hdlr_active = 1;
4225 if (qla83xx_nic_core_reset(base_vha)) {
4226 /* NIC Core reset failed. */
4227 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4228 "NIC Core reset failed.\n");
4229 }
4230 ha->flags.nic_core_reset_hdlr_active = 0;
4231 }
4232 }
4233
4234 /* Work: Handle 8200 IDC aens */
4235 void
4236 qla83xx_service_idc_aen(struct work_struct *work)
4237 {
4238 struct qla_hw_data *ha =
4239 container_of(work, struct qla_hw_data, idc_aen);
4240 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4241 uint32_t dev_state, idc_control;
4242
4243 qla83xx_idc_lock(base_vha, 0);
4244 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4245 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4246 qla83xx_idc_unlock(base_vha, 0);
4247 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4248 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4249 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4250 "Application requested NIC Core Reset.\n");
4251 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4252 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4253 QLA_SUCCESS) {
4254 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4255 "Other protocol driver requested NIC Core Reset.\n");
4256 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4257 }
4258 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4259 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4260 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4261 }
4262 }
4263
4264 static void
4265 qla83xx_wait_logic(void)
4266 {
4267 int i;
4268
4269 /* Yield CPU */
4270 if (!in_interrupt()) {
4271 /*
4272 * Wait about 200ms before retrying again.
4273 * This controls the number of retries for single
4274 * lock operation.
4275 */
4276 msleep(100);
4277 schedule();
4278 } else {
4279 for (i = 0; i < 20; i++)
4280 cpu_relax(); /* This a nop instr on i386 */
4281 }
4282 }
4283
4284 static int
4285 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4286 {
4287 int rval;
4288 uint32_t data;
4289 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4290 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4291 struct qla_hw_data *ha = base_vha->hw;
4292 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4293 "Trying force recovery of the IDC lock.\n");
4294
4295 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4296 if (rval)
4297 return rval;
4298
4299 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4300 return QLA_SUCCESS;
4301 } else {
4302 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4303 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4304 data);
4305 if (rval)
4306 return rval;
4307
4308 msleep(200);
4309
4310 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4311 &data);
4312 if (rval)
4313 return rval;
4314
4315 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4316 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4317 ~(idc_lck_rcvry_stage_mask));
4318 rval = qla83xx_wr_reg(base_vha,
4319 QLA83XX_IDC_LOCK_RECOVERY, data);
4320 if (rval)
4321 return rval;
4322
4323 /* Forcefully perform IDC UnLock */
4324 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4325 &data);
4326 if (rval)
4327 return rval;
4328 /* Clear lock-id by setting 0xff */
4329 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4330 0xff);
4331 if (rval)
4332 return rval;
4333 /* Clear lock-recovery by setting 0x0 */
4334 rval = qla83xx_wr_reg(base_vha,
4335 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4336 if (rval)
4337 return rval;
4338 } else
4339 return QLA_SUCCESS;
4340 }
4341
4342 return rval;
4343 }
4344
4345 static int
4346 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4347 {
4348 int rval = QLA_SUCCESS;
4349 uint32_t o_drv_lockid, n_drv_lockid;
4350 unsigned long lock_recovery_timeout;
4351
4352 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4353 retry_lockid:
4354 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4355 if (rval)
4356 goto exit;
4357
4358 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4359 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4360 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4361 return QLA_SUCCESS;
4362 else
4363 return QLA_FUNCTION_FAILED;
4364 }
4365
4366 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4367 if (rval)
4368 goto exit;
4369
4370 if (o_drv_lockid == n_drv_lockid) {
4371 qla83xx_wait_logic();
4372 goto retry_lockid;
4373 } else
4374 return QLA_SUCCESS;
4375
4376 exit:
4377 return rval;
4378 }
4379
4380 void
4381 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4382 {
4383 uint16_t options = (requester_id << 15) | BIT_6;
4384 uint32_t data;
4385 uint32_t lock_owner;
4386 struct qla_hw_data *ha = base_vha->hw;
4387
4388 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4389 retry_lock:
4390 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4391 == QLA_SUCCESS) {
4392 if (data) {
4393 /* Setting lock-id to our function-number */
4394 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4395 ha->portnum);
4396 } else {
4397 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4398 &lock_owner);
4399 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4400 "Failed to acquire IDC lock, acquired by %d, "
4401 "retrying...\n", lock_owner);
4402
4403 /* Retry/Perform IDC-Lock recovery */
4404 if (qla83xx_idc_lock_recovery(base_vha)
4405 == QLA_SUCCESS) {
4406 qla83xx_wait_logic();
4407 goto retry_lock;
4408 } else
4409 ql_log(ql_log_warn, base_vha, 0xb075,
4410 "IDC Lock recovery FAILED.\n");
4411 }
4412
4413 }
4414
4415 return;
4416
4417 /* XXX: IDC-lock implementation using access-control mbx */
4418 retry_lock2:
4419 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4420 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4421 "Failed to acquire IDC lock. retrying...\n");
4422 /* Retry/Perform IDC-Lock recovery */
4423 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4424 qla83xx_wait_logic();
4425 goto retry_lock2;
4426 } else
4427 ql_log(ql_log_warn, base_vha, 0xb076,
4428 "IDC Lock recovery FAILED.\n");
4429 }
4430
4431 return;
4432 }
4433
4434 void
4435 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4436 {
4437 uint16_t options = (requester_id << 15) | BIT_7, retry;
4438 uint32_t data;
4439 struct qla_hw_data *ha = base_vha->hw;
4440
4441 /* IDC-unlock implementation using driver-unlock/lock-id
4442 * remote registers
4443 */
4444 retry = 0;
4445 retry_unlock:
4446 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4447 == QLA_SUCCESS) {
4448 if (data == ha->portnum) {
4449 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4450 /* Clearing lock-id by setting 0xff */
4451 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4452 } else if (retry < 10) {
4453 /* SV: XXX: IDC unlock retrying needed here? */
4454
4455 /* Retry for IDC-unlock */
4456 qla83xx_wait_logic();
4457 retry++;
4458 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4459 "Failed to release IDC lock, retyring=%d\n", retry);
4460 goto retry_unlock;
4461 }
4462 } else if (retry < 10) {
4463 /* Retry for IDC-unlock */
4464 qla83xx_wait_logic();
4465 retry++;
4466 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4467 "Failed to read drv-lockid, retyring=%d\n", retry);
4468 goto retry_unlock;
4469 }
4470
4471 return;
4472
4473 /* XXX: IDC-unlock implementation using access-control mbx */
4474 retry = 0;
4475 retry_unlock2:
4476 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4477 if (retry < 10) {
4478 /* Retry for IDC-unlock */
4479 qla83xx_wait_logic();
4480 retry++;
4481 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4482 "Failed to release IDC lock, retyring=%d\n", retry);
4483 goto retry_unlock2;
4484 }
4485 }
4486
4487 return;
4488 }
4489
4490 int
4491 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4492 {
4493 int rval = QLA_SUCCESS;
4494 struct qla_hw_data *ha = vha->hw;
4495 uint32_t drv_presence;
4496
4497 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4498 if (rval == QLA_SUCCESS) {
4499 drv_presence |= (1 << ha->portnum);
4500 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4501 drv_presence);
4502 }
4503
4504 return rval;
4505 }
4506
4507 int
4508 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4509 {
4510 int rval = QLA_SUCCESS;
4511
4512 qla83xx_idc_lock(vha, 0);
4513 rval = __qla83xx_set_drv_presence(vha);
4514 qla83xx_idc_unlock(vha, 0);
4515
4516 return rval;
4517 }
4518
4519 int
4520 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4521 {
4522 int rval = QLA_SUCCESS;
4523 struct qla_hw_data *ha = vha->hw;
4524 uint32_t drv_presence;
4525
4526 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4527 if (rval == QLA_SUCCESS) {
4528 drv_presence &= ~(1 << ha->portnum);
4529 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4530 drv_presence);
4531 }
4532
4533 return rval;
4534 }
4535
4536 int
4537 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4538 {
4539 int rval = QLA_SUCCESS;
4540
4541 qla83xx_idc_lock(vha, 0);
4542 rval = __qla83xx_clear_drv_presence(vha);
4543 qla83xx_idc_unlock(vha, 0);
4544
4545 return rval;
4546 }
4547
4548 static void
4549 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4550 {
4551 struct qla_hw_data *ha = vha->hw;
4552 uint32_t drv_ack, drv_presence;
4553 unsigned long ack_timeout;
4554
4555 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4556 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4557 while (1) {
4558 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4559 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4560 if ((drv_ack & drv_presence) == drv_presence)
4561 break;
4562
4563 if (time_after_eq(jiffies, ack_timeout)) {
4564 ql_log(ql_log_warn, vha, 0xb067,
4565 "RESET ACK TIMEOUT! drv_presence=0x%x "
4566 "drv_ack=0x%x\n", drv_presence, drv_ack);
4567 /*
4568 * The function(s) which did not ack in time are forced
4569 * to withdraw any further participation in the IDC
4570 * reset.
4571 */
4572 if (drv_ack != drv_presence)
4573 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4574 drv_ack);
4575 break;
4576 }
4577
4578 qla83xx_idc_unlock(vha, 0);
4579 msleep(1000);
4580 qla83xx_idc_lock(vha, 0);
4581 }
4582
4583 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4584 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4585 }
4586
4587 static int
4588 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4589 {
4590 int rval = QLA_SUCCESS;
4591 uint32_t idc_control;
4592
4593 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4594 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4595
4596 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4597 __qla83xx_get_idc_control(vha, &idc_control);
4598 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4599 __qla83xx_set_idc_control(vha, 0);
4600
4601 qla83xx_idc_unlock(vha, 0);
4602 rval = qla83xx_restart_nic_firmware(vha);
4603 qla83xx_idc_lock(vha, 0);
4604
4605 if (rval != QLA_SUCCESS) {
4606 ql_log(ql_log_fatal, vha, 0xb06a,
4607 "Failed to restart NIC f/w.\n");
4608 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4609 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4610 } else {
4611 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4612 "Success in restarting nic f/w.\n");
4613 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4614 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4615 }
4616
4617 return rval;
4618 }
4619
4620 /* Assumes idc_lock always held on entry */
4621 int
4622 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4623 {
4624 struct qla_hw_data *ha = base_vha->hw;
4625 int rval = QLA_SUCCESS;
4626 unsigned long dev_init_timeout;
4627 uint32_t dev_state;
4628
4629 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4630 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4631
4632 while (1) {
4633
4634 if (time_after_eq(jiffies, dev_init_timeout)) {
4635 ql_log(ql_log_warn, base_vha, 0xb06e,
4636 "Initialization TIMEOUT!\n");
4637 /* Init timeout. Disable further NIC Core
4638 * communication.
4639 */
4640 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4641 QLA8XXX_DEV_FAILED);
4642 ql_log(ql_log_info, base_vha, 0xb06f,
4643 "HW State: FAILED.\n");
4644 }
4645
4646 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4647 switch (dev_state) {
4648 case QLA8XXX_DEV_READY:
4649 if (ha->flags.nic_core_reset_owner)
4650 qla83xx_idc_audit(base_vha,
4651 IDC_AUDIT_COMPLETION);
4652 ha->flags.nic_core_reset_owner = 0;
4653 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4654 "Reset_owner reset by 0x%x.\n",
4655 ha->portnum);
4656 goto exit;
4657 case QLA8XXX_DEV_COLD:
4658 if (ha->flags.nic_core_reset_owner)
4659 rval = qla83xx_device_bootstrap(base_vha);
4660 else {
4661 /* Wait for AEN to change device-state */
4662 qla83xx_idc_unlock(base_vha, 0);
4663 msleep(1000);
4664 qla83xx_idc_lock(base_vha, 0);
4665 }
4666 break;
4667 case QLA8XXX_DEV_INITIALIZING:
4668 /* Wait for AEN to change device-state */
4669 qla83xx_idc_unlock(base_vha, 0);
4670 msleep(1000);
4671 qla83xx_idc_lock(base_vha, 0);
4672 break;
4673 case QLA8XXX_DEV_NEED_RESET:
4674 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4675 qla83xx_need_reset_handler(base_vha);
4676 else {
4677 /* Wait for AEN to change device-state */
4678 qla83xx_idc_unlock(base_vha, 0);
4679 msleep(1000);
4680 qla83xx_idc_lock(base_vha, 0);
4681 }
4682 /* reset timeout value after need reset handler */
4683 dev_init_timeout = jiffies +
4684 (ha->fcoe_dev_init_timeout * HZ);
4685 break;
4686 case QLA8XXX_DEV_NEED_QUIESCENT:
4687 /* XXX: DEBUG for now */
4688 qla83xx_idc_unlock(base_vha, 0);
4689 msleep(1000);
4690 qla83xx_idc_lock(base_vha, 0);
4691 break;
4692 case QLA8XXX_DEV_QUIESCENT:
4693 /* XXX: DEBUG for now */
4694 if (ha->flags.quiesce_owner)
4695 goto exit;
4696
4697 qla83xx_idc_unlock(base_vha, 0);
4698 msleep(1000);
4699 qla83xx_idc_lock(base_vha, 0);
4700 dev_init_timeout = jiffies +
4701 (ha->fcoe_dev_init_timeout * HZ);
4702 break;
4703 case QLA8XXX_DEV_FAILED:
4704 if (ha->flags.nic_core_reset_owner)
4705 qla83xx_idc_audit(base_vha,
4706 IDC_AUDIT_COMPLETION);
4707 ha->flags.nic_core_reset_owner = 0;
4708 __qla83xx_clear_drv_presence(base_vha);
4709 qla83xx_idc_unlock(base_vha, 0);
4710 qla8xxx_dev_failed_handler(base_vha);
4711 rval = QLA_FUNCTION_FAILED;
4712 qla83xx_idc_lock(base_vha, 0);
4713 goto exit;
4714 case QLA8XXX_BAD_VALUE:
4715 qla83xx_idc_unlock(base_vha, 0);
4716 msleep(1000);
4717 qla83xx_idc_lock(base_vha, 0);
4718 break;
4719 default:
4720 ql_log(ql_log_warn, base_vha, 0xb071,
4721 "Unknow Device State: %x.\n", dev_state);
4722 qla83xx_idc_unlock(base_vha, 0);
4723 qla8xxx_dev_failed_handler(base_vha);
4724 rval = QLA_FUNCTION_FAILED;
4725 qla83xx_idc_lock(base_vha, 0);
4726 goto exit;
4727 }
4728 }
4729
4730 exit:
4731 return rval;
4732 }
4733
4734 /**************************************************************************
4735 * qla2x00_do_dpc
4736 * This kernel thread is a task that is schedule by the interrupt handler
4737 * to perform the background processing for interrupts.
4738 *
4739 * Notes:
4740 * This task always run in the context of a kernel thread. It
4741 * is kick-off by the driver's detect code and starts up
4742 * up one per adapter. It immediately goes to sleep and waits for
4743 * some fibre event. When either the interrupt handler or
4744 * the timer routine detects a event it will one of the task
4745 * bits then wake us up.
4746 **************************************************************************/
4747 static int
4748 qla2x00_do_dpc(void *data)
4749 {
4750 int rval;
4751 scsi_qla_host_t *base_vha;
4752 struct qla_hw_data *ha;
4753
4754 ha = (struct qla_hw_data *)data;
4755 base_vha = pci_get_drvdata(ha->pdev);
4756
4757 set_user_nice(current, -20);
4758
4759 set_current_state(TASK_INTERRUPTIBLE);
4760 while (!kthread_should_stop()) {
4761 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4762 "DPC handler sleeping.\n");
4763
4764 schedule();
4765 __set_current_state(TASK_RUNNING);
4766
4767 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4768 goto end_loop;
4769
4770 if (ha->flags.eeh_busy) {
4771 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4772 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4773 goto end_loop;
4774 }
4775
4776 ha->dpc_active = 1;
4777
4778 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4779 "DPC handler waking up, dpc_flags=0x%lx.\n",
4780 base_vha->dpc_flags);
4781
4782 qla2x00_do_work(base_vha);
4783
4784 if (IS_P3P_TYPE(ha)) {
4785 if (IS_QLA8044(ha)) {
4786 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4787 &base_vha->dpc_flags)) {
4788 qla8044_idc_lock(ha);
4789 qla8044_wr_direct(base_vha,
4790 QLA8044_CRB_DEV_STATE_INDEX,
4791 QLA8XXX_DEV_FAILED);
4792 qla8044_idc_unlock(ha);
4793 ql_log(ql_log_info, base_vha, 0x4004,
4794 "HW State: FAILED.\n");
4795 qla8044_device_state_handler(base_vha);
4796 continue;
4797 }
4798
4799 } else {
4800 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4801 &base_vha->dpc_flags)) {
4802 qla82xx_idc_lock(ha);
4803 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4804 QLA8XXX_DEV_FAILED);
4805 qla82xx_idc_unlock(ha);
4806 ql_log(ql_log_info, base_vha, 0x0151,
4807 "HW State: FAILED.\n");
4808 qla82xx_device_state_handler(base_vha);
4809 continue;
4810 }
4811 }
4812
4813 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4814 &base_vha->dpc_flags)) {
4815
4816 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4817 "FCoE context reset scheduled.\n");
4818 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4819 &base_vha->dpc_flags))) {
4820 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4821 /* FCoE-ctx reset failed.
4822 * Escalate to chip-reset
4823 */
4824 set_bit(ISP_ABORT_NEEDED,
4825 &base_vha->dpc_flags);
4826 }
4827 clear_bit(ABORT_ISP_ACTIVE,
4828 &base_vha->dpc_flags);
4829 }
4830
4831 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4832 "FCoE context reset end.\n");
4833 }
4834 } else if (IS_QLAFX00(ha)) {
4835 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4836 &base_vha->dpc_flags)) {
4837 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4838 "Firmware Reset Recovery\n");
4839 if (qlafx00_reset_initialize(base_vha)) {
4840 /* Failed. Abort isp later. */
4841 if (!test_bit(UNLOADING,
4842 &base_vha->dpc_flags))
4843 set_bit(ISP_UNRECOVERABLE,
4844 &base_vha->dpc_flags);
4845 ql_dbg(ql_dbg_dpc, base_vha,
4846 0x4021,
4847 "Reset Recovery Failed\n");
4848 }
4849 }
4850
4851 if (test_and_clear_bit(FX00_TARGET_SCAN,
4852 &base_vha->dpc_flags)) {
4853 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4854 "ISPFx00 Target Scan scheduled\n");
4855 if (qlafx00_rescan_isp(base_vha)) {
4856 if (!test_bit(UNLOADING,
4857 &base_vha->dpc_flags))
4858 set_bit(ISP_UNRECOVERABLE,
4859 &base_vha->dpc_flags);
4860 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4861 "ISPFx00 Target Scan Failed\n");
4862 }
4863 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4864 "ISPFx00 Target Scan End\n");
4865 }
4866 }
4867
4868 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4869 &base_vha->dpc_flags)) {
4870
4871 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4872 "ISP abort scheduled.\n");
4873 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4874 &base_vha->dpc_flags))) {
4875
4876 if (ha->isp_ops->abort_isp(base_vha)) {
4877 /* failed. retry later */
4878 set_bit(ISP_ABORT_NEEDED,
4879 &base_vha->dpc_flags);
4880 }
4881 clear_bit(ABORT_ISP_ACTIVE,
4882 &base_vha->dpc_flags);
4883 }
4884
4885 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4886 "ISP abort end.\n");
4887 }
4888
4889 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4890 &base_vha->dpc_flags)) {
4891 qla2x00_update_fcports(base_vha);
4892 }
4893
4894 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4895 int ret;
4896 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4897 if (ret != QLA_SUCCESS)
4898 ql_log(ql_log_warn, base_vha, 0x121,
4899 "Failed to enable receiving of RSCN "
4900 "requests: 0x%x.\n", ret);
4901 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4902 }
4903
4904 if (IS_QLAFX00(ha))
4905 goto loop_resync_check;
4906
4907 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4908 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4909 "Quiescence mode scheduled.\n");
4910 if (IS_P3P_TYPE(ha)) {
4911 if (IS_QLA82XX(ha))
4912 qla82xx_device_state_handler(base_vha);
4913 if (IS_QLA8044(ha))
4914 qla8044_device_state_handler(base_vha);
4915 clear_bit(ISP_QUIESCE_NEEDED,
4916 &base_vha->dpc_flags);
4917 if (!ha->flags.quiesce_owner) {
4918 qla2x00_perform_loop_resync(base_vha);
4919 if (IS_QLA82XX(ha)) {
4920 qla82xx_idc_lock(ha);
4921 qla82xx_clear_qsnt_ready(
4922 base_vha);
4923 qla82xx_idc_unlock(ha);
4924 } else if (IS_QLA8044(ha)) {
4925 qla8044_idc_lock(ha);
4926 qla8044_clear_qsnt_ready(
4927 base_vha);
4928 qla8044_idc_unlock(ha);
4929 }
4930 }
4931 } else {
4932 clear_bit(ISP_QUIESCE_NEEDED,
4933 &base_vha->dpc_flags);
4934 qla2x00_quiesce_io(base_vha);
4935 }
4936 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4937 "Quiescence mode end.\n");
4938 }
4939
4940 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4941 &base_vha->dpc_flags) &&
4942 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
4943
4944 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4945 "Reset marker scheduled.\n");
4946 qla2x00_rst_aen(base_vha);
4947 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
4948 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4949 "Reset marker end.\n");
4950 }
4951
4952 /* Retry each device up to login retry count */
4953 if ((test_and_clear_bit(RELOGIN_NEEDED,
4954 &base_vha->dpc_flags)) &&
4955 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4956 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
4957
4958 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4959 "Relogin scheduled.\n");
4960 qla2x00_relogin(base_vha);
4961 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4962 "Relogin end.\n");
4963 }
4964 loop_resync_check:
4965 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4966 &base_vha->dpc_flags)) {
4967
4968 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4969 "Loop resync scheduled.\n");
4970
4971 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
4972 &base_vha->dpc_flags))) {
4973
4974 rval = qla2x00_loop_resync(base_vha);
4975
4976 clear_bit(LOOP_RESYNC_ACTIVE,
4977 &base_vha->dpc_flags);
4978 }
4979
4980 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4981 "Loop resync end.\n");
4982 }
4983
4984 if (IS_QLAFX00(ha))
4985 goto intr_on_check;
4986
4987 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4988 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4989 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4990 qla2xxx_flash_npiv_conf(base_vha);
4991 }
4992
4993 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4994 &base_vha->dpc_flags)) {
4995 /* Prevents simultaneous ramp up and down */
4996 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4997 &base_vha->dpc_flags);
4998 qla2x00_host_ramp_down_queuedepth(base_vha);
4999 }
5000
5001 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5002 &base_vha->dpc_flags))
5003 qla2x00_host_ramp_up_queuedepth(base_vha);
5004 intr_on_check:
5005 if (!ha->interrupts_on)
5006 ha->isp_ops->enable_intrs(ha);
5007
5008 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5009 &base_vha->dpc_flags))
5010 ha->isp_ops->beacon_blink(base_vha);
5011
5012 if (!IS_QLAFX00(ha))
5013 qla2x00_do_dpc_all_vps(base_vha);
5014
5015 ha->dpc_active = 0;
5016 end_loop:
5017 set_current_state(TASK_INTERRUPTIBLE);
5018 } /* End of while(1) */
5019 __set_current_state(TASK_RUNNING);
5020
5021 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5022 "DPC handler exiting.\n");
5023
5024 /*
5025 * Make sure that nobody tries to wake us up again.
5026 */
5027 ha->dpc_active = 0;
5028
5029 /* Cleanup any residual CTX SRBs. */
5030 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5031
5032 return 0;
5033 }
5034
5035 void
5036 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5037 {
5038 struct qla_hw_data *ha = vha->hw;
5039 struct task_struct *t = ha->dpc_thread;
5040
5041 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5042 wake_up_process(t);
5043 }
5044
5045 /*
5046 * qla2x00_rst_aen
5047 * Processes asynchronous reset.
5048 *
5049 * Input:
5050 * ha = adapter block pointer.
5051 */
5052 static void
5053 qla2x00_rst_aen(scsi_qla_host_t *vha)
5054 {
5055 if (vha->flags.online && !vha->flags.reset_active &&
5056 !atomic_read(&vha->loop_down_timer) &&
5057 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5058 do {
5059 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5060
5061 /*
5062 * Issue marker command only when we are going to start
5063 * the I/O.
5064 */
5065 vha->marker_needed = 1;
5066 } while (!atomic_read(&vha->loop_down_timer) &&
5067 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5068 }
5069 }
5070
5071 /**************************************************************************
5072 * qla2x00_timer
5073 *
5074 * Description:
5075 * One second timer
5076 *
5077 * Context: Interrupt
5078 ***************************************************************************/
5079 void
5080 qla2x00_timer(scsi_qla_host_t *vha)
5081 {
5082 unsigned long cpu_flags = 0;
5083 int start_dpc = 0;
5084 int index;
5085 srb_t *sp;
5086 uint16_t w;
5087 struct qla_hw_data *ha = vha->hw;
5088 struct req_que *req;
5089
5090 if (ha->flags.eeh_busy) {
5091 ql_dbg(ql_dbg_timer, vha, 0x6000,
5092 "EEH = %d, restarting timer.\n",
5093 ha->flags.eeh_busy);
5094 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5095 return;
5096 }
5097
5098 /* Hardware read to raise pending EEH errors during mailbox waits. */
5099 if (!pci_channel_offline(ha->pdev))
5100 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5101
5102 /* Make sure qla82xx_watchdog is run only for physical port */
5103 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5104 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5105 start_dpc++;
5106 if (IS_QLA82XX(ha))
5107 qla82xx_watchdog(vha);
5108 else if (IS_QLA8044(ha))
5109 qla8044_watchdog(vha);
5110 }
5111
5112 if (!vha->vp_idx && IS_QLAFX00(ha))
5113 qlafx00_timer_routine(vha);
5114
5115 /* Loop down handler. */
5116 if (atomic_read(&vha->loop_down_timer) > 0 &&
5117 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5118 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5119 && vha->flags.online) {
5120
5121 if (atomic_read(&vha->loop_down_timer) ==
5122 vha->loop_down_abort_time) {
5123
5124 ql_log(ql_log_info, vha, 0x6008,
5125 "Loop down - aborting the queues before time expires.\n");
5126
5127 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5128 atomic_set(&vha->loop_state, LOOP_DEAD);
5129
5130 /*
5131 * Schedule an ISP abort to return any FCP2-device
5132 * commands.
5133 */
5134 /* NPIV - scan physical port only */
5135 if (!vha->vp_idx) {
5136 spin_lock_irqsave(&ha->hardware_lock,
5137 cpu_flags);
5138 req = ha->req_q_map[0];
5139 for (index = 1;
5140 index < req->num_outstanding_cmds;
5141 index++) {
5142 fc_port_t *sfcp;
5143
5144 sp = req->outstanding_cmds[index];
5145 if (!sp)
5146 continue;
5147 if (sp->type != SRB_SCSI_CMD)
5148 continue;
5149 sfcp = sp->fcport;
5150 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5151 continue;
5152
5153 if (IS_QLA82XX(ha))
5154 set_bit(FCOE_CTX_RESET_NEEDED,
5155 &vha->dpc_flags);
5156 else
5157 set_bit(ISP_ABORT_NEEDED,
5158 &vha->dpc_flags);
5159 break;
5160 }
5161 spin_unlock_irqrestore(&ha->hardware_lock,
5162 cpu_flags);
5163 }
5164 start_dpc++;
5165 }
5166
5167 /* if the loop has been down for 4 minutes, reinit adapter */
5168 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5169 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5170 ql_log(ql_log_warn, vha, 0x6009,
5171 "Loop down - aborting ISP.\n");
5172
5173 if (IS_QLA82XX(ha))
5174 set_bit(FCOE_CTX_RESET_NEEDED,
5175 &vha->dpc_flags);
5176 else
5177 set_bit(ISP_ABORT_NEEDED,
5178 &vha->dpc_flags);
5179 }
5180 }
5181 ql_dbg(ql_dbg_timer, vha, 0x600a,
5182 "Loop down - seconds remaining %d.\n",
5183 atomic_read(&vha->loop_down_timer));
5184 }
5185
5186 /* Check if beacon LED needs to be blinked for physical host only */
5187 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5188 /* There is no beacon_blink function for ISP82xx */
5189 if (!IS_P3P_TYPE(ha)) {
5190 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5191 start_dpc++;
5192 }
5193 }
5194
5195 /* Process any deferred work. */
5196 if (!list_empty(&vha->work_list))
5197 start_dpc++;
5198
5199 /* Schedule the DPC routine if needed */
5200 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5201 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5202 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5203 start_dpc ||
5204 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5205 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5206 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5207 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5208 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5209 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5210 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5211 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
5212 ql_dbg(ql_dbg_timer, vha, 0x600b,
5213 "isp_abort_needed=%d loop_resync_needed=%d "
5214 "fcport_update_needed=%d start_dpc=%d "
5215 "reset_marker_needed=%d",
5216 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5217 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5218 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5219 start_dpc,
5220 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5221 ql_dbg(ql_dbg_timer, vha, 0x600c,
5222 "beacon_blink_needed=%d isp_unrecoverable=%d "
5223 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5224 "relogin_needed=%d, host_ramp_down_needed=%d "
5225 "host_ramp_up_needed=%d.\n",
5226 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5227 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5228 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5229 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5230 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5231 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5232 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
5233 qla2xxx_wake_dpc(vha);
5234 }
5235
5236 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5237 }
5238
5239 /* Firmware interface routines. */
5240
5241 #define FW_BLOBS 10
5242 #define FW_ISP21XX 0
5243 #define FW_ISP22XX 1
5244 #define FW_ISP2300 2
5245 #define FW_ISP2322 3
5246 #define FW_ISP24XX 4
5247 #define FW_ISP25XX 5
5248 #define FW_ISP81XX 6
5249 #define FW_ISP82XX 7
5250 #define FW_ISP2031 8
5251 #define FW_ISP8031 9
5252
5253 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5254 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5255 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5256 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5257 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5258 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5259 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5260 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5261 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5262 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5263
5264 static DEFINE_MUTEX(qla_fw_lock);
5265
5266 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5267 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5268 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5269 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5270 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5271 { .name = FW_FILE_ISP24XX, },
5272 { .name = FW_FILE_ISP25XX, },
5273 { .name = FW_FILE_ISP81XX, },
5274 { .name = FW_FILE_ISP82XX, },
5275 { .name = FW_FILE_ISP2031, },
5276 { .name = FW_FILE_ISP8031, },
5277 };
5278
5279 struct fw_blob *
5280 qla2x00_request_firmware(scsi_qla_host_t *vha)
5281 {
5282 struct qla_hw_data *ha = vha->hw;
5283 struct fw_blob *blob;
5284
5285 if (IS_QLA2100(ha)) {
5286 blob = &qla_fw_blobs[FW_ISP21XX];
5287 } else if (IS_QLA2200(ha)) {
5288 blob = &qla_fw_blobs[FW_ISP22XX];
5289 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5290 blob = &qla_fw_blobs[FW_ISP2300];
5291 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5292 blob = &qla_fw_blobs[FW_ISP2322];
5293 } else if (IS_QLA24XX_TYPE(ha)) {
5294 blob = &qla_fw_blobs[FW_ISP24XX];
5295 } else if (IS_QLA25XX(ha)) {
5296 blob = &qla_fw_blobs[FW_ISP25XX];
5297 } else if (IS_QLA81XX(ha)) {
5298 blob = &qla_fw_blobs[FW_ISP81XX];
5299 } else if (IS_QLA82XX(ha)) {
5300 blob = &qla_fw_blobs[FW_ISP82XX];
5301 } else if (IS_QLA2031(ha)) {
5302 blob = &qla_fw_blobs[FW_ISP2031];
5303 } else if (IS_QLA8031(ha)) {
5304 blob = &qla_fw_blobs[FW_ISP8031];
5305 } else {
5306 return NULL;
5307 }
5308
5309 mutex_lock(&qla_fw_lock);
5310 if (blob->fw)
5311 goto out;
5312
5313 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5314 ql_log(ql_log_warn, vha, 0x0063,
5315 "Failed to load firmware image (%s).\n", blob->name);
5316 blob->fw = NULL;
5317 blob = NULL;
5318 goto out;
5319 }
5320
5321 out:
5322 mutex_unlock(&qla_fw_lock);
5323 return blob;
5324 }
5325
5326 static void
5327 qla2x00_release_firmware(void)
5328 {
5329 int idx;
5330
5331 mutex_lock(&qla_fw_lock);
5332 for (idx = 0; idx < FW_BLOBS; idx++)
5333 release_firmware(qla_fw_blobs[idx].fw);
5334 mutex_unlock(&qla_fw_lock);
5335 }
5336
5337 static pci_ers_result_t
5338 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5339 {
5340 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5341 struct qla_hw_data *ha = vha->hw;
5342
5343 ql_dbg(ql_dbg_aer, vha, 0x9000,
5344 "PCI error detected, state %x.\n", state);
5345
5346 switch (state) {
5347 case pci_channel_io_normal:
5348 ha->flags.eeh_busy = 0;
5349 return PCI_ERS_RESULT_CAN_RECOVER;
5350 case pci_channel_io_frozen:
5351 ha->flags.eeh_busy = 1;
5352 /* For ISP82XX complete any pending mailbox cmd */
5353 if (IS_QLA82XX(ha)) {
5354 ha->flags.isp82xx_fw_hung = 1;
5355 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5356 qla82xx_clear_pending_mbx(vha);
5357 }
5358 qla2x00_free_irqs(vha);
5359 pci_disable_device(pdev);
5360 /* Return back all IOs */
5361 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5362 return PCI_ERS_RESULT_NEED_RESET;
5363 case pci_channel_io_perm_failure:
5364 ha->flags.pci_channel_io_perm_failure = 1;
5365 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5366 return PCI_ERS_RESULT_DISCONNECT;
5367 }
5368 return PCI_ERS_RESULT_NEED_RESET;
5369 }
5370
5371 static pci_ers_result_t
5372 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5373 {
5374 int risc_paused = 0;
5375 uint32_t stat;
5376 unsigned long flags;
5377 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5378 struct qla_hw_data *ha = base_vha->hw;
5379 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5380 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5381
5382 if (IS_QLA82XX(ha))
5383 return PCI_ERS_RESULT_RECOVERED;
5384
5385 spin_lock_irqsave(&ha->hardware_lock, flags);
5386 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5387 stat = RD_REG_DWORD(&reg->hccr);
5388 if (stat & HCCR_RISC_PAUSE)
5389 risc_paused = 1;
5390 } else if (IS_QLA23XX(ha)) {
5391 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5392 if (stat & HSR_RISC_PAUSED)
5393 risc_paused = 1;
5394 } else if (IS_FWI2_CAPABLE(ha)) {
5395 stat = RD_REG_DWORD(&reg24->host_status);
5396 if (stat & HSRX_RISC_PAUSED)
5397 risc_paused = 1;
5398 }
5399 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5400
5401 if (risc_paused) {
5402 ql_log(ql_log_info, base_vha, 0x9003,
5403 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5404 ha->isp_ops->fw_dump(base_vha, 0);
5405
5406 return PCI_ERS_RESULT_NEED_RESET;
5407 } else
5408 return PCI_ERS_RESULT_RECOVERED;
5409 }
5410
5411 static uint32_t
5412 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5413 {
5414 uint32_t rval = QLA_FUNCTION_FAILED;
5415 uint32_t drv_active = 0;
5416 struct qla_hw_data *ha = base_vha->hw;
5417 int fn;
5418 struct pci_dev *other_pdev = NULL;
5419
5420 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5421 "Entered %s.\n", __func__);
5422
5423 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5424
5425 if (base_vha->flags.online) {
5426 /* Abort all outstanding commands,
5427 * so as to be requeued later */
5428 qla2x00_abort_isp_cleanup(base_vha);
5429 }
5430
5431
5432 fn = PCI_FUNC(ha->pdev->devfn);
5433 while (fn > 0) {
5434 fn--;
5435 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5436 "Finding pci device at function = 0x%x.\n", fn);
5437 other_pdev =
5438 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5439 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5440 fn));
5441
5442 if (!other_pdev)
5443 continue;
5444 if (atomic_read(&other_pdev->enable_cnt)) {
5445 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5446 "Found PCI func available and enable at 0x%x.\n",
5447 fn);
5448 pci_dev_put(other_pdev);
5449 break;
5450 }
5451 pci_dev_put(other_pdev);
5452 }
5453
5454 if (!fn) {
5455 /* Reset owner */
5456 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5457 "This devfn is reset owner = 0x%x.\n",
5458 ha->pdev->devfn);
5459 qla82xx_idc_lock(ha);
5460
5461 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5462 QLA8XXX_DEV_INITIALIZING);
5463
5464 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5465 QLA82XX_IDC_VERSION);
5466
5467 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5468 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5469 "drv_active = 0x%x.\n", drv_active);
5470
5471 qla82xx_idc_unlock(ha);
5472 /* Reset if device is not already reset
5473 * drv_active would be 0 if a reset has already been done
5474 */
5475 if (drv_active)
5476 rval = qla82xx_start_firmware(base_vha);
5477 else
5478 rval = QLA_SUCCESS;
5479 qla82xx_idc_lock(ha);
5480
5481 if (rval != QLA_SUCCESS) {
5482 ql_log(ql_log_info, base_vha, 0x900b,
5483 "HW State: FAILED.\n");
5484 qla82xx_clear_drv_active(ha);
5485 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5486 QLA8XXX_DEV_FAILED);
5487 } else {
5488 ql_log(ql_log_info, base_vha, 0x900c,
5489 "HW State: READY.\n");
5490 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5491 QLA8XXX_DEV_READY);
5492 qla82xx_idc_unlock(ha);
5493 ha->flags.isp82xx_fw_hung = 0;
5494 rval = qla82xx_restart_isp(base_vha);
5495 qla82xx_idc_lock(ha);
5496 /* Clear driver state register */
5497 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5498 qla82xx_set_drv_active(base_vha);
5499 }
5500 qla82xx_idc_unlock(ha);
5501 } else {
5502 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5503 "This devfn is not reset owner = 0x%x.\n",
5504 ha->pdev->devfn);
5505 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5506 QLA8XXX_DEV_READY)) {
5507 ha->flags.isp82xx_fw_hung = 0;
5508 rval = qla82xx_restart_isp(base_vha);
5509 qla82xx_idc_lock(ha);
5510 qla82xx_set_drv_active(base_vha);
5511 qla82xx_idc_unlock(ha);
5512 }
5513 }
5514 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5515
5516 return rval;
5517 }
5518
5519 static pci_ers_result_t
5520 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5521 {
5522 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5523 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5524 struct qla_hw_data *ha = base_vha->hw;
5525 struct rsp_que *rsp;
5526 int rc, retries = 10;
5527
5528 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5529 "Slot Reset.\n");
5530
5531 /* Workaround: qla2xxx driver which access hardware earlier
5532 * needs error state to be pci_channel_io_online.
5533 * Otherwise mailbox command timesout.
5534 */
5535 pdev->error_state = pci_channel_io_normal;
5536
5537 pci_restore_state(pdev);
5538
5539 /* pci_restore_state() clears the saved_state flag of the device
5540 * save restored state which resets saved_state flag
5541 */
5542 pci_save_state(pdev);
5543
5544 if (ha->mem_only)
5545 rc = pci_enable_device_mem(pdev);
5546 else
5547 rc = pci_enable_device(pdev);
5548
5549 if (rc) {
5550 ql_log(ql_log_warn, base_vha, 0x9005,
5551 "Can't re-enable PCI device after reset.\n");
5552 goto exit_slot_reset;
5553 }
5554
5555 rsp = ha->rsp_q_map[0];
5556 if (qla2x00_request_irqs(ha, rsp))
5557 goto exit_slot_reset;
5558
5559 if (ha->isp_ops->pci_config(base_vha))
5560 goto exit_slot_reset;
5561
5562 if (IS_QLA82XX(ha)) {
5563 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5564 ret = PCI_ERS_RESULT_RECOVERED;
5565 goto exit_slot_reset;
5566 } else
5567 goto exit_slot_reset;
5568 }
5569
5570 while (ha->flags.mbox_busy && retries--)
5571 msleep(1000);
5572
5573 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5574 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5575 ret = PCI_ERS_RESULT_RECOVERED;
5576 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5577
5578
5579 exit_slot_reset:
5580 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5581 "slot_reset return %x.\n", ret);
5582
5583 return ret;
5584 }
5585
5586 static void
5587 qla2xxx_pci_resume(struct pci_dev *pdev)
5588 {
5589 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5590 struct qla_hw_data *ha = base_vha->hw;
5591 int ret;
5592
5593 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5594 "pci_resume.\n");
5595
5596 ret = qla2x00_wait_for_hba_online(base_vha);
5597 if (ret != QLA_SUCCESS) {
5598 ql_log(ql_log_fatal, base_vha, 0x9002,
5599 "The device failed to resume I/O from slot/link_reset.\n");
5600 }
5601
5602 pci_cleanup_aer_uncorrect_error_status(pdev);
5603
5604 ha->flags.eeh_busy = 0;
5605 }
5606
5607 static const struct pci_error_handlers qla2xxx_err_handler = {
5608 .error_detected = qla2xxx_pci_error_detected,
5609 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5610 .slot_reset = qla2xxx_pci_slot_reset,
5611 .resume = qla2xxx_pci_resume,
5612 };
5613
5614 static struct pci_device_id qla2xxx_pci_tbl[] = {
5615 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5616 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5617 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5618 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5634 { 0 },
5635 };
5636 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5637
5638 static struct pci_driver qla2xxx_pci_driver = {
5639 .name = QLA2XXX_DRIVER_NAME,
5640 .driver = {
5641 .owner = THIS_MODULE,
5642 },
5643 .id_table = qla2xxx_pci_tbl,
5644 .probe = qla2x00_probe_one,
5645 .remove = qla2x00_remove_one,
5646 .shutdown = qla2x00_shutdown,
5647 .err_handler = &qla2xxx_err_handler,
5648 };
5649
5650 static const struct file_operations apidev_fops = {
5651 .owner = THIS_MODULE,
5652 .llseek = noop_llseek,
5653 };
5654
5655 /**
5656 * qla2x00_module_init - Module initialization.
5657 **/
5658 static int __init
5659 qla2x00_module_init(void)
5660 {
5661 int ret = 0;
5662
5663 /* Allocate cache for SRBs. */
5664 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5665 SLAB_HWCACHE_ALIGN, NULL);
5666 if (srb_cachep == NULL) {
5667 ql_log(ql_log_fatal, NULL, 0x0001,
5668 "Unable to allocate SRB cache...Failing load!.\n");
5669 return -ENOMEM;
5670 }
5671
5672 /* Initialize target kmem_cache and mem_pools */
5673 ret = qlt_init();
5674 if (ret < 0) {
5675 kmem_cache_destroy(srb_cachep);
5676 return ret;
5677 } else if (ret > 0) {
5678 /*
5679 * If initiator mode is explictly disabled by qlt_init(),
5680 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5681 * performing scsi_scan_target() during LOOP UP event.
5682 */
5683 qla2xxx_transport_functions.disable_target_scan = 1;
5684 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5685 }
5686
5687 /* Derive version string. */
5688 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5689 if (ql2xextended_error_logging)
5690 strcat(qla2x00_version_str, "-debug");
5691
5692 qla2xxx_transport_template =
5693 fc_attach_transport(&qla2xxx_transport_functions);
5694 if (!qla2xxx_transport_template) {
5695 kmem_cache_destroy(srb_cachep);
5696 ql_log(ql_log_fatal, NULL, 0x0002,
5697 "fc_attach_transport failed...Failing load!.\n");
5698 qlt_exit();
5699 return -ENODEV;
5700 }
5701
5702 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5703 if (apidev_major < 0) {
5704 ql_log(ql_log_fatal, NULL, 0x0003,
5705 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5706 }
5707
5708 qla2xxx_transport_vport_template =
5709 fc_attach_transport(&qla2xxx_transport_vport_functions);
5710 if (!qla2xxx_transport_vport_template) {
5711 kmem_cache_destroy(srb_cachep);
5712 qlt_exit();
5713 fc_release_transport(qla2xxx_transport_template);
5714 ql_log(ql_log_fatal, NULL, 0x0004,
5715 "fc_attach_transport vport failed...Failing load!.\n");
5716 return -ENODEV;
5717 }
5718 ql_log(ql_log_info, NULL, 0x0005,
5719 "QLogic Fibre Channel HBA Driver: %s.\n",
5720 qla2x00_version_str);
5721 ret = pci_register_driver(&qla2xxx_pci_driver);
5722 if (ret) {
5723 kmem_cache_destroy(srb_cachep);
5724 qlt_exit();
5725 fc_release_transport(qla2xxx_transport_template);
5726 fc_release_transport(qla2xxx_transport_vport_template);
5727 ql_log(ql_log_fatal, NULL, 0x0006,
5728 "pci_register_driver failed...ret=%d Failing load!.\n",
5729 ret);
5730 }
5731 return ret;
5732 }
5733
5734 /**
5735 * qla2x00_module_exit - Module cleanup.
5736 **/
5737 static void __exit
5738 qla2x00_module_exit(void)
5739 {
5740 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5741 pci_unregister_driver(&qla2xxx_pci_driver);
5742 qla2x00_release_firmware();
5743 kmem_cache_destroy(srb_cachep);
5744 qlt_exit();
5745 if (ctx_cachep)
5746 kmem_cache_destroy(ctx_cachep);
5747 fc_release_transport(qla2xxx_transport_template);
5748 fc_release_transport(qla2xxx_transport_vport_template);
5749 }
5750
5751 module_init(qla2x00_module_init);
5752 module_exit(qla2x00_module_exit);
5753
5754 MODULE_AUTHOR("QLogic Corporation");
5755 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5756 MODULE_LICENSE("GPL");
5757 MODULE_VERSION(QLA2XXX_VERSION);
5758 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5759 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5760 MODULE_FIRMWARE(FW_FILE_ISP2300);
5761 MODULE_FIRMWARE(FW_FILE_ISP2322);
5762 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5763 MODULE_FIRMWARE(FW_FILE_ISP25XX);