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1db4819261cd802f75c6b7a50b523540006b4fe0
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
20
21 #include "qla_target.h"
22
23 /*
24 * Driver version
25 */
26 char qla2x00_version_str[40];
27
28 static int apidev_major;
29
30 /*
31 * SRB allocation cache
32 */
33 static struct kmem_cache *srb_cachep;
34
35 /*
36 * CT6 CTX allocation cache
37 */
38 static struct kmem_cache *ctx_cachep;
39 /*
40 * error level for logging
41 */
42 int ql_errlev = ql_log_all;
43
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
50
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
61
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
100
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
112
113 int ql2xmaxqdepth = MAX_Q_DEPTH;
114 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115 MODULE_PARM_DESC(ql2xmaxqdepth,
116 "Maximum queue depth to set for each LUN. "
117 "Default is 32.");
118
119 int ql2xenabledif = 2;
120 module_param(ql2xenabledif, int, S_IRUGO);
121 MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
125
126 int ql2xenablehba_err_chk = 2;
127 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128 MODULE_PARM_DESC(ql2xenablehba_err_chk,
129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
134
135 int ql2xiidmaenable=1;
136 module_param(ql2xiidmaenable, int, S_IRUGO);
137 MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
141 int ql2xmaxqueues = 1;
142 module_param(ql2xmaxqueues, int, S_IRUGO);
143 MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
147
148 int ql2xmultique_tag;
149 module_param(ql2xmultique_tag, int, S_IRUGO);
150 MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
154
155 int ql2xfwloadbin;
156 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
157 MODULE_PARM_DESC(ql2xfwloadbin,
158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
164 int ql2xetsenable;
165 module_param(ql2xetsenable, int, S_IRUGO);
166 MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
170 int ql2xdbwr = 1;
171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xdbwr,
173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
176
177 int ql2xtargetreset = 1;
178 module_param(ql2xtargetreset, int, S_IRUGO);
179 MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
183 int ql2xgffidenable;
184 module_param(ql2xgffidenable, int, S_IRUGO);
185 MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
188
189 int ql2xasynctmfenable;
190 module_param(ql2xasynctmfenable, int, S_IRUGO);
191 MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
194
195 int ql2xdontresethba;
196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
197 MODULE_PARM_DESC(ql2xdontresethba,
198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
201
202 uint ql2xmaxlun = MAX_LUNS;
203 module_param(ql2xmaxlun, uint, S_IRUGO);
204 MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
208 int ql2xmdcapmask = 0x1F;
209 module_param(ql2xmdcapmask, int, S_IRUGO);
210 MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
213
214 int ql2xmdenable = 1;
215 module_param(ql2xmdenable, int, S_IRUGO);
216 MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
220
221 /*
222 * SCSI host template entry points
223 */
224 static int qla2xxx_slave_configure(struct scsi_device * device);
225 static int qla2xxx_slave_alloc(struct scsi_device *);
226 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227 static void qla2xxx_scan_start(struct Scsi_Host *);
228 static void qla2xxx_slave_destroy(struct scsi_device *);
229 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
230 static int qla2xxx_eh_abort(struct scsi_cmnd *);
231 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
232 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
233 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
235
236 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
237 static int qla2x00_change_queue_type(struct scsi_device *, int);
238 static void qla2x00_free_device(scsi_qla_host_t *);
239
240 struct scsi_host_template qla2xxx_driver_template = {
241 .module = THIS_MODULE,
242 .name = QLA2XXX_DRIVER_NAME,
243 .queuecommand = qla2xxx_queuecommand,
244
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
250
251 .slave_configure = qla2xxx_slave_configure,
252
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
259 .this_id = -1,
260 .cmd_per_lun = 3,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
263
264 .max_sectors = 0xFFFF,
265 .shost_attrs = qla2x00_host_attrs,
266
267 .supported_mode = MODE_INITIATOR,
268 };
269
270 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
271 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
272
273 /* TODO Convert to inlines
274 *
275 * Timer routines
276 */
277
278 __inline__ void
279 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
280 {
281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
287 }
288
289 static inline void
290 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
291 {
292 /* Currently used for 82XX only. */
293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
296 return;
297 }
298
299 mod_timer(&vha->timer, jiffies + interval * HZ);
300 }
301
302 static __inline__ void
303 qla2x00_stop_timer(scsi_qla_host_t *vha)
304 {
305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
307 }
308
309 static int qla2x00_do_dpc(void *data);
310
311 static void qla2x00_rst_aen(scsi_qla_host_t *);
312
313 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
315 static void qla2x00_free_fw_dump(struct qla_hw_data *);
316 static void qla2x00_mem_free(struct qla_hw_data *);
317
318 /* -------------------------------------------------------------------------- */
319 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
320 struct rsp_que *rsp)
321 {
322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
324 GFP_KERNEL);
325 if (!ha->req_q_map) {
326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
328 goto fail_req_map;
329 }
330
331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
332 GFP_KERNEL);
333 if (!ha->rsp_q_map) {
334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
336 goto fail_rsp_map;
337 }
338 /*
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
341 */
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
346 return 1;
347
348 fail_rsp_map:
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
351 fail_req_map:
352 return -ENOMEM;
353 }
354
355 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
356 {
357 if (IS_QLAFX00(ha)) {
358 if (req && req->ring_fx00)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length_fx00 + 1) * sizeof(request_t),
361 req->ring_fx00, req->dma_fx00);
362 } else if (req && req->ring)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length + 1) * sizeof(request_t),
365 req->ring, req->dma);
366
367 if (req)
368 kfree(req->outstanding_cmds);
369
370 kfree(req);
371 req = NULL;
372 }
373
374 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
375 {
376 if (IS_QLAFX00(ha)) {
377 if (rsp && rsp->ring)
378 dma_free_coherent(&ha->pdev->dev,
379 (rsp->length_fx00 + 1) * sizeof(request_t),
380 rsp->ring_fx00, rsp->dma_fx00);
381 } else if (rsp && rsp->ring) {
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length + 1) * sizeof(response_t),
384 rsp->ring, rsp->dma);
385 }
386 kfree(rsp);
387 rsp = NULL;
388 }
389
390 static void qla2x00_free_queues(struct qla_hw_data *ha)
391 {
392 struct req_que *req;
393 struct rsp_que *rsp;
394 int cnt;
395
396 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
397 req = ha->req_q_map[cnt];
398 qla2x00_free_req_que(ha, req);
399 }
400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
402
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 rsp = ha->rsp_q_map[cnt];
405 qla2x00_free_rsp_que(ha, rsp);
406 }
407 kfree(ha->rsp_q_map);
408 ha->rsp_q_map = NULL;
409 }
410
411 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
412 {
413 uint16_t options = 0;
414 int ques, req, ret;
415 struct qla_hw_data *ha = vha->hw;
416
417 if (!(ha->fw_attributes & BIT_6)) {
418 ql_log(ql_log_warn, vha, 0x00d8,
419 "Firmware is not multi-queue capable.\n");
420 goto fail;
421 }
422 if (ql2xmultique_tag) {
423 /* create a request queue for IO */
424 options |= BIT_7;
425 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
426 QLA_DEFAULT_QUE_QOS);
427 if (!req) {
428 ql_log(ql_log_warn, vha, 0x00e0,
429 "Failed to create request queue.\n");
430 goto fail;
431 }
432 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
433 vha->req = ha->req_q_map[req];
434 options |= BIT_1;
435 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
436 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
437 if (!ret) {
438 ql_log(ql_log_warn, vha, 0x00e8,
439 "Failed to create response queue.\n");
440 goto fail2;
441 }
442 }
443 ha->flags.cpu_affinity_enabled = 1;
444 ql_dbg(ql_dbg_multiq, vha, 0xc007,
445 "CPU affinity mode enalbed, "
446 "no. of response queues:%d no. of request queues:%d.\n",
447 ha->max_rsp_queues, ha->max_req_queues);
448 ql_dbg(ql_dbg_init, vha, 0x00e9,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 }
453 return 0;
454 fail2:
455 qla25xx_delete_queues(vha);
456 destroy_workqueue(ha->wq);
457 ha->wq = NULL;
458 vha->req = ha->req_q_map[0];
459 fail:
460 ha->mqenable = 0;
461 kfree(ha->req_q_map);
462 kfree(ha->rsp_q_map);
463 ha->max_req_queues = ha->max_rsp_queues = 1;
464 return 1;
465 }
466
467 static char *
468 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
469 {
470 struct qla_hw_data *ha = vha->hw;
471 static char *pci_bus_modes[] = {
472 "33", "66", "100", "133",
473 };
474 uint16_t pci_bus;
475
476 strcpy(str, "PCI");
477 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
478 if (pci_bus) {
479 strcat(str, "-X (");
480 strcat(str, pci_bus_modes[pci_bus]);
481 } else {
482 pci_bus = (ha->pci_attr & BIT_8) >> 8;
483 strcat(str, " (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 }
486 strcat(str, " MHz)");
487
488 return (str);
489 }
490
491 static char *
492 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
493 {
494 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
495 struct qla_hw_data *ha = vha->hw;
496 uint32_t pci_bus;
497 int pcie_reg;
498
499 pcie_reg = pci_pcie_cap(ha->pdev);
500 if (pcie_reg) {
501 char lwstr[6];
502 uint16_t pcie_lstat, lspeed, lwidth;
503
504 pcie_reg += PCI_EXP_LNKCAP;
505 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
506 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
507 lwidth = (pcie_lstat &
508 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
509
510 strcpy(str, "PCIe (");
511 switch (lspeed) {
512 case 1:
513 strcat(str, "2.5GT/s ");
514 break;
515 case 2:
516 strcat(str, "5.0GT/s ");
517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
522 strcat(str, "<unknown> ");
523 break;
524 }
525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548 }
549
550 static char *
551 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
552 {
553 char un_str[10];
554 struct qla_hw_data *ha = vha->hw;
555
556 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version,
558 ha->fw_subminor_version);
559
560 if (ha->fw_attributes & BIT_9) {
561 strcat(str, "FLX");
562 return (str);
563 }
564
565 switch (ha->fw_attributes & 0xFF) {
566 case 0x7:
567 strcat(str, "EF");
568 break;
569 case 0x17:
570 strcat(str, "TP");
571 break;
572 case 0x37:
573 strcat(str, "IP");
574 break;
575 case 0x77:
576 strcat(str, "VI");
577 break;
578 default:
579 sprintf(un_str, "(%x)", ha->fw_attributes);
580 strcat(str, un_str);
581 break;
582 }
583 if (ha->fw_attributes & 0x100)
584 strcat(str, "X");
585
586 return (str);
587 }
588
589 static char *
590 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
591 {
592 struct qla_hw_data *ha = vha->hw;
593
594 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
596 return str;
597 }
598
599 void
600 qla2x00_sp_free_dma(void *vha, void *ptr)
601 {
602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
606
607 if (sp->flags & SRB_DMA_VALID) {
608 scsi_dma_unmap(cmd);
609 sp->flags &= ~SRB_DMA_VALID;
610 }
611
612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
620 qla2x00_clean_dsd_pool(ha, sp);
621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
622 }
623
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
628 }
629
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
632
633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
634 ctx1->fcp_cmnd_dma);
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
639 ctx1 = NULL;
640 }
641
642 CMD_SP(cmd) = NULL;
643 qla2x00_rel_sp(sp->fcport->vha, sp);
644 }
645
646 static void
647 qla2x00_sp_compl(void *data, void *ptr, int res)
648 {
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
652
653 cmd->result = res;
654
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
658 sp, GET_CMD_SP(sp));
659 if (ql2xextended_error_logging & ql_dbg_io)
660 BUG();
661 return;
662 }
663 if (!atomic_dec_and_test(&sp->ref_count))
664 return;
665
666 qla2x00_sp_free_dma(ha, sp);
667 cmd->scsi_done(cmd);
668 }
669
670 /* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
672 */
673 static int
674 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
675 {
676 scsi_qla_host_t *vha = shost_priv(host);
677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
681 srb_t *sp;
682 int rval;
683
684 if (ha->flags.eeh_busy) {
685 if (ha->flags.pci_channel_io_perm_failure) {
686 ql_dbg(ql_dbg_aer, vha, 0x9010,
687 "PCI Channel IO permanent failure, exiting "
688 "cmd=%p.\n", cmd);
689 cmd->result = DID_NO_CONNECT << 16;
690 } else {
691 ql_dbg(ql_dbg_aer, vha, 0x9011,
692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
693 cmd->result = DID_REQUEUE << 16;
694 }
695 goto qc24_fail_command;
696 }
697
698 rval = fc_remote_port_chkready(rport);
699 if (rval) {
700 cmd->result = rval;
701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
703 cmd, rval);
704 goto qc24_fail_command;
705 }
706
707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
711 cmd);
712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
714 }
715
716 if (!fcport) {
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
719 }
720
721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
730 }
731 goto qc24_target_busy;
732 }
733
734 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
735 if (!sp) {
736 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
737 goto qc24_host_busy;
738 }
739
740 sp->u.scmd.cmd = cmd;
741 sp->type = SRB_SCSI_CMD;
742 atomic_set(&sp->ref_count, 1);
743 CMD_SP(cmd) = (void *)sp;
744 sp->free = qla2x00_sp_free_dma;
745 sp->done = qla2x00_sp_compl;
746
747 rval = ha->isp_ops->start_scsi(sp);
748 if (rval != QLA_SUCCESS) {
749 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
750 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
751 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
752 goto qc24_host_busy_free_sp;
753 }
754
755 return 0;
756
757 qc24_host_busy_free_sp:
758 qla2x00_sp_free_dma(ha, sp);
759
760 qc24_host_busy:
761 return SCSI_MLQUEUE_HOST_BUSY;
762
763 qc24_target_busy:
764 return SCSI_MLQUEUE_TARGET_BUSY;
765
766 qc24_fail_command:
767 cmd->scsi_done(cmd);
768
769 return 0;
770 }
771
772 /*
773 * qla2x00_eh_wait_on_command
774 * Waits for the command to be returned by the Firmware for some
775 * max time.
776 *
777 * Input:
778 * cmd = Scsi Command to wait on.
779 *
780 * Return:
781 * Not Found : 0
782 * Found : 1
783 */
784 static int
785 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
786 {
787 #define ABORT_POLLING_PERIOD 1000
788 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
789 unsigned long wait_iter = ABORT_WAIT_ITER;
790 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
791 struct qla_hw_data *ha = vha->hw;
792 int ret = QLA_SUCCESS;
793
794 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
795 ql_dbg(ql_dbg_taskm, vha, 0x8005,
796 "Return:eh_wait.\n");
797 return ret;
798 }
799
800 while (CMD_SP(cmd) && wait_iter--) {
801 msleep(ABORT_POLLING_PERIOD);
802 }
803 if (CMD_SP(cmd))
804 ret = QLA_FUNCTION_FAILED;
805
806 return ret;
807 }
808
809 /*
810 * qla2x00_wait_for_hba_online
811 * Wait till the HBA is online after going through
812 * <= MAX_RETRIES_OF_ISP_ABORT or
813 * finally HBA is disabled ie marked offline
814 *
815 * Input:
816 * ha - pointer to host adapter structure
817 *
818 * Note:
819 * Does context switching-Release SPIN_LOCK
820 * (if any) before calling this routine.
821 *
822 * Return:
823 * Success (Adapter is online) : 0
824 * Failed (Adapter is offline/disabled) : 1
825 */
826 int
827 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
828 {
829 int return_status;
830 unsigned long wait_online;
831 struct qla_hw_data *ha = vha->hw;
832 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
833
834 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
835 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
836 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
837 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
838 ha->dpc_active) && time_before(jiffies, wait_online)) {
839
840 msleep(1000);
841 }
842 if (base_vha->flags.online)
843 return_status = QLA_SUCCESS;
844 else
845 return_status = QLA_FUNCTION_FAILED;
846
847 return (return_status);
848 }
849
850 /*
851 * qla2x00_wait_for_reset_ready
852 * Wait till the HBA is online after going through
853 * <= MAX_RETRIES_OF_ISP_ABORT or
854 * finally HBA is disabled ie marked offline or flash
855 * operations are in progress.
856 *
857 * Input:
858 * ha - pointer to host adapter structure
859 *
860 * Note:
861 * Does context switching-Release SPIN_LOCK
862 * (if any) before calling this routine.
863 *
864 * Return:
865 * Success (Adapter is online/no flash ops) : 0
866 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
867 */
868 static int
869 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
870 {
871 int return_status;
872 unsigned long wait_online;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
875
876 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->optrom_state != QLA_SWAITING ||
881 ha->dpc_active) && time_before(jiffies, wait_online))
882 msleep(1000);
883
884 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
885 return_status = QLA_SUCCESS;
886 else
887 return_status = QLA_FUNCTION_FAILED;
888
889 ql_dbg(ql_dbg_taskm, vha, 0x8019,
890 "%s return status=%d.\n", __func__, return_status);
891
892 return return_status;
893 }
894
895 int
896 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
897 {
898 int return_status;
899 unsigned long wait_reset;
900 struct qla_hw_data *ha = vha->hw;
901 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
902
903 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
904 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
905 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
906 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
907 ha->dpc_active) && time_before(jiffies, wait_reset)) {
908
909 msleep(1000);
910
911 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
912 ha->flags.chip_reset_done)
913 break;
914 }
915 if (ha->flags.chip_reset_done)
916 return_status = QLA_SUCCESS;
917 else
918 return_status = QLA_FUNCTION_FAILED;
919
920 return return_status;
921 }
922
923 static void
924 sp_get(struct srb *sp)
925 {
926 atomic_inc(&sp->ref_count);
927 }
928
929 /**************************************************************************
930 * qla2xxx_eh_abort
931 *
932 * Description:
933 * The abort function will abort the specified command.
934 *
935 * Input:
936 * cmd = Linux SCSI command packet to be aborted.
937 *
938 * Returns:
939 * Either SUCCESS or FAILED.
940 *
941 * Note:
942 * Only return FAILED if command not returned by firmware.
943 **************************************************************************/
944 static int
945 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
946 {
947 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
948 srb_t *sp;
949 int ret;
950 unsigned int id, lun;
951 unsigned long flags;
952 int wait = 0;
953 struct qla_hw_data *ha = vha->hw;
954
955 if (!CMD_SP(cmd))
956 return SUCCESS;
957
958 ret = fc_block_scsi_eh(cmd);
959 if (ret != 0)
960 return ret;
961 ret = SUCCESS;
962
963 id = cmd->device->id;
964 lun = cmd->device->lun;
965
966 spin_lock_irqsave(&ha->hardware_lock, flags);
967 sp = (srb_t *) CMD_SP(cmd);
968 if (!sp) {
969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
970 return SUCCESS;
971 }
972
973 ql_dbg(ql_dbg_taskm, vha, 0x8002,
974 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
975 vha->host_no, id, lun, sp, cmd);
976
977 /* Get a reference to the sp and drop the lock.*/
978 sp_get(sp);
979
980 spin_unlock_irqrestore(&ha->hardware_lock, flags);
981 if (ha->isp_ops->abort_command(sp)) {
982 ret = FAILED;
983 ql_dbg(ql_dbg_taskm, vha, 0x8003,
984 "Abort command mbx failed cmd=%p.\n", cmd);
985 } else {
986 ql_dbg(ql_dbg_taskm, vha, 0x8004,
987 "Abort command mbx success cmd=%p.\n", cmd);
988 wait = 1;
989 }
990
991 spin_lock_irqsave(&ha->hardware_lock, flags);
992 sp->done(ha, sp, 0);
993 spin_unlock_irqrestore(&ha->hardware_lock, flags);
994
995 /* Did the command return during mailbox execution? */
996 if (ret == FAILED && !CMD_SP(cmd))
997 ret = SUCCESS;
998
999 /* Wait for the command to be returned. */
1000 if (wait) {
1001 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1002 ql_log(ql_log_warn, vha, 0x8006,
1003 "Abort handler timed out cmd=%p.\n", cmd);
1004 ret = FAILED;
1005 }
1006 }
1007
1008 ql_log(ql_log_info, vha, 0x801c,
1009 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1010 vha->host_no, id, lun, wait, ret);
1011
1012 return ret;
1013 }
1014
1015 int
1016 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1017 unsigned int l, enum nexus_wait_type type)
1018 {
1019 int cnt, match, status;
1020 unsigned long flags;
1021 struct qla_hw_data *ha = vha->hw;
1022 struct req_que *req;
1023 srb_t *sp;
1024 struct scsi_cmnd *cmd;
1025
1026 status = QLA_SUCCESS;
1027
1028 spin_lock_irqsave(&ha->hardware_lock, flags);
1029 req = vha->req;
1030 for (cnt = 1; status == QLA_SUCCESS &&
1031 cnt < req->num_outstanding_cmds; cnt++) {
1032 sp = req->outstanding_cmds[cnt];
1033 if (!sp)
1034 continue;
1035 if (sp->type != SRB_SCSI_CMD)
1036 continue;
1037 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1038 continue;
1039 match = 0;
1040 cmd = GET_CMD_SP(sp);
1041 switch (type) {
1042 case WAIT_HOST:
1043 match = 1;
1044 break;
1045 case WAIT_TARGET:
1046 match = cmd->device->id == t;
1047 break;
1048 case WAIT_LUN:
1049 match = (cmd->device->id == t &&
1050 cmd->device->lun == l);
1051 break;
1052 }
1053 if (!match)
1054 continue;
1055
1056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1057 status = qla2x00_eh_wait_on_command(cmd);
1058 spin_lock_irqsave(&ha->hardware_lock, flags);
1059 }
1060 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1061
1062 return status;
1063 }
1064
1065 static char *reset_errors[] = {
1066 "HBA not online",
1067 "HBA not ready",
1068 "Task management failed",
1069 "Waiting for command completions",
1070 };
1071
1072 static int
1073 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1074 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1075 {
1076 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1077 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1078 int err;
1079
1080 if (!fcport) {
1081 return FAILED;
1082 }
1083
1084 err = fc_block_scsi_eh(cmd);
1085 if (err != 0)
1086 return err;
1087
1088 ql_log(ql_log_info, vha, 0x8009,
1089 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
1090 cmd->device->id, cmd->device->lun, cmd);
1091
1092 err = 0;
1093 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1094 ql_log(ql_log_warn, vha, 0x800a,
1095 "Wait for hba online failed for cmd=%p.\n", cmd);
1096 goto eh_reset_failed;
1097 }
1098 err = 2;
1099 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1100 != QLA_SUCCESS) {
1101 ql_log(ql_log_warn, vha, 0x800c,
1102 "do_reset failed for cmd=%p.\n", cmd);
1103 goto eh_reset_failed;
1104 }
1105 err = 3;
1106 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1107 cmd->device->lun, type) != QLA_SUCCESS) {
1108 ql_log(ql_log_warn, vha, 0x800d,
1109 "wait for pending cmds failed for cmd=%p.\n", cmd);
1110 goto eh_reset_failed;
1111 }
1112
1113 ql_log(ql_log_info, vha, 0x800e,
1114 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1115 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1116
1117 return SUCCESS;
1118
1119 eh_reset_failed:
1120 ql_log(ql_log_info, vha, 0x800f,
1121 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1122 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1123 cmd);
1124 return FAILED;
1125 }
1126
1127 static int
1128 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1129 {
1130 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1131 struct qla_hw_data *ha = vha->hw;
1132
1133 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1134 ha->isp_ops->lun_reset);
1135 }
1136
1137 static int
1138 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1139 {
1140 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1141 struct qla_hw_data *ha = vha->hw;
1142
1143 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1144 ha->isp_ops->target_reset);
1145 }
1146
1147 /**************************************************************************
1148 * qla2xxx_eh_bus_reset
1149 *
1150 * Description:
1151 * The bus reset function will reset the bus and abort any executing
1152 * commands.
1153 *
1154 * Input:
1155 * cmd = Linux SCSI command packet of the command that cause the
1156 * bus reset.
1157 *
1158 * Returns:
1159 * SUCCESS/FAILURE (defined as macro in scsi.h).
1160 *
1161 **************************************************************************/
1162 static int
1163 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1164 {
1165 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1166 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1167 int ret = FAILED;
1168 unsigned int id, lun;
1169
1170 id = cmd->device->id;
1171 lun = cmd->device->lun;
1172
1173 if (!fcport) {
1174 return ret;
1175 }
1176
1177 ret = fc_block_scsi_eh(cmd);
1178 if (ret != 0)
1179 return ret;
1180 ret = FAILED;
1181
1182 ql_log(ql_log_info, vha, 0x8012,
1183 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1184
1185 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1186 ql_log(ql_log_fatal, vha, 0x8013,
1187 "Wait for hba online failed board disabled.\n");
1188 goto eh_bus_reset_done;
1189 }
1190
1191 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1192 ret = SUCCESS;
1193
1194 if (ret == FAILED)
1195 goto eh_bus_reset_done;
1196
1197 /* Flush outstanding commands. */
1198 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1199 QLA_SUCCESS) {
1200 ql_log(ql_log_warn, vha, 0x8014,
1201 "Wait for pending commands failed.\n");
1202 ret = FAILED;
1203 }
1204
1205 eh_bus_reset_done:
1206 ql_log(ql_log_warn, vha, 0x802b,
1207 "BUS RESET %s nexus=%ld:%d:%d.\n",
1208 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1209
1210 return ret;
1211 }
1212
1213 /**************************************************************************
1214 * qla2xxx_eh_host_reset
1215 *
1216 * Description:
1217 * The reset function will reset the Adapter.
1218 *
1219 * Input:
1220 * cmd = Linux SCSI command packet of the command that cause the
1221 * adapter reset.
1222 *
1223 * Returns:
1224 * Either SUCCESS or FAILED.
1225 *
1226 * Note:
1227 **************************************************************************/
1228 static int
1229 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1230 {
1231 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1232 struct qla_hw_data *ha = vha->hw;
1233 int ret = FAILED;
1234 unsigned int id, lun;
1235 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1236
1237 id = cmd->device->id;
1238 lun = cmd->device->lun;
1239
1240 ql_log(ql_log_info, vha, 0x8018,
1241 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1242
1243 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
1244 goto eh_host_reset_lock;
1245
1246 if (vha != base_vha) {
1247 if (qla2x00_vp_abort_isp(vha))
1248 goto eh_host_reset_lock;
1249 } else {
1250 if (IS_P3P_TYPE(vha->hw)) {
1251 if (!qla82xx_fcoe_ctx_reset(vha)) {
1252 /* Ctx reset success */
1253 ret = SUCCESS;
1254 goto eh_host_reset_lock;
1255 }
1256 /* fall thru if ctx reset failed */
1257 }
1258 if (ha->wq)
1259 flush_workqueue(ha->wq);
1260
1261 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1262 if (ha->isp_ops->abort_isp(base_vha)) {
1263 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1264 /* failed. schedule dpc to try */
1265 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1266
1267 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1268 ql_log(ql_log_warn, vha, 0x802a,
1269 "wait for hba online failed.\n");
1270 goto eh_host_reset_lock;
1271 }
1272 }
1273 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1274 }
1275
1276 /* Waiting for command to be returned to OS.*/
1277 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1278 QLA_SUCCESS)
1279 ret = SUCCESS;
1280
1281 eh_host_reset_lock:
1282 ql_log(ql_log_info, vha, 0x8017,
1283 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1284 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1285
1286 return ret;
1287 }
1288
1289 /*
1290 * qla2x00_loop_reset
1291 * Issue loop reset.
1292 *
1293 * Input:
1294 * ha = adapter block pointer.
1295 *
1296 * Returns:
1297 * 0 = success
1298 */
1299 int
1300 qla2x00_loop_reset(scsi_qla_host_t *vha)
1301 {
1302 int ret;
1303 struct fc_port *fcport;
1304 struct qla_hw_data *ha = vha->hw;
1305
1306 if (IS_QLAFX00(ha)) {
1307 return qlafx00_loop_reset(vha);
1308 }
1309
1310 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1311 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1312 if (fcport->port_type != FCT_TARGET)
1313 continue;
1314
1315 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1316 if (ret != QLA_SUCCESS) {
1317 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1318 "Bus Reset failed: Reset=%d "
1319 "d_id=%x.\n", ret, fcport->d_id.b24);
1320 }
1321 }
1322 }
1323
1324
1325 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1326 atomic_set(&vha->loop_state, LOOP_DOWN);
1327 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1328 qla2x00_mark_all_devices_lost(vha, 0);
1329 ret = qla2x00_full_login_lip(vha);
1330 if (ret != QLA_SUCCESS) {
1331 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1332 "full_login_lip=%d.\n", ret);
1333 }
1334 }
1335
1336 if (ha->flags.enable_lip_reset) {
1337 ret = qla2x00_lip_reset(vha);
1338 if (ret != QLA_SUCCESS)
1339 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1340 "lip_reset failed (%d).\n", ret);
1341 }
1342
1343 /* Issue marker command only when we are going to start the I/O */
1344 vha->marker_needed = 1;
1345
1346 return QLA_SUCCESS;
1347 }
1348
1349 void
1350 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1351 {
1352 int que, cnt;
1353 unsigned long flags;
1354 srb_t *sp;
1355 struct qla_hw_data *ha = vha->hw;
1356 struct req_que *req;
1357
1358 spin_lock_irqsave(&ha->hardware_lock, flags);
1359 for (que = 0; que < ha->max_req_queues; que++) {
1360 req = ha->req_q_map[que];
1361 if (!req)
1362 continue;
1363 if (!req->outstanding_cmds)
1364 continue;
1365 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1366 sp = req->outstanding_cmds[cnt];
1367 if (sp) {
1368 req->outstanding_cmds[cnt] = NULL;
1369 sp->done(vha, sp, res);
1370 }
1371 }
1372 }
1373 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1374 }
1375
1376 static int
1377 qla2xxx_slave_alloc(struct scsi_device *sdev)
1378 {
1379 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1380
1381 if (!rport || fc_remote_port_chkready(rport))
1382 return -ENXIO;
1383
1384 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1385
1386 return 0;
1387 }
1388
1389 static int
1390 qla2xxx_slave_configure(struct scsi_device *sdev)
1391 {
1392 scsi_qla_host_t *vha = shost_priv(sdev->host);
1393 struct req_que *req = vha->req;
1394
1395 if (IS_T10_PI_CAPABLE(vha->hw))
1396 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1397
1398 if (sdev->tagged_supported)
1399 scsi_activate_tcq(sdev, req->max_q_depth);
1400 else
1401 scsi_deactivate_tcq(sdev, req->max_q_depth);
1402 return 0;
1403 }
1404
1405 static void
1406 qla2xxx_slave_destroy(struct scsi_device *sdev)
1407 {
1408 sdev->hostdata = NULL;
1409 }
1410
1411 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1412 {
1413 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1414
1415 if (!scsi_track_queue_full(sdev, qdepth))
1416 return;
1417
1418 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1419 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1420 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1421 }
1422
1423 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1424 {
1425 fc_port_t *fcport = sdev->hostdata;
1426 struct scsi_qla_host *vha = fcport->vha;
1427 struct req_que *req = NULL;
1428
1429 req = vha->req;
1430 if (!req)
1431 return;
1432
1433 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1434 return;
1435
1436 if (sdev->ordered_tags)
1437 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1438 else
1439 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1440
1441 ql_dbg(ql_dbg_io, vha, 0x302a,
1442 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1443 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1444 }
1445
1446 static int
1447 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1448 {
1449 switch (reason) {
1450 case SCSI_QDEPTH_DEFAULT:
1451 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1452 break;
1453 case SCSI_QDEPTH_QFULL:
1454 qla2x00_handle_queue_full(sdev, qdepth);
1455 break;
1456 case SCSI_QDEPTH_RAMP_UP:
1457 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1458 break;
1459 default:
1460 return -EOPNOTSUPP;
1461 }
1462
1463 return sdev->queue_depth;
1464 }
1465
1466 static int
1467 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1468 {
1469 if (sdev->tagged_supported) {
1470 scsi_set_tag_type(sdev, tag_type);
1471 if (tag_type)
1472 scsi_activate_tcq(sdev, sdev->queue_depth);
1473 else
1474 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1475 } else
1476 tag_type = 0;
1477
1478 return tag_type;
1479 }
1480
1481 static void
1482 qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1483 {
1484 scsi_qla_host_t *vp;
1485 struct Scsi_Host *shost;
1486 struct scsi_device *sdev;
1487 struct qla_hw_data *ha = vha->hw;
1488 unsigned long flags;
1489
1490 ha->host_last_rampdown_time = jiffies;
1491
1492 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1493 return;
1494
1495 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1496 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1497 else
1498 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1499
1500 /*
1501 * Geometrically ramp down the queue depth for all devices on this
1502 * adapter
1503 */
1504 spin_lock_irqsave(&ha->vport_slock, flags);
1505 list_for_each_entry(vp, &ha->vp_list, list) {
1506 shost = vp->host;
1507 shost_for_each_device(sdev, shost) {
1508 if (sdev->queue_depth > shost->cmd_per_lun) {
1509 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1510 continue;
1511 ql_dbg(ql_dbg_io, vp, 0x3031,
1512 "%ld:%d:%d: Ramping down queue depth to %d",
1513 vp->host_no, sdev->id, sdev->lun,
1514 ha->cfg_lun_q_depth);
1515 qla2x00_change_queue_depth(sdev,
1516 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1517 }
1518 }
1519 }
1520 spin_unlock_irqrestore(&ha->vport_slock, flags);
1521
1522 return;
1523 }
1524
1525 static void
1526 qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1527 {
1528 scsi_qla_host_t *vp;
1529 struct Scsi_Host *shost;
1530 struct scsi_device *sdev;
1531 struct qla_hw_data *ha = vha->hw;
1532 unsigned long flags;
1533
1534 ha->host_last_rampup_time = jiffies;
1535 ha->cfg_lun_q_depth++;
1536
1537 /*
1538 * Linearly ramp up the queue depth for all devices on this
1539 * adapter
1540 */
1541 spin_lock_irqsave(&ha->vport_slock, flags);
1542 list_for_each_entry(vp, &ha->vp_list, list) {
1543 shost = vp->host;
1544 shost_for_each_device(sdev, shost) {
1545 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1546 continue;
1547 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1548 SCSI_QDEPTH_RAMP_UP);
1549 }
1550 }
1551 spin_unlock_irqrestore(&ha->vport_slock, flags);
1552
1553 return;
1554 }
1555
1556 /**
1557 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1558 * @ha: HA context
1559 *
1560 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1561 * supported addressing method.
1562 */
1563 static void
1564 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1565 {
1566 /* Assume a 32bit DMA mask. */
1567 ha->flags.enable_64bit_addressing = 0;
1568
1569 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1570 /* Any upper-dword bits set? */
1571 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1572 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1573 /* Ok, a 64bit DMA mask is applicable. */
1574 ha->flags.enable_64bit_addressing = 1;
1575 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1576 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1577 return;
1578 }
1579 }
1580
1581 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1582 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1583 }
1584
1585 static void
1586 qla2x00_enable_intrs(struct qla_hw_data *ha)
1587 {
1588 unsigned long flags = 0;
1589 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1590
1591 spin_lock_irqsave(&ha->hardware_lock, flags);
1592 ha->interrupts_on = 1;
1593 /* enable risc and host interrupts */
1594 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1595 RD_REG_WORD(&reg->ictrl);
1596 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1597
1598 }
1599
1600 static void
1601 qla2x00_disable_intrs(struct qla_hw_data *ha)
1602 {
1603 unsigned long flags = 0;
1604 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1605
1606 spin_lock_irqsave(&ha->hardware_lock, flags);
1607 ha->interrupts_on = 0;
1608 /* disable risc and host interrupts */
1609 WRT_REG_WORD(&reg->ictrl, 0);
1610 RD_REG_WORD(&reg->ictrl);
1611 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1612 }
1613
1614 static void
1615 qla24xx_enable_intrs(struct qla_hw_data *ha)
1616 {
1617 unsigned long flags = 0;
1618 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1619
1620 spin_lock_irqsave(&ha->hardware_lock, flags);
1621 ha->interrupts_on = 1;
1622 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1623 RD_REG_DWORD(&reg->ictrl);
1624 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1625 }
1626
1627 static void
1628 qla24xx_disable_intrs(struct qla_hw_data *ha)
1629 {
1630 unsigned long flags = 0;
1631 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1632
1633 if (IS_NOPOLLING_TYPE(ha))
1634 return;
1635 spin_lock_irqsave(&ha->hardware_lock, flags);
1636 ha->interrupts_on = 0;
1637 WRT_REG_DWORD(&reg->ictrl, 0);
1638 RD_REG_DWORD(&reg->ictrl);
1639 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1640 }
1641
1642 static int
1643 qla2x00_iospace_config(struct qla_hw_data *ha)
1644 {
1645 resource_size_t pio;
1646 uint16_t msix;
1647 int cpus;
1648
1649 if (pci_request_selected_regions(ha->pdev, ha->bars,
1650 QLA2XXX_DRIVER_NAME)) {
1651 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1652 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1653 pci_name(ha->pdev));
1654 goto iospace_error_exit;
1655 }
1656 if (!(ha->bars & 1))
1657 goto skip_pio;
1658
1659 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1660 pio = pci_resource_start(ha->pdev, 0);
1661 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1662 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1663 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1664 "Invalid pci I/O region size (%s).\n",
1665 pci_name(ha->pdev));
1666 pio = 0;
1667 }
1668 } else {
1669 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1670 "Region #0 no a PIO resource (%s).\n",
1671 pci_name(ha->pdev));
1672 pio = 0;
1673 }
1674 ha->pio_address = pio;
1675 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1676 "PIO address=%llu.\n",
1677 (unsigned long long)ha->pio_address);
1678
1679 skip_pio:
1680 /* Use MMIO operations for all accesses. */
1681 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1682 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1683 "Region #1 not an MMIO resource (%s), aborting.\n",
1684 pci_name(ha->pdev));
1685 goto iospace_error_exit;
1686 }
1687 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1688 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1689 "Invalid PCI mem region size (%s), aborting.\n",
1690 pci_name(ha->pdev));
1691 goto iospace_error_exit;
1692 }
1693
1694 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1695 if (!ha->iobase) {
1696 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1697 "Cannot remap MMIO (%s), aborting.\n",
1698 pci_name(ha->pdev));
1699 goto iospace_error_exit;
1700 }
1701
1702 /* Determine queue resources */
1703 ha->max_req_queues = ha->max_rsp_queues = 1;
1704 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1705 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1706 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1707 goto mqiobase_exit;
1708
1709 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1710 pci_resource_len(ha->pdev, 3));
1711 if (ha->mqiobase) {
1712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1713 "MQIO Base=%p.\n", ha->mqiobase);
1714 /* Read MSIX vector size of the board */
1715 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1716 ha->msix_count = msix;
1717 /* Max queues are bounded by available msix vectors */
1718 /* queue 0 uses two msix vectors */
1719 if (ql2xmultique_tag) {
1720 cpus = num_online_cpus();
1721 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1722 (cpus + 1) : (ha->msix_count - 1);
1723 ha->max_req_queues = 2;
1724 } else if (ql2xmaxqueues > 1) {
1725 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1726 QLA_MQ_SIZE : ql2xmaxqueues;
1727 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1728 "QoS mode set, max no of request queues:%d.\n",
1729 ha->max_req_queues);
1730 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1731 "QoS mode set, max no of request queues:%d.\n",
1732 ha->max_req_queues);
1733 }
1734 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1735 "MSI-X vector count: %d.\n", msix);
1736 } else
1737 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1738 "BAR 3 not enabled.\n");
1739
1740 mqiobase_exit:
1741 ha->msix_count = ha->max_rsp_queues + 1;
1742 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1743 "MSIX Count:%d.\n", ha->msix_count);
1744 return (0);
1745
1746 iospace_error_exit:
1747 return (-ENOMEM);
1748 }
1749
1750
1751 static int
1752 qla83xx_iospace_config(struct qla_hw_data *ha)
1753 {
1754 uint16_t msix;
1755 int cpus;
1756
1757 if (pci_request_selected_regions(ha->pdev, ha->bars,
1758 QLA2XXX_DRIVER_NAME)) {
1759 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1760 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1761 pci_name(ha->pdev));
1762
1763 goto iospace_error_exit;
1764 }
1765
1766 /* Use MMIO operations for all accesses. */
1767 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1768 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1769 "Invalid pci I/O region size (%s).\n",
1770 pci_name(ha->pdev));
1771 goto iospace_error_exit;
1772 }
1773 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1774 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1775 "Invalid PCI mem region size (%s), aborting\n",
1776 pci_name(ha->pdev));
1777 goto iospace_error_exit;
1778 }
1779
1780 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1781 if (!ha->iobase) {
1782 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1783 "Cannot remap MMIO (%s), aborting.\n",
1784 pci_name(ha->pdev));
1785 goto iospace_error_exit;
1786 }
1787
1788 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1789 /* 83XX 26XX always use MQ type access for queues
1790 * - mbar 2, a.k.a region 4 */
1791 ha->max_req_queues = ha->max_rsp_queues = 1;
1792 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1793 pci_resource_len(ha->pdev, 4));
1794
1795 if (!ha->mqiobase) {
1796 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1797 "BAR2/region4 not enabled\n");
1798 goto mqiobase_exit;
1799 }
1800
1801 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1802 pci_resource_len(ha->pdev, 2));
1803 if (ha->msixbase) {
1804 /* Read MSIX vector size of the board */
1805 pci_read_config_word(ha->pdev,
1806 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1807 ha->msix_count = msix;
1808 /* Max queues are bounded by available msix vectors */
1809 /* queue 0 uses two msix vectors */
1810 if (ql2xmultique_tag) {
1811 cpus = num_online_cpus();
1812 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1813 (cpus + 1) : (ha->msix_count - 1);
1814 ha->max_req_queues = 2;
1815 } else if (ql2xmaxqueues > 1) {
1816 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1817 QLA_MQ_SIZE : ql2xmaxqueues;
1818 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1819 "QoS mode set, max no of request queues:%d.\n",
1820 ha->max_req_queues);
1821 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1822 "QoS mode set, max no of request queues:%d.\n",
1823 ha->max_req_queues);
1824 }
1825 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1826 "MSI-X vector count: %d.\n", msix);
1827 } else
1828 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1829 "BAR 1 not enabled.\n");
1830
1831 mqiobase_exit:
1832 ha->msix_count = ha->max_rsp_queues + 1;
1833
1834 qlt_83xx_iospace_config(ha);
1835
1836 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1837 "MSIX Count:%d.\n", ha->msix_count);
1838 return 0;
1839
1840 iospace_error_exit:
1841 return -ENOMEM;
1842 }
1843
1844 static struct isp_operations qla2100_isp_ops = {
1845 .pci_config = qla2100_pci_config,
1846 .reset_chip = qla2x00_reset_chip,
1847 .chip_diag = qla2x00_chip_diag,
1848 .config_rings = qla2x00_config_rings,
1849 .reset_adapter = qla2x00_reset_adapter,
1850 .nvram_config = qla2x00_nvram_config,
1851 .update_fw_options = qla2x00_update_fw_options,
1852 .load_risc = qla2x00_load_risc,
1853 .pci_info_str = qla2x00_pci_info_str,
1854 .fw_version_str = qla2x00_fw_version_str,
1855 .intr_handler = qla2100_intr_handler,
1856 .enable_intrs = qla2x00_enable_intrs,
1857 .disable_intrs = qla2x00_disable_intrs,
1858 .abort_command = qla2x00_abort_command,
1859 .target_reset = qla2x00_abort_target,
1860 .lun_reset = qla2x00_lun_reset,
1861 .fabric_login = qla2x00_login_fabric,
1862 .fabric_logout = qla2x00_fabric_logout,
1863 .calc_req_entries = qla2x00_calc_iocbs_32,
1864 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1865 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1866 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1867 .read_nvram = qla2x00_read_nvram_data,
1868 .write_nvram = qla2x00_write_nvram_data,
1869 .fw_dump = qla2100_fw_dump,
1870 .beacon_on = NULL,
1871 .beacon_off = NULL,
1872 .beacon_blink = NULL,
1873 .read_optrom = qla2x00_read_optrom_data,
1874 .write_optrom = qla2x00_write_optrom_data,
1875 .get_flash_version = qla2x00_get_flash_version,
1876 .start_scsi = qla2x00_start_scsi,
1877 .abort_isp = qla2x00_abort_isp,
1878 .iospace_config = qla2x00_iospace_config,
1879 .initialize_adapter = qla2x00_initialize_adapter,
1880 };
1881
1882 static struct isp_operations qla2300_isp_ops = {
1883 .pci_config = qla2300_pci_config,
1884 .reset_chip = qla2x00_reset_chip,
1885 .chip_diag = qla2x00_chip_diag,
1886 .config_rings = qla2x00_config_rings,
1887 .reset_adapter = qla2x00_reset_adapter,
1888 .nvram_config = qla2x00_nvram_config,
1889 .update_fw_options = qla2x00_update_fw_options,
1890 .load_risc = qla2x00_load_risc,
1891 .pci_info_str = qla2x00_pci_info_str,
1892 .fw_version_str = qla2x00_fw_version_str,
1893 .intr_handler = qla2300_intr_handler,
1894 .enable_intrs = qla2x00_enable_intrs,
1895 .disable_intrs = qla2x00_disable_intrs,
1896 .abort_command = qla2x00_abort_command,
1897 .target_reset = qla2x00_abort_target,
1898 .lun_reset = qla2x00_lun_reset,
1899 .fabric_login = qla2x00_login_fabric,
1900 .fabric_logout = qla2x00_fabric_logout,
1901 .calc_req_entries = qla2x00_calc_iocbs_32,
1902 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1903 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1904 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1905 .read_nvram = qla2x00_read_nvram_data,
1906 .write_nvram = qla2x00_write_nvram_data,
1907 .fw_dump = qla2300_fw_dump,
1908 .beacon_on = qla2x00_beacon_on,
1909 .beacon_off = qla2x00_beacon_off,
1910 .beacon_blink = qla2x00_beacon_blink,
1911 .read_optrom = qla2x00_read_optrom_data,
1912 .write_optrom = qla2x00_write_optrom_data,
1913 .get_flash_version = qla2x00_get_flash_version,
1914 .start_scsi = qla2x00_start_scsi,
1915 .abort_isp = qla2x00_abort_isp,
1916 .iospace_config = qla2x00_iospace_config,
1917 .initialize_adapter = qla2x00_initialize_adapter,
1918 };
1919
1920 static struct isp_operations qla24xx_isp_ops = {
1921 .pci_config = qla24xx_pci_config,
1922 .reset_chip = qla24xx_reset_chip,
1923 .chip_diag = qla24xx_chip_diag,
1924 .config_rings = qla24xx_config_rings,
1925 .reset_adapter = qla24xx_reset_adapter,
1926 .nvram_config = qla24xx_nvram_config,
1927 .update_fw_options = qla24xx_update_fw_options,
1928 .load_risc = qla24xx_load_risc,
1929 .pci_info_str = qla24xx_pci_info_str,
1930 .fw_version_str = qla24xx_fw_version_str,
1931 .intr_handler = qla24xx_intr_handler,
1932 .enable_intrs = qla24xx_enable_intrs,
1933 .disable_intrs = qla24xx_disable_intrs,
1934 .abort_command = qla24xx_abort_command,
1935 .target_reset = qla24xx_abort_target,
1936 .lun_reset = qla24xx_lun_reset,
1937 .fabric_login = qla24xx_login_fabric,
1938 .fabric_logout = qla24xx_fabric_logout,
1939 .calc_req_entries = NULL,
1940 .build_iocbs = NULL,
1941 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1942 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1943 .read_nvram = qla24xx_read_nvram_data,
1944 .write_nvram = qla24xx_write_nvram_data,
1945 .fw_dump = qla24xx_fw_dump,
1946 .beacon_on = qla24xx_beacon_on,
1947 .beacon_off = qla24xx_beacon_off,
1948 .beacon_blink = qla24xx_beacon_blink,
1949 .read_optrom = qla24xx_read_optrom_data,
1950 .write_optrom = qla24xx_write_optrom_data,
1951 .get_flash_version = qla24xx_get_flash_version,
1952 .start_scsi = qla24xx_start_scsi,
1953 .abort_isp = qla2x00_abort_isp,
1954 .iospace_config = qla2x00_iospace_config,
1955 .initialize_adapter = qla2x00_initialize_adapter,
1956 };
1957
1958 static struct isp_operations qla25xx_isp_ops = {
1959 .pci_config = qla25xx_pci_config,
1960 .reset_chip = qla24xx_reset_chip,
1961 .chip_diag = qla24xx_chip_diag,
1962 .config_rings = qla24xx_config_rings,
1963 .reset_adapter = qla24xx_reset_adapter,
1964 .nvram_config = qla24xx_nvram_config,
1965 .update_fw_options = qla24xx_update_fw_options,
1966 .load_risc = qla24xx_load_risc,
1967 .pci_info_str = qla24xx_pci_info_str,
1968 .fw_version_str = qla24xx_fw_version_str,
1969 .intr_handler = qla24xx_intr_handler,
1970 .enable_intrs = qla24xx_enable_intrs,
1971 .disable_intrs = qla24xx_disable_intrs,
1972 .abort_command = qla24xx_abort_command,
1973 .target_reset = qla24xx_abort_target,
1974 .lun_reset = qla24xx_lun_reset,
1975 .fabric_login = qla24xx_login_fabric,
1976 .fabric_logout = qla24xx_fabric_logout,
1977 .calc_req_entries = NULL,
1978 .build_iocbs = NULL,
1979 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1980 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1981 .read_nvram = qla25xx_read_nvram_data,
1982 .write_nvram = qla25xx_write_nvram_data,
1983 .fw_dump = qla25xx_fw_dump,
1984 .beacon_on = qla24xx_beacon_on,
1985 .beacon_off = qla24xx_beacon_off,
1986 .beacon_blink = qla24xx_beacon_blink,
1987 .read_optrom = qla25xx_read_optrom_data,
1988 .write_optrom = qla24xx_write_optrom_data,
1989 .get_flash_version = qla24xx_get_flash_version,
1990 .start_scsi = qla24xx_dif_start_scsi,
1991 .abort_isp = qla2x00_abort_isp,
1992 .iospace_config = qla2x00_iospace_config,
1993 .initialize_adapter = qla2x00_initialize_adapter,
1994 };
1995
1996 static struct isp_operations qla81xx_isp_ops = {
1997 .pci_config = qla25xx_pci_config,
1998 .reset_chip = qla24xx_reset_chip,
1999 .chip_diag = qla24xx_chip_diag,
2000 .config_rings = qla24xx_config_rings,
2001 .reset_adapter = qla24xx_reset_adapter,
2002 .nvram_config = qla81xx_nvram_config,
2003 .update_fw_options = qla81xx_update_fw_options,
2004 .load_risc = qla81xx_load_risc,
2005 .pci_info_str = qla24xx_pci_info_str,
2006 .fw_version_str = qla24xx_fw_version_str,
2007 .intr_handler = qla24xx_intr_handler,
2008 .enable_intrs = qla24xx_enable_intrs,
2009 .disable_intrs = qla24xx_disable_intrs,
2010 .abort_command = qla24xx_abort_command,
2011 .target_reset = qla24xx_abort_target,
2012 .lun_reset = qla24xx_lun_reset,
2013 .fabric_login = qla24xx_login_fabric,
2014 .fabric_logout = qla24xx_fabric_logout,
2015 .calc_req_entries = NULL,
2016 .build_iocbs = NULL,
2017 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2018 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2019 .read_nvram = NULL,
2020 .write_nvram = NULL,
2021 .fw_dump = qla81xx_fw_dump,
2022 .beacon_on = qla24xx_beacon_on,
2023 .beacon_off = qla24xx_beacon_off,
2024 .beacon_blink = qla83xx_beacon_blink,
2025 .read_optrom = qla25xx_read_optrom_data,
2026 .write_optrom = qla24xx_write_optrom_data,
2027 .get_flash_version = qla24xx_get_flash_version,
2028 .start_scsi = qla24xx_dif_start_scsi,
2029 .abort_isp = qla2x00_abort_isp,
2030 .iospace_config = qla2x00_iospace_config,
2031 .initialize_adapter = qla2x00_initialize_adapter,
2032 };
2033
2034 static struct isp_operations qla82xx_isp_ops = {
2035 .pci_config = qla82xx_pci_config,
2036 .reset_chip = qla82xx_reset_chip,
2037 .chip_diag = qla24xx_chip_diag,
2038 .config_rings = qla82xx_config_rings,
2039 .reset_adapter = qla24xx_reset_adapter,
2040 .nvram_config = qla81xx_nvram_config,
2041 .update_fw_options = qla24xx_update_fw_options,
2042 .load_risc = qla82xx_load_risc,
2043 .pci_info_str = qla24xx_pci_info_str,
2044 .fw_version_str = qla24xx_fw_version_str,
2045 .intr_handler = qla82xx_intr_handler,
2046 .enable_intrs = qla82xx_enable_intrs,
2047 .disable_intrs = qla82xx_disable_intrs,
2048 .abort_command = qla24xx_abort_command,
2049 .target_reset = qla24xx_abort_target,
2050 .lun_reset = qla24xx_lun_reset,
2051 .fabric_login = qla24xx_login_fabric,
2052 .fabric_logout = qla24xx_fabric_logout,
2053 .calc_req_entries = NULL,
2054 .build_iocbs = NULL,
2055 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2056 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2057 .read_nvram = qla24xx_read_nvram_data,
2058 .write_nvram = qla24xx_write_nvram_data,
2059 .fw_dump = qla24xx_fw_dump,
2060 .beacon_on = qla82xx_beacon_on,
2061 .beacon_off = qla82xx_beacon_off,
2062 .beacon_blink = NULL,
2063 .read_optrom = qla82xx_read_optrom_data,
2064 .write_optrom = qla82xx_write_optrom_data,
2065 .get_flash_version = qla82xx_get_flash_version,
2066 .start_scsi = qla82xx_start_scsi,
2067 .abort_isp = qla82xx_abort_isp,
2068 .iospace_config = qla82xx_iospace_config,
2069 .initialize_adapter = qla2x00_initialize_adapter,
2070 };
2071
2072 static struct isp_operations qla8044_isp_ops = {
2073 .pci_config = qla82xx_pci_config,
2074 .reset_chip = qla82xx_reset_chip,
2075 .chip_diag = qla24xx_chip_diag,
2076 .config_rings = qla82xx_config_rings,
2077 .reset_adapter = qla24xx_reset_adapter,
2078 .nvram_config = qla81xx_nvram_config,
2079 .update_fw_options = qla24xx_update_fw_options,
2080 .load_risc = qla82xx_load_risc,
2081 .pci_info_str = qla24xx_pci_info_str,
2082 .fw_version_str = qla24xx_fw_version_str,
2083 .intr_handler = qla8044_intr_handler,
2084 .enable_intrs = qla82xx_enable_intrs,
2085 .disable_intrs = qla82xx_disable_intrs,
2086 .abort_command = qla24xx_abort_command,
2087 .target_reset = qla24xx_abort_target,
2088 .lun_reset = qla24xx_lun_reset,
2089 .fabric_login = qla24xx_login_fabric,
2090 .fabric_logout = qla24xx_fabric_logout,
2091 .calc_req_entries = NULL,
2092 .build_iocbs = NULL,
2093 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2094 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2095 .read_nvram = NULL,
2096 .write_nvram = NULL,
2097 .fw_dump = qla24xx_fw_dump,
2098 .beacon_on = qla82xx_beacon_on,
2099 .beacon_off = qla82xx_beacon_off,
2100 .beacon_blink = NULL,
2101 .read_optrom = qla82xx_read_optrom_data,
2102 .write_optrom = qla8044_write_optrom_data,
2103 .get_flash_version = qla82xx_get_flash_version,
2104 .start_scsi = qla82xx_start_scsi,
2105 .abort_isp = qla8044_abort_isp,
2106 .iospace_config = qla82xx_iospace_config,
2107 .initialize_adapter = qla2x00_initialize_adapter,
2108 };
2109
2110 static struct isp_operations qla83xx_isp_ops = {
2111 .pci_config = qla25xx_pci_config,
2112 .reset_chip = qla24xx_reset_chip,
2113 .chip_diag = qla24xx_chip_diag,
2114 .config_rings = qla24xx_config_rings,
2115 .reset_adapter = qla24xx_reset_adapter,
2116 .nvram_config = qla81xx_nvram_config,
2117 .update_fw_options = qla81xx_update_fw_options,
2118 .load_risc = qla81xx_load_risc,
2119 .pci_info_str = qla24xx_pci_info_str,
2120 .fw_version_str = qla24xx_fw_version_str,
2121 .intr_handler = qla24xx_intr_handler,
2122 .enable_intrs = qla24xx_enable_intrs,
2123 .disable_intrs = qla24xx_disable_intrs,
2124 .abort_command = qla24xx_abort_command,
2125 .target_reset = qla24xx_abort_target,
2126 .lun_reset = qla24xx_lun_reset,
2127 .fabric_login = qla24xx_login_fabric,
2128 .fabric_logout = qla24xx_fabric_logout,
2129 .calc_req_entries = NULL,
2130 .build_iocbs = NULL,
2131 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2132 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2133 .read_nvram = NULL,
2134 .write_nvram = NULL,
2135 .fw_dump = qla83xx_fw_dump,
2136 .beacon_on = qla24xx_beacon_on,
2137 .beacon_off = qla24xx_beacon_off,
2138 .beacon_blink = qla83xx_beacon_blink,
2139 .read_optrom = qla25xx_read_optrom_data,
2140 .write_optrom = qla24xx_write_optrom_data,
2141 .get_flash_version = qla24xx_get_flash_version,
2142 .start_scsi = qla24xx_dif_start_scsi,
2143 .abort_isp = qla2x00_abort_isp,
2144 .iospace_config = qla83xx_iospace_config,
2145 .initialize_adapter = qla2x00_initialize_adapter,
2146 };
2147
2148 static struct isp_operations qlafx00_isp_ops = {
2149 .pci_config = qlafx00_pci_config,
2150 .reset_chip = qlafx00_soft_reset,
2151 .chip_diag = qlafx00_chip_diag,
2152 .config_rings = qlafx00_config_rings,
2153 .reset_adapter = qlafx00_soft_reset,
2154 .nvram_config = NULL,
2155 .update_fw_options = NULL,
2156 .load_risc = NULL,
2157 .pci_info_str = qlafx00_pci_info_str,
2158 .fw_version_str = qlafx00_fw_version_str,
2159 .intr_handler = qlafx00_intr_handler,
2160 .enable_intrs = qlafx00_enable_intrs,
2161 .disable_intrs = qlafx00_disable_intrs,
2162 .abort_command = qlafx00_abort_command,
2163 .target_reset = qlafx00_abort_target,
2164 .lun_reset = qlafx00_lun_reset,
2165 .fabric_login = NULL,
2166 .fabric_logout = NULL,
2167 .calc_req_entries = NULL,
2168 .build_iocbs = NULL,
2169 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2170 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2171 .read_nvram = qla24xx_read_nvram_data,
2172 .write_nvram = qla24xx_write_nvram_data,
2173 .fw_dump = NULL,
2174 .beacon_on = qla24xx_beacon_on,
2175 .beacon_off = qla24xx_beacon_off,
2176 .beacon_blink = NULL,
2177 .read_optrom = qla24xx_read_optrom_data,
2178 .write_optrom = qla24xx_write_optrom_data,
2179 .get_flash_version = qla24xx_get_flash_version,
2180 .start_scsi = qlafx00_start_scsi,
2181 .abort_isp = qlafx00_abort_isp,
2182 .iospace_config = qlafx00_iospace_config,
2183 .initialize_adapter = qlafx00_initialize_adapter,
2184 };
2185
2186 static inline void
2187 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2188 {
2189 ha->device_type = DT_EXTENDED_IDS;
2190 switch (ha->pdev->device) {
2191 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2192 ha->device_type |= DT_ISP2100;
2193 ha->device_type &= ~DT_EXTENDED_IDS;
2194 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2195 break;
2196 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2197 ha->device_type |= DT_ISP2200;
2198 ha->device_type &= ~DT_EXTENDED_IDS;
2199 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2200 break;
2201 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2202 ha->device_type |= DT_ISP2300;
2203 ha->device_type |= DT_ZIO_SUPPORTED;
2204 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2205 break;
2206 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2207 ha->device_type |= DT_ISP2312;
2208 ha->device_type |= DT_ZIO_SUPPORTED;
2209 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2210 break;
2211 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2212 ha->device_type |= DT_ISP2322;
2213 ha->device_type |= DT_ZIO_SUPPORTED;
2214 if (ha->pdev->subsystem_vendor == 0x1028 &&
2215 ha->pdev->subsystem_device == 0x0170)
2216 ha->device_type |= DT_OEM_001;
2217 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2218 break;
2219 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2220 ha->device_type |= DT_ISP6312;
2221 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2222 break;
2223 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2224 ha->device_type |= DT_ISP6322;
2225 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2226 break;
2227 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2228 ha->device_type |= DT_ISP2422;
2229 ha->device_type |= DT_ZIO_SUPPORTED;
2230 ha->device_type |= DT_FWI2;
2231 ha->device_type |= DT_IIDMA;
2232 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2233 break;
2234 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2235 ha->device_type |= DT_ISP2432;
2236 ha->device_type |= DT_ZIO_SUPPORTED;
2237 ha->device_type |= DT_FWI2;
2238 ha->device_type |= DT_IIDMA;
2239 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2240 break;
2241 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2242 ha->device_type |= DT_ISP8432;
2243 ha->device_type |= DT_ZIO_SUPPORTED;
2244 ha->device_type |= DT_FWI2;
2245 ha->device_type |= DT_IIDMA;
2246 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2247 break;
2248 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2249 ha->device_type |= DT_ISP5422;
2250 ha->device_type |= DT_FWI2;
2251 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2252 break;
2253 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2254 ha->device_type |= DT_ISP5432;
2255 ha->device_type |= DT_FWI2;
2256 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2257 break;
2258 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2259 ha->device_type |= DT_ISP2532;
2260 ha->device_type |= DT_ZIO_SUPPORTED;
2261 ha->device_type |= DT_FWI2;
2262 ha->device_type |= DT_IIDMA;
2263 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2264 break;
2265 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2266 ha->device_type |= DT_ISP8001;
2267 ha->device_type |= DT_ZIO_SUPPORTED;
2268 ha->device_type |= DT_FWI2;
2269 ha->device_type |= DT_IIDMA;
2270 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2271 break;
2272 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2273 ha->device_type |= DT_ISP8021;
2274 ha->device_type |= DT_ZIO_SUPPORTED;
2275 ha->device_type |= DT_FWI2;
2276 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2277 /* Initialize 82XX ISP flags */
2278 qla82xx_init_flags(ha);
2279 break;
2280 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2281 ha->device_type |= DT_ISP8044;
2282 ha->device_type |= DT_ZIO_SUPPORTED;
2283 ha->device_type |= DT_FWI2;
2284 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2285 /* Initialize 82XX ISP flags */
2286 qla82xx_init_flags(ha);
2287 break;
2288 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2289 ha->device_type |= DT_ISP2031;
2290 ha->device_type |= DT_ZIO_SUPPORTED;
2291 ha->device_type |= DT_FWI2;
2292 ha->device_type |= DT_IIDMA;
2293 ha->device_type |= DT_T10_PI;
2294 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2295 break;
2296 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2297 ha->device_type |= DT_ISP8031;
2298 ha->device_type |= DT_ZIO_SUPPORTED;
2299 ha->device_type |= DT_FWI2;
2300 ha->device_type |= DT_IIDMA;
2301 ha->device_type |= DT_T10_PI;
2302 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2303 break;
2304 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2305 ha->device_type |= DT_ISPFX00;
2306 break;
2307 }
2308
2309 if (IS_QLA82XX(ha))
2310 ha->port_no = !(ha->portnum & 1);
2311 else
2312 /* Get adapter physical port no from interrupt pin register. */
2313 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2314
2315 if (ha->port_no & 1)
2316 ha->flags.port0 = 1;
2317 else
2318 ha->flags.port0 = 0;
2319 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2320 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2321 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
2322 }
2323
2324 static void
2325 qla2xxx_scan_start(struct Scsi_Host *shost)
2326 {
2327 scsi_qla_host_t *vha = shost_priv(shost);
2328
2329 if (vha->hw->flags.running_gold_fw)
2330 return;
2331
2332 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2333 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2334 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2335 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2336 }
2337
2338 static int
2339 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2340 {
2341 scsi_qla_host_t *vha = shost_priv(shost);
2342
2343 if (!vha->host)
2344 return 1;
2345 if (time > vha->hw->loop_reset_delay * HZ)
2346 return 1;
2347
2348 return atomic_read(&vha->loop_state) == LOOP_READY;
2349 }
2350
2351 /*
2352 * PCI driver interface
2353 */
2354 static int
2355 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2356 {
2357 int ret = -ENODEV;
2358 struct Scsi_Host *host;
2359 scsi_qla_host_t *base_vha = NULL;
2360 struct qla_hw_data *ha;
2361 char pci_info[30];
2362 char fw_str[30], wq_name[30];
2363 struct scsi_host_template *sht;
2364 int bars, mem_only = 0;
2365 uint16_t req_length = 0, rsp_length = 0;
2366 struct req_que *req = NULL;
2367 struct rsp_que *rsp = NULL;
2368 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2369 sht = &qla2xxx_driver_template;
2370 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2371 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2372 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2373 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2374 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2375 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2376 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2377 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2378 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2379 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2380 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2381 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) {
2382 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2383 mem_only = 1;
2384 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2385 "Mem only adapter.\n");
2386 }
2387 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2388 "Bars=%d.\n", bars);
2389
2390 if (mem_only) {
2391 if (pci_enable_device_mem(pdev))
2392 goto probe_out;
2393 } else {
2394 if (pci_enable_device(pdev))
2395 goto probe_out;
2396 }
2397
2398 /* This may fail but that's ok */
2399 pci_enable_pcie_error_reporting(pdev);
2400
2401 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2402 if (!ha) {
2403 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2404 "Unable to allocate memory for ha.\n");
2405 goto probe_out;
2406 }
2407 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2408 "Memory allocated for ha=%p.\n", ha);
2409 ha->pdev = pdev;
2410 ha->tgt.enable_class_2 = ql2xenableclass2;
2411
2412 /* Clear our data area */
2413 ha->bars = bars;
2414 ha->mem_only = mem_only;
2415 spin_lock_init(&ha->hardware_lock);
2416 spin_lock_init(&ha->vport_slock);
2417 mutex_init(&ha->selflogin_lock);
2418
2419 /* Set ISP-type information. */
2420 qla2x00_set_isp_flags(ha);
2421
2422 /* Set EEH reset type to fundamental if required by hba */
2423 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2424 IS_QLA83XX(ha))
2425 pdev->needs_freset = 1;
2426
2427 ha->prev_topology = 0;
2428 ha->init_cb_size = sizeof(init_cb_t);
2429 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2430 ha->optrom_size = OPTROM_SIZE_2300;
2431 ha->cfg_lun_q_depth = ql2xmaxqdepth;
2432
2433 /* Assign ISP specific operations. */
2434 if (IS_QLA2100(ha)) {
2435 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2436 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2437 req_length = REQUEST_ENTRY_CNT_2100;
2438 rsp_length = RESPONSE_ENTRY_CNT_2100;
2439 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2440 ha->gid_list_info_size = 4;
2441 ha->flash_conf_off = ~0;
2442 ha->flash_data_off = ~0;
2443 ha->nvram_conf_off = ~0;
2444 ha->nvram_data_off = ~0;
2445 ha->isp_ops = &qla2100_isp_ops;
2446 } else if (IS_QLA2200(ha)) {
2447 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2448 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2449 req_length = REQUEST_ENTRY_CNT_2200;
2450 rsp_length = RESPONSE_ENTRY_CNT_2100;
2451 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2452 ha->gid_list_info_size = 4;
2453 ha->flash_conf_off = ~0;
2454 ha->flash_data_off = ~0;
2455 ha->nvram_conf_off = ~0;
2456 ha->nvram_data_off = ~0;
2457 ha->isp_ops = &qla2100_isp_ops;
2458 } else if (IS_QLA23XX(ha)) {
2459 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2460 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2461 req_length = REQUEST_ENTRY_CNT_2200;
2462 rsp_length = RESPONSE_ENTRY_CNT_2300;
2463 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2464 ha->gid_list_info_size = 6;
2465 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2466 ha->optrom_size = OPTROM_SIZE_2322;
2467 ha->flash_conf_off = ~0;
2468 ha->flash_data_off = ~0;
2469 ha->nvram_conf_off = ~0;
2470 ha->nvram_data_off = ~0;
2471 ha->isp_ops = &qla2300_isp_ops;
2472 } else if (IS_QLA24XX_TYPE(ha)) {
2473 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2474 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2475 req_length = REQUEST_ENTRY_CNT_24XX;
2476 rsp_length = RESPONSE_ENTRY_CNT_2300;
2477 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2478 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2479 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2480 ha->gid_list_info_size = 8;
2481 ha->optrom_size = OPTROM_SIZE_24XX;
2482 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2483 ha->isp_ops = &qla24xx_isp_ops;
2484 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2485 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2486 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2487 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2488 } else if (IS_QLA25XX(ha)) {
2489 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2490 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2491 req_length = REQUEST_ENTRY_CNT_24XX;
2492 rsp_length = RESPONSE_ENTRY_CNT_2300;
2493 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2494 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2495 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2496 ha->gid_list_info_size = 8;
2497 ha->optrom_size = OPTROM_SIZE_25XX;
2498 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2499 ha->isp_ops = &qla25xx_isp_ops;
2500 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2501 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2502 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2503 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2504 } else if (IS_QLA81XX(ha)) {
2505 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2506 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2507 req_length = REQUEST_ENTRY_CNT_24XX;
2508 rsp_length = RESPONSE_ENTRY_CNT_2300;
2509 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2510 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2511 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2512 ha->gid_list_info_size = 8;
2513 ha->optrom_size = OPTROM_SIZE_81XX;
2514 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2515 ha->isp_ops = &qla81xx_isp_ops;
2516 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2517 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2518 ha->nvram_conf_off = ~0;
2519 ha->nvram_data_off = ~0;
2520 } else if (IS_QLA82XX(ha)) {
2521 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2522 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2523 req_length = REQUEST_ENTRY_CNT_82XX;
2524 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2525 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2526 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2527 ha->gid_list_info_size = 8;
2528 ha->optrom_size = OPTROM_SIZE_82XX;
2529 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2530 ha->isp_ops = &qla82xx_isp_ops;
2531 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2532 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2533 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2534 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2535 } else if (IS_QLA8044(ha)) {
2536 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2537 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2538 req_length = REQUEST_ENTRY_CNT_82XX;
2539 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2540 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2541 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2542 ha->gid_list_info_size = 8;
2543 ha->optrom_size = OPTROM_SIZE_83XX;
2544 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2545 ha->isp_ops = &qla8044_isp_ops;
2546 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2547 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2548 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2549 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2550 } else if (IS_QLA83XX(ha)) {
2551 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2552 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2553 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2554 req_length = REQUEST_ENTRY_CNT_24XX;
2555 rsp_length = RESPONSE_ENTRY_CNT_2300;
2556 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2557 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2558 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2559 ha->gid_list_info_size = 8;
2560 ha->optrom_size = OPTROM_SIZE_83XX;
2561 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2562 ha->isp_ops = &qla83xx_isp_ops;
2563 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2564 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2565 ha->nvram_conf_off = ~0;
2566 ha->nvram_data_off = ~0;
2567 } else if (IS_QLAFX00(ha)) {
2568 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2569 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2570 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2571 req_length = REQUEST_ENTRY_CNT_FX00;
2572 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2573 ha->init_cb_size = sizeof(struct init_cb_fx);
2574 ha->isp_ops = &qlafx00_isp_ops;
2575 ha->port_down_retry_count = 30; /* default value */
2576 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2577 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2578 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2579 ha->mr.fw_hbt_en = 1;
2580 }
2581
2582 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2583 "mbx_count=%d, req_length=%d, "
2584 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2585 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2586 "max_fibre_devices=%d.\n",
2587 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2588 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2589 ha->nvram_npiv_size, ha->max_fibre_devices);
2590 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2591 "isp_ops=%p, flash_conf_off=%d, "
2592 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2593 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2594 ha->nvram_conf_off, ha->nvram_data_off);
2595
2596 /* Configure PCI I/O space */
2597 ret = ha->isp_ops->iospace_config(ha);
2598 if (ret)
2599 goto iospace_config_failed;
2600
2601 ql_log_pci(ql_log_info, pdev, 0x001d,
2602 "Found an ISP%04X irq %d iobase 0x%p.\n",
2603 pdev->device, pdev->irq, ha->iobase);
2604 mutex_init(&ha->vport_lock);
2605 init_completion(&ha->mbx_cmd_comp);
2606 complete(&ha->mbx_cmd_comp);
2607 init_completion(&ha->mbx_intr_comp);
2608 init_completion(&ha->dcbx_comp);
2609 init_completion(&ha->lb_portup_comp);
2610
2611 set_bit(0, (unsigned long *) ha->vp_idx_map);
2612
2613 qla2x00_config_dma_addressing(ha);
2614 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2615 "64 Bit addressing is %s.\n",
2616 ha->flags.enable_64bit_addressing ? "enable" :
2617 "disable");
2618 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2619 if (!ret) {
2620 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2621 "Failed to allocate memory for adapter, aborting.\n");
2622
2623 goto probe_hw_failed;
2624 }
2625
2626 req->max_q_depth = MAX_Q_DEPTH;
2627 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2628 req->max_q_depth = ql2xmaxqdepth;
2629
2630
2631 base_vha = qla2x00_create_host(sht, ha);
2632 if (!base_vha) {
2633 ret = -ENOMEM;
2634 qla2x00_mem_free(ha);
2635 qla2x00_free_req_que(ha, req);
2636 qla2x00_free_rsp_que(ha, rsp);
2637 goto probe_hw_failed;
2638 }
2639
2640 pci_set_drvdata(pdev, base_vha);
2641
2642 host = base_vha->host;
2643 base_vha->req = req;
2644 if (IS_QLAFX00(ha))
2645 host->can_queue = 1024;
2646 else
2647 host->can_queue = req->length + 128;
2648 if (IS_QLA2XXX_MIDTYPE(ha))
2649 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2650 else
2651 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2652 base_vha->vp_idx;
2653
2654 /* Setup fcport template structure. */
2655 ha->mr.fcport.vha = base_vha;
2656 ha->mr.fcport.port_type = FCT_UNKNOWN;
2657 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2658 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2659 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2660 ha->mr.fcport.scan_state = 1;
2661
2662 /* Set the SG table size based on ISP type */
2663 if (!IS_FWI2_CAPABLE(ha)) {
2664 if (IS_QLA2100(ha))
2665 host->sg_tablesize = 32;
2666 } else {
2667 if (!IS_QLA82XX(ha))
2668 host->sg_tablesize = QLA_SG_ALL;
2669 }
2670 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2671 "can_queue=%d, req=%p, "
2672 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2673 host->can_queue, base_vha->req,
2674 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2675 host->max_id = ha->max_fibre_devices;
2676 host->cmd_per_lun = 3;
2677 host->unique_id = host->host_no;
2678 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2679 host->max_cmd_len = 32;
2680 else
2681 host->max_cmd_len = MAX_CMDSZ;
2682 host->max_channel = MAX_BUSES - 1;
2683 host->max_lun = ql2xmaxlun;
2684 host->transportt = qla2xxx_transport_template;
2685 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2686
2687 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2688 "max_id=%d this_id=%d "
2689 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2690 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
2691 host->this_id, host->cmd_per_lun, host->unique_id,
2692 host->max_cmd_len, host->max_channel, host->max_lun,
2693 host->transportt, sht->vendor_id);
2694
2695 que_init:
2696 /* Alloc arrays of request and response ring ptrs */
2697 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2698 ql_log(ql_log_fatal, base_vha, 0x003d,
2699 "Failed to allocate memory for queue pointers..."
2700 "aborting.\n");
2701 goto probe_init_failed;
2702 }
2703
2704 qlt_probe_one_stage1(base_vha, ha);
2705
2706 /* Set up the irqs */
2707 ret = qla2x00_request_irqs(ha, rsp);
2708 if (ret)
2709 goto probe_init_failed;
2710
2711 pci_save_state(pdev);
2712
2713 /* Assign back pointers */
2714 rsp->req = req;
2715 req->rsp = rsp;
2716
2717 if (IS_QLAFX00(ha)) {
2718 ha->rsp_q_map[0] = rsp;
2719 ha->req_q_map[0] = req;
2720 set_bit(0, ha->req_qid_map);
2721 set_bit(0, ha->rsp_qid_map);
2722 }
2723
2724 /* FWI2-capable only. */
2725 req->req_q_in = &ha->iobase->isp24.req_q_in;
2726 req->req_q_out = &ha->iobase->isp24.req_q_out;
2727 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2728 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2729 if (ha->mqenable || IS_QLA83XX(ha)) {
2730 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2731 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2732 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2733 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2734 }
2735
2736 if (IS_QLAFX00(ha)) {
2737 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2738 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2739 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2740 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2741 }
2742
2743 if (IS_P3P_TYPE(ha)) {
2744 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2745 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2746 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2747 }
2748
2749 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2750 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2751 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2752 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2753 "req->req_q_in=%p req->req_q_out=%p "
2754 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2755 req->req_q_in, req->req_q_out,
2756 rsp->rsp_q_in, rsp->rsp_q_out);
2757 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2758 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2759 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2760 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2761 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2762 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2763
2764 if (ha->isp_ops->initialize_adapter(base_vha)) {
2765 ql_log(ql_log_fatal, base_vha, 0x00d6,
2766 "Failed to initialize adapter - Adapter flags %x.\n",
2767 base_vha->device_flags);
2768
2769 if (IS_QLA82XX(ha)) {
2770 qla82xx_idc_lock(ha);
2771 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2772 QLA8XXX_DEV_FAILED);
2773 qla82xx_idc_unlock(ha);
2774 ql_log(ql_log_fatal, base_vha, 0x00d7,
2775 "HW State: FAILED.\n");
2776 } else if (IS_QLA8044(ha)) {
2777 qla8044_idc_lock(ha);
2778 qla8044_wr_direct(base_vha,
2779 QLA8044_CRB_DEV_STATE_INDEX,
2780 QLA8XXX_DEV_FAILED);
2781 qla8044_idc_unlock(ha);
2782 ql_log(ql_log_fatal, base_vha, 0x0150,
2783 "HW State: FAILED.\n");
2784 }
2785
2786 ret = -ENODEV;
2787 goto probe_failed;
2788 }
2789
2790 if (ha->mqenable) {
2791 if (qla25xx_setup_mode(base_vha)) {
2792 ql_log(ql_log_warn, base_vha, 0x00ec,
2793 "Failed to create queues, falling back to single queue mode.\n");
2794 goto que_init;
2795 }
2796 }
2797
2798 if (ha->flags.running_gold_fw)
2799 goto skip_dpc;
2800
2801 /*
2802 * Startup the kernel thread for this host adapter
2803 */
2804 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2805 "%s_dpc", base_vha->host_str);
2806 if (IS_ERR(ha->dpc_thread)) {
2807 ql_log(ql_log_fatal, base_vha, 0x00ed,
2808 "Failed to start DPC thread.\n");
2809 ret = PTR_ERR(ha->dpc_thread);
2810 goto probe_failed;
2811 }
2812 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2813 "DPC thread started successfully.\n");
2814
2815 /*
2816 * If we're not coming up in initiator mode, we might sit for
2817 * a while without waking up the dpc thread, which leads to a
2818 * stuck process warning. So just kick the dpc once here and
2819 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2820 */
2821 qla2xxx_wake_dpc(base_vha);
2822
2823 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2824 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2825 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2826 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2827
2828 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2829 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2830 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2831 INIT_WORK(&ha->idc_state_handler,
2832 qla83xx_idc_state_handler_work);
2833 INIT_WORK(&ha->nic_core_unrecoverable,
2834 qla83xx_nic_core_unrecoverable_work);
2835 }
2836
2837 skip_dpc:
2838 list_add_tail(&base_vha->list, &ha->vp_list);
2839 base_vha->host->irq = ha->pdev->irq;
2840
2841 /* Initialized the timer */
2842 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2843 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2844 "Started qla2x00_timer with "
2845 "interval=%d.\n", WATCH_INTERVAL);
2846 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2847 "Detected hba at address=%p.\n",
2848 ha);
2849
2850 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2851 if (ha->fw_attributes & BIT_4) {
2852 int prot = 0, guard;
2853 base_vha->flags.difdix_supported = 1;
2854 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2855 "Registering for DIF/DIX type 1 and 3 protection.\n");
2856 if (ql2xenabledif == 1)
2857 prot = SHOST_DIX_TYPE0_PROTECTION;
2858 scsi_host_set_prot(host,
2859 prot | SHOST_DIF_TYPE1_PROTECTION
2860 | SHOST_DIF_TYPE2_PROTECTION
2861 | SHOST_DIF_TYPE3_PROTECTION
2862 | SHOST_DIX_TYPE1_PROTECTION
2863 | SHOST_DIX_TYPE2_PROTECTION
2864 | SHOST_DIX_TYPE3_PROTECTION);
2865
2866 guard = SHOST_DIX_GUARD_CRC;
2867
2868 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2869 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2870 guard |= SHOST_DIX_GUARD_IP;
2871
2872 scsi_host_set_guard(host, guard);
2873 } else
2874 base_vha->flags.difdix_supported = 0;
2875 }
2876
2877 ha->isp_ops->enable_intrs(ha);
2878
2879 if (IS_QLAFX00(ha)) {
2880 ret = qlafx00_fx_disc(base_vha,
2881 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2882 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2883 QLA_SG_ALL : 128;
2884 }
2885
2886 ret = scsi_add_host(host, &pdev->dev);
2887 if (ret)
2888 goto probe_failed;
2889
2890 base_vha->flags.init_done = 1;
2891 base_vha->flags.online = 1;
2892
2893 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2894 "Init done and hba is online.\n");
2895
2896 if (qla_ini_mode_enabled(base_vha))
2897 scsi_scan_host(host);
2898 else
2899 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2900 "skipping scsi_scan_host() for non-initiator port\n");
2901
2902 qla2x00_alloc_sysfs_attr(base_vha);
2903
2904 if (IS_QLAFX00(ha)) {
2905 ret = qlafx00_fx_disc(base_vha,
2906 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2907
2908 /* Register system information */
2909 ret = qlafx00_fx_disc(base_vha,
2910 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2911 }
2912
2913 qla2x00_init_host_attr(base_vha);
2914
2915 qla2x00_dfs_setup(base_vha);
2916
2917 ql_log(ql_log_info, base_vha, 0x00fb,
2918 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2919 ql_log(ql_log_info, base_vha, 0x00fc,
2920 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2921 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2922 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2923 base_vha->host_no,
2924 ha->isp_ops->fw_version_str(base_vha, fw_str));
2925
2926 qlt_add_target(ha, base_vha);
2927
2928 return 0;
2929
2930 probe_init_failed:
2931 qla2x00_free_req_que(ha, req);
2932 ha->req_q_map[0] = NULL;
2933 clear_bit(0, ha->req_qid_map);
2934 qla2x00_free_rsp_que(ha, rsp);
2935 ha->rsp_q_map[0] = NULL;
2936 clear_bit(0, ha->rsp_qid_map);
2937 ha->max_req_queues = ha->max_rsp_queues = 0;
2938
2939 probe_failed:
2940 if (base_vha->timer_active)
2941 qla2x00_stop_timer(base_vha);
2942 base_vha->flags.online = 0;
2943 if (ha->dpc_thread) {
2944 struct task_struct *t = ha->dpc_thread;
2945
2946 ha->dpc_thread = NULL;
2947 kthread_stop(t);
2948 }
2949
2950 qla2x00_free_device(base_vha);
2951
2952 scsi_host_put(base_vha->host);
2953
2954 probe_hw_failed:
2955 if (IS_QLA82XX(ha)) {
2956 qla82xx_idc_lock(ha);
2957 qla82xx_clear_drv_active(ha);
2958 qla82xx_idc_unlock(ha);
2959 }
2960 if (IS_QLA8044(ha)) {
2961 qla8044_idc_lock(ha);
2962 qla8044_clear_drv_active(base_vha);
2963 qla8044_idc_unlock(ha);
2964 }
2965 iospace_config_failed:
2966 if (IS_P3P_TYPE(ha)) {
2967 if (!ha->nx_pcibase)
2968 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2969 if (!ql2xdbwr)
2970 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2971 } else {
2972 if (ha->iobase)
2973 iounmap(ha->iobase);
2974 if (ha->cregbase)
2975 iounmap(ha->cregbase);
2976 }
2977 pci_release_selected_regions(ha->pdev, ha->bars);
2978 kfree(ha);
2979 ha = NULL;
2980
2981 probe_out:
2982 pci_disable_device(pdev);
2983 return ret;
2984 }
2985
2986 static void
2987 qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2988 {
2989 struct qla_hw_data *ha = vha->hw;
2990 struct task_struct *t = ha->dpc_thread;
2991
2992 if (ha->dpc_thread == NULL)
2993 return;
2994 /*
2995 * qla2xxx_wake_dpc checks for ->dpc_thread
2996 * so we need to zero it out.
2997 */
2998 ha->dpc_thread = NULL;
2999 kthread_stop(t);
3000 }
3001
3002 static void
3003 qla2x00_shutdown(struct pci_dev *pdev)
3004 {
3005 scsi_qla_host_t *vha;
3006 struct qla_hw_data *ha;
3007
3008 if (!atomic_read(&pdev->enable_cnt))
3009 return;
3010
3011 vha = pci_get_drvdata(pdev);
3012 ha = vha->hw;
3013
3014 /* Notify ISPFX00 firmware */
3015 if (IS_QLAFX00(ha))
3016 qlafx00_driver_shutdown(vha, 20);
3017
3018 /* Turn-off FCE trace */
3019 if (ha->flags.fce_enabled) {
3020 qla2x00_disable_fce_trace(vha, NULL, NULL);
3021 ha->flags.fce_enabled = 0;
3022 }
3023
3024 /* Turn-off EFT trace */
3025 if (ha->eft)
3026 qla2x00_disable_eft_trace(vha);
3027
3028 /* Stop currently executing firmware. */
3029 qla2x00_try_to_stop_firmware(vha);
3030
3031 /* Turn adapter off line */
3032 vha->flags.online = 0;
3033
3034 /* turn-off interrupts on the card */
3035 if (ha->interrupts_on) {
3036 vha->flags.init_done = 0;
3037 ha->isp_ops->disable_intrs(ha);
3038 }
3039
3040 qla2x00_free_irqs(vha);
3041
3042 qla2x00_free_fw_dump(ha);
3043 }
3044
3045 static void
3046 qla2x00_remove_one(struct pci_dev *pdev)
3047 {
3048 scsi_qla_host_t *base_vha, *vha;
3049 struct qla_hw_data *ha;
3050 unsigned long flags;
3051
3052 /*
3053 * If the PCI device is disabled that means that probe failed and any
3054 * resources should be have cleaned up on probe exit.
3055 */
3056 if (!atomic_read(&pdev->enable_cnt))
3057 return;
3058
3059 base_vha = pci_get_drvdata(pdev);
3060 ha = base_vha->hw;
3061
3062 ha->flags.host_shutting_down = 1;
3063
3064 set_bit(UNLOADING, &base_vha->dpc_flags);
3065 if (IS_QLAFX00(ha))
3066 qlafx00_driver_shutdown(base_vha, 20);
3067
3068 mutex_lock(&ha->vport_lock);
3069 while (ha->cur_vport_count) {
3070 spin_lock_irqsave(&ha->vport_slock, flags);
3071
3072 BUG_ON(base_vha->list.next == &ha->vp_list);
3073 /* This assumes first entry in ha->vp_list is always base vha */
3074 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3075 scsi_host_get(vha->host);
3076
3077 spin_unlock_irqrestore(&ha->vport_slock, flags);
3078 mutex_unlock(&ha->vport_lock);
3079
3080 fc_vport_terminate(vha->fc_vport);
3081 scsi_host_put(vha->host);
3082
3083 mutex_lock(&ha->vport_lock);
3084 }
3085 mutex_unlock(&ha->vport_lock);
3086
3087 if (IS_QLA8031(ha)) {
3088 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3089 "Clearing fcoe driver presence.\n");
3090 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3091 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3092 "Error while clearing DRV-Presence.\n");
3093 }
3094
3095 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3096
3097 qla2x00_dfs_remove(base_vha);
3098
3099 qla84xx_put_chip(base_vha);
3100
3101 /* Disable timer */
3102 if (base_vha->timer_active)
3103 qla2x00_stop_timer(base_vha);
3104
3105 base_vha->flags.online = 0;
3106
3107 /* Flush the work queue and remove it */
3108 if (ha->wq) {
3109 flush_workqueue(ha->wq);
3110 destroy_workqueue(ha->wq);
3111 ha->wq = NULL;
3112 }
3113
3114 /* Cancel all work and destroy DPC workqueues */
3115 if (ha->dpc_lp_wq) {
3116 cancel_work_sync(&ha->idc_aen);
3117 destroy_workqueue(ha->dpc_lp_wq);
3118 ha->dpc_lp_wq = NULL;
3119 }
3120
3121 if (ha->dpc_hp_wq) {
3122 cancel_work_sync(&ha->nic_core_reset);
3123 cancel_work_sync(&ha->idc_state_handler);
3124 cancel_work_sync(&ha->nic_core_unrecoverable);
3125 destroy_workqueue(ha->dpc_hp_wq);
3126 ha->dpc_hp_wq = NULL;
3127 }
3128
3129 /* Kill the kernel thread for this host */
3130 if (ha->dpc_thread) {
3131 struct task_struct *t = ha->dpc_thread;
3132
3133 /*
3134 * qla2xxx_wake_dpc checks for ->dpc_thread
3135 * so we need to zero it out.
3136 */
3137 ha->dpc_thread = NULL;
3138 kthread_stop(t);
3139 }
3140 qlt_remove_target(ha, base_vha);
3141
3142 qla2x00_free_sysfs_attr(base_vha);
3143
3144 fc_remove_host(base_vha->host);
3145
3146 scsi_remove_host(base_vha->host);
3147
3148 qla2x00_free_device(base_vha);
3149
3150 scsi_host_put(base_vha->host);
3151
3152 if (IS_QLA8044(ha)) {
3153 qla8044_idc_lock(ha);
3154 qla8044_clear_drv_active(base_vha);
3155 qla8044_idc_unlock(ha);
3156 }
3157 if (IS_QLA82XX(ha)) {
3158 qla82xx_idc_lock(ha);
3159 qla82xx_clear_drv_active(ha);
3160 qla82xx_idc_unlock(ha);
3161
3162 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3163 if (!ql2xdbwr)
3164 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3165 } else {
3166 if (ha->iobase)
3167 iounmap(ha->iobase);
3168
3169 if (ha->cregbase)
3170 iounmap(ha->cregbase);
3171
3172 if (ha->mqiobase)
3173 iounmap(ha->mqiobase);
3174
3175 if (IS_QLA83XX(ha) && ha->msixbase)
3176 iounmap(ha->msixbase);
3177 }
3178
3179 pci_release_selected_regions(ha->pdev, ha->bars);
3180 kfree(ha);
3181 ha = NULL;
3182
3183 pci_disable_pcie_error_reporting(pdev);
3184
3185 pci_disable_device(pdev);
3186 }
3187
3188 static void
3189 qla2x00_free_device(scsi_qla_host_t *vha)
3190 {
3191 struct qla_hw_data *ha = vha->hw;
3192
3193 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3194
3195 /* Disable timer */
3196 if (vha->timer_active)
3197 qla2x00_stop_timer(vha);
3198
3199 qla2x00_stop_dpc_thread(vha);
3200
3201 qla25xx_delete_queues(vha);
3202 if (ha->flags.fce_enabled)
3203 qla2x00_disable_fce_trace(vha, NULL, NULL);
3204
3205 if (ha->eft)
3206 qla2x00_disable_eft_trace(vha);
3207
3208 /* Stop currently executing firmware. */
3209 qla2x00_try_to_stop_firmware(vha);
3210
3211 vha->flags.online = 0;
3212
3213 /* turn-off interrupts on the card */
3214 if (ha->interrupts_on) {
3215 vha->flags.init_done = 0;
3216 ha->isp_ops->disable_intrs(ha);
3217 }
3218
3219 qla2x00_free_irqs(vha);
3220
3221 qla2x00_free_fcports(vha);
3222
3223 qla2x00_mem_free(ha);
3224
3225 qla82xx_md_free(vha);
3226
3227 qla2x00_free_queues(ha);
3228 }
3229
3230 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3231 {
3232 fc_port_t *fcport, *tfcport;
3233
3234 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3235 list_del(&fcport->list);
3236 qla2x00_clear_loop_id(fcport);
3237 kfree(fcport);
3238 fcport = NULL;
3239 }
3240 }
3241
3242 static inline void
3243 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3244 int defer)
3245 {
3246 struct fc_rport *rport;
3247 scsi_qla_host_t *base_vha;
3248 unsigned long flags;
3249
3250 if (!fcport->rport)
3251 return;
3252
3253 rport = fcport->rport;
3254 if (defer) {
3255 base_vha = pci_get_drvdata(vha->hw->pdev);
3256 spin_lock_irqsave(vha->host->host_lock, flags);
3257 fcport->drport = rport;
3258 spin_unlock_irqrestore(vha->host->host_lock, flags);
3259 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3260 qla2xxx_wake_dpc(base_vha);
3261 } else {
3262 fc_remote_port_delete(rport);
3263 qlt_fc_port_deleted(vha, fcport);
3264 }
3265 }
3266
3267 /*
3268 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3269 *
3270 * Input: ha = adapter block pointer. fcport = port structure pointer.
3271 *
3272 * Return: None.
3273 *
3274 * Context:
3275 */
3276 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3277 int do_login, int defer)
3278 {
3279 if (IS_QLAFX00(vha->hw)) {
3280 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3281 qla2x00_schedule_rport_del(vha, fcport, defer);
3282 return;
3283 }
3284
3285 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3286 vha->vp_idx == fcport->vha->vp_idx) {
3287 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3288 qla2x00_schedule_rport_del(vha, fcport, defer);
3289 }
3290 /*
3291 * We may need to retry the login, so don't change the state of the
3292 * port but do the retries.
3293 */
3294 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3295 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3296
3297 if (!do_login)
3298 return;
3299
3300 if (fcport->login_retry == 0) {
3301 fcport->login_retry = vha->hw->login_retry_count;
3302 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3303
3304 ql_dbg(ql_dbg_disc, vha, 0x2067,
3305 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3306 fcport->port_name, fcport->loop_id, fcport->login_retry);
3307 }
3308 }
3309
3310 /*
3311 * qla2x00_mark_all_devices_lost
3312 * Updates fcport state when device goes offline.
3313 *
3314 * Input:
3315 * ha = adapter block pointer.
3316 * fcport = port structure pointer.
3317 *
3318 * Return:
3319 * None.
3320 *
3321 * Context:
3322 */
3323 void
3324 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3325 {
3326 fc_port_t *fcport;
3327
3328 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3329 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3330 continue;
3331
3332 /*
3333 * No point in marking the device as lost, if the device is
3334 * already DEAD.
3335 */
3336 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3337 continue;
3338 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3339 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3340 if (defer)
3341 qla2x00_schedule_rport_del(vha, fcport, defer);
3342 else if (vha->vp_idx == fcport->vha->vp_idx)
3343 qla2x00_schedule_rport_del(vha, fcport, defer);
3344 }
3345 }
3346 }
3347
3348 /*
3349 * qla2x00_mem_alloc
3350 * Allocates adapter memory.
3351 *
3352 * Returns:
3353 * 0 = success.
3354 * !0 = failure.
3355 */
3356 static int
3357 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3358 struct req_que **req, struct rsp_que **rsp)
3359 {
3360 char name[16];
3361
3362 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3363 &ha->init_cb_dma, GFP_KERNEL);
3364 if (!ha->init_cb)
3365 goto fail;
3366
3367 if (qlt_mem_alloc(ha) < 0)
3368 goto fail_free_init_cb;
3369
3370 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3371 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3372 if (!ha->gid_list)
3373 goto fail_free_tgt_mem;
3374
3375 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3376 if (!ha->srb_mempool)
3377 goto fail_free_gid_list;
3378
3379 if (IS_P3P_TYPE(ha)) {
3380 /* Allocate cache for CT6 Ctx. */
3381 if (!ctx_cachep) {
3382 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3383 sizeof(struct ct6_dsd), 0,
3384 SLAB_HWCACHE_ALIGN, NULL);
3385 if (!ctx_cachep)
3386 goto fail_free_gid_list;
3387 }
3388 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3389 ctx_cachep);
3390 if (!ha->ctx_mempool)
3391 goto fail_free_srb_mempool;
3392 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3393 "ctx_cachep=%p ctx_mempool=%p.\n",
3394 ctx_cachep, ha->ctx_mempool);
3395 }
3396
3397 /* Get memory for cached NVRAM */
3398 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3399 if (!ha->nvram)
3400 goto fail_free_ctx_mempool;
3401
3402 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3403 ha->pdev->device);
3404 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3405 DMA_POOL_SIZE, 8, 0);
3406 if (!ha->s_dma_pool)
3407 goto fail_free_nvram;
3408
3409 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3410 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3411 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3412
3413 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3414 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3415 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3416 if (!ha->dl_dma_pool) {
3417 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3418 "Failed to allocate memory for dl_dma_pool.\n");
3419 goto fail_s_dma_pool;
3420 }
3421
3422 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3423 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3424 if (!ha->fcp_cmnd_dma_pool) {
3425 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3426 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3427 goto fail_dl_dma_pool;
3428 }
3429 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3430 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3431 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3432 }
3433
3434 /* Allocate memory for SNS commands */
3435 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3436 /* Get consistent memory allocated for SNS commands */
3437 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3438 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3439 if (!ha->sns_cmd)
3440 goto fail_dma_pool;
3441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3442 "sns_cmd: %p.\n", ha->sns_cmd);
3443 } else {
3444 /* Get consistent memory allocated for MS IOCB */
3445 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3446 &ha->ms_iocb_dma);
3447 if (!ha->ms_iocb)
3448 goto fail_dma_pool;
3449 /* Get consistent memory allocated for CT SNS commands */
3450 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3451 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3452 if (!ha->ct_sns)
3453 goto fail_free_ms_iocb;
3454 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3455 "ms_iocb=%p ct_sns=%p.\n",
3456 ha->ms_iocb, ha->ct_sns);
3457 }
3458
3459 /* Allocate memory for request ring */
3460 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3461 if (!*req) {
3462 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3463 "Failed to allocate memory for req.\n");
3464 goto fail_req;
3465 }
3466 (*req)->length = req_len;
3467 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3468 ((*req)->length + 1) * sizeof(request_t),
3469 &(*req)->dma, GFP_KERNEL);
3470 if (!(*req)->ring) {
3471 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3472 "Failed to allocate memory for req_ring.\n");
3473 goto fail_req_ring;
3474 }
3475 /* Allocate memory for response ring */
3476 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3477 if (!*rsp) {
3478 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3479 "Failed to allocate memory for rsp.\n");
3480 goto fail_rsp;
3481 }
3482 (*rsp)->hw = ha;
3483 (*rsp)->length = rsp_len;
3484 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3485 ((*rsp)->length + 1) * sizeof(response_t),
3486 &(*rsp)->dma, GFP_KERNEL);
3487 if (!(*rsp)->ring) {
3488 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3489 "Failed to allocate memory for rsp_ring.\n");
3490 goto fail_rsp_ring;
3491 }
3492 (*req)->rsp = *rsp;
3493 (*rsp)->req = *req;
3494 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3495 "req=%p req->length=%d req->ring=%p rsp=%p "
3496 "rsp->length=%d rsp->ring=%p.\n",
3497 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3498 (*rsp)->ring);
3499 /* Allocate memory for NVRAM data for vports */
3500 if (ha->nvram_npiv_size) {
3501 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3502 ha->nvram_npiv_size, GFP_KERNEL);
3503 if (!ha->npiv_info) {
3504 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3505 "Failed to allocate memory for npiv_info.\n");
3506 goto fail_npiv_info;
3507 }
3508 } else
3509 ha->npiv_info = NULL;
3510
3511 /* Get consistent memory allocated for EX-INIT-CB. */
3512 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
3513 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3514 &ha->ex_init_cb_dma);
3515 if (!ha->ex_init_cb)
3516 goto fail_ex_init_cb;
3517 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3518 "ex_init_cb=%p.\n", ha->ex_init_cb);
3519 }
3520
3521 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3522
3523 /* Get consistent memory allocated for Async Port-Database. */
3524 if (!IS_FWI2_CAPABLE(ha)) {
3525 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3526 &ha->async_pd_dma);
3527 if (!ha->async_pd)
3528 goto fail_async_pd;
3529 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3530 "async_pd=%p.\n", ha->async_pd);
3531 }
3532
3533 INIT_LIST_HEAD(&ha->vp_list);
3534
3535 /* Allocate memory for our loop_id bitmap */
3536 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3537 GFP_KERNEL);
3538 if (!ha->loop_id_map)
3539 goto fail_async_pd;
3540 else {
3541 qla2x00_set_reserved_loop_ids(ha);
3542 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3543 "loop_id_map=%p. \n", ha->loop_id_map);
3544 }
3545
3546 return 1;
3547
3548 fail_async_pd:
3549 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3550 fail_ex_init_cb:
3551 kfree(ha->npiv_info);
3552 fail_npiv_info:
3553 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3554 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3555 (*rsp)->ring = NULL;
3556 (*rsp)->dma = 0;
3557 fail_rsp_ring:
3558 kfree(*rsp);
3559 fail_rsp:
3560 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3561 sizeof(request_t), (*req)->ring, (*req)->dma);
3562 (*req)->ring = NULL;
3563 (*req)->dma = 0;
3564 fail_req_ring:
3565 kfree(*req);
3566 fail_req:
3567 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3568 ha->ct_sns, ha->ct_sns_dma);
3569 ha->ct_sns = NULL;
3570 ha->ct_sns_dma = 0;
3571 fail_free_ms_iocb:
3572 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3573 ha->ms_iocb = NULL;
3574 ha->ms_iocb_dma = 0;
3575 fail_dma_pool:
3576 if (IS_QLA82XX(ha) || ql2xenabledif) {
3577 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3578 ha->fcp_cmnd_dma_pool = NULL;
3579 }
3580 fail_dl_dma_pool:
3581 if (IS_QLA82XX(ha) || ql2xenabledif) {
3582 dma_pool_destroy(ha->dl_dma_pool);
3583 ha->dl_dma_pool = NULL;
3584 }
3585 fail_s_dma_pool:
3586 dma_pool_destroy(ha->s_dma_pool);
3587 ha->s_dma_pool = NULL;
3588 fail_free_nvram:
3589 kfree(ha->nvram);
3590 ha->nvram = NULL;
3591 fail_free_ctx_mempool:
3592 mempool_destroy(ha->ctx_mempool);
3593 ha->ctx_mempool = NULL;
3594 fail_free_srb_mempool:
3595 mempool_destroy(ha->srb_mempool);
3596 ha->srb_mempool = NULL;
3597 fail_free_gid_list:
3598 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3599 ha->gid_list,
3600 ha->gid_list_dma);
3601 ha->gid_list = NULL;
3602 ha->gid_list_dma = 0;
3603 fail_free_tgt_mem:
3604 qlt_mem_free(ha);
3605 fail_free_init_cb:
3606 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3607 ha->init_cb_dma);
3608 ha->init_cb = NULL;
3609 ha->init_cb_dma = 0;
3610 fail:
3611 ql_log(ql_log_fatal, NULL, 0x0030,
3612 "Memory allocation failure.\n");
3613 return -ENOMEM;
3614 }
3615
3616 /*
3617 * qla2x00_free_fw_dump
3618 * Frees fw dump stuff.
3619 *
3620 * Input:
3621 * ha = adapter block pointer
3622 */
3623 static void
3624 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3625 {
3626 if (ha->fce)
3627 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
3628 ha->fce_dma);
3629
3630 if (ha->fw_dump) {
3631 if (ha->eft)
3632 dma_free_coherent(&ha->pdev->dev,
3633 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
3634 vfree(ha->fw_dump);
3635 }
3636 ha->fce = NULL;
3637 ha->fce_dma = 0;
3638 ha->eft = NULL;
3639 ha->eft_dma = 0;
3640 ha->fw_dump = NULL;
3641 ha->fw_dumped = 0;
3642 ha->fw_dump_reading = 0;
3643 }
3644
3645 /*
3646 * qla2x00_mem_free
3647 * Frees all adapter allocated memory.
3648 *
3649 * Input:
3650 * ha = adapter block pointer.
3651 */
3652 static void
3653 qla2x00_mem_free(struct qla_hw_data *ha)
3654 {
3655 qla2x00_free_fw_dump(ha);
3656
3657 if (ha->mctp_dump)
3658 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3659 ha->mctp_dump_dma);
3660
3661 if (ha->srb_mempool)
3662 mempool_destroy(ha->srb_mempool);
3663
3664 if (ha->dcbx_tlv)
3665 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3666 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3667
3668 if (ha->xgmac_data)
3669 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3670 ha->xgmac_data, ha->xgmac_data_dma);
3671
3672 if (ha->sns_cmd)
3673 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3674 ha->sns_cmd, ha->sns_cmd_dma);
3675
3676 if (ha->ct_sns)
3677 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3678 ha->ct_sns, ha->ct_sns_dma);
3679
3680 if (ha->sfp_data)
3681 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3682
3683 if (ha->ms_iocb)
3684 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3685
3686 if (ha->ex_init_cb)
3687 dma_pool_free(ha->s_dma_pool,
3688 ha->ex_init_cb, ha->ex_init_cb_dma);
3689
3690 if (ha->async_pd)
3691 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3692
3693 if (ha->s_dma_pool)
3694 dma_pool_destroy(ha->s_dma_pool);
3695
3696 if (ha->gid_list)
3697 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3698 ha->gid_list, ha->gid_list_dma);
3699
3700 if (IS_QLA82XX(ha)) {
3701 if (!list_empty(&ha->gbl_dsd_list)) {
3702 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3703
3704 /* clean up allocated prev pool */
3705 list_for_each_entry_safe(dsd_ptr,
3706 tdsd_ptr, &ha->gbl_dsd_list, list) {
3707 dma_pool_free(ha->dl_dma_pool,
3708 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3709 list_del(&dsd_ptr->list);
3710 kfree(dsd_ptr);
3711 }
3712 }
3713 }
3714
3715 if (ha->dl_dma_pool)
3716 dma_pool_destroy(ha->dl_dma_pool);
3717
3718 if (ha->fcp_cmnd_dma_pool)
3719 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3720
3721 if (ha->ctx_mempool)
3722 mempool_destroy(ha->ctx_mempool);
3723
3724 qlt_mem_free(ha);
3725
3726 if (ha->init_cb)
3727 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3728 ha->init_cb, ha->init_cb_dma);
3729 vfree(ha->optrom_buffer);
3730 kfree(ha->nvram);
3731 kfree(ha->npiv_info);
3732 kfree(ha->swl);
3733 kfree(ha->loop_id_map);
3734
3735 ha->srb_mempool = NULL;
3736 ha->ctx_mempool = NULL;
3737 ha->sns_cmd = NULL;
3738 ha->sns_cmd_dma = 0;
3739 ha->ct_sns = NULL;
3740 ha->ct_sns_dma = 0;
3741 ha->ms_iocb = NULL;
3742 ha->ms_iocb_dma = 0;
3743 ha->init_cb = NULL;
3744 ha->init_cb_dma = 0;
3745 ha->ex_init_cb = NULL;
3746 ha->ex_init_cb_dma = 0;
3747 ha->async_pd = NULL;
3748 ha->async_pd_dma = 0;
3749
3750 ha->s_dma_pool = NULL;
3751 ha->dl_dma_pool = NULL;
3752 ha->fcp_cmnd_dma_pool = NULL;
3753
3754 ha->gid_list = NULL;
3755 ha->gid_list_dma = 0;
3756
3757 ha->tgt.atio_ring = NULL;
3758 ha->tgt.atio_dma = 0;
3759 ha->tgt.tgt_vp_map = NULL;
3760 }
3761
3762 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3763 struct qla_hw_data *ha)
3764 {
3765 struct Scsi_Host *host;
3766 struct scsi_qla_host *vha = NULL;
3767
3768 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3769 if (host == NULL) {
3770 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3771 "Failed to allocate host from the scsi layer, aborting.\n");
3772 goto fail;
3773 }
3774
3775 /* Clear our data area */
3776 vha = shost_priv(host);
3777 memset(vha, 0, sizeof(scsi_qla_host_t));
3778
3779 vha->host = host;
3780 vha->host_no = host->host_no;
3781 vha->hw = ha;
3782
3783 INIT_LIST_HEAD(&vha->vp_fcports);
3784 INIT_LIST_HEAD(&vha->work_list);
3785 INIT_LIST_HEAD(&vha->list);
3786
3787 spin_lock_init(&vha->work_lock);
3788
3789 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3790 ql_dbg(ql_dbg_init, vha, 0x0041,
3791 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3792 vha->host, vha->hw, vha,
3793 dev_name(&(ha->pdev->dev)));
3794
3795 return vha;
3796
3797 fail:
3798 return vha;
3799 }
3800
3801 static struct qla_work_evt *
3802 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3803 {
3804 struct qla_work_evt *e;
3805 uint8_t bail;
3806
3807 QLA_VHA_MARK_BUSY(vha, bail);
3808 if (bail)
3809 return NULL;
3810
3811 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3812 if (!e) {
3813 QLA_VHA_MARK_NOT_BUSY(vha);
3814 return NULL;
3815 }
3816
3817 INIT_LIST_HEAD(&e->list);
3818 e->type = type;
3819 e->flags = QLA_EVT_FLAG_FREE;
3820 return e;
3821 }
3822
3823 static int
3824 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3825 {
3826 unsigned long flags;
3827
3828 spin_lock_irqsave(&vha->work_lock, flags);
3829 list_add_tail(&e->list, &vha->work_list);
3830 spin_unlock_irqrestore(&vha->work_lock, flags);
3831 qla2xxx_wake_dpc(vha);
3832
3833 return QLA_SUCCESS;
3834 }
3835
3836 int
3837 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3838 u32 data)
3839 {
3840 struct qla_work_evt *e;
3841
3842 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3843 if (!e)
3844 return QLA_FUNCTION_FAILED;
3845
3846 e->u.aen.code = code;
3847 e->u.aen.data = data;
3848 return qla2x00_post_work(vha, e);
3849 }
3850
3851 int
3852 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3853 {
3854 struct qla_work_evt *e;
3855
3856 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3857 if (!e)
3858 return QLA_FUNCTION_FAILED;
3859
3860 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3861 return qla2x00_post_work(vha, e);
3862 }
3863
3864 #define qla2x00_post_async_work(name, type) \
3865 int qla2x00_post_async_##name##_work( \
3866 struct scsi_qla_host *vha, \
3867 fc_port_t *fcport, uint16_t *data) \
3868 { \
3869 struct qla_work_evt *e; \
3870 \
3871 e = qla2x00_alloc_work(vha, type); \
3872 if (!e) \
3873 return QLA_FUNCTION_FAILED; \
3874 \
3875 e->u.logio.fcport = fcport; \
3876 if (data) { \
3877 e->u.logio.data[0] = data[0]; \
3878 e->u.logio.data[1] = data[1]; \
3879 } \
3880 return qla2x00_post_work(vha, e); \
3881 }
3882
3883 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3884 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3885 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3886 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3887 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3888 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3889
3890 int
3891 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3892 {
3893 struct qla_work_evt *e;
3894
3895 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3896 if (!e)
3897 return QLA_FUNCTION_FAILED;
3898
3899 e->u.uevent.code = code;
3900 return qla2x00_post_work(vha, e);
3901 }
3902
3903 static void
3904 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3905 {
3906 char event_string[40];
3907 char *envp[] = { event_string, NULL };
3908
3909 switch (code) {
3910 case QLA_UEVENT_CODE_FW_DUMP:
3911 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3912 vha->host_no);
3913 break;
3914 default:
3915 /* do nothing */
3916 break;
3917 }
3918 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3919 }
3920
3921 int
3922 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3923 uint32_t *data, int cnt)
3924 {
3925 struct qla_work_evt *e;
3926
3927 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3928 if (!e)
3929 return QLA_FUNCTION_FAILED;
3930
3931 e->u.aenfx.evtcode = evtcode;
3932 e->u.aenfx.count = cnt;
3933 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3934 return qla2x00_post_work(vha, e);
3935 }
3936
3937 void
3938 qla2x00_do_work(struct scsi_qla_host *vha)
3939 {
3940 struct qla_work_evt *e, *tmp;
3941 unsigned long flags;
3942 LIST_HEAD(work);
3943
3944 spin_lock_irqsave(&vha->work_lock, flags);
3945 list_splice_init(&vha->work_list, &work);
3946 spin_unlock_irqrestore(&vha->work_lock, flags);
3947
3948 list_for_each_entry_safe(e, tmp, &work, list) {
3949 list_del_init(&e->list);
3950
3951 switch (e->type) {
3952 case QLA_EVT_AEN:
3953 fc_host_post_event(vha->host, fc_get_event_number(),
3954 e->u.aen.code, e->u.aen.data);
3955 break;
3956 case QLA_EVT_IDC_ACK:
3957 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3958 break;
3959 case QLA_EVT_ASYNC_LOGIN:
3960 qla2x00_async_login(vha, e->u.logio.fcport,
3961 e->u.logio.data);
3962 break;
3963 case QLA_EVT_ASYNC_LOGIN_DONE:
3964 qla2x00_async_login_done(vha, e->u.logio.fcport,
3965 e->u.logio.data);
3966 break;
3967 case QLA_EVT_ASYNC_LOGOUT:
3968 qla2x00_async_logout(vha, e->u.logio.fcport);
3969 break;
3970 case QLA_EVT_ASYNC_LOGOUT_DONE:
3971 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3972 e->u.logio.data);
3973 break;
3974 case QLA_EVT_ASYNC_ADISC:
3975 qla2x00_async_adisc(vha, e->u.logio.fcport,
3976 e->u.logio.data);
3977 break;
3978 case QLA_EVT_ASYNC_ADISC_DONE:
3979 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3980 e->u.logio.data);
3981 break;
3982 case QLA_EVT_UEVENT:
3983 qla2x00_uevent_emit(vha, e->u.uevent.code);
3984 break;
3985 case QLA_EVT_AENFX:
3986 qlafx00_process_aen(vha, e);
3987 break;
3988 }
3989 if (e->flags & QLA_EVT_FLAG_FREE)
3990 kfree(e);
3991
3992 /* For each work completed decrement vha ref count */
3993 QLA_VHA_MARK_NOT_BUSY(vha);
3994 }
3995 }
3996
3997 /* Relogins all the fcports of a vport
3998 * Context: dpc thread
3999 */
4000 void qla2x00_relogin(struct scsi_qla_host *vha)
4001 {
4002 fc_port_t *fcport;
4003 int status;
4004 uint16_t next_loopid = 0;
4005 struct qla_hw_data *ha = vha->hw;
4006 uint16_t data[2];
4007
4008 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4009 /*
4010 * If the port is not ONLINE then try to login
4011 * to it if we haven't run out of retries.
4012 */
4013 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4014 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
4015 fcport->login_retry--;
4016 if (fcport->flags & FCF_FABRIC_DEVICE) {
4017 if (fcport->flags & FCF_FCP2_DEVICE)
4018 ha->isp_ops->fabric_logout(vha,
4019 fcport->loop_id,
4020 fcport->d_id.b.domain,
4021 fcport->d_id.b.area,
4022 fcport->d_id.b.al_pa);
4023
4024 if (fcport->loop_id == FC_NO_LOOP_ID) {
4025 fcport->loop_id = next_loopid =
4026 ha->min_external_loopid;
4027 status = qla2x00_find_new_loop_id(
4028 vha, fcport);
4029 if (status != QLA_SUCCESS) {
4030 /* Ran out of IDs to use */
4031 break;
4032 }
4033 }
4034
4035 if (IS_ALOGIO_CAPABLE(ha)) {
4036 fcport->flags |= FCF_ASYNC_SENT;
4037 data[0] = 0;
4038 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4039 status = qla2x00_post_async_login_work(
4040 vha, fcport, data);
4041 if (status == QLA_SUCCESS)
4042 continue;
4043 /* Attempt a retry. */
4044 status = 1;
4045 } else {
4046 status = qla2x00_fabric_login(vha,
4047 fcport, &next_loopid);
4048 if (status == QLA_SUCCESS) {
4049 int status2;
4050 uint8_t opts;
4051
4052 opts = 0;
4053 if (fcport->flags &
4054 FCF_FCP2_DEVICE)
4055 opts |= BIT_1;
4056 status2 =
4057 qla2x00_get_port_database(
4058 vha, fcport, opts);
4059 if (status2 != QLA_SUCCESS)
4060 status = 1;
4061 }
4062 }
4063 } else
4064 status = qla2x00_local_device_login(vha,
4065 fcport);
4066
4067 if (status == QLA_SUCCESS) {
4068 fcport->old_loop_id = fcport->loop_id;
4069
4070 ql_dbg(ql_dbg_disc, vha, 0x2003,
4071 "Port login OK: logged in ID 0x%x.\n",
4072 fcport->loop_id);
4073
4074 qla2x00_update_fcport(vha, fcport);
4075
4076 } else if (status == 1) {
4077 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4078 /* retry the login again */
4079 ql_dbg(ql_dbg_disc, vha, 0x2007,
4080 "Retrying %d login again loop_id 0x%x.\n",
4081 fcport->login_retry, fcport->loop_id);
4082 } else {
4083 fcport->login_retry = 0;
4084 }
4085
4086 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4087 qla2x00_clear_loop_id(fcport);
4088 }
4089 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4090 break;
4091 }
4092 }
4093
4094 /* Schedule work on any of the dpc-workqueues */
4095 void
4096 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4097 {
4098 struct qla_hw_data *ha = base_vha->hw;
4099
4100 switch (work_code) {
4101 case MBA_IDC_AEN: /* 0x8200 */
4102 if (ha->dpc_lp_wq)
4103 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4104 break;
4105
4106 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4107 if (!ha->flags.nic_core_reset_hdlr_active) {
4108 if (ha->dpc_hp_wq)
4109 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4110 } else
4111 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4112 "NIC Core reset is already active. Skip "
4113 "scheduling it again.\n");
4114 break;
4115 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4116 if (ha->dpc_hp_wq)
4117 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4118 break;
4119 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4120 if (ha->dpc_hp_wq)
4121 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4122 break;
4123 default:
4124 ql_log(ql_log_warn, base_vha, 0xb05f,
4125 "Unknow work-code=0x%x.\n", work_code);
4126 }
4127
4128 return;
4129 }
4130
4131 /* Work: Perform NIC Core Unrecoverable state handling */
4132 void
4133 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4134 {
4135 struct qla_hw_data *ha =
4136 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4137 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4138 uint32_t dev_state = 0;
4139
4140 qla83xx_idc_lock(base_vha, 0);
4141 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4142 qla83xx_reset_ownership(base_vha);
4143 if (ha->flags.nic_core_reset_owner) {
4144 ha->flags.nic_core_reset_owner = 0;
4145 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4146 QLA8XXX_DEV_FAILED);
4147 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4148 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4149 }
4150 qla83xx_idc_unlock(base_vha, 0);
4151 }
4152
4153 /* Work: Execute IDC state handler */
4154 void
4155 qla83xx_idc_state_handler_work(struct work_struct *work)
4156 {
4157 struct qla_hw_data *ha =
4158 container_of(work, struct qla_hw_data, idc_state_handler);
4159 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4160 uint32_t dev_state = 0;
4161
4162 qla83xx_idc_lock(base_vha, 0);
4163 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4164 if (dev_state == QLA8XXX_DEV_FAILED ||
4165 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4166 qla83xx_idc_state_handler(base_vha);
4167 qla83xx_idc_unlock(base_vha, 0);
4168 }
4169
4170 static int
4171 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4172 {
4173 int rval = QLA_SUCCESS;
4174 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4175 uint32_t heart_beat_counter1, heart_beat_counter2;
4176
4177 do {
4178 if (time_after(jiffies, heart_beat_wait)) {
4179 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4180 "Nic Core f/w is not alive.\n");
4181 rval = QLA_FUNCTION_FAILED;
4182 break;
4183 }
4184
4185 qla83xx_idc_lock(base_vha, 0);
4186 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4187 &heart_beat_counter1);
4188 qla83xx_idc_unlock(base_vha, 0);
4189 msleep(100);
4190 qla83xx_idc_lock(base_vha, 0);
4191 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4192 &heart_beat_counter2);
4193 qla83xx_idc_unlock(base_vha, 0);
4194 } while (heart_beat_counter1 == heart_beat_counter2);
4195
4196 return rval;
4197 }
4198
4199 /* Work: Perform NIC Core Reset handling */
4200 void
4201 qla83xx_nic_core_reset_work(struct work_struct *work)
4202 {
4203 struct qla_hw_data *ha =
4204 container_of(work, struct qla_hw_data, nic_core_reset);
4205 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4206 uint32_t dev_state = 0;
4207
4208 if (IS_QLA2031(ha)) {
4209 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4210 ql_log(ql_log_warn, base_vha, 0xb081,
4211 "Failed to dump mctp\n");
4212 return;
4213 }
4214
4215 if (!ha->flags.nic_core_reset_hdlr_active) {
4216 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4217 qla83xx_idc_lock(base_vha, 0);
4218 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4219 &dev_state);
4220 qla83xx_idc_unlock(base_vha, 0);
4221 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4222 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4223 "Nic Core f/w is alive.\n");
4224 return;
4225 }
4226 }
4227
4228 ha->flags.nic_core_reset_hdlr_active = 1;
4229 if (qla83xx_nic_core_reset(base_vha)) {
4230 /* NIC Core reset failed. */
4231 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4232 "NIC Core reset failed.\n");
4233 }
4234 ha->flags.nic_core_reset_hdlr_active = 0;
4235 }
4236 }
4237
4238 /* Work: Handle 8200 IDC aens */
4239 void
4240 qla83xx_service_idc_aen(struct work_struct *work)
4241 {
4242 struct qla_hw_data *ha =
4243 container_of(work, struct qla_hw_data, idc_aen);
4244 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4245 uint32_t dev_state, idc_control;
4246
4247 qla83xx_idc_lock(base_vha, 0);
4248 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4249 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4250 qla83xx_idc_unlock(base_vha, 0);
4251 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4252 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4253 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4254 "Application requested NIC Core Reset.\n");
4255 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4256 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4257 QLA_SUCCESS) {
4258 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4259 "Other protocol driver requested NIC Core Reset.\n");
4260 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4261 }
4262 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4263 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4264 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4265 }
4266 }
4267
4268 static void
4269 qla83xx_wait_logic(void)
4270 {
4271 int i;
4272
4273 /* Yield CPU */
4274 if (!in_interrupt()) {
4275 /*
4276 * Wait about 200ms before retrying again.
4277 * This controls the number of retries for single
4278 * lock operation.
4279 */
4280 msleep(100);
4281 schedule();
4282 } else {
4283 for (i = 0; i < 20; i++)
4284 cpu_relax(); /* This a nop instr on i386 */
4285 }
4286 }
4287
4288 static int
4289 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4290 {
4291 int rval;
4292 uint32_t data;
4293 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4294 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4295 struct qla_hw_data *ha = base_vha->hw;
4296 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4297 "Trying force recovery of the IDC lock.\n");
4298
4299 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4300 if (rval)
4301 return rval;
4302
4303 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4304 return QLA_SUCCESS;
4305 } else {
4306 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4307 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4308 data);
4309 if (rval)
4310 return rval;
4311
4312 msleep(200);
4313
4314 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4315 &data);
4316 if (rval)
4317 return rval;
4318
4319 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4320 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4321 ~(idc_lck_rcvry_stage_mask));
4322 rval = qla83xx_wr_reg(base_vha,
4323 QLA83XX_IDC_LOCK_RECOVERY, data);
4324 if (rval)
4325 return rval;
4326
4327 /* Forcefully perform IDC UnLock */
4328 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4329 &data);
4330 if (rval)
4331 return rval;
4332 /* Clear lock-id by setting 0xff */
4333 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4334 0xff);
4335 if (rval)
4336 return rval;
4337 /* Clear lock-recovery by setting 0x0 */
4338 rval = qla83xx_wr_reg(base_vha,
4339 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4340 if (rval)
4341 return rval;
4342 } else
4343 return QLA_SUCCESS;
4344 }
4345
4346 return rval;
4347 }
4348
4349 static int
4350 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4351 {
4352 int rval = QLA_SUCCESS;
4353 uint32_t o_drv_lockid, n_drv_lockid;
4354 unsigned long lock_recovery_timeout;
4355
4356 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4357 retry_lockid:
4358 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4359 if (rval)
4360 goto exit;
4361
4362 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4363 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4364 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4365 return QLA_SUCCESS;
4366 else
4367 return QLA_FUNCTION_FAILED;
4368 }
4369
4370 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4371 if (rval)
4372 goto exit;
4373
4374 if (o_drv_lockid == n_drv_lockid) {
4375 qla83xx_wait_logic();
4376 goto retry_lockid;
4377 } else
4378 return QLA_SUCCESS;
4379
4380 exit:
4381 return rval;
4382 }
4383
4384 void
4385 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4386 {
4387 uint16_t options = (requester_id << 15) | BIT_6;
4388 uint32_t data;
4389 uint32_t lock_owner;
4390 struct qla_hw_data *ha = base_vha->hw;
4391
4392 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4393 retry_lock:
4394 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4395 == QLA_SUCCESS) {
4396 if (data) {
4397 /* Setting lock-id to our function-number */
4398 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4399 ha->portnum);
4400 } else {
4401 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4402 &lock_owner);
4403 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4404 "Failed to acquire IDC lock, acquired by %d, "
4405 "retrying...\n", lock_owner);
4406
4407 /* Retry/Perform IDC-Lock recovery */
4408 if (qla83xx_idc_lock_recovery(base_vha)
4409 == QLA_SUCCESS) {
4410 qla83xx_wait_logic();
4411 goto retry_lock;
4412 } else
4413 ql_log(ql_log_warn, base_vha, 0xb075,
4414 "IDC Lock recovery FAILED.\n");
4415 }
4416
4417 }
4418
4419 return;
4420
4421 /* XXX: IDC-lock implementation using access-control mbx */
4422 retry_lock2:
4423 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4424 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4425 "Failed to acquire IDC lock. retrying...\n");
4426 /* Retry/Perform IDC-Lock recovery */
4427 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4428 qla83xx_wait_logic();
4429 goto retry_lock2;
4430 } else
4431 ql_log(ql_log_warn, base_vha, 0xb076,
4432 "IDC Lock recovery FAILED.\n");
4433 }
4434
4435 return;
4436 }
4437
4438 void
4439 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4440 {
4441 uint16_t options = (requester_id << 15) | BIT_7, retry;
4442 uint32_t data;
4443 struct qla_hw_data *ha = base_vha->hw;
4444
4445 /* IDC-unlock implementation using driver-unlock/lock-id
4446 * remote registers
4447 */
4448 retry = 0;
4449 retry_unlock:
4450 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4451 == QLA_SUCCESS) {
4452 if (data == ha->portnum) {
4453 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4454 /* Clearing lock-id by setting 0xff */
4455 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4456 } else if (retry < 10) {
4457 /* SV: XXX: IDC unlock retrying needed here? */
4458
4459 /* Retry for IDC-unlock */
4460 qla83xx_wait_logic();
4461 retry++;
4462 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4463 "Failed to release IDC lock, retyring=%d\n", retry);
4464 goto retry_unlock;
4465 }
4466 } else if (retry < 10) {
4467 /* Retry for IDC-unlock */
4468 qla83xx_wait_logic();
4469 retry++;
4470 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4471 "Failed to read drv-lockid, retyring=%d\n", retry);
4472 goto retry_unlock;
4473 }
4474
4475 return;
4476
4477 /* XXX: IDC-unlock implementation using access-control mbx */
4478 retry = 0;
4479 retry_unlock2:
4480 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4481 if (retry < 10) {
4482 /* Retry for IDC-unlock */
4483 qla83xx_wait_logic();
4484 retry++;
4485 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4486 "Failed to release IDC lock, retyring=%d\n", retry);
4487 goto retry_unlock2;
4488 }
4489 }
4490
4491 return;
4492 }
4493
4494 int
4495 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4496 {
4497 int rval = QLA_SUCCESS;
4498 struct qla_hw_data *ha = vha->hw;
4499 uint32_t drv_presence;
4500
4501 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4502 if (rval == QLA_SUCCESS) {
4503 drv_presence |= (1 << ha->portnum);
4504 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4505 drv_presence);
4506 }
4507
4508 return rval;
4509 }
4510
4511 int
4512 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4513 {
4514 int rval = QLA_SUCCESS;
4515
4516 qla83xx_idc_lock(vha, 0);
4517 rval = __qla83xx_set_drv_presence(vha);
4518 qla83xx_idc_unlock(vha, 0);
4519
4520 return rval;
4521 }
4522
4523 int
4524 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4525 {
4526 int rval = QLA_SUCCESS;
4527 struct qla_hw_data *ha = vha->hw;
4528 uint32_t drv_presence;
4529
4530 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4531 if (rval == QLA_SUCCESS) {
4532 drv_presence &= ~(1 << ha->portnum);
4533 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4534 drv_presence);
4535 }
4536
4537 return rval;
4538 }
4539
4540 int
4541 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4542 {
4543 int rval = QLA_SUCCESS;
4544
4545 qla83xx_idc_lock(vha, 0);
4546 rval = __qla83xx_clear_drv_presence(vha);
4547 qla83xx_idc_unlock(vha, 0);
4548
4549 return rval;
4550 }
4551
4552 static void
4553 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4554 {
4555 struct qla_hw_data *ha = vha->hw;
4556 uint32_t drv_ack, drv_presence;
4557 unsigned long ack_timeout;
4558
4559 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4560 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4561 while (1) {
4562 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4563 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4564 if ((drv_ack & drv_presence) == drv_presence)
4565 break;
4566
4567 if (time_after_eq(jiffies, ack_timeout)) {
4568 ql_log(ql_log_warn, vha, 0xb067,
4569 "RESET ACK TIMEOUT! drv_presence=0x%x "
4570 "drv_ack=0x%x\n", drv_presence, drv_ack);
4571 /*
4572 * The function(s) which did not ack in time are forced
4573 * to withdraw any further participation in the IDC
4574 * reset.
4575 */
4576 if (drv_ack != drv_presence)
4577 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4578 drv_ack);
4579 break;
4580 }
4581
4582 qla83xx_idc_unlock(vha, 0);
4583 msleep(1000);
4584 qla83xx_idc_lock(vha, 0);
4585 }
4586
4587 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4588 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4589 }
4590
4591 static int
4592 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4593 {
4594 int rval = QLA_SUCCESS;
4595 uint32_t idc_control;
4596
4597 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4598 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4599
4600 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4601 __qla83xx_get_idc_control(vha, &idc_control);
4602 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4603 __qla83xx_set_idc_control(vha, 0);
4604
4605 qla83xx_idc_unlock(vha, 0);
4606 rval = qla83xx_restart_nic_firmware(vha);
4607 qla83xx_idc_lock(vha, 0);
4608
4609 if (rval != QLA_SUCCESS) {
4610 ql_log(ql_log_fatal, vha, 0xb06a,
4611 "Failed to restart NIC f/w.\n");
4612 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4613 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4614 } else {
4615 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4616 "Success in restarting nic f/w.\n");
4617 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4618 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4619 }
4620
4621 return rval;
4622 }
4623
4624 /* Assumes idc_lock always held on entry */
4625 int
4626 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4627 {
4628 struct qla_hw_data *ha = base_vha->hw;
4629 int rval = QLA_SUCCESS;
4630 unsigned long dev_init_timeout;
4631 uint32_t dev_state;
4632
4633 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4634 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4635
4636 while (1) {
4637
4638 if (time_after_eq(jiffies, dev_init_timeout)) {
4639 ql_log(ql_log_warn, base_vha, 0xb06e,
4640 "Initialization TIMEOUT!\n");
4641 /* Init timeout. Disable further NIC Core
4642 * communication.
4643 */
4644 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4645 QLA8XXX_DEV_FAILED);
4646 ql_log(ql_log_info, base_vha, 0xb06f,
4647 "HW State: FAILED.\n");
4648 }
4649
4650 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4651 switch (dev_state) {
4652 case QLA8XXX_DEV_READY:
4653 if (ha->flags.nic_core_reset_owner)
4654 qla83xx_idc_audit(base_vha,
4655 IDC_AUDIT_COMPLETION);
4656 ha->flags.nic_core_reset_owner = 0;
4657 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4658 "Reset_owner reset by 0x%x.\n",
4659 ha->portnum);
4660 goto exit;
4661 case QLA8XXX_DEV_COLD:
4662 if (ha->flags.nic_core_reset_owner)
4663 rval = qla83xx_device_bootstrap(base_vha);
4664 else {
4665 /* Wait for AEN to change device-state */
4666 qla83xx_idc_unlock(base_vha, 0);
4667 msleep(1000);
4668 qla83xx_idc_lock(base_vha, 0);
4669 }
4670 break;
4671 case QLA8XXX_DEV_INITIALIZING:
4672 /* Wait for AEN to change device-state */
4673 qla83xx_idc_unlock(base_vha, 0);
4674 msleep(1000);
4675 qla83xx_idc_lock(base_vha, 0);
4676 break;
4677 case QLA8XXX_DEV_NEED_RESET:
4678 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4679 qla83xx_need_reset_handler(base_vha);
4680 else {
4681 /* Wait for AEN to change device-state */
4682 qla83xx_idc_unlock(base_vha, 0);
4683 msleep(1000);
4684 qla83xx_idc_lock(base_vha, 0);
4685 }
4686 /* reset timeout value after need reset handler */
4687 dev_init_timeout = jiffies +
4688 (ha->fcoe_dev_init_timeout * HZ);
4689 break;
4690 case QLA8XXX_DEV_NEED_QUIESCENT:
4691 /* XXX: DEBUG for now */
4692 qla83xx_idc_unlock(base_vha, 0);
4693 msleep(1000);
4694 qla83xx_idc_lock(base_vha, 0);
4695 break;
4696 case QLA8XXX_DEV_QUIESCENT:
4697 /* XXX: DEBUG for now */
4698 if (ha->flags.quiesce_owner)
4699 goto exit;
4700
4701 qla83xx_idc_unlock(base_vha, 0);
4702 msleep(1000);
4703 qla83xx_idc_lock(base_vha, 0);
4704 dev_init_timeout = jiffies +
4705 (ha->fcoe_dev_init_timeout * HZ);
4706 break;
4707 case QLA8XXX_DEV_FAILED:
4708 if (ha->flags.nic_core_reset_owner)
4709 qla83xx_idc_audit(base_vha,
4710 IDC_AUDIT_COMPLETION);
4711 ha->flags.nic_core_reset_owner = 0;
4712 __qla83xx_clear_drv_presence(base_vha);
4713 qla83xx_idc_unlock(base_vha, 0);
4714 qla8xxx_dev_failed_handler(base_vha);
4715 rval = QLA_FUNCTION_FAILED;
4716 qla83xx_idc_lock(base_vha, 0);
4717 goto exit;
4718 case QLA8XXX_BAD_VALUE:
4719 qla83xx_idc_unlock(base_vha, 0);
4720 msleep(1000);
4721 qla83xx_idc_lock(base_vha, 0);
4722 break;
4723 default:
4724 ql_log(ql_log_warn, base_vha, 0xb071,
4725 "Unknow Device State: %x.\n", dev_state);
4726 qla83xx_idc_unlock(base_vha, 0);
4727 qla8xxx_dev_failed_handler(base_vha);
4728 rval = QLA_FUNCTION_FAILED;
4729 qla83xx_idc_lock(base_vha, 0);
4730 goto exit;
4731 }
4732 }
4733
4734 exit:
4735 return rval;
4736 }
4737
4738 /**************************************************************************
4739 * qla2x00_do_dpc
4740 * This kernel thread is a task that is schedule by the interrupt handler
4741 * to perform the background processing for interrupts.
4742 *
4743 * Notes:
4744 * This task always run in the context of a kernel thread. It
4745 * is kick-off by the driver's detect code and starts up
4746 * up one per adapter. It immediately goes to sleep and waits for
4747 * some fibre event. When either the interrupt handler or
4748 * the timer routine detects a event it will one of the task
4749 * bits then wake us up.
4750 **************************************************************************/
4751 static int
4752 qla2x00_do_dpc(void *data)
4753 {
4754 int rval;
4755 scsi_qla_host_t *base_vha;
4756 struct qla_hw_data *ha;
4757
4758 ha = (struct qla_hw_data *)data;
4759 base_vha = pci_get_drvdata(ha->pdev);
4760
4761 set_user_nice(current, -20);
4762
4763 set_current_state(TASK_INTERRUPTIBLE);
4764 while (!kthread_should_stop()) {
4765 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4766 "DPC handler sleeping.\n");
4767
4768 schedule();
4769 __set_current_state(TASK_RUNNING);
4770
4771 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4772 goto end_loop;
4773
4774 if (ha->flags.eeh_busy) {
4775 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4776 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4777 goto end_loop;
4778 }
4779
4780 ha->dpc_active = 1;
4781
4782 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4783 "DPC handler waking up, dpc_flags=0x%lx.\n",
4784 base_vha->dpc_flags);
4785
4786 qla2x00_do_work(base_vha);
4787
4788 if (IS_P3P_TYPE(ha)) {
4789 if (IS_QLA8044(ha)) {
4790 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4791 &base_vha->dpc_flags)) {
4792 qla8044_idc_lock(ha);
4793 qla8044_wr_direct(base_vha,
4794 QLA8044_CRB_DEV_STATE_INDEX,
4795 QLA8XXX_DEV_FAILED);
4796 qla8044_idc_unlock(ha);
4797 ql_log(ql_log_info, base_vha, 0x4004,
4798 "HW State: FAILED.\n");
4799 qla8044_device_state_handler(base_vha);
4800 continue;
4801 }
4802
4803 } else {
4804 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4805 &base_vha->dpc_flags)) {
4806 qla82xx_idc_lock(ha);
4807 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4808 QLA8XXX_DEV_FAILED);
4809 qla82xx_idc_unlock(ha);
4810 ql_log(ql_log_info, base_vha, 0x0151,
4811 "HW State: FAILED.\n");
4812 qla82xx_device_state_handler(base_vha);
4813 continue;
4814 }
4815 }
4816
4817 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4818 &base_vha->dpc_flags)) {
4819
4820 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4821 "FCoE context reset scheduled.\n");
4822 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4823 &base_vha->dpc_flags))) {
4824 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4825 /* FCoE-ctx reset failed.
4826 * Escalate to chip-reset
4827 */
4828 set_bit(ISP_ABORT_NEEDED,
4829 &base_vha->dpc_flags);
4830 }
4831 clear_bit(ABORT_ISP_ACTIVE,
4832 &base_vha->dpc_flags);
4833 }
4834
4835 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4836 "FCoE context reset end.\n");
4837 }
4838 } else if (IS_QLAFX00(ha)) {
4839 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4840 &base_vha->dpc_flags)) {
4841 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4842 "Firmware Reset Recovery\n");
4843 if (qlafx00_reset_initialize(base_vha)) {
4844 /* Failed. Abort isp later. */
4845 if (!test_bit(UNLOADING,
4846 &base_vha->dpc_flags))
4847 set_bit(ISP_UNRECOVERABLE,
4848 &base_vha->dpc_flags);
4849 ql_dbg(ql_dbg_dpc, base_vha,
4850 0x4021,
4851 "Reset Recovery Failed\n");
4852 }
4853 }
4854
4855 if (test_and_clear_bit(FX00_TARGET_SCAN,
4856 &base_vha->dpc_flags)) {
4857 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4858 "ISPFx00 Target Scan scheduled\n");
4859 if (qlafx00_rescan_isp(base_vha)) {
4860 if (!test_bit(UNLOADING,
4861 &base_vha->dpc_flags))
4862 set_bit(ISP_UNRECOVERABLE,
4863 &base_vha->dpc_flags);
4864 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4865 "ISPFx00 Target Scan Failed\n");
4866 }
4867 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4868 "ISPFx00 Target Scan End\n");
4869 }
4870 }
4871
4872 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4873 &base_vha->dpc_flags)) {
4874
4875 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4876 "ISP abort scheduled.\n");
4877 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4878 &base_vha->dpc_flags))) {
4879
4880 if (ha->isp_ops->abort_isp(base_vha)) {
4881 /* failed. retry later */
4882 set_bit(ISP_ABORT_NEEDED,
4883 &base_vha->dpc_flags);
4884 }
4885 clear_bit(ABORT_ISP_ACTIVE,
4886 &base_vha->dpc_flags);
4887 }
4888
4889 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4890 "ISP abort end.\n");
4891 }
4892
4893 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4894 &base_vha->dpc_flags)) {
4895 qla2x00_update_fcports(base_vha);
4896 }
4897
4898 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4899 int ret;
4900 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4901 if (ret != QLA_SUCCESS)
4902 ql_log(ql_log_warn, base_vha, 0x121,
4903 "Failed to enable receiving of RSCN "
4904 "requests: 0x%x.\n", ret);
4905 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4906 }
4907
4908 if (IS_QLAFX00(ha))
4909 goto loop_resync_check;
4910
4911 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4912 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4913 "Quiescence mode scheduled.\n");
4914 if (IS_P3P_TYPE(ha)) {
4915 if (IS_QLA82XX(ha))
4916 qla82xx_device_state_handler(base_vha);
4917 if (IS_QLA8044(ha))
4918 qla8044_device_state_handler(base_vha);
4919 clear_bit(ISP_QUIESCE_NEEDED,
4920 &base_vha->dpc_flags);
4921 if (!ha->flags.quiesce_owner) {
4922 qla2x00_perform_loop_resync(base_vha);
4923 if (IS_QLA82XX(ha)) {
4924 qla82xx_idc_lock(ha);
4925 qla82xx_clear_qsnt_ready(
4926 base_vha);
4927 qla82xx_idc_unlock(ha);
4928 } else if (IS_QLA8044(ha)) {
4929 qla8044_idc_lock(ha);
4930 qla8044_clear_qsnt_ready(
4931 base_vha);
4932 qla8044_idc_unlock(ha);
4933 }
4934 }
4935 } else {
4936 clear_bit(ISP_QUIESCE_NEEDED,
4937 &base_vha->dpc_flags);
4938 qla2x00_quiesce_io(base_vha);
4939 }
4940 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4941 "Quiescence mode end.\n");
4942 }
4943
4944 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4945 &base_vha->dpc_flags) &&
4946 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
4947
4948 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4949 "Reset marker scheduled.\n");
4950 qla2x00_rst_aen(base_vha);
4951 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
4952 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4953 "Reset marker end.\n");
4954 }
4955
4956 /* Retry each device up to login retry count */
4957 if ((test_and_clear_bit(RELOGIN_NEEDED,
4958 &base_vha->dpc_flags)) &&
4959 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4960 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
4961
4962 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4963 "Relogin scheduled.\n");
4964 qla2x00_relogin(base_vha);
4965 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4966 "Relogin end.\n");
4967 }
4968 loop_resync_check:
4969 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4970 &base_vha->dpc_flags)) {
4971
4972 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4973 "Loop resync scheduled.\n");
4974
4975 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
4976 &base_vha->dpc_flags))) {
4977
4978 rval = qla2x00_loop_resync(base_vha);
4979
4980 clear_bit(LOOP_RESYNC_ACTIVE,
4981 &base_vha->dpc_flags);
4982 }
4983
4984 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4985 "Loop resync end.\n");
4986 }
4987
4988 if (IS_QLAFX00(ha))
4989 goto intr_on_check;
4990
4991 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4992 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4993 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4994 qla2xxx_flash_npiv_conf(base_vha);
4995 }
4996
4997 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4998 &base_vha->dpc_flags)) {
4999 /* Prevents simultaneous ramp up and down */
5000 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5001 &base_vha->dpc_flags);
5002 qla2x00_host_ramp_down_queuedepth(base_vha);
5003 }
5004
5005 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
5006 &base_vha->dpc_flags))
5007 qla2x00_host_ramp_up_queuedepth(base_vha);
5008 intr_on_check:
5009 if (!ha->interrupts_on)
5010 ha->isp_ops->enable_intrs(ha);
5011
5012 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5013 &base_vha->dpc_flags))
5014 ha->isp_ops->beacon_blink(base_vha);
5015
5016 if (!IS_QLAFX00(ha))
5017 qla2x00_do_dpc_all_vps(base_vha);
5018
5019 ha->dpc_active = 0;
5020 end_loop:
5021 set_current_state(TASK_INTERRUPTIBLE);
5022 } /* End of while(1) */
5023 __set_current_state(TASK_RUNNING);
5024
5025 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5026 "DPC handler exiting.\n");
5027
5028 /*
5029 * Make sure that nobody tries to wake us up again.
5030 */
5031 ha->dpc_active = 0;
5032
5033 /* Cleanup any residual CTX SRBs. */
5034 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5035
5036 return 0;
5037 }
5038
5039 void
5040 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
5041 {
5042 struct qla_hw_data *ha = vha->hw;
5043 struct task_struct *t = ha->dpc_thread;
5044
5045 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
5046 wake_up_process(t);
5047 }
5048
5049 /*
5050 * qla2x00_rst_aen
5051 * Processes asynchronous reset.
5052 *
5053 * Input:
5054 * ha = adapter block pointer.
5055 */
5056 static void
5057 qla2x00_rst_aen(scsi_qla_host_t *vha)
5058 {
5059 if (vha->flags.online && !vha->flags.reset_active &&
5060 !atomic_read(&vha->loop_down_timer) &&
5061 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
5062 do {
5063 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5064
5065 /*
5066 * Issue marker command only when we are going to start
5067 * the I/O.
5068 */
5069 vha->marker_needed = 1;
5070 } while (!atomic_read(&vha->loop_down_timer) &&
5071 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
5072 }
5073 }
5074
5075 /**************************************************************************
5076 * qla2x00_timer
5077 *
5078 * Description:
5079 * One second timer
5080 *
5081 * Context: Interrupt
5082 ***************************************************************************/
5083 void
5084 qla2x00_timer(scsi_qla_host_t *vha)
5085 {
5086 unsigned long cpu_flags = 0;
5087 int start_dpc = 0;
5088 int index;
5089 srb_t *sp;
5090 uint16_t w;
5091 struct qla_hw_data *ha = vha->hw;
5092 struct req_que *req;
5093
5094 if (ha->flags.eeh_busy) {
5095 ql_dbg(ql_dbg_timer, vha, 0x6000,
5096 "EEH = %d, restarting timer.\n",
5097 ha->flags.eeh_busy);
5098 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5099 return;
5100 }
5101
5102 /* Hardware read to raise pending EEH errors during mailbox waits. */
5103 if (!pci_channel_offline(ha->pdev))
5104 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
5105
5106 /* Make sure qla82xx_watchdog is run only for physical port */
5107 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
5108 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5109 start_dpc++;
5110 if (IS_QLA82XX(ha))
5111 qla82xx_watchdog(vha);
5112 else if (IS_QLA8044(ha))
5113 qla8044_watchdog(vha);
5114 }
5115
5116 if (!vha->vp_idx && IS_QLAFX00(ha))
5117 qlafx00_timer_routine(vha);
5118
5119 /* Loop down handler. */
5120 if (atomic_read(&vha->loop_down_timer) > 0 &&
5121 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5122 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5123 && vha->flags.online) {
5124
5125 if (atomic_read(&vha->loop_down_timer) ==
5126 vha->loop_down_abort_time) {
5127
5128 ql_log(ql_log_info, vha, 0x6008,
5129 "Loop down - aborting the queues before time expires.\n");
5130
5131 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5132 atomic_set(&vha->loop_state, LOOP_DEAD);
5133
5134 /*
5135 * Schedule an ISP abort to return any FCP2-device
5136 * commands.
5137 */
5138 /* NPIV - scan physical port only */
5139 if (!vha->vp_idx) {
5140 spin_lock_irqsave(&ha->hardware_lock,
5141 cpu_flags);
5142 req = ha->req_q_map[0];
5143 for (index = 1;
5144 index < req->num_outstanding_cmds;
5145 index++) {
5146 fc_port_t *sfcp;
5147
5148 sp = req->outstanding_cmds[index];
5149 if (!sp)
5150 continue;
5151 if (sp->type != SRB_SCSI_CMD)
5152 continue;
5153 sfcp = sp->fcport;
5154 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5155 continue;
5156
5157 if (IS_QLA82XX(ha))
5158 set_bit(FCOE_CTX_RESET_NEEDED,
5159 &vha->dpc_flags);
5160 else
5161 set_bit(ISP_ABORT_NEEDED,
5162 &vha->dpc_flags);
5163 break;
5164 }
5165 spin_unlock_irqrestore(&ha->hardware_lock,
5166 cpu_flags);
5167 }
5168 start_dpc++;
5169 }
5170
5171 /* if the loop has been down for 4 minutes, reinit adapter */
5172 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5173 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5174 ql_log(ql_log_warn, vha, 0x6009,
5175 "Loop down - aborting ISP.\n");
5176
5177 if (IS_QLA82XX(ha))
5178 set_bit(FCOE_CTX_RESET_NEEDED,
5179 &vha->dpc_flags);
5180 else
5181 set_bit(ISP_ABORT_NEEDED,
5182 &vha->dpc_flags);
5183 }
5184 }
5185 ql_dbg(ql_dbg_timer, vha, 0x600a,
5186 "Loop down - seconds remaining %d.\n",
5187 atomic_read(&vha->loop_down_timer));
5188 }
5189
5190 /* Check if beacon LED needs to be blinked for physical host only */
5191 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5192 /* There is no beacon_blink function for ISP82xx */
5193 if (!IS_P3P_TYPE(ha)) {
5194 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5195 start_dpc++;
5196 }
5197 }
5198
5199 /* Process any deferred work. */
5200 if (!list_empty(&vha->work_list))
5201 start_dpc++;
5202
5203 /* Schedule the DPC routine if needed */
5204 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5205 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5206 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5207 start_dpc ||
5208 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5209 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5210 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5211 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5212 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5213 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5214 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5215 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
5216 ql_dbg(ql_dbg_timer, vha, 0x600b,
5217 "isp_abort_needed=%d loop_resync_needed=%d "
5218 "fcport_update_needed=%d start_dpc=%d "
5219 "reset_marker_needed=%d",
5220 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5221 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5222 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5223 start_dpc,
5224 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5225 ql_dbg(ql_dbg_timer, vha, 0x600c,
5226 "beacon_blink_needed=%d isp_unrecoverable=%d "
5227 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5228 "relogin_needed=%d, host_ramp_down_needed=%d "
5229 "host_ramp_up_needed=%d.\n",
5230 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5231 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5232 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5233 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5234 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5235 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5236 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
5237 qla2xxx_wake_dpc(vha);
5238 }
5239
5240 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5241 }
5242
5243 /* Firmware interface routines. */
5244
5245 #define FW_BLOBS 10
5246 #define FW_ISP21XX 0
5247 #define FW_ISP22XX 1
5248 #define FW_ISP2300 2
5249 #define FW_ISP2322 3
5250 #define FW_ISP24XX 4
5251 #define FW_ISP25XX 5
5252 #define FW_ISP81XX 6
5253 #define FW_ISP82XX 7
5254 #define FW_ISP2031 8
5255 #define FW_ISP8031 9
5256
5257 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5258 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5259 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5260 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5261 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5262 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5263 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5264 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5265 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5266 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5267
5268 static DEFINE_MUTEX(qla_fw_lock);
5269
5270 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5271 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5272 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5273 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5274 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5275 { .name = FW_FILE_ISP24XX, },
5276 { .name = FW_FILE_ISP25XX, },
5277 { .name = FW_FILE_ISP81XX, },
5278 { .name = FW_FILE_ISP82XX, },
5279 { .name = FW_FILE_ISP2031, },
5280 { .name = FW_FILE_ISP8031, },
5281 };
5282
5283 struct fw_blob *
5284 qla2x00_request_firmware(scsi_qla_host_t *vha)
5285 {
5286 struct qla_hw_data *ha = vha->hw;
5287 struct fw_blob *blob;
5288
5289 if (IS_QLA2100(ha)) {
5290 blob = &qla_fw_blobs[FW_ISP21XX];
5291 } else if (IS_QLA2200(ha)) {
5292 blob = &qla_fw_blobs[FW_ISP22XX];
5293 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5294 blob = &qla_fw_blobs[FW_ISP2300];
5295 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5296 blob = &qla_fw_blobs[FW_ISP2322];
5297 } else if (IS_QLA24XX_TYPE(ha)) {
5298 blob = &qla_fw_blobs[FW_ISP24XX];
5299 } else if (IS_QLA25XX(ha)) {
5300 blob = &qla_fw_blobs[FW_ISP25XX];
5301 } else if (IS_QLA81XX(ha)) {
5302 blob = &qla_fw_blobs[FW_ISP81XX];
5303 } else if (IS_QLA82XX(ha)) {
5304 blob = &qla_fw_blobs[FW_ISP82XX];
5305 } else if (IS_QLA2031(ha)) {
5306 blob = &qla_fw_blobs[FW_ISP2031];
5307 } else if (IS_QLA8031(ha)) {
5308 blob = &qla_fw_blobs[FW_ISP8031];
5309 } else {
5310 return NULL;
5311 }
5312
5313 mutex_lock(&qla_fw_lock);
5314 if (blob->fw)
5315 goto out;
5316
5317 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5318 ql_log(ql_log_warn, vha, 0x0063,
5319 "Failed to load firmware image (%s).\n", blob->name);
5320 blob->fw = NULL;
5321 blob = NULL;
5322 goto out;
5323 }
5324
5325 out:
5326 mutex_unlock(&qla_fw_lock);
5327 return blob;
5328 }
5329
5330 static void
5331 qla2x00_release_firmware(void)
5332 {
5333 int idx;
5334
5335 mutex_lock(&qla_fw_lock);
5336 for (idx = 0; idx < FW_BLOBS; idx++)
5337 release_firmware(qla_fw_blobs[idx].fw);
5338 mutex_unlock(&qla_fw_lock);
5339 }
5340
5341 static pci_ers_result_t
5342 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5343 {
5344 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5345 struct qla_hw_data *ha = vha->hw;
5346
5347 ql_dbg(ql_dbg_aer, vha, 0x9000,
5348 "PCI error detected, state %x.\n", state);
5349
5350 switch (state) {
5351 case pci_channel_io_normal:
5352 ha->flags.eeh_busy = 0;
5353 return PCI_ERS_RESULT_CAN_RECOVER;
5354 case pci_channel_io_frozen:
5355 ha->flags.eeh_busy = 1;
5356 /* For ISP82XX complete any pending mailbox cmd */
5357 if (IS_QLA82XX(ha)) {
5358 ha->flags.isp82xx_fw_hung = 1;
5359 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5360 qla82xx_clear_pending_mbx(vha);
5361 }
5362 qla2x00_free_irqs(vha);
5363 pci_disable_device(pdev);
5364 /* Return back all IOs */
5365 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5366 return PCI_ERS_RESULT_NEED_RESET;
5367 case pci_channel_io_perm_failure:
5368 ha->flags.pci_channel_io_perm_failure = 1;
5369 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5370 return PCI_ERS_RESULT_DISCONNECT;
5371 }
5372 return PCI_ERS_RESULT_NEED_RESET;
5373 }
5374
5375 static pci_ers_result_t
5376 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5377 {
5378 int risc_paused = 0;
5379 uint32_t stat;
5380 unsigned long flags;
5381 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5382 struct qla_hw_data *ha = base_vha->hw;
5383 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5384 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5385
5386 if (IS_QLA82XX(ha))
5387 return PCI_ERS_RESULT_RECOVERED;
5388
5389 spin_lock_irqsave(&ha->hardware_lock, flags);
5390 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5391 stat = RD_REG_DWORD(&reg->hccr);
5392 if (stat & HCCR_RISC_PAUSE)
5393 risc_paused = 1;
5394 } else if (IS_QLA23XX(ha)) {
5395 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5396 if (stat & HSR_RISC_PAUSED)
5397 risc_paused = 1;
5398 } else if (IS_FWI2_CAPABLE(ha)) {
5399 stat = RD_REG_DWORD(&reg24->host_status);
5400 if (stat & HSRX_RISC_PAUSED)
5401 risc_paused = 1;
5402 }
5403 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5404
5405 if (risc_paused) {
5406 ql_log(ql_log_info, base_vha, 0x9003,
5407 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5408 ha->isp_ops->fw_dump(base_vha, 0);
5409
5410 return PCI_ERS_RESULT_NEED_RESET;
5411 } else
5412 return PCI_ERS_RESULT_RECOVERED;
5413 }
5414
5415 static uint32_t
5416 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5417 {
5418 uint32_t rval = QLA_FUNCTION_FAILED;
5419 uint32_t drv_active = 0;
5420 struct qla_hw_data *ha = base_vha->hw;
5421 int fn;
5422 struct pci_dev *other_pdev = NULL;
5423
5424 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5425 "Entered %s.\n", __func__);
5426
5427 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5428
5429 if (base_vha->flags.online) {
5430 /* Abort all outstanding commands,
5431 * so as to be requeued later */
5432 qla2x00_abort_isp_cleanup(base_vha);
5433 }
5434
5435
5436 fn = PCI_FUNC(ha->pdev->devfn);
5437 while (fn > 0) {
5438 fn--;
5439 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5440 "Finding pci device at function = 0x%x.\n", fn);
5441 other_pdev =
5442 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5443 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5444 fn));
5445
5446 if (!other_pdev)
5447 continue;
5448 if (atomic_read(&other_pdev->enable_cnt)) {
5449 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5450 "Found PCI func available and enable at 0x%x.\n",
5451 fn);
5452 pci_dev_put(other_pdev);
5453 break;
5454 }
5455 pci_dev_put(other_pdev);
5456 }
5457
5458 if (!fn) {
5459 /* Reset owner */
5460 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5461 "This devfn is reset owner = 0x%x.\n",
5462 ha->pdev->devfn);
5463 qla82xx_idc_lock(ha);
5464
5465 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5466 QLA8XXX_DEV_INITIALIZING);
5467
5468 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5469 QLA82XX_IDC_VERSION);
5470
5471 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5472 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5473 "drv_active = 0x%x.\n", drv_active);
5474
5475 qla82xx_idc_unlock(ha);
5476 /* Reset if device is not already reset
5477 * drv_active would be 0 if a reset has already been done
5478 */
5479 if (drv_active)
5480 rval = qla82xx_start_firmware(base_vha);
5481 else
5482 rval = QLA_SUCCESS;
5483 qla82xx_idc_lock(ha);
5484
5485 if (rval != QLA_SUCCESS) {
5486 ql_log(ql_log_info, base_vha, 0x900b,
5487 "HW State: FAILED.\n");
5488 qla82xx_clear_drv_active(ha);
5489 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5490 QLA8XXX_DEV_FAILED);
5491 } else {
5492 ql_log(ql_log_info, base_vha, 0x900c,
5493 "HW State: READY.\n");
5494 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5495 QLA8XXX_DEV_READY);
5496 qla82xx_idc_unlock(ha);
5497 ha->flags.isp82xx_fw_hung = 0;
5498 rval = qla82xx_restart_isp(base_vha);
5499 qla82xx_idc_lock(ha);
5500 /* Clear driver state register */
5501 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5502 qla82xx_set_drv_active(base_vha);
5503 }
5504 qla82xx_idc_unlock(ha);
5505 } else {
5506 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5507 "This devfn is not reset owner = 0x%x.\n",
5508 ha->pdev->devfn);
5509 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5510 QLA8XXX_DEV_READY)) {
5511 ha->flags.isp82xx_fw_hung = 0;
5512 rval = qla82xx_restart_isp(base_vha);
5513 qla82xx_idc_lock(ha);
5514 qla82xx_set_drv_active(base_vha);
5515 qla82xx_idc_unlock(ha);
5516 }
5517 }
5518 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5519
5520 return rval;
5521 }
5522
5523 static pci_ers_result_t
5524 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5525 {
5526 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5527 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5528 struct qla_hw_data *ha = base_vha->hw;
5529 struct rsp_que *rsp;
5530 int rc, retries = 10;
5531
5532 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5533 "Slot Reset.\n");
5534
5535 /* Workaround: qla2xxx driver which access hardware earlier
5536 * needs error state to be pci_channel_io_online.
5537 * Otherwise mailbox command timesout.
5538 */
5539 pdev->error_state = pci_channel_io_normal;
5540
5541 pci_restore_state(pdev);
5542
5543 /* pci_restore_state() clears the saved_state flag of the device
5544 * save restored state which resets saved_state flag
5545 */
5546 pci_save_state(pdev);
5547
5548 if (ha->mem_only)
5549 rc = pci_enable_device_mem(pdev);
5550 else
5551 rc = pci_enable_device(pdev);
5552
5553 if (rc) {
5554 ql_log(ql_log_warn, base_vha, 0x9005,
5555 "Can't re-enable PCI device after reset.\n");
5556 goto exit_slot_reset;
5557 }
5558
5559 rsp = ha->rsp_q_map[0];
5560 if (qla2x00_request_irqs(ha, rsp))
5561 goto exit_slot_reset;
5562
5563 if (ha->isp_ops->pci_config(base_vha))
5564 goto exit_slot_reset;
5565
5566 if (IS_QLA82XX(ha)) {
5567 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5568 ret = PCI_ERS_RESULT_RECOVERED;
5569 goto exit_slot_reset;
5570 } else
5571 goto exit_slot_reset;
5572 }
5573
5574 while (ha->flags.mbox_busy && retries--)
5575 msleep(1000);
5576
5577 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5578 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5579 ret = PCI_ERS_RESULT_RECOVERED;
5580 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5581
5582
5583 exit_slot_reset:
5584 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5585 "slot_reset return %x.\n", ret);
5586
5587 return ret;
5588 }
5589
5590 static void
5591 qla2xxx_pci_resume(struct pci_dev *pdev)
5592 {
5593 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5594 struct qla_hw_data *ha = base_vha->hw;
5595 int ret;
5596
5597 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5598 "pci_resume.\n");
5599
5600 ret = qla2x00_wait_for_hba_online(base_vha);
5601 if (ret != QLA_SUCCESS) {
5602 ql_log(ql_log_fatal, base_vha, 0x9002,
5603 "The device failed to resume I/O from slot/link_reset.\n");
5604 }
5605
5606 pci_cleanup_aer_uncorrect_error_status(pdev);
5607
5608 ha->flags.eeh_busy = 0;
5609 }
5610
5611 static const struct pci_error_handlers qla2xxx_err_handler = {
5612 .error_detected = qla2xxx_pci_error_detected,
5613 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5614 .slot_reset = qla2xxx_pci_slot_reset,
5615 .resume = qla2xxx_pci_resume,
5616 };
5617
5618 static struct pci_device_id qla2xxx_pci_tbl[] = {
5619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5638 { 0 },
5639 };
5640 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5641
5642 static struct pci_driver qla2xxx_pci_driver = {
5643 .name = QLA2XXX_DRIVER_NAME,
5644 .driver = {
5645 .owner = THIS_MODULE,
5646 },
5647 .id_table = qla2xxx_pci_tbl,
5648 .probe = qla2x00_probe_one,
5649 .remove = qla2x00_remove_one,
5650 .shutdown = qla2x00_shutdown,
5651 .err_handler = &qla2xxx_err_handler,
5652 };
5653
5654 static const struct file_operations apidev_fops = {
5655 .owner = THIS_MODULE,
5656 .llseek = noop_llseek,
5657 };
5658
5659 /**
5660 * qla2x00_module_init - Module initialization.
5661 **/
5662 static int __init
5663 qla2x00_module_init(void)
5664 {
5665 int ret = 0;
5666
5667 /* Allocate cache for SRBs. */
5668 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5669 SLAB_HWCACHE_ALIGN, NULL);
5670 if (srb_cachep == NULL) {
5671 ql_log(ql_log_fatal, NULL, 0x0001,
5672 "Unable to allocate SRB cache...Failing load!.\n");
5673 return -ENOMEM;
5674 }
5675
5676 /* Initialize target kmem_cache and mem_pools */
5677 ret = qlt_init();
5678 if (ret < 0) {
5679 kmem_cache_destroy(srb_cachep);
5680 return ret;
5681 } else if (ret > 0) {
5682 /*
5683 * If initiator mode is explictly disabled by qlt_init(),
5684 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5685 * performing scsi_scan_target() during LOOP UP event.
5686 */
5687 qla2xxx_transport_functions.disable_target_scan = 1;
5688 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5689 }
5690
5691 /* Derive version string. */
5692 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5693 if (ql2xextended_error_logging)
5694 strcat(qla2x00_version_str, "-debug");
5695
5696 qla2xxx_transport_template =
5697 fc_attach_transport(&qla2xxx_transport_functions);
5698 if (!qla2xxx_transport_template) {
5699 kmem_cache_destroy(srb_cachep);
5700 ql_log(ql_log_fatal, NULL, 0x0002,
5701 "fc_attach_transport failed...Failing load!.\n");
5702 qlt_exit();
5703 return -ENODEV;
5704 }
5705
5706 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5707 if (apidev_major < 0) {
5708 ql_log(ql_log_fatal, NULL, 0x0003,
5709 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5710 }
5711
5712 qla2xxx_transport_vport_template =
5713 fc_attach_transport(&qla2xxx_transport_vport_functions);
5714 if (!qla2xxx_transport_vport_template) {
5715 kmem_cache_destroy(srb_cachep);
5716 qlt_exit();
5717 fc_release_transport(qla2xxx_transport_template);
5718 ql_log(ql_log_fatal, NULL, 0x0004,
5719 "fc_attach_transport vport failed...Failing load!.\n");
5720 return -ENODEV;
5721 }
5722 ql_log(ql_log_info, NULL, 0x0005,
5723 "QLogic Fibre Channel HBA Driver: %s.\n",
5724 qla2x00_version_str);
5725 ret = pci_register_driver(&qla2xxx_pci_driver);
5726 if (ret) {
5727 kmem_cache_destroy(srb_cachep);
5728 qlt_exit();
5729 fc_release_transport(qla2xxx_transport_template);
5730 fc_release_transport(qla2xxx_transport_vport_template);
5731 ql_log(ql_log_fatal, NULL, 0x0006,
5732 "pci_register_driver failed...ret=%d Failing load!.\n",
5733 ret);
5734 }
5735 return ret;
5736 }
5737
5738 /**
5739 * qla2x00_module_exit - Module cleanup.
5740 **/
5741 static void __exit
5742 qla2x00_module_exit(void)
5743 {
5744 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5745 pci_unregister_driver(&qla2xxx_pci_driver);
5746 qla2x00_release_firmware();
5747 kmem_cache_destroy(srb_cachep);
5748 qlt_exit();
5749 if (ctx_cachep)
5750 kmem_cache_destroy(ctx_cachep);
5751 fc_release_transport(qla2xxx_transport_template);
5752 fc_release_transport(qla2xxx_transport_vport_template);
5753 }
5754
5755 module_init(qla2x00_module_init);
5756 module_exit(qla2x00_module_exit);
5757
5758 MODULE_AUTHOR("QLogic Corporation");
5759 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5760 MODULE_LICENSE("GPL");
5761 MODULE_VERSION(QLA2XXX_VERSION);
5762 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5763 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5764 MODULE_FIRMWARE(FW_FILE_ISP2300);
5765 MODULE_FIRMWARE(FW_FILE_ISP2322);
5766 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5767 MODULE_FIRMWARE(FW_FILE_ISP25XX);