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[SCSI] update fc_transport for removal of block/unblock functions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_def.h
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_DEF_H
8 #define __QLA_DEF_H
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <asm/semaphore.h>
26
27 #include <scsi/scsi.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_device.h>
30 #include <scsi/scsi_cmnd.h>
31
32 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
33 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
34 #else
35 #define IS_QLA2100(ha) 0
36 #endif
37
38 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
39 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
40 #else
41 #define IS_QLA2200(ha) 0
42 #endif
43
44 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
45 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
46 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
47 #else
48 #define IS_QLA2300(ha) 0
49 #define IS_QLA2312(ha) 0
50 #endif
51
52 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
53 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
54 #else
55 #define IS_QLA2322(ha) 0
56 #endif
57
58 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
59 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
60 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
61 #else
62 #define IS_QLA6312(ha) 0
63 #define IS_QLA6322(ha) 0
64 #endif
65
66 #if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
67 #define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
68 #define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
69 #else
70 #define IS_QLA2422(ha) 0
71 #define IS_QLA2432(ha) 0
72 #endif
73
74 #if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
75 #define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
76 #define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
77 #else
78 #define IS_QLA2512(ha) 0
79 #define IS_QLA2522(ha) 0
80 #endif
81
82 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
83 IS_QLA6312(ha) || IS_QLA6322(ha))
84
85 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
86 #define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
87
88 /*
89 * Only non-ISP2[12]00 have extended addressing support in the firmware.
90 */
91 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
92
93 /*
94 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
95 * but that's fine as we don't look at the last 24 ones for
96 * ISP2100 HBAs.
97 */
98 #define MAILBOX_REGISTER_COUNT_2100 8
99 #define MAILBOX_REGISTER_COUNT 32
100
101 #define QLA2200A_RISC_ROM_VER 4
102 #define FPM_2300 6
103 #define FPM_2310 7
104
105 #include "qla_settings.h"
106
107 /*
108 * Data bit definitions
109 */
110 #define BIT_0 0x1
111 #define BIT_1 0x2
112 #define BIT_2 0x4
113 #define BIT_3 0x8
114 #define BIT_4 0x10
115 #define BIT_5 0x20
116 #define BIT_6 0x40
117 #define BIT_7 0x80
118 #define BIT_8 0x100
119 #define BIT_9 0x200
120 #define BIT_10 0x400
121 #define BIT_11 0x800
122 #define BIT_12 0x1000
123 #define BIT_13 0x2000
124 #define BIT_14 0x4000
125 #define BIT_15 0x8000
126 #define BIT_16 0x10000
127 #define BIT_17 0x20000
128 #define BIT_18 0x40000
129 #define BIT_19 0x80000
130 #define BIT_20 0x100000
131 #define BIT_21 0x200000
132 #define BIT_22 0x400000
133 #define BIT_23 0x800000
134 #define BIT_24 0x1000000
135 #define BIT_25 0x2000000
136 #define BIT_26 0x4000000
137 #define BIT_27 0x8000000
138 #define BIT_28 0x10000000
139 #define BIT_29 0x20000000
140 #define BIT_30 0x40000000
141 #define BIT_31 0x80000000
142
143 #define LSB(x) ((uint8_t)(x))
144 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
145
146 #define LSW(x) ((uint16_t)(x))
147 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
148
149 #define LSD(x) ((uint32_t)((uint64_t)(x)))
150 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
151
152
153 /*
154 * I/O register
155 */
156
157 #define RD_REG_BYTE(addr) readb(addr)
158 #define RD_REG_WORD(addr) readw(addr)
159 #define RD_REG_DWORD(addr) readl(addr)
160 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
161 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
162 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
163 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
164 #define WRT_REG_WORD(addr, data) writew(data,addr)
165 #define WRT_REG_DWORD(addr, data) writel(data,addr)
166
167 /*
168 * Fibre Channel device definitions.
169 */
170 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
171 #define MAX_FIBRE_DEVICES 512
172 #define MAX_FIBRE_LUNS 0xFFFF
173 #define MAX_RSCN_COUNT 32
174 #define MAX_HOST_COUNT 16
175
176 /*
177 * Host adapter default definitions.
178 */
179 #define MAX_BUSES 1 /* We only have one bus today */
180 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
181 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
182 #define MIN_LUNS 8
183 #define MAX_LUNS MAX_FIBRE_LUNS
184 #define MAX_CMDS_PER_LUN 255
185
186 /*
187 * Fibre Channel device definitions.
188 */
189 #define SNS_LAST_LOOP_ID_2100 0xfe
190 #define SNS_LAST_LOOP_ID_2300 0x7ff
191
192 #define LAST_LOCAL_LOOP_ID 0x7d
193 #define SNS_FL_PORT 0x7e
194 #define FABRIC_CONTROLLER 0x7f
195 #define SIMPLE_NAME_SERVER 0x80
196 #define SNS_FIRST_LOOP_ID 0x81
197 #define MANAGEMENT_SERVER 0xfe
198 #define BROADCAST 0xff
199
200 /*
201 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
202 * valid range of an N-PORT id is 0 through 0x7ef.
203 */
204 #define NPH_LAST_HANDLE 0x7ef
205 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
206 #define NPH_SNS 0x7fc /* FFFFFC */
207 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
208 #define NPH_F_PORT 0x7fe /* FFFFFE */
209 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
210
211 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
212 #include "qla_fw.h"
213
214 /*
215 * Timeout timer counts in seconds
216 */
217 #define PORT_RETRY_TIME 1
218 #define LOOP_DOWN_TIMEOUT 60
219 #define LOOP_DOWN_TIME 255 /* 240 */
220 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
221
222 /* Maximum outstanding commands in ISP queues (1-65535) */
223 #define MAX_OUTSTANDING_COMMANDS 1024
224
225 /* ISP request and response entry counts (37-65535) */
226 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
227 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
228 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
229 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
230 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
231 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
232
233 /*
234 * SCSI Request Block
235 */
236 typedef struct srb {
237 struct list_head list;
238
239 struct scsi_qla_host *ha; /* HA the SP is queued on */
240 struct fc_port *fcport;
241
242 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
243
244 struct timer_list timer; /* Command timer */
245 atomic_t ref_count; /* Reference count for this structure */
246 uint16_t flags;
247
248 /* Request state */
249 uint16_t state;
250
251 /* Single transfer DMA context */
252 dma_addr_t dma_handle;
253
254 uint32_t request_sense_length;
255 uint8_t *request_sense_ptr;
256
257 /* SRB magic number */
258 uint16_t magic;
259 #define SRB_MAGIC 0x10CB
260 } srb_t;
261
262 /*
263 * SRB flag definitions
264 */
265 #define SRB_TIMEOUT BIT_0 /* Command timed out */
266 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
267 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
268 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
269
270 #define SRB_ABORTED BIT_4 /* Command aborted command already */
271 #define SRB_RETRY BIT_5 /* Command needs retrying */
272 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
273 #define SRB_FAILOVER BIT_7 /* Command in failover state */
274
275 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
276 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
277 #define SRB_IOCTL BIT_10 /* IOCTL command. */
278 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
279
280 /*
281 * SRB state definitions
282 */
283 #define SRB_FREE_STATE 0 /* returned back */
284 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
285 #define SRB_ACTIVE_STATE 2 /* in Active Array */
286 #define SRB_DONE_STATE 3 /* queued in Done Queue */
287 #define SRB_RETRY_STATE 4 /* in Retry Queue */
288 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
289 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
290 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
291 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
292 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
293
294
295 /*
296 * ISP I/O Register Set structure definitions.
297 */
298 struct device_reg_2xxx {
299 uint16_t flash_address; /* Flash BIOS address */
300 uint16_t flash_data; /* Flash BIOS data */
301 uint16_t unused_1[1]; /* Gap */
302 uint16_t ctrl_status; /* Control/Status */
303 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
304 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
305 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
306
307 uint16_t ictrl; /* Interrupt control */
308 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
309 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
310
311 uint16_t istatus; /* Interrupt status */
312 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
313
314 uint16_t semaphore; /* Semaphore */
315 uint16_t nvram; /* NVRAM register. */
316 #define NVR_DESELECT 0
317 #define NVR_BUSY BIT_15
318 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
319 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
320 #define NVR_DATA_IN BIT_3
321 #define NVR_DATA_OUT BIT_2
322 #define NVR_SELECT BIT_1
323 #define NVR_CLOCK BIT_0
324
325 union {
326 struct {
327 uint16_t mailbox0;
328 uint16_t mailbox1;
329 uint16_t mailbox2;
330 uint16_t mailbox3;
331 uint16_t mailbox4;
332 uint16_t mailbox5;
333 uint16_t mailbox6;
334 uint16_t mailbox7;
335 uint16_t unused_2[59]; /* Gap */
336 } __attribute__((packed)) isp2100;
337 struct {
338 /* Request Queue */
339 uint16_t req_q_in; /* In-Pointer */
340 uint16_t req_q_out; /* Out-Pointer */
341 /* Response Queue */
342 uint16_t rsp_q_in; /* In-Pointer */
343 uint16_t rsp_q_out; /* Out-Pointer */
344
345 /* RISC to Host Status */
346 uint32_t host_status;
347 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
348 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
349
350 /* Host to Host Semaphore */
351 uint16_t host_semaphore;
352 uint16_t unused_3[17]; /* Gap */
353 uint16_t mailbox0;
354 uint16_t mailbox1;
355 uint16_t mailbox2;
356 uint16_t mailbox3;
357 uint16_t mailbox4;
358 uint16_t mailbox5;
359 uint16_t mailbox6;
360 uint16_t mailbox7;
361 uint16_t mailbox8;
362 uint16_t mailbox9;
363 uint16_t mailbox10;
364 uint16_t mailbox11;
365 uint16_t mailbox12;
366 uint16_t mailbox13;
367 uint16_t mailbox14;
368 uint16_t mailbox15;
369 uint16_t mailbox16;
370 uint16_t mailbox17;
371 uint16_t mailbox18;
372 uint16_t mailbox19;
373 uint16_t mailbox20;
374 uint16_t mailbox21;
375 uint16_t mailbox22;
376 uint16_t mailbox23;
377 uint16_t mailbox24;
378 uint16_t mailbox25;
379 uint16_t mailbox26;
380 uint16_t mailbox27;
381 uint16_t mailbox28;
382 uint16_t mailbox29;
383 uint16_t mailbox30;
384 uint16_t mailbox31;
385 uint16_t fb_cmd;
386 uint16_t unused_4[10]; /* Gap */
387 } __attribute__((packed)) isp2300;
388 } u;
389
390 uint16_t fpm_diag_config;
391 uint16_t unused_5[0x6]; /* Gap */
392 uint16_t pcr; /* Processor Control Register. */
393 uint16_t unused_6[0x5]; /* Gap */
394 uint16_t mctr; /* Memory Configuration and Timing. */
395 uint16_t unused_7[0x3]; /* Gap */
396 uint16_t fb_cmd_2100; /* Unused on 23XX */
397 uint16_t unused_8[0x3]; /* Gap */
398 uint16_t hccr; /* Host command & control register. */
399 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
400 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
401 /* HCCR commands */
402 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
403 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
404 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
405 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
406 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
407 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
408 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
409 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
410
411 uint16_t unused_9[5]; /* Gap */
412 uint16_t gpiod; /* GPIO Data register. */
413 uint16_t gpioe; /* GPIO Enable register. */
414 #define GPIO_LED_MASK 0x00C0
415 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
416 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
417 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
418 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
419
420 union {
421 struct {
422 uint16_t unused_10[8]; /* Gap */
423 uint16_t mailbox8;
424 uint16_t mailbox9;
425 uint16_t mailbox10;
426 uint16_t mailbox11;
427 uint16_t mailbox12;
428 uint16_t mailbox13;
429 uint16_t mailbox14;
430 uint16_t mailbox15;
431 uint16_t mailbox16;
432 uint16_t mailbox17;
433 uint16_t mailbox18;
434 uint16_t mailbox19;
435 uint16_t mailbox20;
436 uint16_t mailbox21;
437 uint16_t mailbox22;
438 uint16_t mailbox23; /* Also probe reg. */
439 } __attribute__((packed)) isp2200;
440 } u_end;
441 };
442
443 typedef union {
444 struct device_reg_2xxx isp;
445 struct device_reg_24xx isp24;
446 } device_reg_t;
447
448 #define ISP_REQ_Q_IN(ha, reg) \
449 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
450 &(reg)->u.isp2100.mailbox4 : \
451 &(reg)->u.isp2300.req_q_in)
452 #define ISP_REQ_Q_OUT(ha, reg) \
453 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
454 &(reg)->u.isp2100.mailbox4 : \
455 &(reg)->u.isp2300.req_q_out)
456 #define ISP_RSP_Q_IN(ha, reg) \
457 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
458 &(reg)->u.isp2100.mailbox5 : \
459 &(reg)->u.isp2300.rsp_q_in)
460 #define ISP_RSP_Q_OUT(ha, reg) \
461 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
462 &(reg)->u.isp2100.mailbox5 : \
463 &(reg)->u.isp2300.rsp_q_out)
464
465 #define MAILBOX_REG(ha, reg, num) \
466 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
467 (num < 8 ? \
468 &(reg)->u.isp2100.mailbox0 + (num) : \
469 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
470 &(reg)->u.isp2300.mailbox0 + (num))
471 #define RD_MAILBOX_REG(ha, reg, num) \
472 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
473 #define WRT_MAILBOX_REG(ha, reg, num, data) \
474 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
475
476 #define FB_CMD_REG(ha, reg) \
477 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
478 &(reg)->fb_cmd_2100 : \
479 &(reg)->u.isp2300.fb_cmd)
480 #define RD_FB_CMD_REG(ha, reg) \
481 RD_REG_WORD(FB_CMD_REG(ha, reg))
482 #define WRT_FB_CMD_REG(ha, reg, data) \
483 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
484
485 typedef struct {
486 uint32_t out_mb; /* outbound from driver */
487 uint32_t in_mb; /* Incoming from RISC */
488 uint16_t mb[MAILBOX_REGISTER_COUNT];
489 long buf_size;
490 void *bufp;
491 uint32_t tov;
492 uint8_t flags;
493 #define MBX_DMA_IN BIT_0
494 #define MBX_DMA_OUT BIT_1
495 #define IOCTL_CMD BIT_2
496 } mbx_cmd_t;
497
498 #define MBX_TOV_SECONDS 30
499
500 /*
501 * ISP product identification definitions in mailboxes after reset.
502 */
503 #define PROD_ID_1 0x4953
504 #define PROD_ID_2 0x0000
505 #define PROD_ID_2a 0x5020
506 #define PROD_ID_3 0x2020
507
508 /*
509 * ISP mailbox Self-Test status codes
510 */
511 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
512 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
513 #define MBS_BUSY 4 /* Busy. */
514
515 /*
516 * ISP mailbox command complete status codes
517 */
518 #define MBS_COMMAND_COMPLETE 0x4000
519 #define MBS_INVALID_COMMAND 0x4001
520 #define MBS_HOST_INTERFACE_ERROR 0x4002
521 #define MBS_TEST_FAILED 0x4003
522 #define MBS_COMMAND_ERROR 0x4005
523 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
524 #define MBS_PORT_ID_USED 0x4007
525 #define MBS_LOOP_ID_USED 0x4008
526 #define MBS_ALL_IDS_IN_USE 0x4009
527 #define MBS_NOT_LOGGED_IN 0x400A
528 #define MBS_LINK_DOWN_ERROR 0x400B
529 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
530
531 /*
532 * ISP mailbox asynchronous event status codes
533 */
534 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
535 #define MBA_RESET 0x8001 /* Reset Detected. */
536 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
537 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
538 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
539 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
540 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
541 /* occurred. */
542 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
543 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
544 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
545 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
546 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
547 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
548 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
549 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
550 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
551 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
552 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
553 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
554 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
555 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
556 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
557 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
558 /* used. */
559 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
560 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
561 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
562 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
563 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
564 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
565 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
566 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
567 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
568 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
569 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
570 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
571 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
572
573 /*
574 * Firmware options 1, 2, 3.
575 */
576 #define FO1_AE_ON_LIPF8 BIT_0
577 #define FO1_AE_ALL_LIP_RESET BIT_1
578 #define FO1_CTIO_RETRY BIT_3
579 #define FO1_DISABLE_LIP_F7_SW BIT_4
580 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
581 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
582 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
583 #define FO1_SET_EMPHASIS_SWING BIT_8
584 #define FO1_AE_AUTO_BYPASS BIT_9
585 #define FO1_ENABLE_PURE_IOCB BIT_10
586 #define FO1_AE_PLOGI_RJT BIT_11
587 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
588 #define FO1_AE_QUEUE_FULL BIT_13
589
590 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
591 #define FO2_REV_LOOPBACK BIT_1
592
593 #define FO3_ENABLE_EMERG_IOCB BIT_0
594 #define FO3_AE_RND_ERROR BIT_1
595
596 /* 24XX additional firmware options */
597 #define ADD_FO_COUNT 3
598 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
599 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
600
601 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
602
603 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
604
605 /*
606 * ISP mailbox commands
607 */
608 #define MBC_LOAD_RAM 1 /* Load RAM. */
609 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
610 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
611 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
612 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
613 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
614 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
615 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
616 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
617 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
618 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
619 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
620 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
621 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
622 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
623 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
624 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
625 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
626 #define MBC_RESET 0x18 /* Reset. */
627 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
628 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
629 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
630 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
631 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
632 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
633 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
634 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
635 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
636 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
637 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
638 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
639 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
640 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
641 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
642 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
643 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
644 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
645 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
646 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
647 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
648 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
649 /* Initialization Procedure */
650 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
651 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
652 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
653 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
654 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
655 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
656 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
657 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
658 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
659 #define MBC_LIP_RESET 0x6c /* LIP reset. */
660 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
661 /* commandd. */
662 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
663 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
664 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
665 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
666 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
667 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
668 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
669 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
670 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
671 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
672 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
673
674 /*
675 * ISP24xx mailbox commands
676 */
677 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
678 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
679 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
680 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
681 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
682 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
683 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
684 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
685 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
686 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
687 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
688 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
689
690 /* Firmware return data sizes */
691 #define FCAL_MAP_SIZE 128
692
693 /* Mailbox bit definitions for out_mb and in_mb */
694 #define MBX_31 BIT_31
695 #define MBX_30 BIT_30
696 #define MBX_29 BIT_29
697 #define MBX_28 BIT_28
698 #define MBX_27 BIT_27
699 #define MBX_26 BIT_26
700 #define MBX_25 BIT_25
701 #define MBX_24 BIT_24
702 #define MBX_23 BIT_23
703 #define MBX_22 BIT_22
704 #define MBX_21 BIT_21
705 #define MBX_20 BIT_20
706 #define MBX_19 BIT_19
707 #define MBX_18 BIT_18
708 #define MBX_17 BIT_17
709 #define MBX_16 BIT_16
710 #define MBX_15 BIT_15
711 #define MBX_14 BIT_14
712 #define MBX_13 BIT_13
713 #define MBX_12 BIT_12
714 #define MBX_11 BIT_11
715 #define MBX_10 BIT_10
716 #define MBX_9 BIT_9
717 #define MBX_8 BIT_8
718 #define MBX_7 BIT_7
719 #define MBX_6 BIT_6
720 #define MBX_5 BIT_5
721 #define MBX_4 BIT_4
722 #define MBX_3 BIT_3
723 #define MBX_2 BIT_2
724 #define MBX_1 BIT_1
725 #define MBX_0 BIT_0
726
727 /*
728 * Firmware state codes from get firmware state mailbox command
729 */
730 #define FSTATE_CONFIG_WAIT 0
731 #define FSTATE_WAIT_AL_PA 1
732 #define FSTATE_WAIT_LOGIN 2
733 #define FSTATE_READY 3
734 #define FSTATE_LOSS_OF_SYNC 4
735 #define FSTATE_ERROR 5
736 #define FSTATE_REINIT 6
737 #define FSTATE_NON_PART 7
738
739 #define FSTATE_CONFIG_CORRECT 0
740 #define FSTATE_P2P_RCV_LIP 1
741 #define FSTATE_P2P_CHOOSE_LOOP 2
742 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
743 #define FSTATE_FATAL_ERROR 4
744 #define FSTATE_LOOP_BACK_CONN 5
745
746 /*
747 * Port Database structure definition
748 * Little endian except where noted.
749 */
750 #define PORT_DATABASE_SIZE 128 /* bytes */
751 typedef struct {
752 uint8_t options;
753 uint8_t control;
754 uint8_t master_state;
755 uint8_t slave_state;
756 uint8_t reserved[2];
757 uint8_t hard_address;
758 uint8_t reserved_1;
759 uint8_t port_id[4];
760 uint8_t node_name[WWN_SIZE];
761 uint8_t port_name[WWN_SIZE];
762 uint16_t execution_throttle;
763 uint16_t execution_count;
764 uint8_t reset_count;
765 uint8_t reserved_2;
766 uint16_t resource_allocation;
767 uint16_t current_allocation;
768 uint16_t queue_head;
769 uint16_t queue_tail;
770 uint16_t transmit_execution_list_next;
771 uint16_t transmit_execution_list_previous;
772 uint16_t common_features;
773 uint16_t total_concurrent_sequences;
774 uint16_t RO_by_information_category;
775 uint8_t recipient;
776 uint8_t initiator;
777 uint16_t receive_data_size;
778 uint16_t concurrent_sequences;
779 uint16_t open_sequences_per_exchange;
780 uint16_t lun_abort_flags;
781 uint16_t lun_stop_flags;
782 uint16_t stop_queue_head;
783 uint16_t stop_queue_tail;
784 uint16_t port_retry_timer;
785 uint16_t next_sequence_id;
786 uint16_t frame_count;
787 uint16_t PRLI_payload_length;
788 uint8_t prli_svc_param_word_0[2]; /* Big endian */
789 /* Bits 15-0 of word 0 */
790 uint8_t prli_svc_param_word_3[2]; /* Big endian */
791 /* Bits 15-0 of word 3 */
792 uint16_t loop_id;
793 uint16_t extended_lun_info_list_pointer;
794 uint16_t extended_lun_stop_list_pointer;
795 } port_database_t;
796
797 /*
798 * Port database slave/master states
799 */
800 #define PD_STATE_DISCOVERY 0
801 #define PD_STATE_WAIT_DISCOVERY_ACK 1
802 #define PD_STATE_PORT_LOGIN 2
803 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
804 #define PD_STATE_PROCESS_LOGIN 4
805 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
806 #define PD_STATE_PORT_LOGGED_IN 6
807 #define PD_STATE_PORT_UNAVAILABLE 7
808 #define PD_STATE_PROCESS_LOGOUT 8
809 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
810 #define PD_STATE_PORT_LOGOUT 10
811 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
812
813
814 #define QLA_ZIO_MODE_5 (BIT_2 | BIT_0)
815 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
816 #define QLA_ZIO_DISABLED 0
817 #define QLA_ZIO_DEFAULT_TIMER 2
818
819 /*
820 * ISP Initialization Control Block.
821 * Little endian except where noted.
822 */
823 #define ICB_VERSION 1
824 typedef struct {
825 uint8_t version;
826 uint8_t reserved_1;
827
828 /*
829 * LSB BIT 0 = Enable Hard Loop Id
830 * LSB BIT 1 = Enable Fairness
831 * LSB BIT 2 = Enable Full-Duplex
832 * LSB BIT 3 = Enable Fast Posting
833 * LSB BIT 4 = Enable Target Mode
834 * LSB BIT 5 = Disable Initiator Mode
835 * LSB BIT 6 = Enable ADISC
836 * LSB BIT 7 = Enable Target Inquiry Data
837 *
838 * MSB BIT 0 = Enable PDBC Notify
839 * MSB BIT 1 = Non Participating LIP
840 * MSB BIT 2 = Descending Loop ID Search
841 * MSB BIT 3 = Acquire Loop ID in LIPA
842 * MSB BIT 4 = Stop PortQ on Full Status
843 * MSB BIT 5 = Full Login after LIP
844 * MSB BIT 6 = Node Name Option
845 * MSB BIT 7 = Ext IFWCB enable bit
846 */
847 uint8_t firmware_options[2];
848
849 uint16_t frame_payload_size;
850 uint16_t max_iocb_allocation;
851 uint16_t execution_throttle;
852 uint8_t retry_count;
853 uint8_t retry_delay; /* unused */
854 uint8_t port_name[WWN_SIZE]; /* Big endian. */
855 uint16_t hard_address;
856 uint8_t inquiry_data;
857 uint8_t login_timeout;
858 uint8_t node_name[WWN_SIZE]; /* Big endian. */
859
860 uint16_t request_q_outpointer;
861 uint16_t response_q_inpointer;
862 uint16_t request_q_length;
863 uint16_t response_q_length;
864 uint32_t request_q_address[2];
865 uint32_t response_q_address[2];
866
867 uint16_t lun_enables;
868 uint8_t command_resource_count;
869 uint8_t immediate_notify_resource_count;
870 uint16_t timeout;
871 uint8_t reserved_2[2];
872
873 /*
874 * LSB BIT 0 = Timer Operation mode bit 0
875 * LSB BIT 1 = Timer Operation mode bit 1
876 * LSB BIT 2 = Timer Operation mode bit 2
877 * LSB BIT 3 = Timer Operation mode bit 3
878 * LSB BIT 4 = Init Config Mode bit 0
879 * LSB BIT 5 = Init Config Mode bit 1
880 * LSB BIT 6 = Init Config Mode bit 2
881 * LSB BIT 7 = Enable Non part on LIHA failure
882 *
883 * MSB BIT 0 = Enable class 2
884 * MSB BIT 1 = Enable ACK0
885 * MSB BIT 2 =
886 * MSB BIT 3 =
887 * MSB BIT 4 = FC Tape Enable
888 * MSB BIT 5 = Enable FC Confirm
889 * MSB BIT 6 = Enable command queuing in target mode
890 * MSB BIT 7 = No Logo On Link Down
891 */
892 uint8_t add_firmware_options[2];
893
894 uint8_t response_accumulation_timer;
895 uint8_t interrupt_delay_timer;
896
897 /*
898 * LSB BIT 0 = Enable Read xfr_rdy
899 * LSB BIT 1 = Soft ID only
900 * LSB BIT 2 =
901 * LSB BIT 3 =
902 * LSB BIT 4 = FCP RSP Payload [0]
903 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
904 * LSB BIT 6 = Enable Out-of-Order frame handling
905 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
906 *
907 * MSB BIT 0 = Sbus enable - 2300
908 * MSB BIT 1 =
909 * MSB BIT 2 =
910 * MSB BIT 3 =
911 * MSB BIT 4 = LED mode
912 * MSB BIT 5 = enable 50 ohm termination
913 * MSB BIT 6 = Data Rate (2300 only)
914 * MSB BIT 7 = Data Rate (2300 only)
915 */
916 uint8_t special_options[2];
917
918 uint8_t reserved_3[26];
919 } init_cb_t;
920
921 /*
922 * Get Link Status mailbox command return buffer.
923 */
924 #define GLSO_SEND_RPS BIT_0
925 #define GLSO_USE_DID BIT_3
926
927 typedef struct {
928 uint32_t link_fail_cnt;
929 uint32_t loss_sync_cnt;
930 uint32_t loss_sig_cnt;
931 uint32_t prim_seq_err_cnt;
932 uint32_t inval_xmit_word_cnt;
933 uint32_t inval_crc_cnt;
934 } link_stat_t;
935
936 /*
937 * NVRAM Command values.
938 */
939 #define NV_START_BIT BIT_2
940 #define NV_WRITE_OP (BIT_26+BIT_24)
941 #define NV_READ_OP (BIT_26+BIT_25)
942 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
943 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
944 #define NV_DELAY_COUNT 10
945
946 /*
947 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
948 */
949 typedef struct {
950 /*
951 * NVRAM header
952 */
953 uint8_t id[4];
954 uint8_t nvram_version;
955 uint8_t reserved_0;
956
957 /*
958 * NVRAM RISC parameter block
959 */
960 uint8_t parameter_block_version;
961 uint8_t reserved_1;
962
963 /*
964 * LSB BIT 0 = Enable Hard Loop Id
965 * LSB BIT 1 = Enable Fairness
966 * LSB BIT 2 = Enable Full-Duplex
967 * LSB BIT 3 = Enable Fast Posting
968 * LSB BIT 4 = Enable Target Mode
969 * LSB BIT 5 = Disable Initiator Mode
970 * LSB BIT 6 = Enable ADISC
971 * LSB BIT 7 = Enable Target Inquiry Data
972 *
973 * MSB BIT 0 = Enable PDBC Notify
974 * MSB BIT 1 = Non Participating LIP
975 * MSB BIT 2 = Descending Loop ID Search
976 * MSB BIT 3 = Acquire Loop ID in LIPA
977 * MSB BIT 4 = Stop PortQ on Full Status
978 * MSB BIT 5 = Full Login after LIP
979 * MSB BIT 6 = Node Name Option
980 * MSB BIT 7 = Ext IFWCB enable bit
981 */
982 uint8_t firmware_options[2];
983
984 uint16_t frame_payload_size;
985 uint16_t max_iocb_allocation;
986 uint16_t execution_throttle;
987 uint8_t retry_count;
988 uint8_t retry_delay; /* unused */
989 uint8_t port_name[WWN_SIZE]; /* Big endian. */
990 uint16_t hard_address;
991 uint8_t inquiry_data;
992 uint8_t login_timeout;
993 uint8_t node_name[WWN_SIZE]; /* Big endian. */
994
995 /*
996 * LSB BIT 0 = Timer Operation mode bit 0
997 * LSB BIT 1 = Timer Operation mode bit 1
998 * LSB BIT 2 = Timer Operation mode bit 2
999 * LSB BIT 3 = Timer Operation mode bit 3
1000 * LSB BIT 4 = Init Config Mode bit 0
1001 * LSB BIT 5 = Init Config Mode bit 1
1002 * LSB BIT 6 = Init Config Mode bit 2
1003 * LSB BIT 7 = Enable Non part on LIHA failure
1004 *
1005 * MSB BIT 0 = Enable class 2
1006 * MSB BIT 1 = Enable ACK0
1007 * MSB BIT 2 =
1008 * MSB BIT 3 =
1009 * MSB BIT 4 = FC Tape Enable
1010 * MSB BIT 5 = Enable FC Confirm
1011 * MSB BIT 6 = Enable command queuing in target mode
1012 * MSB BIT 7 = No Logo On Link Down
1013 */
1014 uint8_t add_firmware_options[2];
1015
1016 uint8_t response_accumulation_timer;
1017 uint8_t interrupt_delay_timer;
1018
1019 /*
1020 * LSB BIT 0 = Enable Read xfr_rdy
1021 * LSB BIT 1 = Soft ID only
1022 * LSB BIT 2 =
1023 * LSB BIT 3 =
1024 * LSB BIT 4 = FCP RSP Payload [0]
1025 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1026 * LSB BIT 6 = Enable Out-of-Order frame handling
1027 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1028 *
1029 * MSB BIT 0 = Sbus enable - 2300
1030 * MSB BIT 1 =
1031 * MSB BIT 2 =
1032 * MSB BIT 3 =
1033 * MSB BIT 4 = LED mode
1034 * MSB BIT 5 = enable 50 ohm termination
1035 * MSB BIT 6 = Data Rate (2300 only)
1036 * MSB BIT 7 = Data Rate (2300 only)
1037 */
1038 uint8_t special_options[2];
1039
1040 /* Reserved for expanded RISC parameter block */
1041 uint8_t reserved_2[22];
1042
1043 /*
1044 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1045 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1046 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1047 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1048 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1049 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1050 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1051 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1052 *
1053 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1054 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1055 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1056 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1057 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1058 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1059 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1060 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1061 *
1062 * LSB BIT 0 = Output Swing 1G bit 0
1063 * LSB BIT 1 = Output Swing 1G bit 1
1064 * LSB BIT 2 = Output Swing 1G bit 2
1065 * LSB BIT 3 = Output Emphasis 1G bit 0
1066 * LSB BIT 4 = Output Emphasis 1G bit 1
1067 * LSB BIT 5 = Output Swing 2G bit 0
1068 * LSB BIT 6 = Output Swing 2G bit 1
1069 * LSB BIT 7 = Output Swing 2G bit 2
1070 *
1071 * MSB BIT 0 = Output Emphasis 2G bit 0
1072 * MSB BIT 1 = Output Emphasis 2G bit 1
1073 * MSB BIT 2 = Output Enable
1074 * MSB BIT 3 =
1075 * MSB BIT 4 =
1076 * MSB BIT 5 =
1077 * MSB BIT 6 =
1078 * MSB BIT 7 =
1079 */
1080 uint8_t seriallink_options[4];
1081
1082 /*
1083 * NVRAM host parameter block
1084 *
1085 * LSB BIT 0 = Enable spinup delay
1086 * LSB BIT 1 = Disable BIOS
1087 * LSB BIT 2 = Enable Memory Map BIOS
1088 * LSB BIT 3 = Enable Selectable Boot
1089 * LSB BIT 4 = Disable RISC code load
1090 * LSB BIT 5 = Set cache line size 1
1091 * LSB BIT 6 = PCI Parity Disable
1092 * LSB BIT 7 = Enable extended logging
1093 *
1094 * MSB BIT 0 = Enable 64bit addressing
1095 * MSB BIT 1 = Enable lip reset
1096 * MSB BIT 2 = Enable lip full login
1097 * MSB BIT 3 = Enable target reset
1098 * MSB BIT 4 = Enable database storage
1099 * MSB BIT 5 = Enable cache flush read
1100 * MSB BIT 6 = Enable database load
1101 * MSB BIT 7 = Enable alternate WWN
1102 */
1103 uint8_t host_p[2];
1104
1105 uint8_t boot_node_name[WWN_SIZE];
1106 uint8_t boot_lun_number;
1107 uint8_t reset_delay;
1108 uint8_t port_down_retry_count;
1109 uint8_t boot_id_number;
1110 uint16_t max_luns_per_target;
1111 uint8_t fcode_boot_port_name[WWN_SIZE];
1112 uint8_t alternate_port_name[WWN_SIZE];
1113 uint8_t alternate_node_name[WWN_SIZE];
1114
1115 /*
1116 * BIT 0 = Selective Login
1117 * BIT 1 = Alt-Boot Enable
1118 * BIT 2 =
1119 * BIT 3 = Boot Order List
1120 * BIT 4 =
1121 * BIT 5 = Selective LUN
1122 * BIT 6 =
1123 * BIT 7 = unused
1124 */
1125 uint8_t efi_parameters;
1126
1127 uint8_t link_down_timeout;
1128
1129 uint8_t adapter_id[16];
1130
1131 uint8_t alt1_boot_node_name[WWN_SIZE];
1132 uint16_t alt1_boot_lun_number;
1133 uint8_t alt2_boot_node_name[WWN_SIZE];
1134 uint16_t alt2_boot_lun_number;
1135 uint8_t alt3_boot_node_name[WWN_SIZE];
1136 uint16_t alt3_boot_lun_number;
1137 uint8_t alt4_boot_node_name[WWN_SIZE];
1138 uint16_t alt4_boot_lun_number;
1139 uint8_t alt5_boot_node_name[WWN_SIZE];
1140 uint16_t alt5_boot_lun_number;
1141 uint8_t alt6_boot_node_name[WWN_SIZE];
1142 uint16_t alt6_boot_lun_number;
1143 uint8_t alt7_boot_node_name[WWN_SIZE];
1144 uint16_t alt7_boot_lun_number;
1145
1146 uint8_t reserved_3[2];
1147
1148 /* Offset 200-215 : Model Number */
1149 uint8_t model_number[16];
1150
1151 /* OEM related items */
1152 uint8_t oem_specific[16];
1153
1154 /*
1155 * NVRAM Adapter Features offset 232-239
1156 *
1157 * LSB BIT 0 = External GBIC
1158 * LSB BIT 1 = Risc RAM parity
1159 * LSB BIT 2 = Buffer Plus Module
1160 * LSB BIT 3 = Multi Chip Adapter
1161 * LSB BIT 4 = Internal connector
1162 * LSB BIT 5 =
1163 * LSB BIT 6 =
1164 * LSB BIT 7 =
1165 *
1166 * MSB BIT 0 =
1167 * MSB BIT 1 =
1168 * MSB BIT 2 =
1169 * MSB BIT 3 =
1170 * MSB BIT 4 =
1171 * MSB BIT 5 =
1172 * MSB BIT 6 =
1173 * MSB BIT 7 =
1174 */
1175 uint8_t adapter_features[2];
1176
1177 uint8_t reserved_4[16];
1178
1179 /* Subsystem vendor ID for ISP2200 */
1180 uint16_t subsystem_vendor_id_2200;
1181
1182 /* Subsystem device ID for ISP2200 */
1183 uint16_t subsystem_device_id_2200;
1184
1185 uint8_t reserved_5;
1186 uint8_t checksum;
1187 } nvram_t;
1188
1189 /*
1190 * ISP queue - response queue entry definition.
1191 */
1192 typedef struct {
1193 uint8_t data[60];
1194 uint32_t signature;
1195 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1196 } response_t;
1197
1198 typedef union {
1199 uint16_t extended;
1200 struct {
1201 uint8_t reserved;
1202 uint8_t standard;
1203 } id;
1204 } target_id_t;
1205
1206 #define SET_TARGET_ID(ha, to, from) \
1207 do { \
1208 if (HAS_EXTENDED_IDS(ha)) \
1209 to.extended = cpu_to_le16(from); \
1210 else \
1211 to.id.standard = (uint8_t)from; \
1212 } while (0)
1213
1214 /*
1215 * ISP queue - command entry structure definition.
1216 */
1217 #define COMMAND_TYPE 0x11 /* Command entry */
1218 typedef struct {
1219 uint8_t entry_type; /* Entry type. */
1220 uint8_t entry_count; /* Entry count. */
1221 uint8_t sys_define; /* System defined. */
1222 uint8_t entry_status; /* Entry Status. */
1223 uint32_t handle; /* System handle. */
1224 target_id_t target; /* SCSI ID */
1225 uint16_t lun; /* SCSI LUN */
1226 uint16_t control_flags; /* Control flags. */
1227 #define CF_WRITE BIT_6
1228 #define CF_READ BIT_5
1229 #define CF_SIMPLE_TAG BIT_3
1230 #define CF_ORDERED_TAG BIT_2
1231 #define CF_HEAD_TAG BIT_1
1232 uint16_t reserved_1;
1233 uint16_t timeout; /* Command timeout. */
1234 uint16_t dseg_count; /* Data segment count. */
1235 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1236 uint32_t byte_count; /* Total byte count. */
1237 uint32_t dseg_0_address; /* Data segment 0 address. */
1238 uint32_t dseg_0_length; /* Data segment 0 length. */
1239 uint32_t dseg_1_address; /* Data segment 1 address. */
1240 uint32_t dseg_1_length; /* Data segment 1 length. */
1241 uint32_t dseg_2_address; /* Data segment 2 address. */
1242 uint32_t dseg_2_length; /* Data segment 2 length. */
1243 } cmd_entry_t;
1244
1245 /*
1246 * ISP queue - 64-Bit addressing, command entry structure definition.
1247 */
1248 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1249 typedef struct {
1250 uint8_t entry_type; /* Entry type. */
1251 uint8_t entry_count; /* Entry count. */
1252 uint8_t sys_define; /* System defined. */
1253 uint8_t entry_status; /* Entry Status. */
1254 uint32_t handle; /* System handle. */
1255 target_id_t target; /* SCSI ID */
1256 uint16_t lun; /* SCSI LUN */
1257 uint16_t control_flags; /* Control flags. */
1258 uint16_t reserved_1;
1259 uint16_t timeout; /* Command timeout. */
1260 uint16_t dseg_count; /* Data segment count. */
1261 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1262 uint32_t byte_count; /* Total byte count. */
1263 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1264 uint32_t dseg_0_length; /* Data segment 0 length. */
1265 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1266 uint32_t dseg_1_length; /* Data segment 1 length. */
1267 } cmd_a64_entry_t, request_t;
1268
1269 /*
1270 * ISP queue - continuation entry structure definition.
1271 */
1272 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1273 typedef struct {
1274 uint8_t entry_type; /* Entry type. */
1275 uint8_t entry_count; /* Entry count. */
1276 uint8_t sys_define; /* System defined. */
1277 uint8_t entry_status; /* Entry Status. */
1278 uint32_t reserved;
1279 uint32_t dseg_0_address; /* Data segment 0 address. */
1280 uint32_t dseg_0_length; /* Data segment 0 length. */
1281 uint32_t dseg_1_address; /* Data segment 1 address. */
1282 uint32_t dseg_1_length; /* Data segment 1 length. */
1283 uint32_t dseg_2_address; /* Data segment 2 address. */
1284 uint32_t dseg_2_length; /* Data segment 2 length. */
1285 uint32_t dseg_3_address; /* Data segment 3 address. */
1286 uint32_t dseg_3_length; /* Data segment 3 length. */
1287 uint32_t dseg_4_address; /* Data segment 4 address. */
1288 uint32_t dseg_4_length; /* Data segment 4 length. */
1289 uint32_t dseg_5_address; /* Data segment 5 address. */
1290 uint32_t dseg_5_length; /* Data segment 5 length. */
1291 uint32_t dseg_6_address; /* Data segment 6 address. */
1292 uint32_t dseg_6_length; /* Data segment 6 length. */
1293 } cont_entry_t;
1294
1295 /*
1296 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1297 */
1298 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1299 typedef struct {
1300 uint8_t entry_type; /* Entry type. */
1301 uint8_t entry_count; /* Entry count. */
1302 uint8_t sys_define; /* System defined. */
1303 uint8_t entry_status; /* Entry Status. */
1304 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1305 uint32_t dseg_0_length; /* Data segment 0 length. */
1306 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1307 uint32_t dseg_1_length; /* Data segment 1 length. */
1308 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1309 uint32_t dseg_2_length; /* Data segment 2 length. */
1310 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1311 uint32_t dseg_3_length; /* Data segment 3 length. */
1312 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1313 uint32_t dseg_4_length; /* Data segment 4 length. */
1314 } cont_a64_entry_t;
1315
1316 /*
1317 * ISP queue - status entry structure definition.
1318 */
1319 #define STATUS_TYPE 0x03 /* Status entry. */
1320 typedef struct {
1321 uint8_t entry_type; /* Entry type. */
1322 uint8_t entry_count; /* Entry count. */
1323 uint8_t sys_define; /* System defined. */
1324 uint8_t entry_status; /* Entry Status. */
1325 uint32_t handle; /* System handle. */
1326 uint16_t scsi_status; /* SCSI status. */
1327 uint16_t comp_status; /* Completion status. */
1328 uint16_t state_flags; /* State flags. */
1329 uint16_t status_flags; /* Status flags. */
1330 uint16_t rsp_info_len; /* Response Info Length. */
1331 uint16_t req_sense_length; /* Request sense data length. */
1332 uint32_t residual_length; /* Residual transfer length. */
1333 uint8_t rsp_info[8]; /* FCP response information. */
1334 uint8_t req_sense_data[32]; /* Request sense data. */
1335 } sts_entry_t;
1336
1337 /*
1338 * Status entry entry status
1339 */
1340 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1341 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1342 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1343 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1344 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1345 #define RF_BUSY BIT_1 /* Busy */
1346 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1347 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1348 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1349 RF_INV_E_TYPE)
1350
1351 /*
1352 * Status entry SCSI status bit definitions.
1353 */
1354 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1355 #define SS_RESIDUAL_UNDER BIT_11
1356 #define SS_RESIDUAL_OVER BIT_10
1357 #define SS_SENSE_LEN_VALID BIT_9
1358 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1359
1360 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1361 #define SS_BUSY_CONDITION BIT_3
1362 #define SS_CONDITION_MET BIT_2
1363 #define SS_CHECK_CONDITION BIT_1
1364
1365 /*
1366 * Status entry completion status
1367 */
1368 #define CS_COMPLETE 0x0 /* No errors */
1369 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1370 #define CS_DMA 0x2 /* A DMA direction error. */
1371 #define CS_TRANSPORT 0x3 /* Transport error. */
1372 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1373 #define CS_ABORTED 0x5 /* System aborted command. */
1374 #define CS_TIMEOUT 0x6 /* Timeout error. */
1375 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1376
1377 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1378 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1379 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1380 /* (selection timeout) */
1381 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1382 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1383 #define CS_PORT_BUSY 0x2B /* Port Busy */
1384 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1385 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1386 #define CS_UNKNOWN 0x81 /* Driver defined */
1387 #define CS_RETRY 0x82 /* Driver defined */
1388 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1389
1390 /*
1391 * Status entry status flags
1392 */
1393 #define SF_ABTS_TERMINATED BIT_10
1394 #define SF_LOGOUT_SENT BIT_13
1395
1396 /*
1397 * ISP queue - status continuation entry structure definition.
1398 */
1399 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1400 typedef struct {
1401 uint8_t entry_type; /* Entry type. */
1402 uint8_t entry_count; /* Entry count. */
1403 uint8_t sys_define; /* System defined. */
1404 uint8_t entry_status; /* Entry Status. */
1405 uint8_t data[60]; /* data */
1406 } sts_cont_entry_t;
1407
1408 /*
1409 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1410 * structure definition.
1411 */
1412 #define STATUS_TYPE_21 0x21 /* Status entry. */
1413 typedef struct {
1414 uint8_t entry_type; /* Entry type. */
1415 uint8_t entry_count; /* Entry count. */
1416 uint8_t handle_count; /* Handle count. */
1417 uint8_t entry_status; /* Entry Status. */
1418 uint32_t handle[15]; /* System handles. */
1419 } sts21_entry_t;
1420
1421 /*
1422 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1423 * structure definition.
1424 */
1425 #define STATUS_TYPE_22 0x22 /* Status entry. */
1426 typedef struct {
1427 uint8_t entry_type; /* Entry type. */
1428 uint8_t entry_count; /* Entry count. */
1429 uint8_t handle_count; /* Handle count. */
1430 uint8_t entry_status; /* Entry Status. */
1431 uint16_t handle[30]; /* System handles. */
1432 } sts22_entry_t;
1433
1434 /*
1435 * ISP queue - marker entry structure definition.
1436 */
1437 #define MARKER_TYPE 0x04 /* Marker entry. */
1438 typedef struct {
1439 uint8_t entry_type; /* Entry type. */
1440 uint8_t entry_count; /* Entry count. */
1441 uint8_t handle_count; /* Handle count. */
1442 uint8_t entry_status; /* Entry Status. */
1443 uint32_t sys_define_2; /* System defined. */
1444 target_id_t target; /* SCSI ID */
1445 uint8_t modifier; /* Modifier (7-0). */
1446 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1447 #define MK_SYNC_ID 1 /* Synchronize ID */
1448 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1449 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1450 /* clear port changed, */
1451 /* use sequence number. */
1452 uint8_t reserved_1;
1453 uint16_t sequence_number; /* Sequence number of event */
1454 uint16_t lun; /* SCSI LUN */
1455 uint8_t reserved_2[48];
1456 } mrk_entry_t;
1457
1458 /*
1459 * ISP queue - Management Server entry structure definition.
1460 */
1461 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1462 typedef struct {
1463 uint8_t entry_type; /* Entry type. */
1464 uint8_t entry_count; /* Entry count. */
1465 uint8_t handle_count; /* Handle count. */
1466 uint8_t entry_status; /* Entry Status. */
1467 uint32_t handle1; /* System handle. */
1468 target_id_t loop_id;
1469 uint16_t status;
1470 uint16_t control_flags; /* Control flags. */
1471 uint16_t reserved2;
1472 uint16_t timeout;
1473 uint16_t cmd_dsd_count;
1474 uint16_t total_dsd_count;
1475 uint8_t type;
1476 uint8_t r_ctl;
1477 uint16_t rx_id;
1478 uint16_t reserved3;
1479 uint32_t handle2;
1480 uint32_t rsp_bytecount;
1481 uint32_t req_bytecount;
1482 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1483 uint32_t dseg_req_length; /* Data segment 0 length. */
1484 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1485 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1486 } ms_iocb_entry_t;
1487
1488
1489 /*
1490 * ISP queue - Mailbox Command entry structure definition.
1491 */
1492 #define MBX_IOCB_TYPE 0x39
1493 struct mbx_entry {
1494 uint8_t entry_type;
1495 uint8_t entry_count;
1496 uint8_t sys_define1;
1497 /* Use sys_define1 for source type */
1498 #define SOURCE_SCSI 0x00
1499 #define SOURCE_IP 0x01
1500 #define SOURCE_VI 0x02
1501 #define SOURCE_SCTP 0x03
1502 #define SOURCE_MP 0x04
1503 #define SOURCE_MPIOCTL 0x05
1504 #define SOURCE_ASYNC_IOCB 0x07
1505
1506 uint8_t entry_status;
1507
1508 uint32_t handle;
1509 target_id_t loop_id;
1510
1511 uint16_t status;
1512 uint16_t state_flags;
1513 uint16_t status_flags;
1514
1515 uint32_t sys_define2[2];
1516
1517 uint16_t mb0;
1518 uint16_t mb1;
1519 uint16_t mb2;
1520 uint16_t mb3;
1521 uint16_t mb6;
1522 uint16_t mb7;
1523 uint16_t mb9;
1524 uint16_t mb10;
1525 uint32_t reserved_2[2];
1526 uint8_t node_name[WWN_SIZE];
1527 uint8_t port_name[WWN_SIZE];
1528 };
1529
1530 /*
1531 * ISP request and response queue entry sizes
1532 */
1533 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1534 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1535
1536
1537 /*
1538 * 24 bit port ID type definition.
1539 */
1540 typedef union {
1541 uint32_t b24 : 24;
1542
1543 struct {
1544 uint8_t d_id[3];
1545 uint8_t rsvd_1;
1546 } r;
1547
1548 struct {
1549 uint8_t al_pa;
1550 uint8_t area;
1551 uint8_t domain;
1552 uint8_t rsvd_1;
1553 } b;
1554 } port_id_t;
1555 #define INVALID_PORT_ID 0xFFFFFF
1556
1557 /*
1558 * Switch info gathering structure.
1559 */
1560 typedef struct {
1561 port_id_t d_id;
1562 uint8_t node_name[WWN_SIZE];
1563 uint8_t port_name[WWN_SIZE];
1564 } sw_info_t;
1565
1566 /*
1567 * Inquiry command structure.
1568 */
1569 #define INQ_DATA_SIZE 36
1570
1571 /*
1572 * Inquiry mailbox IOCB packet definition.
1573 */
1574 typedef struct {
1575 union {
1576 cmd_a64_entry_t cmd;
1577 sts_entry_t rsp;
1578 struct cmd_type_7 cmd24;
1579 struct sts_entry_24xx rsp24;
1580 } p;
1581 uint8_t inq[INQ_DATA_SIZE];
1582 } inq_cmd_rsp_t;
1583
1584 /*
1585 * Report LUN command structure.
1586 */
1587 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1588
1589 typedef struct {
1590 uint32_t len;
1591 uint32_t rsrv;
1592 } rpt_hdr_t;
1593
1594 typedef struct {
1595 struct {
1596 uint8_t b : 6;
1597 uint8_t address_method : 2;
1598 } msb;
1599 uint8_t lsb;
1600 uint8_t unused[6];
1601 } rpt_lun_t;
1602
1603 typedef struct {
1604 rpt_hdr_t hdr;
1605 rpt_lun_t lst[MAX_LUNS];
1606 } rpt_lun_lst_t;
1607
1608 /*
1609 * Report Lun mailbox IOCB packet definition.
1610 */
1611 typedef struct {
1612 union {
1613 cmd_a64_entry_t cmd;
1614 sts_entry_t rsp;
1615 struct cmd_type_7 cmd24;
1616 struct sts_entry_24xx rsp24;
1617 } p;
1618 rpt_lun_lst_t list;
1619 } rpt_lun_cmd_rsp_t;
1620
1621
1622 /*
1623 * Fibre channel port type.
1624 */
1625 typedef enum {
1626 FCT_UNKNOWN,
1627 FCT_RSCN,
1628 FCT_SWITCH,
1629 FCT_BROADCAST,
1630 FCT_INITIATOR,
1631 FCT_TARGET
1632 } fc_port_type_t;
1633
1634 /*
1635 * Fibre channel port structure.
1636 */
1637 typedef struct fc_port {
1638 struct list_head list;
1639 struct scsi_qla_host *ha;
1640 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1641
1642 uint8_t node_name[WWN_SIZE];
1643 uint8_t port_name[WWN_SIZE];
1644 port_id_t d_id;
1645 uint16_t loop_id;
1646 uint16_t old_loop_id;
1647
1648 fc_port_type_t port_type;
1649
1650 atomic_t state;
1651 uint32_t flags;
1652
1653 unsigned int os_target_id;
1654
1655 uint16_t iodesc_idx_sent;
1656
1657 int port_login_retry_count;
1658 int login_retry;
1659 atomic_t port_down_timer;
1660
1661 uint8_t device_type;
1662 uint8_t unused;
1663
1664 uint8_t mp_byte; /* multi-path byte (not used) */
1665 uint8_t cur_path; /* current path id */
1666
1667 struct fc_rport *rport;
1668 u32 supported_classes;
1669 struct work_struct rport_add_work;
1670 struct work_struct rport_del_work;
1671 } fc_port_t;
1672
1673 /*
1674 * Fibre channel port/lun states.
1675 */
1676 #define FCS_UNCONFIGURED 1
1677 #define FCS_DEVICE_DEAD 2
1678 #define FCS_DEVICE_LOST 3
1679 #define FCS_ONLINE 4
1680 #define FCS_NOT_SUPPORTED 5
1681 #define FCS_FAILOVER 6
1682 #define FCS_FAILOVER_FAILED 7
1683
1684 /*
1685 * FC port flags.
1686 */
1687 #define FCF_FABRIC_DEVICE BIT_0
1688 #define FCF_LOGIN_NEEDED BIT_1
1689 #define FCF_FO_MASKED BIT_2
1690 #define FCF_FAILOVER_NEEDED BIT_3
1691 #define FCF_RESET_NEEDED BIT_4
1692 #define FCF_PERSISTENT_BOUND BIT_5
1693 #define FCF_TAPE_PRESENT BIT_6
1694 #define FCF_FARP_DONE BIT_7
1695 #define FCF_FARP_FAILED BIT_8
1696 #define FCF_FARP_REPLY_NEEDED BIT_9
1697 #define FCF_AUTH_REQ BIT_10
1698 #define FCF_SEND_AUTH_REQ BIT_11
1699 #define FCF_RECEIVE_AUTH_REQ BIT_12
1700 #define FCF_AUTH_SUCCESS BIT_13
1701 #define FCF_RLC_SUPPORT BIT_14
1702 #define FCF_CONFIG BIT_15 /* Needed? */
1703 #define FCF_RESCAN_NEEDED BIT_16
1704 #define FCF_XP_DEVICE BIT_17
1705 #define FCF_MSA_DEVICE BIT_18
1706 #define FCF_EVA_DEVICE BIT_19
1707 #define FCF_MSA_PORT_ACTIVE BIT_20
1708 #define FCF_FAILBACK_DISABLE BIT_21
1709 #define FCF_FAILOVER_DISABLE BIT_22
1710 #define FCF_DSXXX_DEVICE BIT_23
1711 #define FCF_AA_EVA_DEVICE BIT_24
1712 #define FCF_AA_MSA_DEVICE BIT_25
1713
1714 /* No loop ID flag. */
1715 #define FC_NO_LOOP_ID 0x1000
1716
1717 /*
1718 * FC-CT interface
1719 *
1720 * NOTE: All structures are big-endian in form.
1721 */
1722
1723 #define CT_REJECT_RESPONSE 0x8001
1724 #define CT_ACCEPT_RESPONSE 0x8002
1725 #define CT_REASON_CANNOT_PERFORM 0x09
1726 #define CT_EXPL_ALREADY_REGISTERED 0x10
1727
1728 #define NS_N_PORT_TYPE 0x01
1729 #define NS_NL_PORT_TYPE 0x02
1730 #define NS_NX_PORT_TYPE 0x7F
1731
1732 #define GA_NXT_CMD 0x100
1733 #define GA_NXT_REQ_SIZE (16 + 4)
1734 #define GA_NXT_RSP_SIZE (16 + 620)
1735
1736 #define GID_PT_CMD 0x1A1
1737 #define GID_PT_REQ_SIZE (16 + 4)
1738 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1739
1740 #define GPN_ID_CMD 0x112
1741 #define GPN_ID_REQ_SIZE (16 + 4)
1742 #define GPN_ID_RSP_SIZE (16 + 8)
1743
1744 #define GNN_ID_CMD 0x113
1745 #define GNN_ID_REQ_SIZE (16 + 4)
1746 #define GNN_ID_RSP_SIZE (16 + 8)
1747
1748 #define GFT_ID_CMD 0x117
1749 #define GFT_ID_REQ_SIZE (16 + 4)
1750 #define GFT_ID_RSP_SIZE (16 + 32)
1751
1752 #define RFT_ID_CMD 0x217
1753 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1754 #define RFT_ID_RSP_SIZE 16
1755
1756 #define RFF_ID_CMD 0x21F
1757 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1758 #define RFF_ID_RSP_SIZE 16
1759
1760 #define RNN_ID_CMD 0x213
1761 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1762 #define RNN_ID_RSP_SIZE 16
1763
1764 #define RSNN_NN_CMD 0x239
1765 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1766 #define RSNN_NN_RSP_SIZE 16
1767
1768 /*
1769 * HBA attribute types.
1770 */
1771 #define FDMI_HBA_ATTR_COUNT 9
1772 #define FDMI_HBA_NODE_NAME 1
1773 #define FDMI_HBA_MANUFACTURER 2
1774 #define FDMI_HBA_SERIAL_NUMBER 3
1775 #define FDMI_HBA_MODEL 4
1776 #define FDMI_HBA_MODEL_DESCRIPTION 5
1777 #define FDMI_HBA_HARDWARE_VERSION 6
1778 #define FDMI_HBA_DRIVER_VERSION 7
1779 #define FDMI_HBA_OPTION_ROM_VERSION 8
1780 #define FDMI_HBA_FIRMWARE_VERSION 9
1781 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1782 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1783
1784 struct ct_fdmi_hba_attr {
1785 uint16_t type;
1786 uint16_t len;
1787 union {
1788 uint8_t node_name[WWN_SIZE];
1789 uint8_t manufacturer[32];
1790 uint8_t serial_num[8];
1791 uint8_t model[16];
1792 uint8_t model_desc[80];
1793 uint8_t hw_version[16];
1794 uint8_t driver_version[32];
1795 uint8_t orom_version[16];
1796 uint8_t fw_version[16];
1797 uint8_t os_version[128];
1798 uint8_t max_ct_len[4];
1799 } a;
1800 };
1801
1802 struct ct_fdmi_hba_attributes {
1803 uint32_t count;
1804 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1805 };
1806
1807 /*
1808 * Port attribute types.
1809 */
1810 #define FDMI_PORT_ATTR_COUNT 5
1811 #define FDMI_PORT_FC4_TYPES 1
1812 #define FDMI_PORT_SUPPORT_SPEED 2
1813 #define FDMI_PORT_CURRENT_SPEED 3
1814 #define FDMI_PORT_MAX_FRAME_SIZE 4
1815 #define FDMI_PORT_OS_DEVICE_NAME 5
1816 #define FDMI_PORT_HOST_NAME 6
1817
1818 struct ct_fdmi_port_attr {
1819 uint16_t type;
1820 uint16_t len;
1821 union {
1822 uint8_t fc4_types[32];
1823 uint32_t sup_speed;
1824 uint32_t cur_speed;
1825 uint32_t max_frame_size;
1826 uint8_t os_dev_name[32];
1827 uint8_t host_name[32];
1828 } a;
1829 };
1830
1831 /*
1832 * Port Attribute Block.
1833 */
1834 struct ct_fdmi_port_attributes {
1835 uint32_t count;
1836 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1837 };
1838
1839 /* FDMI definitions. */
1840 #define GRHL_CMD 0x100
1841 #define GHAT_CMD 0x101
1842 #define GRPL_CMD 0x102
1843 #define GPAT_CMD 0x110
1844
1845 #define RHBA_CMD 0x200
1846 #define RHBA_RSP_SIZE 16
1847
1848 #define RHAT_CMD 0x201
1849 #define RPRT_CMD 0x210
1850
1851 #define RPA_CMD 0x211
1852 #define RPA_RSP_SIZE 16
1853
1854 #define DHBA_CMD 0x300
1855 #define DHBA_REQ_SIZE (16 + 8)
1856 #define DHBA_RSP_SIZE 16
1857
1858 #define DHAT_CMD 0x301
1859 #define DPRT_CMD 0x310
1860 #define DPA_CMD 0x311
1861
1862 /* CT command header -- request/response common fields */
1863 struct ct_cmd_hdr {
1864 uint8_t revision;
1865 uint8_t in_id[3];
1866 uint8_t gs_type;
1867 uint8_t gs_subtype;
1868 uint8_t options;
1869 uint8_t reserved;
1870 };
1871
1872 /* CT command request */
1873 struct ct_sns_req {
1874 struct ct_cmd_hdr header;
1875 uint16_t command;
1876 uint16_t max_rsp_size;
1877 uint8_t fragment_id;
1878 uint8_t reserved[3];
1879
1880 union {
1881 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1882 struct {
1883 uint8_t reserved;
1884 uint8_t port_id[3];
1885 } port_id;
1886
1887 struct {
1888 uint8_t port_type;
1889 uint8_t domain;
1890 uint8_t area;
1891 uint8_t reserved;
1892 } gid_pt;
1893
1894 struct {
1895 uint8_t reserved;
1896 uint8_t port_id[3];
1897 uint8_t fc4_types[32];
1898 } rft_id;
1899
1900 struct {
1901 uint8_t reserved;
1902 uint8_t port_id[3];
1903 uint16_t reserved2;
1904 uint8_t fc4_feature;
1905 uint8_t fc4_type;
1906 } rff_id;
1907
1908 struct {
1909 uint8_t reserved;
1910 uint8_t port_id[3];
1911 uint8_t node_name[8];
1912 } rnn_id;
1913
1914 struct {
1915 uint8_t node_name[8];
1916 uint8_t name_len;
1917 uint8_t sym_node_name[255];
1918 } rsnn_nn;
1919
1920 struct {
1921 uint8_t hba_indentifier[8];
1922 } ghat;
1923
1924 struct {
1925 uint8_t hba_identifier[8];
1926 uint32_t entry_count;
1927 uint8_t port_name[8];
1928 struct ct_fdmi_hba_attributes attrs;
1929 } rhba;
1930
1931 struct {
1932 uint8_t hba_identifier[8];
1933 struct ct_fdmi_hba_attributes attrs;
1934 } rhat;
1935
1936 struct {
1937 uint8_t port_name[8];
1938 struct ct_fdmi_port_attributes attrs;
1939 } rpa;
1940
1941 struct {
1942 uint8_t port_name[8];
1943 } dhba;
1944
1945 struct {
1946 uint8_t port_name[8];
1947 } dhat;
1948
1949 struct {
1950 uint8_t port_name[8];
1951 } dprt;
1952
1953 struct {
1954 uint8_t port_name[8];
1955 } dpa;
1956 } req;
1957 };
1958
1959 /* CT command response header */
1960 struct ct_rsp_hdr {
1961 struct ct_cmd_hdr header;
1962 uint16_t response;
1963 uint16_t residual;
1964 uint8_t fragment_id;
1965 uint8_t reason_code;
1966 uint8_t explanation_code;
1967 uint8_t vendor_unique;
1968 };
1969
1970 struct ct_sns_gid_pt_data {
1971 uint8_t control_byte;
1972 uint8_t port_id[3];
1973 };
1974
1975 struct ct_sns_rsp {
1976 struct ct_rsp_hdr header;
1977
1978 union {
1979 struct {
1980 uint8_t port_type;
1981 uint8_t port_id[3];
1982 uint8_t port_name[8];
1983 uint8_t sym_port_name_len;
1984 uint8_t sym_port_name[255];
1985 uint8_t node_name[8];
1986 uint8_t sym_node_name_len;
1987 uint8_t sym_node_name[255];
1988 uint8_t init_proc_assoc[8];
1989 uint8_t node_ip_addr[16];
1990 uint8_t class_of_service[4];
1991 uint8_t fc4_types[32];
1992 uint8_t ip_address[16];
1993 uint8_t fabric_port_name[8];
1994 uint8_t reserved;
1995 uint8_t hard_address[3];
1996 } ga_nxt;
1997
1998 struct {
1999 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2000 } gid_pt;
2001
2002 struct {
2003 uint8_t port_name[8];
2004 } gpn_id;
2005
2006 struct {
2007 uint8_t node_name[8];
2008 } gnn_id;
2009
2010 struct {
2011 uint8_t fc4_types[32];
2012 } gft_id;
2013
2014 struct {
2015 uint32_t entry_count;
2016 uint8_t port_name[8];
2017 struct ct_fdmi_hba_attributes attrs;
2018 } ghat;
2019 } rsp;
2020 };
2021
2022 struct ct_sns_pkt {
2023 union {
2024 struct ct_sns_req req;
2025 struct ct_sns_rsp rsp;
2026 } p;
2027 };
2028
2029 /*
2030 * SNS command structures -- for 2200 compatability.
2031 */
2032 #define RFT_ID_SNS_SCMD_LEN 22
2033 #define RFT_ID_SNS_CMD_SIZE 60
2034 #define RFT_ID_SNS_DATA_SIZE 16
2035
2036 #define RNN_ID_SNS_SCMD_LEN 10
2037 #define RNN_ID_SNS_CMD_SIZE 36
2038 #define RNN_ID_SNS_DATA_SIZE 16
2039
2040 #define GA_NXT_SNS_SCMD_LEN 6
2041 #define GA_NXT_SNS_CMD_SIZE 28
2042 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2043
2044 #define GID_PT_SNS_SCMD_LEN 6
2045 #define GID_PT_SNS_CMD_SIZE 28
2046 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2047
2048 #define GPN_ID_SNS_SCMD_LEN 6
2049 #define GPN_ID_SNS_CMD_SIZE 28
2050 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2051
2052 #define GNN_ID_SNS_SCMD_LEN 6
2053 #define GNN_ID_SNS_CMD_SIZE 28
2054 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2055
2056 struct sns_cmd_pkt {
2057 union {
2058 struct {
2059 uint16_t buffer_length;
2060 uint16_t reserved_1;
2061 uint32_t buffer_address[2];
2062 uint16_t subcommand_length;
2063 uint16_t reserved_2;
2064 uint16_t subcommand;
2065 uint16_t size;
2066 uint32_t reserved_3;
2067 uint8_t param[36];
2068 } cmd;
2069
2070 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2071 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2072 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2073 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2074 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2075 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2076 } p;
2077 };
2078
2079 /* IO descriptors */
2080 #define MAX_IO_DESCRIPTORS 32
2081
2082 #define ABORT_IOCB_CB 0
2083 #define ADISC_PORT_IOCB_CB 1
2084 #define LOGOUT_PORT_IOCB_CB 2
2085 #define LOGIN_PORT_IOCB_CB 3
2086 #define LAST_IOCB_CB 4
2087
2088 #define IODESC_INVALID_INDEX 0xFFFF
2089 #define IODESC_ADISC_NEEDED 0xFFFE
2090 #define IODESC_LOGIN_NEEDED 0xFFFD
2091
2092 struct io_descriptor {
2093 uint16_t used:1;
2094 uint16_t idx:11;
2095 uint16_t cb_idx:4;
2096
2097 struct timer_list timer;
2098
2099 struct scsi_qla_host *ha;
2100
2101 port_id_t d_id;
2102 fc_port_t *remote_fcport;
2103
2104 uint32_t signature;
2105 };
2106
2107 struct qla_fw_info {
2108 unsigned short addressing; /* addressing method used to load fw */
2109 #define FW_INFO_ADDR_NORMAL 0
2110 #define FW_INFO_ADDR_EXTENDED 1
2111 #define FW_INFO_ADDR_NOMORE 0xffff
2112 unsigned short *fwcode; /* pointer to FW array */
2113 unsigned short *fwlen; /* number of words in array */
2114 unsigned short *fwstart; /* start address for F/W */
2115 unsigned long *lfwstart; /* start address (long) for F/W */
2116 };
2117
2118 struct qla_board_info {
2119 char *drv_name;
2120
2121 char isp_name[8];
2122 struct qla_fw_info *fw_info;
2123 char *fw_fname;
2124 struct scsi_host_template *sht;
2125 };
2126
2127 /* Return data from MBC_GET_ID_LIST call. */
2128 struct gid_list_info {
2129 uint8_t al_pa;
2130 uint8_t area;
2131 uint8_t domain;
2132 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2133 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2134 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2135 };
2136 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2137
2138 /*
2139 * ISP operations
2140 */
2141 struct isp_operations {
2142
2143 int (*pci_config) (struct scsi_qla_host *);
2144 void (*reset_chip) (struct scsi_qla_host *);
2145 int (*chip_diag) (struct scsi_qla_host *);
2146 void (*config_rings) (struct scsi_qla_host *);
2147 void (*reset_adapter) (struct scsi_qla_host *);
2148 int (*nvram_config) (struct scsi_qla_host *);
2149 void (*update_fw_options) (struct scsi_qla_host *);
2150 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2151
2152 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2153 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2154
2155 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2156 void (*enable_intrs) (struct scsi_qla_host *);
2157 void (*disable_intrs) (struct scsi_qla_host *);
2158
2159 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2160 int (*abort_target) (struct fc_port *);
2161 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2162 uint8_t, uint8_t, uint16_t *, uint8_t);
2163 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2164 uint8_t, uint8_t);
2165
2166 uint16_t (*calc_req_entries) (uint16_t);
2167 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2168 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2169 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2170 uint32_t);
2171
2172 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2173 uint32_t, uint32_t);
2174 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2175 uint32_t);
2176
2177 void (*fw_dump) (struct scsi_qla_host *, int);
2178 void (*ascii_fw_dump) (struct scsi_qla_host *);
2179 };
2180
2181 /*
2182 * Linux Host Adapter structure
2183 */
2184 typedef struct scsi_qla_host {
2185 struct list_head list;
2186
2187 /* Commonly used flags and state information. */
2188 struct Scsi_Host *host;
2189 struct pci_dev *pdev;
2190
2191 unsigned long host_no;
2192 unsigned long instance;
2193
2194 volatile struct {
2195 uint32_t init_done :1;
2196 uint32_t online :1;
2197 uint32_t mbox_int :1;
2198 uint32_t mbox_busy :1;
2199 uint32_t rscn_queue_overflow :1;
2200 uint32_t reset_active :1;
2201
2202 uint32_t management_server_logged_in :1;
2203 uint32_t process_response_queue :1;
2204
2205 uint32_t disable_risc_code_load :1;
2206 uint32_t enable_64bit_addressing :1;
2207 uint32_t enable_lip_reset :1;
2208 uint32_t enable_lip_full_login :1;
2209 uint32_t enable_target_reset :1;
2210 uint32_t enable_led_scheme :1;
2211 uint32_t msi_enabled :1;
2212 uint32_t msix_enabled :1;
2213 } flags;
2214
2215 atomic_t loop_state;
2216 #define LOOP_TIMEOUT 1
2217 #define LOOP_DOWN 2
2218 #define LOOP_UP 3
2219 #define LOOP_UPDATE 4
2220 #define LOOP_READY 5
2221 #define LOOP_DEAD 6
2222
2223 unsigned long dpc_flags;
2224 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2225 #define RESET_ACTIVE 1
2226 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2227 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2228 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2229 #define LOOP_RESYNC_ACTIVE 5
2230 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2231 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2232 #define MAILBOX_RETRY 8
2233 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2234 #define FAILOVER_EVENT_NEEDED 10
2235 #define FAILOVER_EVENT 11
2236 #define FAILOVER_NEEDED 12
2237 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2238 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2239 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2240 #define ABORT_QUEUES_NEEDED 16
2241 #define RELOGIN_NEEDED 17
2242 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2243 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2244 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2245 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2246 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2247 #define IOCTL_ERROR_RECOVERY 23
2248 #define LOOP_RESET_NEEDED 24
2249 #define BEACON_BLINK_NEEDED 25
2250 #define REGISTER_FDMI_NEEDED 26
2251
2252 uint32_t device_flags;
2253 #define DFLG_LOCAL_DEVICES BIT_0
2254 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2255 #define DFLG_FABRIC_DEVICES BIT_2
2256 #define SWITCH_FOUND BIT_3
2257 #define DFLG_NO_CABLE BIT_4
2258
2259 /* SRB cache. */
2260 #define SRB_MIN_REQ 128
2261 mempool_t *srb_mempool;
2262
2263 /* This spinlock is used to protect "io transactions", you must
2264 * aquire it before doing any IO to the card, eg with RD_REG*() and
2265 * WRT_REG*() for the duration of your entire commandtransaction.
2266 *
2267 * This spinlock is of lower priority than the io request lock.
2268 */
2269
2270 spinlock_t hardware_lock ____cacheline_aligned;
2271
2272 device_reg_t __iomem *iobase; /* Base I/O address */
2273 unsigned long pio_address;
2274 unsigned long pio_length;
2275 #define MIN_IOBASE_LEN 0x100
2276
2277 /* ISP ring lock, rings, and indexes */
2278 dma_addr_t request_dma; /* Physical address. */
2279 request_t *request_ring; /* Base virtual address */
2280 request_t *request_ring_ptr; /* Current address. */
2281 uint16_t req_ring_index; /* Current index. */
2282 uint16_t req_q_cnt; /* Number of available entries. */
2283 uint16_t request_q_length;
2284
2285 dma_addr_t response_dma; /* Physical address. */
2286 response_t *response_ring; /* Base virtual address */
2287 response_t *response_ring_ptr; /* Current address. */
2288 uint16_t rsp_ring_index; /* Current index. */
2289 uint16_t response_q_length;
2290
2291 struct isp_operations isp_ops;
2292
2293 /* Outstandings ISP commands. */
2294 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2295 uint32_t current_outstanding_cmd;
2296 srb_t *status_srb; /* Status continuation entry. */
2297
2298 uint16_t revision;
2299 uint8_t ports;
2300
2301 /* ISP configuration data. */
2302 uint16_t loop_id; /* Host adapter loop id */
2303 uint16_t fb_rev;
2304
2305 port_id_t d_id; /* Host adapter port id */
2306 uint16_t max_public_loop_ids;
2307 uint16_t min_external_loopid; /* First external loop Id */
2308
2309 uint16_t link_data_rate; /* F/W operating speed */
2310
2311 uint8_t current_topology;
2312 uint8_t prev_topology;
2313 #define ISP_CFG_NL 1
2314 #define ISP_CFG_N 2
2315 #define ISP_CFG_FL 4
2316 #define ISP_CFG_F 8
2317
2318 uint8_t operating_mode; /* F/W operating mode */
2319 #define LOOP 0
2320 #define P2P 1
2321 #define LOOP_P2P 2
2322 #define P2P_LOOP 3
2323
2324 uint8_t marker_needed;
2325
2326 uint8_t interrupts_on;
2327
2328 /* HBA serial number */
2329 uint8_t serial0;
2330 uint8_t serial1;
2331 uint8_t serial2;
2332
2333 /* NVRAM configuration data */
2334 uint16_t nvram_size;
2335 uint16_t nvram_base;
2336
2337 uint16_t loop_reset_delay;
2338 uint8_t retry_count;
2339 uint8_t login_timeout;
2340 uint16_t r_a_tov;
2341 int port_down_retry_count;
2342 uint8_t mbx_count;
2343 uint16_t last_loop_id;
2344 uint16_t mgmt_svr_loop_id;
2345
2346 uint32_t login_retry_count;
2347
2348 /* Fibre Channel Device List. */
2349 struct list_head fcports;
2350 struct list_head rscn_fcports;
2351
2352 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2353 uint16_t iodesc_signature;
2354
2355 /* RSCN queue. */
2356 uint32_t rscn_queue[MAX_RSCN_COUNT];
2357 uint8_t rscn_in_ptr;
2358 uint8_t rscn_out_ptr;
2359
2360 /* SNS command interfaces. */
2361 ms_iocb_entry_t *ms_iocb;
2362 dma_addr_t ms_iocb_dma;
2363 struct ct_sns_pkt *ct_sns;
2364 dma_addr_t ct_sns_dma;
2365 /* SNS command interfaces for 2200. */
2366 struct sns_cmd_pkt *sns_cmd;
2367 dma_addr_t sns_cmd_dma;
2368
2369 pid_t dpc_pid;
2370 int dpc_should_die;
2371 struct completion dpc_inited;
2372 struct completion dpc_exited;
2373 struct semaphore *dpc_wait;
2374 uint8_t dpc_active; /* DPC routine is active */
2375
2376 /* Timeout timers. */
2377 uint8_t loop_down_abort_time; /* port down timer */
2378 atomic_t loop_down_timer; /* loop down timer */
2379 uint8_t link_down_timeout; /* link down timeout */
2380
2381 uint32_t timer_active;
2382 struct timer_list timer;
2383
2384 dma_addr_t gid_list_dma;
2385 struct gid_list_info *gid_list;
2386 int gid_list_info_size;
2387
2388 dma_addr_t rlc_rsp_dma;
2389 rpt_lun_cmd_rsp_t *rlc_rsp;
2390
2391 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2392 #define DMA_POOL_SIZE 256
2393 struct dma_pool *s_dma_pool;
2394
2395 dma_addr_t init_cb_dma;
2396 init_cb_t *init_cb;
2397 int init_cb_size;
2398
2399 dma_addr_t iodesc_pd_dma;
2400 port_database_t *iodesc_pd;
2401
2402 /* These are used by mailbox operations. */
2403 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2404
2405 mbx_cmd_t *mcp;
2406 unsigned long mbx_cmd_flags;
2407 #define MBX_INTERRUPT 1
2408 #define MBX_INTR_WAIT 2
2409 #define MBX_UPDATE_FLASH_ACTIVE 3
2410
2411 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2412
2413 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2414 struct semaphore mbx_intr_sem; /* Used for completion notification */
2415
2416 uint32_t mbx_flags;
2417 #define MBX_IN_PROGRESS BIT_0
2418 #define MBX_BUSY BIT_1 /* Got the Access */
2419 #define MBX_SLEEPING_ON_SEM BIT_2
2420 #define MBX_POLLING_FOR_COMP BIT_3
2421 #define MBX_COMPLETED BIT_4
2422 #define MBX_TIMEDOUT BIT_5
2423 #define MBX_ACCESS_TIMEDOUT BIT_6
2424
2425 mbx_cmd_t mc;
2426
2427 /* Basic firmware related information. */
2428 struct qla_board_info *brd_info;
2429 uint16_t fw_major_version;
2430 uint16_t fw_minor_version;
2431 uint16_t fw_subminor_version;
2432 uint16_t fw_attributes;
2433 uint32_t fw_memory_size;
2434 uint32_t fw_transfer_size;
2435
2436 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2437 uint8_t fw_seriallink_options[4];
2438 uint16_t fw_seriallink_options24[4];
2439
2440 /* Firmware dump information. */
2441 void *fw_dump;
2442 int fw_dump_order;
2443 int fw_dump_reading;
2444 char *fw_dump_buffer;
2445 int fw_dump_buffer_len;
2446
2447 int fw_dumped;
2448 void *fw_dump24;
2449 int fw_dump24_len;
2450
2451 uint8_t host_str[16];
2452 uint32_t pci_attr;
2453
2454 uint16_t product_id[4];
2455
2456 uint8_t model_number[16+1];
2457 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2458 char *model_desc;
2459 uint8_t adapter_id[16+1];
2460
2461 uint8_t *node_name;
2462 uint8_t *port_name;
2463 uint32_t isp_abort_cnt;
2464
2465 /* Needed for BEACON */
2466 uint16_t beacon_blink_led;
2467 uint16_t beacon_green_on;
2468
2469 uint16_t zio_mode;
2470 uint16_t zio_timer;
2471 } scsi_qla_host_t;
2472
2473
2474 /*
2475 * Macros to help code, maintain, etc.
2476 */
2477 #define LOOP_TRANSITION(ha) \
2478 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2479 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2480
2481 #define LOOP_NOT_READY(ha) \
2482 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2483 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2484 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2485 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2486 atomic_read(&ha->loop_state) == LOOP_DOWN)
2487
2488 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2489
2490 #define TGT_Q(ha, t) (ha->otgt[t])
2491
2492 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2493
2494 #define qla_printk(level, ha, format, arg...) \
2495 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2496
2497 /*
2498 * qla2x00 local function return status codes
2499 */
2500 #define MBS_MASK 0x3fff
2501
2502 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2503 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2504 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2505 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2506 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2507 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2508 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2509 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2510 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2511 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2512
2513 #define QLA_FUNCTION_TIMEOUT 0x100
2514 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2515 #define QLA_FUNCTION_FAILED 0x102
2516 #define QLA_MEMORY_ALLOC_FAILED 0x103
2517 #define QLA_LOCK_TIMEOUT 0x104
2518 #define QLA_ABORTED 0x105
2519 #define QLA_SUSPENDED 0x106
2520 #define QLA_BUSY 0x107
2521 #define QLA_RSCNS_HANDLED 0x108
2522 #define QLA_ALREADY_REGISTERED 0x109
2523
2524 /*
2525 * Stat info for all adpaters
2526 */
2527 struct _qla2x00stats {
2528 unsigned long mboxtout; /* mailbox timeouts */
2529 unsigned long mboxerr; /* mailbox errors */
2530 unsigned long ispAbort; /* ISP aborts */
2531 unsigned long debugNo;
2532 unsigned long loop_resync;
2533 unsigned long outarray_full;
2534 unsigned long retry_q_cnt;
2535 };
2536
2537 #define NVRAM_DELAY() udelay(10)
2538
2539 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2540
2541 /*
2542 * Flash support definitions
2543 */
2544 #define FLASH_IMAGE_SIZE 131072
2545
2546 #include "qla_gbl.h"
2547 #include "qla_dbg.h"
2548 #include "qla_inline.h"
2549
2550 /*
2551 * String arrays
2552 */
2553 #define LINESIZE 256
2554 #define MAXARGS 26
2555
2556 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2557 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2558 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2559 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2560 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2561 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2562
2563 #endif
kernel source for telekom puls (alcatel/mediatek)