2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x0120 | 0x4b,0xba,0xfa |
15 * | Mailbox commands | 0x113e | 0x112c-0x112e |
17 * | Device Discovery | 0x2086 | 0x2020-0x2022 |
18 * | Queue Command and IO tracing | 0x302f | 0x3006,0x3008 |
19 * | | | 0x302d-0x302e |
20 * | DPC Thread | 0x401c | |
21 * | Async Events | 0x505d | 0x502b-0x502f |
22 * | | | 0x5047,0x5052 |
23 * | Timer Routines | 0x6011 | 0x600e-0x600f |
24 * | User Space Interactions | 0x709f | 0x7018,0x702e, |
25 * | | | 0x7039,0x7045, |
26 * | | | 0x7073-0x7075, |
28 * | Task Management | 0x803c | 0x8025-0x8026 |
29 * | | | 0x800b,0x8039 |
30 * | AER/EEH | 0x900f | |
31 * | Virtual Port | 0xa007 | |
32 * | ISP82XX Specific | 0xb054 | 0xb053 |
33 * | MultiQ | 0xc00c | |
35 * ----------------------------------------------------------------------
40 #include <linux/delay.h>
42 static uint32_t ql_dbg_offset
= 0x800;
45 qla2xxx_prep_dump(struct qla_hw_data
*ha
, struct qla2xxx_fw_dump
*fw_dump
)
47 fw_dump
->fw_major_version
= htonl(ha
->fw_major_version
);
48 fw_dump
->fw_minor_version
= htonl(ha
->fw_minor_version
);
49 fw_dump
->fw_subminor_version
= htonl(ha
->fw_subminor_version
);
50 fw_dump
->fw_attributes
= htonl(ha
->fw_attributes
);
52 fw_dump
->vendor
= htonl(ha
->pdev
->vendor
);
53 fw_dump
->device
= htonl(ha
->pdev
->device
);
54 fw_dump
->subsystem_vendor
= htonl(ha
->pdev
->subsystem_vendor
);
55 fw_dump
->subsystem_device
= htonl(ha
->pdev
->subsystem_device
);
59 qla2xxx_copy_queues(struct qla_hw_data
*ha
, void *ptr
)
61 struct req_que
*req
= ha
->req_q_map
[0];
62 struct rsp_que
*rsp
= ha
->rsp_q_map
[0];
64 memcpy(ptr
, req
->ring
, req
->length
*
68 ptr
+= req
->length
* sizeof(request_t
);
69 memcpy(ptr
, rsp
->ring
, rsp
->length
*
72 return ptr
+ (rsp
->length
* sizeof(response_t
));
76 qla24xx_dump_ram(struct qla_hw_data
*ha
, uint32_t addr
, uint32_t *ram
,
77 uint32_t ram_dwords
, void **nxt
)
80 uint32_t cnt
, stat
, timer
, dwords
, idx
;
82 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
83 dma_addr_t dump_dma
= ha
->gid_list_dma
;
84 uint32_t *dump
= (uint32_t *)ha
->gid_list
;
89 WRT_REG_WORD(®
->mailbox0
, MBC_DUMP_RISC_RAM_EXTENDED
);
90 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
92 dwords
= qla2x00_gid_list_size(ha
) / 4;
93 for (cnt
= 0; cnt
< ram_dwords
&& rval
== QLA_SUCCESS
;
94 cnt
+= dwords
, addr
+= dwords
) {
95 if (cnt
+ dwords
> ram_dwords
)
96 dwords
= ram_dwords
- cnt
;
98 WRT_REG_WORD(®
->mailbox1
, LSW(addr
));
99 WRT_REG_WORD(®
->mailbox8
, MSW(addr
));
101 WRT_REG_WORD(®
->mailbox2
, MSW(dump_dma
));
102 WRT_REG_WORD(®
->mailbox3
, LSW(dump_dma
));
103 WRT_REG_WORD(®
->mailbox6
, MSW(MSD(dump_dma
)));
104 WRT_REG_WORD(®
->mailbox7
, LSW(MSD(dump_dma
)));
106 WRT_REG_WORD(®
->mailbox4
, MSW(dwords
));
107 WRT_REG_WORD(®
->mailbox5
, LSW(dwords
));
108 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_HOST_INT
);
110 for (timer
= 6000000; timer
; timer
--) {
111 /* Check for pending interrupts. */
112 stat
= RD_REG_DWORD(®
->host_status
);
113 if (stat
& HSRX_RISC_INT
) {
116 if (stat
== 0x1 || stat
== 0x2 ||
117 stat
== 0x10 || stat
== 0x11) {
118 set_bit(MBX_INTERRUPT
,
121 mb0
= RD_REG_WORD(®
->mailbox0
);
123 WRT_REG_DWORD(®
->hccr
,
125 RD_REG_DWORD(®
->hccr
);
129 /* Clear this intr; it wasn't a mailbox intr */
130 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_INT
);
131 RD_REG_DWORD(®
->hccr
);
136 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
137 rval
= mb0
& MBS_MASK
;
138 for (idx
= 0; idx
< dwords
; idx
++)
139 ram
[cnt
+ idx
] = swab32(dump
[idx
]);
141 rval
= QLA_FUNCTION_FAILED
;
145 *nxt
= rval
== QLA_SUCCESS
? &ram
[cnt
]: NULL
;
150 qla24xx_dump_memory(struct qla_hw_data
*ha
, uint32_t *code_ram
,
151 uint32_t cram_size
, void **nxt
)
156 rval
= qla24xx_dump_ram(ha
, 0x20000, code_ram
, cram_size
/ 4, nxt
);
157 if (rval
!= QLA_SUCCESS
)
160 /* External Memory. */
161 return qla24xx_dump_ram(ha
, 0x100000, *nxt
,
162 ha
->fw_memory_size
- 0x100000 + 1, nxt
);
166 qla24xx_read_window(struct device_reg_24xx __iomem
*reg
, uint32_t iobase
,
167 uint32_t count
, uint32_t *buf
)
169 uint32_t __iomem
*dmp_reg
;
171 WRT_REG_DWORD(®
->iobase_addr
, iobase
);
172 dmp_reg
= ®
->iobase_window
;
174 *buf
++ = htonl(RD_REG_DWORD(dmp_reg
++));
180 qla24xx_pause_risc(struct device_reg_24xx __iomem
*reg
)
182 int rval
= QLA_SUCCESS
;
185 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_PAUSE
);
187 ((RD_REG_DWORD(®
->host_status
) & HSRX_RISC_PAUSED
) == 0) &&
188 rval
== QLA_SUCCESS
; cnt
--) {
192 rval
= QLA_FUNCTION_TIMEOUT
;
199 qla24xx_soft_reset(struct qla_hw_data
*ha
)
201 int rval
= QLA_SUCCESS
;
204 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
207 WRT_REG_DWORD(®
->ctrl_status
, CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
208 for (cnt
= 0; cnt
< 30000; cnt
++) {
209 if ((RD_REG_DWORD(®
->ctrl_status
) & CSRX_DMA_ACTIVE
) == 0)
215 WRT_REG_DWORD(®
->ctrl_status
,
216 CSRX_ISP_SOFT_RESET
|CSRX_DMA_SHUTDOWN
|MWB_4096_BYTES
);
217 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
220 /* Wait for firmware to complete NVRAM accesses. */
221 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
222 for (cnt
= 10000 ; cnt
&& mb0
; cnt
--) {
224 mb0
= (uint32_t) RD_REG_WORD(®
->mailbox0
);
228 /* Wait for soft-reset to complete. */
229 for (cnt
= 0; cnt
< 30000; cnt
++) {
230 if ((RD_REG_DWORD(®
->ctrl_status
) &
231 CSRX_ISP_SOFT_RESET
) == 0)
236 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_RESET
);
237 RD_REG_DWORD(®
->hccr
); /* PCI Posting. */
239 for (cnt
= 30000; RD_REG_WORD(®
->mailbox0
) != 0 &&
240 rval
== QLA_SUCCESS
; cnt
--) {
244 rval
= QLA_FUNCTION_TIMEOUT
;
251 qla2xxx_dump_ram(struct qla_hw_data
*ha
, uint32_t addr
, uint16_t *ram
,
252 uint32_t ram_words
, void **nxt
)
255 uint32_t cnt
, stat
, timer
, words
, idx
;
257 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
258 dma_addr_t dump_dma
= ha
->gid_list_dma
;
259 uint16_t *dump
= (uint16_t *)ha
->gid_list
;
264 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_DUMP_RISC_RAM_EXTENDED
);
265 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
267 words
= qla2x00_gid_list_size(ha
) / 2;
268 for (cnt
= 0; cnt
< ram_words
&& rval
== QLA_SUCCESS
;
269 cnt
+= words
, addr
+= words
) {
270 if (cnt
+ words
> ram_words
)
271 words
= ram_words
- cnt
;
273 WRT_MAILBOX_REG(ha
, reg
, 1, LSW(addr
));
274 WRT_MAILBOX_REG(ha
, reg
, 8, MSW(addr
));
276 WRT_MAILBOX_REG(ha
, reg
, 2, MSW(dump_dma
));
277 WRT_MAILBOX_REG(ha
, reg
, 3, LSW(dump_dma
));
278 WRT_MAILBOX_REG(ha
, reg
, 6, MSW(MSD(dump_dma
)));
279 WRT_MAILBOX_REG(ha
, reg
, 7, LSW(MSD(dump_dma
)));
281 WRT_MAILBOX_REG(ha
, reg
, 4, words
);
282 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
284 for (timer
= 6000000; timer
; timer
--) {
285 /* Check for pending interrupts. */
286 stat
= RD_REG_DWORD(®
->u
.isp2300
.host_status
);
287 if (stat
& HSR_RISC_INT
) {
290 if (stat
== 0x1 || stat
== 0x2) {
291 set_bit(MBX_INTERRUPT
,
294 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
296 /* Release mailbox registers. */
297 WRT_REG_WORD(®
->semaphore
, 0);
298 WRT_REG_WORD(®
->hccr
,
300 RD_REG_WORD(®
->hccr
);
302 } else if (stat
== 0x10 || stat
== 0x11) {
303 set_bit(MBX_INTERRUPT
,
306 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
308 WRT_REG_WORD(®
->hccr
,
310 RD_REG_WORD(®
->hccr
);
314 /* clear this intr; it wasn't a mailbox intr */
315 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
316 RD_REG_WORD(®
->hccr
);
321 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
322 rval
= mb0
& MBS_MASK
;
323 for (idx
= 0; idx
< words
; idx
++)
324 ram
[cnt
+ idx
] = swab16(dump
[idx
]);
326 rval
= QLA_FUNCTION_FAILED
;
330 *nxt
= rval
== QLA_SUCCESS
? &ram
[cnt
]: NULL
;
335 qla2xxx_read_window(struct device_reg_2xxx __iomem
*reg
, uint32_t count
,
338 uint16_t __iomem
*dmp_reg
= ®
->u
.isp2300
.fb_cmd
;
341 *buf
++ = htons(RD_REG_WORD(dmp_reg
++));
345 qla24xx_copy_eft(struct qla_hw_data
*ha
, void *ptr
)
350 memcpy(ptr
, ha
->eft
, ntohl(ha
->fw_dump
->eft_size
));
351 return ptr
+ ntohl(ha
->fw_dump
->eft_size
);
355 qla25xx_copy_fce(struct qla_hw_data
*ha
, void *ptr
, uint32_t **last_chain
)
359 struct qla2xxx_fce_chain
*fcec
= ptr
;
364 *last_chain
= &fcec
->type
;
365 fcec
->type
= __constant_htonl(DUMP_CHAIN_FCE
);
366 fcec
->chain_size
= htonl(sizeof(struct qla2xxx_fce_chain
) +
367 fce_calc_size(ha
->fce_bufs
));
368 fcec
->size
= htonl(fce_calc_size(ha
->fce_bufs
));
369 fcec
->addr_l
= htonl(LSD(ha
->fce_dma
));
370 fcec
->addr_h
= htonl(MSD(ha
->fce_dma
));
372 iter_reg
= fcec
->eregs
;
373 for (cnt
= 0; cnt
< 8; cnt
++)
374 *iter_reg
++ = htonl(ha
->fce_mb
[cnt
]);
376 memcpy(iter_reg
, ha
->fce
, ntohl(fcec
->size
));
378 return (char *)iter_reg
+ ntohl(fcec
->size
);
382 qla25xx_copy_mqueues(struct qla_hw_data
*ha
, void *ptr
, uint32_t **last_chain
)
384 struct qla2xxx_mqueue_chain
*q
;
385 struct qla2xxx_mqueue_header
*qh
;
394 for (que
= 1; que
< ha
->max_req_queues
; que
++) {
395 req
= ha
->req_q_map
[que
];
401 *last_chain
= &q
->type
;
402 q
->type
= __constant_htonl(DUMP_CHAIN_QUEUE
);
403 q
->chain_size
= htonl(
404 sizeof(struct qla2xxx_mqueue_chain
) +
405 sizeof(struct qla2xxx_mqueue_header
) +
406 (req
->length
* sizeof(request_t
)));
407 ptr
+= sizeof(struct qla2xxx_mqueue_chain
);
411 qh
->queue
= __constant_htonl(TYPE_REQUEST_QUEUE
);
412 qh
->number
= htonl(que
);
413 qh
->size
= htonl(req
->length
* sizeof(request_t
));
414 ptr
+= sizeof(struct qla2xxx_mqueue_header
);
417 memcpy(ptr
, req
->ring
, req
->length
* sizeof(request_t
));
418 ptr
+= req
->length
* sizeof(request_t
);
421 /* Response queues */
422 for (que
= 1; que
< ha
->max_rsp_queues
; que
++) {
423 rsp
= ha
->rsp_q_map
[que
];
429 *last_chain
= &q
->type
;
430 q
->type
= __constant_htonl(DUMP_CHAIN_QUEUE
);
431 q
->chain_size
= htonl(
432 sizeof(struct qla2xxx_mqueue_chain
) +
433 sizeof(struct qla2xxx_mqueue_header
) +
434 (rsp
->length
* sizeof(response_t
)));
435 ptr
+= sizeof(struct qla2xxx_mqueue_chain
);
439 qh
->queue
= __constant_htonl(TYPE_RESPONSE_QUEUE
);
440 qh
->number
= htonl(que
);
441 qh
->size
= htonl(rsp
->length
* sizeof(response_t
));
442 ptr
+= sizeof(struct qla2xxx_mqueue_header
);
445 memcpy(ptr
, rsp
->ring
, rsp
->length
* sizeof(response_t
));
446 ptr
+= rsp
->length
* sizeof(response_t
);
453 qla25xx_copy_mq(struct qla_hw_data
*ha
, void *ptr
, uint32_t **last_chain
)
455 uint32_t cnt
, que_idx
;
457 struct qla2xxx_mq_chain
*mq
= ptr
;
458 struct device_reg_25xxmq __iomem
*reg
;
460 if (!ha
->mqenable
|| IS_QLA83XX(ha
))
464 *last_chain
= &mq
->type
;
465 mq
->type
= __constant_htonl(DUMP_CHAIN_MQ
);
466 mq
->chain_size
= __constant_htonl(sizeof(struct qla2xxx_mq_chain
));
468 que_cnt
= ha
->max_req_queues
> ha
->max_rsp_queues
?
469 ha
->max_req_queues
: ha
->max_rsp_queues
;
470 mq
->count
= htonl(que_cnt
);
471 for (cnt
= 0; cnt
< que_cnt
; cnt
++) {
472 reg
= (struct device_reg_25xxmq
*) ((void *)
473 ha
->mqiobase
+ cnt
* QLA_QUE_PAGE
);
475 mq
->qregs
[que_idx
] = htonl(RD_REG_DWORD(®
->req_q_in
));
476 mq
->qregs
[que_idx
+1] = htonl(RD_REG_DWORD(®
->req_q_out
));
477 mq
->qregs
[que_idx
+2] = htonl(RD_REG_DWORD(®
->rsp_q_in
));
478 mq
->qregs
[que_idx
+3] = htonl(RD_REG_DWORD(®
->rsp_q_out
));
481 return ptr
+ sizeof(struct qla2xxx_mq_chain
);
485 qla2xxx_dump_post_process(scsi_qla_host_t
*vha
, int rval
)
487 struct qla_hw_data
*ha
= vha
->hw
;
489 if (rval
!= QLA_SUCCESS
) {
490 ql_log(ql_log_warn
, vha
, 0xd000,
491 "Failed to dump firmware (%x).\n", rval
);
494 ql_log(ql_log_info
, vha
, 0xd001,
495 "Firmware dump saved to temp buffer (%ld/%p).\n",
496 vha
->host_no
, ha
->fw_dump
);
498 qla2x00_post_uevent_work(vha
, QLA_UEVENT_CODE_FW_DUMP
);
503 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
505 * @hardware_locked: Called with the hardware_lock
508 qla2300_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
512 struct qla_hw_data
*ha
= vha
->hw
;
513 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
514 uint16_t __iomem
*dmp_reg
;
516 struct qla2300_fw_dump
*fw
;
518 struct scsi_qla_host
*base_vha
= pci_get_drvdata(ha
->pdev
);
522 if (!hardware_locked
)
523 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
526 ql_log(ql_log_warn
, vha
, 0xd002,
527 "No buffer available for dump.\n");
528 goto qla2300_fw_dump_failed
;
532 ql_log(ql_log_warn
, vha
, 0xd003,
533 "Firmware has been previously dumped (%p) "
534 "-- ignoring request.\n",
536 goto qla2300_fw_dump_failed
;
538 fw
= &ha
->fw_dump
->isp
.isp23
;
539 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
542 fw
->hccr
= htons(RD_REG_WORD(®
->hccr
));
545 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
546 if (IS_QLA2300(ha
)) {
548 (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
549 rval
== QLA_SUCCESS
; cnt
--) {
553 rval
= QLA_FUNCTION_TIMEOUT
;
556 RD_REG_WORD(®
->hccr
); /* PCI Posting. */
560 if (rval
== QLA_SUCCESS
) {
561 dmp_reg
= ®
->flash_address
;
562 for (cnt
= 0; cnt
< sizeof(fw
->pbiu_reg
) / 2; cnt
++)
563 fw
->pbiu_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
565 dmp_reg
= ®
->u
.isp2300
.req_q_in
;
566 for (cnt
= 0; cnt
< sizeof(fw
->risc_host_reg
) / 2; cnt
++)
567 fw
->risc_host_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
569 dmp_reg
= ®
->u
.isp2300
.mailbox0
;
570 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
571 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
573 WRT_REG_WORD(®
->ctrl_status
, 0x40);
574 qla2xxx_read_window(reg
, 32, fw
->resp_dma_reg
);
576 WRT_REG_WORD(®
->ctrl_status
, 0x50);
577 qla2xxx_read_window(reg
, 48, fw
->dma_reg
);
579 WRT_REG_WORD(®
->ctrl_status
, 0x00);
580 dmp_reg
= ®
->risc_hw
;
581 for (cnt
= 0; cnt
< sizeof(fw
->risc_hdw_reg
) / 2; cnt
++)
582 fw
->risc_hdw_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
584 WRT_REG_WORD(®
->pcr
, 0x2000);
585 qla2xxx_read_window(reg
, 16, fw
->risc_gp0_reg
);
587 WRT_REG_WORD(®
->pcr
, 0x2200);
588 qla2xxx_read_window(reg
, 16, fw
->risc_gp1_reg
);
590 WRT_REG_WORD(®
->pcr
, 0x2400);
591 qla2xxx_read_window(reg
, 16, fw
->risc_gp2_reg
);
593 WRT_REG_WORD(®
->pcr
, 0x2600);
594 qla2xxx_read_window(reg
, 16, fw
->risc_gp3_reg
);
596 WRT_REG_WORD(®
->pcr
, 0x2800);
597 qla2xxx_read_window(reg
, 16, fw
->risc_gp4_reg
);
599 WRT_REG_WORD(®
->pcr
, 0x2A00);
600 qla2xxx_read_window(reg
, 16, fw
->risc_gp5_reg
);
602 WRT_REG_WORD(®
->pcr
, 0x2C00);
603 qla2xxx_read_window(reg
, 16, fw
->risc_gp6_reg
);
605 WRT_REG_WORD(®
->pcr
, 0x2E00);
606 qla2xxx_read_window(reg
, 16, fw
->risc_gp7_reg
);
608 WRT_REG_WORD(®
->ctrl_status
, 0x10);
609 qla2xxx_read_window(reg
, 64, fw
->frame_buf_hdw_reg
);
611 WRT_REG_WORD(®
->ctrl_status
, 0x20);
612 qla2xxx_read_window(reg
, 64, fw
->fpm_b0_reg
);
614 WRT_REG_WORD(®
->ctrl_status
, 0x30);
615 qla2xxx_read_window(reg
, 64, fw
->fpm_b1_reg
);
618 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
619 for (cnt
= 0; cnt
< 30000; cnt
++) {
620 if ((RD_REG_WORD(®
->ctrl_status
) &
621 CSR_ISP_SOFT_RESET
) == 0)
628 if (!IS_QLA2300(ha
)) {
629 for (cnt
= 30000; RD_MAILBOX_REG(ha
, reg
, 0) != 0 &&
630 rval
== QLA_SUCCESS
; cnt
--) {
634 rval
= QLA_FUNCTION_TIMEOUT
;
639 if (rval
== QLA_SUCCESS
)
640 rval
= qla2xxx_dump_ram(ha
, 0x800, fw
->risc_ram
,
641 sizeof(fw
->risc_ram
) / 2, &nxt
);
643 /* Get stack SRAM. */
644 if (rval
== QLA_SUCCESS
)
645 rval
= qla2xxx_dump_ram(ha
, 0x10000, fw
->stack_ram
,
646 sizeof(fw
->stack_ram
) / 2, &nxt
);
649 if (rval
== QLA_SUCCESS
)
650 rval
= qla2xxx_dump_ram(ha
, 0x11000, fw
->data_ram
,
651 ha
->fw_memory_size
- 0x11000 + 1, &nxt
);
653 if (rval
== QLA_SUCCESS
)
654 qla2xxx_copy_queues(ha
, nxt
);
656 qla2xxx_dump_post_process(base_vha
, rval
);
658 qla2300_fw_dump_failed
:
659 if (!hardware_locked
)
660 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
664 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
666 * @hardware_locked: Called with the hardware_lock
669 qla2100_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
673 uint16_t risc_address
;
675 struct qla_hw_data
*ha
= vha
->hw
;
676 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
677 uint16_t __iomem
*dmp_reg
;
679 struct qla2100_fw_dump
*fw
;
680 struct scsi_qla_host
*base_vha
= pci_get_drvdata(ha
->pdev
);
686 if (!hardware_locked
)
687 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
690 ql_log(ql_log_warn
, vha
, 0xd004,
691 "No buffer available for dump.\n");
692 goto qla2100_fw_dump_failed
;
696 ql_log(ql_log_warn
, vha
, 0xd005,
697 "Firmware has been previously dumped (%p) "
698 "-- ignoring request.\n",
700 goto qla2100_fw_dump_failed
;
702 fw
= &ha
->fw_dump
->isp
.isp21
;
703 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
706 fw
->hccr
= htons(RD_REG_WORD(®
->hccr
));
709 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
710 for (cnt
= 30000; (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
711 rval
== QLA_SUCCESS
; cnt
--) {
715 rval
= QLA_FUNCTION_TIMEOUT
;
717 if (rval
== QLA_SUCCESS
) {
718 dmp_reg
= ®
->flash_address
;
719 for (cnt
= 0; cnt
< sizeof(fw
->pbiu_reg
) / 2; cnt
++)
720 fw
->pbiu_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
722 dmp_reg
= ®
->u
.isp2100
.mailbox0
;
723 for (cnt
= 0; cnt
< ha
->mbx_count
; cnt
++) {
725 dmp_reg
= ®
->u_end
.isp2200
.mailbox8
;
727 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
730 dmp_reg
= ®
->u
.isp2100
.unused_2
[0];
731 for (cnt
= 0; cnt
< sizeof(fw
->dma_reg
) / 2; cnt
++)
732 fw
->dma_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
734 WRT_REG_WORD(®
->ctrl_status
, 0x00);
735 dmp_reg
= ®
->risc_hw
;
736 for (cnt
= 0; cnt
< sizeof(fw
->risc_hdw_reg
) / 2; cnt
++)
737 fw
->risc_hdw_reg
[cnt
] = htons(RD_REG_WORD(dmp_reg
++));
739 WRT_REG_WORD(®
->pcr
, 0x2000);
740 qla2xxx_read_window(reg
, 16, fw
->risc_gp0_reg
);
742 WRT_REG_WORD(®
->pcr
, 0x2100);
743 qla2xxx_read_window(reg
, 16, fw
->risc_gp1_reg
);
745 WRT_REG_WORD(®
->pcr
, 0x2200);
746 qla2xxx_read_window(reg
, 16, fw
->risc_gp2_reg
);
748 WRT_REG_WORD(®
->pcr
, 0x2300);
749 qla2xxx_read_window(reg
, 16, fw
->risc_gp3_reg
);
751 WRT_REG_WORD(®
->pcr
, 0x2400);
752 qla2xxx_read_window(reg
, 16, fw
->risc_gp4_reg
);
754 WRT_REG_WORD(®
->pcr
, 0x2500);
755 qla2xxx_read_window(reg
, 16, fw
->risc_gp5_reg
);
757 WRT_REG_WORD(®
->pcr
, 0x2600);
758 qla2xxx_read_window(reg
, 16, fw
->risc_gp6_reg
);
760 WRT_REG_WORD(®
->pcr
, 0x2700);
761 qla2xxx_read_window(reg
, 16, fw
->risc_gp7_reg
);
763 WRT_REG_WORD(®
->ctrl_status
, 0x10);
764 qla2xxx_read_window(reg
, 16, fw
->frame_buf_hdw_reg
);
766 WRT_REG_WORD(®
->ctrl_status
, 0x20);
767 qla2xxx_read_window(reg
, 64, fw
->fpm_b0_reg
);
769 WRT_REG_WORD(®
->ctrl_status
, 0x30);
770 qla2xxx_read_window(reg
, 64, fw
->fpm_b1_reg
);
773 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
776 for (cnt
= 30000; RD_MAILBOX_REG(ha
, reg
, 0) != 0 &&
777 rval
== QLA_SUCCESS
; cnt
--) {
781 rval
= QLA_FUNCTION_TIMEOUT
;
785 if (rval
== QLA_SUCCESS
&& (IS_QLA2200(ha
) || (IS_QLA2100(ha
) &&
786 (RD_REG_WORD(®
->mctr
) & (BIT_1
| BIT_0
)) != 0))) {
788 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
790 (RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) == 0 &&
791 rval
== QLA_SUCCESS
; cnt
--) {
795 rval
= QLA_FUNCTION_TIMEOUT
;
797 if (rval
== QLA_SUCCESS
) {
798 /* Set memory configuration and timing. */
800 WRT_REG_WORD(®
->mctr
, 0xf1);
802 WRT_REG_WORD(®
->mctr
, 0xf2);
803 RD_REG_WORD(®
->mctr
); /* PCI Posting. */
806 WRT_REG_WORD(®
->hccr
, HCCR_RELEASE_RISC
);
810 if (rval
== QLA_SUCCESS
) {
812 risc_address
= 0x1000;
813 WRT_MAILBOX_REG(ha
, reg
, 0, MBC_READ_RAM_WORD
);
814 clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
);
816 for (cnt
= 0; cnt
< sizeof(fw
->risc_ram
) / 2 && rval
== QLA_SUCCESS
;
817 cnt
++, risc_address
++) {
818 WRT_MAILBOX_REG(ha
, reg
, 1, risc_address
);
819 WRT_REG_WORD(®
->hccr
, HCCR_SET_HOST_INT
);
821 for (timer
= 6000000; timer
!= 0; timer
--) {
822 /* Check for pending interrupts. */
823 if (RD_REG_WORD(®
->istatus
) & ISR_RISC_INT
) {
824 if (RD_REG_WORD(®
->semaphore
) & BIT_0
) {
825 set_bit(MBX_INTERRUPT
,
828 mb0
= RD_MAILBOX_REG(ha
, reg
, 0);
829 mb2
= RD_MAILBOX_REG(ha
, reg
, 2);
831 WRT_REG_WORD(®
->semaphore
, 0);
832 WRT_REG_WORD(®
->hccr
,
834 RD_REG_WORD(®
->hccr
);
837 WRT_REG_WORD(®
->hccr
, HCCR_CLR_RISC_INT
);
838 RD_REG_WORD(®
->hccr
);
843 if (test_and_clear_bit(MBX_INTERRUPT
, &ha
->mbx_cmd_flags
)) {
844 rval
= mb0
& MBS_MASK
;
845 fw
->risc_ram
[cnt
] = htons(mb2
);
847 rval
= QLA_FUNCTION_FAILED
;
851 if (rval
== QLA_SUCCESS
)
852 qla2xxx_copy_queues(ha
, &fw
->risc_ram
[cnt
]);
854 qla2xxx_dump_post_process(base_vha
, rval
);
856 qla2100_fw_dump_failed
:
857 if (!hardware_locked
)
858 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
862 qla24xx_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
866 uint32_t risc_address
;
867 struct qla_hw_data
*ha
= vha
->hw
;
868 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
869 uint32_t __iomem
*dmp_reg
;
871 uint16_t __iomem
*mbx_reg
;
873 struct qla24xx_fw_dump
*fw
;
874 uint32_t ext_mem_cnt
;
876 struct scsi_qla_host
*base_vha
= pci_get_drvdata(ha
->pdev
);
881 risc_address
= ext_mem_cnt
= 0;
884 if (!hardware_locked
)
885 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
888 ql_log(ql_log_warn
, vha
, 0xd006,
889 "No buffer available for dump.\n");
890 goto qla24xx_fw_dump_failed
;
894 ql_log(ql_log_warn
, vha
, 0xd007,
895 "Firmware has been previously dumped (%p) "
896 "-- ignoring request.\n",
898 goto qla24xx_fw_dump_failed
;
900 fw
= &ha
->fw_dump
->isp
.isp24
;
901 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
903 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
906 rval
= qla24xx_pause_risc(reg
);
907 if (rval
!= QLA_SUCCESS
)
908 goto qla24xx_fw_dump_failed_0
;
910 /* Host interface registers. */
911 dmp_reg
= ®
->flash_addr
;
912 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
913 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
915 /* Disable interrupts. */
916 WRT_REG_DWORD(®
->ictrl
, 0);
917 RD_REG_DWORD(®
->ictrl
);
919 /* Shadow registers. */
920 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
921 RD_REG_DWORD(®
->iobase_addr
);
922 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
923 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
925 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
926 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
928 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
929 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
931 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
932 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
934 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
935 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
937 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
938 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
940 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
941 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
943 /* Mailbox registers. */
944 mbx_reg
= ®
->mailbox0
;
945 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
946 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
948 /* Transfer sequence registers. */
949 iter_reg
= fw
->xseq_gp_reg
;
950 iter_reg
= qla24xx_read_window(reg
, 0xBF00, 16, iter_reg
);
951 iter_reg
= qla24xx_read_window(reg
, 0xBF10, 16, iter_reg
);
952 iter_reg
= qla24xx_read_window(reg
, 0xBF20, 16, iter_reg
);
953 iter_reg
= qla24xx_read_window(reg
, 0xBF30, 16, iter_reg
);
954 iter_reg
= qla24xx_read_window(reg
, 0xBF40, 16, iter_reg
);
955 iter_reg
= qla24xx_read_window(reg
, 0xBF50, 16, iter_reg
);
956 iter_reg
= qla24xx_read_window(reg
, 0xBF60, 16, iter_reg
);
957 qla24xx_read_window(reg
, 0xBF70, 16, iter_reg
);
959 qla24xx_read_window(reg
, 0xBFE0, 16, fw
->xseq_0_reg
);
960 qla24xx_read_window(reg
, 0xBFF0, 16, fw
->xseq_1_reg
);
962 /* Receive sequence registers. */
963 iter_reg
= fw
->rseq_gp_reg
;
964 iter_reg
= qla24xx_read_window(reg
, 0xFF00, 16, iter_reg
);
965 iter_reg
= qla24xx_read_window(reg
, 0xFF10, 16, iter_reg
);
966 iter_reg
= qla24xx_read_window(reg
, 0xFF20, 16, iter_reg
);
967 iter_reg
= qla24xx_read_window(reg
, 0xFF30, 16, iter_reg
);
968 iter_reg
= qla24xx_read_window(reg
, 0xFF40, 16, iter_reg
);
969 iter_reg
= qla24xx_read_window(reg
, 0xFF50, 16, iter_reg
);
970 iter_reg
= qla24xx_read_window(reg
, 0xFF60, 16, iter_reg
);
971 qla24xx_read_window(reg
, 0xFF70, 16, iter_reg
);
973 qla24xx_read_window(reg
, 0xFFD0, 16, fw
->rseq_0_reg
);
974 qla24xx_read_window(reg
, 0xFFE0, 16, fw
->rseq_1_reg
);
975 qla24xx_read_window(reg
, 0xFFF0, 16, fw
->rseq_2_reg
);
977 /* Command DMA registers. */
978 qla24xx_read_window(reg
, 0x7100, 16, fw
->cmd_dma_reg
);
981 iter_reg
= fw
->req0_dma_reg
;
982 iter_reg
= qla24xx_read_window(reg
, 0x7200, 8, iter_reg
);
983 dmp_reg
= ®
->iobase_q
;
984 for (cnt
= 0; cnt
< 7; cnt
++)
985 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
987 iter_reg
= fw
->resp0_dma_reg
;
988 iter_reg
= qla24xx_read_window(reg
, 0x7300, 8, iter_reg
);
989 dmp_reg
= ®
->iobase_q
;
990 for (cnt
= 0; cnt
< 7; cnt
++)
991 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
993 iter_reg
= fw
->req1_dma_reg
;
994 iter_reg
= qla24xx_read_window(reg
, 0x7400, 8, iter_reg
);
995 dmp_reg
= ®
->iobase_q
;
996 for (cnt
= 0; cnt
< 7; cnt
++)
997 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
999 /* Transmit DMA registers. */
1000 iter_reg
= fw
->xmt0_dma_reg
;
1001 iter_reg
= qla24xx_read_window(reg
, 0x7600, 16, iter_reg
);
1002 qla24xx_read_window(reg
, 0x7610, 16, iter_reg
);
1004 iter_reg
= fw
->xmt1_dma_reg
;
1005 iter_reg
= qla24xx_read_window(reg
, 0x7620, 16, iter_reg
);
1006 qla24xx_read_window(reg
, 0x7630, 16, iter_reg
);
1008 iter_reg
= fw
->xmt2_dma_reg
;
1009 iter_reg
= qla24xx_read_window(reg
, 0x7640, 16, iter_reg
);
1010 qla24xx_read_window(reg
, 0x7650, 16, iter_reg
);
1012 iter_reg
= fw
->xmt3_dma_reg
;
1013 iter_reg
= qla24xx_read_window(reg
, 0x7660, 16, iter_reg
);
1014 qla24xx_read_window(reg
, 0x7670, 16, iter_reg
);
1016 iter_reg
= fw
->xmt4_dma_reg
;
1017 iter_reg
= qla24xx_read_window(reg
, 0x7680, 16, iter_reg
);
1018 qla24xx_read_window(reg
, 0x7690, 16, iter_reg
);
1020 qla24xx_read_window(reg
, 0x76A0, 16, fw
->xmt_data_dma_reg
);
1022 /* Receive DMA registers. */
1023 iter_reg
= fw
->rcvt0_data_dma_reg
;
1024 iter_reg
= qla24xx_read_window(reg
, 0x7700, 16, iter_reg
);
1025 qla24xx_read_window(reg
, 0x7710, 16, iter_reg
);
1027 iter_reg
= fw
->rcvt1_data_dma_reg
;
1028 iter_reg
= qla24xx_read_window(reg
, 0x7720, 16, iter_reg
);
1029 qla24xx_read_window(reg
, 0x7730, 16, iter_reg
);
1031 /* RISC registers. */
1032 iter_reg
= fw
->risc_gp_reg
;
1033 iter_reg
= qla24xx_read_window(reg
, 0x0F00, 16, iter_reg
);
1034 iter_reg
= qla24xx_read_window(reg
, 0x0F10, 16, iter_reg
);
1035 iter_reg
= qla24xx_read_window(reg
, 0x0F20, 16, iter_reg
);
1036 iter_reg
= qla24xx_read_window(reg
, 0x0F30, 16, iter_reg
);
1037 iter_reg
= qla24xx_read_window(reg
, 0x0F40, 16, iter_reg
);
1038 iter_reg
= qla24xx_read_window(reg
, 0x0F50, 16, iter_reg
);
1039 iter_reg
= qla24xx_read_window(reg
, 0x0F60, 16, iter_reg
);
1040 qla24xx_read_window(reg
, 0x0F70, 16, iter_reg
);
1042 /* Local memory controller registers. */
1043 iter_reg
= fw
->lmc_reg
;
1044 iter_reg
= qla24xx_read_window(reg
, 0x3000, 16, iter_reg
);
1045 iter_reg
= qla24xx_read_window(reg
, 0x3010, 16, iter_reg
);
1046 iter_reg
= qla24xx_read_window(reg
, 0x3020, 16, iter_reg
);
1047 iter_reg
= qla24xx_read_window(reg
, 0x3030, 16, iter_reg
);
1048 iter_reg
= qla24xx_read_window(reg
, 0x3040, 16, iter_reg
);
1049 iter_reg
= qla24xx_read_window(reg
, 0x3050, 16, iter_reg
);
1050 qla24xx_read_window(reg
, 0x3060, 16, iter_reg
);
1052 /* Fibre Protocol Module registers. */
1053 iter_reg
= fw
->fpm_hdw_reg
;
1054 iter_reg
= qla24xx_read_window(reg
, 0x4000, 16, iter_reg
);
1055 iter_reg
= qla24xx_read_window(reg
, 0x4010, 16, iter_reg
);
1056 iter_reg
= qla24xx_read_window(reg
, 0x4020, 16, iter_reg
);
1057 iter_reg
= qla24xx_read_window(reg
, 0x4030, 16, iter_reg
);
1058 iter_reg
= qla24xx_read_window(reg
, 0x4040, 16, iter_reg
);
1059 iter_reg
= qla24xx_read_window(reg
, 0x4050, 16, iter_reg
);
1060 iter_reg
= qla24xx_read_window(reg
, 0x4060, 16, iter_reg
);
1061 iter_reg
= qla24xx_read_window(reg
, 0x4070, 16, iter_reg
);
1062 iter_reg
= qla24xx_read_window(reg
, 0x4080, 16, iter_reg
);
1063 iter_reg
= qla24xx_read_window(reg
, 0x4090, 16, iter_reg
);
1064 iter_reg
= qla24xx_read_window(reg
, 0x40A0, 16, iter_reg
);
1065 qla24xx_read_window(reg
, 0x40B0, 16, iter_reg
);
1067 /* Frame Buffer registers. */
1068 iter_reg
= fw
->fb_hdw_reg
;
1069 iter_reg
= qla24xx_read_window(reg
, 0x6000, 16, iter_reg
);
1070 iter_reg
= qla24xx_read_window(reg
, 0x6010, 16, iter_reg
);
1071 iter_reg
= qla24xx_read_window(reg
, 0x6020, 16, iter_reg
);
1072 iter_reg
= qla24xx_read_window(reg
, 0x6030, 16, iter_reg
);
1073 iter_reg
= qla24xx_read_window(reg
, 0x6040, 16, iter_reg
);
1074 iter_reg
= qla24xx_read_window(reg
, 0x6100, 16, iter_reg
);
1075 iter_reg
= qla24xx_read_window(reg
, 0x6130, 16, iter_reg
);
1076 iter_reg
= qla24xx_read_window(reg
, 0x6150, 16, iter_reg
);
1077 iter_reg
= qla24xx_read_window(reg
, 0x6170, 16, iter_reg
);
1078 iter_reg
= qla24xx_read_window(reg
, 0x6190, 16, iter_reg
);
1079 qla24xx_read_window(reg
, 0x61B0, 16, iter_reg
);
1081 rval
= qla24xx_soft_reset(ha
);
1082 if (rval
!= QLA_SUCCESS
)
1083 goto qla24xx_fw_dump_failed_0
;
1085 rval
= qla24xx_dump_memory(ha
, fw
->code_ram
, sizeof(fw
->code_ram
),
1087 if (rval
!= QLA_SUCCESS
)
1088 goto qla24xx_fw_dump_failed_0
;
1090 nxt
= qla2xxx_copy_queues(ha
, nxt
);
1092 qla24xx_copy_eft(ha
, nxt
);
1094 qla24xx_fw_dump_failed_0
:
1095 qla2xxx_dump_post_process(base_vha
, rval
);
1097 qla24xx_fw_dump_failed
:
1098 if (!hardware_locked
)
1099 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1103 qla25xx_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
1107 uint32_t risc_address
;
1108 struct qla_hw_data
*ha
= vha
->hw
;
1109 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1110 uint32_t __iomem
*dmp_reg
;
1112 uint16_t __iomem
*mbx_reg
;
1113 unsigned long flags
;
1114 struct qla25xx_fw_dump
*fw
;
1115 uint32_t ext_mem_cnt
;
1116 void *nxt
, *nxt_chain
;
1117 uint32_t *last_chain
= NULL
;
1118 struct scsi_qla_host
*base_vha
= pci_get_drvdata(ha
->pdev
);
1120 risc_address
= ext_mem_cnt
= 0;
1123 if (!hardware_locked
)
1124 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1127 ql_log(ql_log_warn
, vha
, 0xd008,
1128 "No buffer available for dump.\n");
1129 goto qla25xx_fw_dump_failed
;
1132 if (ha
->fw_dumped
) {
1133 ql_log(ql_log_warn
, vha
, 0xd009,
1134 "Firmware has been previously dumped (%p) "
1135 "-- ignoring request.\n",
1137 goto qla25xx_fw_dump_failed
;
1139 fw
= &ha
->fw_dump
->isp
.isp25
;
1140 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
1141 ha
->fw_dump
->version
= __constant_htonl(2);
1143 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
1146 rval
= qla24xx_pause_risc(reg
);
1147 if (rval
!= QLA_SUCCESS
)
1148 goto qla25xx_fw_dump_failed_0
;
1150 /* Host/Risc registers. */
1151 iter_reg
= fw
->host_risc_reg
;
1152 iter_reg
= qla24xx_read_window(reg
, 0x7000, 16, iter_reg
);
1153 qla24xx_read_window(reg
, 0x7010, 16, iter_reg
);
1155 /* PCIe registers. */
1156 WRT_REG_DWORD(®
->iobase_addr
, 0x7C00);
1157 RD_REG_DWORD(®
->iobase_addr
);
1158 WRT_REG_DWORD(®
->iobase_window
, 0x01);
1159 dmp_reg
= ®
->iobase_c4
;
1160 fw
->pcie_regs
[0] = htonl(RD_REG_DWORD(dmp_reg
++));
1161 fw
->pcie_regs
[1] = htonl(RD_REG_DWORD(dmp_reg
++));
1162 fw
->pcie_regs
[2] = htonl(RD_REG_DWORD(dmp_reg
));
1163 fw
->pcie_regs
[3] = htonl(RD_REG_DWORD(®
->iobase_window
));
1165 WRT_REG_DWORD(®
->iobase_window
, 0x00);
1166 RD_REG_DWORD(®
->iobase_window
);
1168 /* Host interface registers. */
1169 dmp_reg
= ®
->flash_addr
;
1170 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
1171 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1173 /* Disable interrupts. */
1174 WRT_REG_DWORD(®
->ictrl
, 0);
1175 RD_REG_DWORD(®
->ictrl
);
1177 /* Shadow registers. */
1178 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1179 RD_REG_DWORD(®
->iobase_addr
);
1180 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
1181 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1183 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
1184 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1186 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
1187 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1189 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
1190 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1192 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
1193 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1195 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
1196 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1198 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
1199 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1201 WRT_REG_DWORD(®
->iobase_select
, 0xB0700000);
1202 fw
->shadow_reg
[7] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1204 WRT_REG_DWORD(®
->iobase_select
, 0xB0800000);
1205 fw
->shadow_reg
[8] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1207 WRT_REG_DWORD(®
->iobase_select
, 0xB0900000);
1208 fw
->shadow_reg
[9] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1210 WRT_REG_DWORD(®
->iobase_select
, 0xB0A00000);
1211 fw
->shadow_reg
[10] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1213 /* RISC I/O register. */
1214 WRT_REG_DWORD(®
->iobase_addr
, 0x0010);
1215 fw
->risc_io_reg
= htonl(RD_REG_DWORD(®
->iobase_window
));
1217 /* Mailbox registers. */
1218 mbx_reg
= ®
->mailbox0
;
1219 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
1220 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
1222 /* Transfer sequence registers. */
1223 iter_reg
= fw
->xseq_gp_reg
;
1224 iter_reg
= qla24xx_read_window(reg
, 0xBF00, 16, iter_reg
);
1225 iter_reg
= qla24xx_read_window(reg
, 0xBF10, 16, iter_reg
);
1226 iter_reg
= qla24xx_read_window(reg
, 0xBF20, 16, iter_reg
);
1227 iter_reg
= qla24xx_read_window(reg
, 0xBF30, 16, iter_reg
);
1228 iter_reg
= qla24xx_read_window(reg
, 0xBF40, 16, iter_reg
);
1229 iter_reg
= qla24xx_read_window(reg
, 0xBF50, 16, iter_reg
);
1230 iter_reg
= qla24xx_read_window(reg
, 0xBF60, 16, iter_reg
);
1231 qla24xx_read_window(reg
, 0xBF70, 16, iter_reg
);
1233 iter_reg
= fw
->xseq_0_reg
;
1234 iter_reg
= qla24xx_read_window(reg
, 0xBFC0, 16, iter_reg
);
1235 iter_reg
= qla24xx_read_window(reg
, 0xBFD0, 16, iter_reg
);
1236 qla24xx_read_window(reg
, 0xBFE0, 16, iter_reg
);
1238 qla24xx_read_window(reg
, 0xBFF0, 16, fw
->xseq_1_reg
);
1240 /* Receive sequence registers. */
1241 iter_reg
= fw
->rseq_gp_reg
;
1242 iter_reg
= qla24xx_read_window(reg
, 0xFF00, 16, iter_reg
);
1243 iter_reg
= qla24xx_read_window(reg
, 0xFF10, 16, iter_reg
);
1244 iter_reg
= qla24xx_read_window(reg
, 0xFF20, 16, iter_reg
);
1245 iter_reg
= qla24xx_read_window(reg
, 0xFF30, 16, iter_reg
);
1246 iter_reg
= qla24xx_read_window(reg
, 0xFF40, 16, iter_reg
);
1247 iter_reg
= qla24xx_read_window(reg
, 0xFF50, 16, iter_reg
);
1248 iter_reg
= qla24xx_read_window(reg
, 0xFF60, 16, iter_reg
);
1249 qla24xx_read_window(reg
, 0xFF70, 16, iter_reg
);
1251 iter_reg
= fw
->rseq_0_reg
;
1252 iter_reg
= qla24xx_read_window(reg
, 0xFFC0, 16, iter_reg
);
1253 qla24xx_read_window(reg
, 0xFFD0, 16, iter_reg
);
1255 qla24xx_read_window(reg
, 0xFFE0, 16, fw
->rseq_1_reg
);
1256 qla24xx_read_window(reg
, 0xFFF0, 16, fw
->rseq_2_reg
);
1258 /* Auxiliary sequence registers. */
1259 iter_reg
= fw
->aseq_gp_reg
;
1260 iter_reg
= qla24xx_read_window(reg
, 0xB000, 16, iter_reg
);
1261 iter_reg
= qla24xx_read_window(reg
, 0xB010, 16, iter_reg
);
1262 iter_reg
= qla24xx_read_window(reg
, 0xB020, 16, iter_reg
);
1263 iter_reg
= qla24xx_read_window(reg
, 0xB030, 16, iter_reg
);
1264 iter_reg
= qla24xx_read_window(reg
, 0xB040, 16, iter_reg
);
1265 iter_reg
= qla24xx_read_window(reg
, 0xB050, 16, iter_reg
);
1266 iter_reg
= qla24xx_read_window(reg
, 0xB060, 16, iter_reg
);
1267 qla24xx_read_window(reg
, 0xB070, 16, iter_reg
);
1269 iter_reg
= fw
->aseq_0_reg
;
1270 iter_reg
= qla24xx_read_window(reg
, 0xB0C0, 16, iter_reg
);
1271 qla24xx_read_window(reg
, 0xB0D0, 16, iter_reg
);
1273 qla24xx_read_window(reg
, 0xB0E0, 16, fw
->aseq_1_reg
);
1274 qla24xx_read_window(reg
, 0xB0F0, 16, fw
->aseq_2_reg
);
1276 /* Command DMA registers. */
1277 qla24xx_read_window(reg
, 0x7100, 16, fw
->cmd_dma_reg
);
1280 iter_reg
= fw
->req0_dma_reg
;
1281 iter_reg
= qla24xx_read_window(reg
, 0x7200, 8, iter_reg
);
1282 dmp_reg
= ®
->iobase_q
;
1283 for (cnt
= 0; cnt
< 7; cnt
++)
1284 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1286 iter_reg
= fw
->resp0_dma_reg
;
1287 iter_reg
= qla24xx_read_window(reg
, 0x7300, 8, iter_reg
);
1288 dmp_reg
= ®
->iobase_q
;
1289 for (cnt
= 0; cnt
< 7; cnt
++)
1290 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1292 iter_reg
= fw
->req1_dma_reg
;
1293 iter_reg
= qla24xx_read_window(reg
, 0x7400, 8, iter_reg
);
1294 dmp_reg
= ®
->iobase_q
;
1295 for (cnt
= 0; cnt
< 7; cnt
++)
1296 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1298 /* Transmit DMA registers. */
1299 iter_reg
= fw
->xmt0_dma_reg
;
1300 iter_reg
= qla24xx_read_window(reg
, 0x7600, 16, iter_reg
);
1301 qla24xx_read_window(reg
, 0x7610, 16, iter_reg
);
1303 iter_reg
= fw
->xmt1_dma_reg
;
1304 iter_reg
= qla24xx_read_window(reg
, 0x7620, 16, iter_reg
);
1305 qla24xx_read_window(reg
, 0x7630, 16, iter_reg
);
1307 iter_reg
= fw
->xmt2_dma_reg
;
1308 iter_reg
= qla24xx_read_window(reg
, 0x7640, 16, iter_reg
);
1309 qla24xx_read_window(reg
, 0x7650, 16, iter_reg
);
1311 iter_reg
= fw
->xmt3_dma_reg
;
1312 iter_reg
= qla24xx_read_window(reg
, 0x7660, 16, iter_reg
);
1313 qla24xx_read_window(reg
, 0x7670, 16, iter_reg
);
1315 iter_reg
= fw
->xmt4_dma_reg
;
1316 iter_reg
= qla24xx_read_window(reg
, 0x7680, 16, iter_reg
);
1317 qla24xx_read_window(reg
, 0x7690, 16, iter_reg
);
1319 qla24xx_read_window(reg
, 0x76A0, 16, fw
->xmt_data_dma_reg
);
1321 /* Receive DMA registers. */
1322 iter_reg
= fw
->rcvt0_data_dma_reg
;
1323 iter_reg
= qla24xx_read_window(reg
, 0x7700, 16, iter_reg
);
1324 qla24xx_read_window(reg
, 0x7710, 16, iter_reg
);
1326 iter_reg
= fw
->rcvt1_data_dma_reg
;
1327 iter_reg
= qla24xx_read_window(reg
, 0x7720, 16, iter_reg
);
1328 qla24xx_read_window(reg
, 0x7730, 16, iter_reg
);
1330 /* RISC registers. */
1331 iter_reg
= fw
->risc_gp_reg
;
1332 iter_reg
= qla24xx_read_window(reg
, 0x0F00, 16, iter_reg
);
1333 iter_reg
= qla24xx_read_window(reg
, 0x0F10, 16, iter_reg
);
1334 iter_reg
= qla24xx_read_window(reg
, 0x0F20, 16, iter_reg
);
1335 iter_reg
= qla24xx_read_window(reg
, 0x0F30, 16, iter_reg
);
1336 iter_reg
= qla24xx_read_window(reg
, 0x0F40, 16, iter_reg
);
1337 iter_reg
= qla24xx_read_window(reg
, 0x0F50, 16, iter_reg
);
1338 iter_reg
= qla24xx_read_window(reg
, 0x0F60, 16, iter_reg
);
1339 qla24xx_read_window(reg
, 0x0F70, 16, iter_reg
);
1341 /* Local memory controller registers. */
1342 iter_reg
= fw
->lmc_reg
;
1343 iter_reg
= qla24xx_read_window(reg
, 0x3000, 16, iter_reg
);
1344 iter_reg
= qla24xx_read_window(reg
, 0x3010, 16, iter_reg
);
1345 iter_reg
= qla24xx_read_window(reg
, 0x3020, 16, iter_reg
);
1346 iter_reg
= qla24xx_read_window(reg
, 0x3030, 16, iter_reg
);
1347 iter_reg
= qla24xx_read_window(reg
, 0x3040, 16, iter_reg
);
1348 iter_reg
= qla24xx_read_window(reg
, 0x3050, 16, iter_reg
);
1349 iter_reg
= qla24xx_read_window(reg
, 0x3060, 16, iter_reg
);
1350 qla24xx_read_window(reg
, 0x3070, 16, iter_reg
);
1352 /* Fibre Protocol Module registers. */
1353 iter_reg
= fw
->fpm_hdw_reg
;
1354 iter_reg
= qla24xx_read_window(reg
, 0x4000, 16, iter_reg
);
1355 iter_reg
= qla24xx_read_window(reg
, 0x4010, 16, iter_reg
);
1356 iter_reg
= qla24xx_read_window(reg
, 0x4020, 16, iter_reg
);
1357 iter_reg
= qla24xx_read_window(reg
, 0x4030, 16, iter_reg
);
1358 iter_reg
= qla24xx_read_window(reg
, 0x4040, 16, iter_reg
);
1359 iter_reg
= qla24xx_read_window(reg
, 0x4050, 16, iter_reg
);
1360 iter_reg
= qla24xx_read_window(reg
, 0x4060, 16, iter_reg
);
1361 iter_reg
= qla24xx_read_window(reg
, 0x4070, 16, iter_reg
);
1362 iter_reg
= qla24xx_read_window(reg
, 0x4080, 16, iter_reg
);
1363 iter_reg
= qla24xx_read_window(reg
, 0x4090, 16, iter_reg
);
1364 iter_reg
= qla24xx_read_window(reg
, 0x40A0, 16, iter_reg
);
1365 qla24xx_read_window(reg
, 0x40B0, 16, iter_reg
);
1367 /* Frame Buffer registers. */
1368 iter_reg
= fw
->fb_hdw_reg
;
1369 iter_reg
= qla24xx_read_window(reg
, 0x6000, 16, iter_reg
);
1370 iter_reg
= qla24xx_read_window(reg
, 0x6010, 16, iter_reg
);
1371 iter_reg
= qla24xx_read_window(reg
, 0x6020, 16, iter_reg
);
1372 iter_reg
= qla24xx_read_window(reg
, 0x6030, 16, iter_reg
);
1373 iter_reg
= qla24xx_read_window(reg
, 0x6040, 16, iter_reg
);
1374 iter_reg
= qla24xx_read_window(reg
, 0x6100, 16, iter_reg
);
1375 iter_reg
= qla24xx_read_window(reg
, 0x6130, 16, iter_reg
);
1376 iter_reg
= qla24xx_read_window(reg
, 0x6150, 16, iter_reg
);
1377 iter_reg
= qla24xx_read_window(reg
, 0x6170, 16, iter_reg
);
1378 iter_reg
= qla24xx_read_window(reg
, 0x6190, 16, iter_reg
);
1379 iter_reg
= qla24xx_read_window(reg
, 0x61B0, 16, iter_reg
);
1380 qla24xx_read_window(reg
, 0x6F00, 16, iter_reg
);
1382 /* Multi queue registers */
1383 nxt_chain
= qla25xx_copy_mq(ha
, (void *)ha
->fw_dump
+ ha
->chain_offset
,
1386 rval
= qla24xx_soft_reset(ha
);
1387 if (rval
!= QLA_SUCCESS
)
1388 goto qla25xx_fw_dump_failed_0
;
1390 rval
= qla24xx_dump_memory(ha
, fw
->code_ram
, sizeof(fw
->code_ram
),
1392 if (rval
!= QLA_SUCCESS
)
1393 goto qla25xx_fw_dump_failed_0
;
1395 nxt
= qla2xxx_copy_queues(ha
, nxt
);
1397 nxt
= qla24xx_copy_eft(ha
, nxt
);
1399 /* Chain entries -- started with MQ. */
1400 nxt_chain
= qla25xx_copy_fce(ha
, nxt_chain
, &last_chain
);
1401 nxt_chain
= qla25xx_copy_mqueues(ha
, nxt_chain
, &last_chain
);
1403 ha
->fw_dump
->version
|= __constant_htonl(DUMP_CHAIN_VARIANT
);
1404 *last_chain
|= __constant_htonl(DUMP_CHAIN_LAST
);
1407 /* Adjust valid length. */
1408 ha
->fw_dump_len
= (nxt_chain
- (void *)ha
->fw_dump
);
1410 qla25xx_fw_dump_failed_0
:
1411 qla2xxx_dump_post_process(base_vha
, rval
);
1413 qla25xx_fw_dump_failed
:
1414 if (!hardware_locked
)
1415 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1419 qla81xx_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
1423 uint32_t risc_address
;
1424 struct qla_hw_data
*ha
= vha
->hw
;
1425 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1426 uint32_t __iomem
*dmp_reg
;
1428 uint16_t __iomem
*mbx_reg
;
1429 unsigned long flags
;
1430 struct qla81xx_fw_dump
*fw
;
1431 uint32_t ext_mem_cnt
;
1432 void *nxt
, *nxt_chain
;
1433 uint32_t *last_chain
= NULL
;
1434 struct scsi_qla_host
*base_vha
= pci_get_drvdata(ha
->pdev
);
1436 risc_address
= ext_mem_cnt
= 0;
1439 if (!hardware_locked
)
1440 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1443 ql_log(ql_log_warn
, vha
, 0xd00a,
1444 "No buffer available for dump.\n");
1445 goto qla81xx_fw_dump_failed
;
1448 if (ha
->fw_dumped
) {
1449 ql_log(ql_log_warn
, vha
, 0xd00b,
1450 "Firmware has been previously dumped (%p) "
1451 "-- ignoring request.\n",
1453 goto qla81xx_fw_dump_failed
;
1455 fw
= &ha
->fw_dump
->isp
.isp81
;
1456 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
1458 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
1461 rval
= qla24xx_pause_risc(reg
);
1462 if (rval
!= QLA_SUCCESS
)
1463 goto qla81xx_fw_dump_failed_0
;
1465 /* Host/Risc registers. */
1466 iter_reg
= fw
->host_risc_reg
;
1467 iter_reg
= qla24xx_read_window(reg
, 0x7000, 16, iter_reg
);
1468 qla24xx_read_window(reg
, 0x7010, 16, iter_reg
);
1470 /* PCIe registers. */
1471 WRT_REG_DWORD(®
->iobase_addr
, 0x7C00);
1472 RD_REG_DWORD(®
->iobase_addr
);
1473 WRT_REG_DWORD(®
->iobase_window
, 0x01);
1474 dmp_reg
= ®
->iobase_c4
;
1475 fw
->pcie_regs
[0] = htonl(RD_REG_DWORD(dmp_reg
++));
1476 fw
->pcie_regs
[1] = htonl(RD_REG_DWORD(dmp_reg
++));
1477 fw
->pcie_regs
[2] = htonl(RD_REG_DWORD(dmp_reg
));
1478 fw
->pcie_regs
[3] = htonl(RD_REG_DWORD(®
->iobase_window
));
1480 WRT_REG_DWORD(®
->iobase_window
, 0x00);
1481 RD_REG_DWORD(®
->iobase_window
);
1483 /* Host interface registers. */
1484 dmp_reg
= ®
->flash_addr
;
1485 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
1486 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1488 /* Disable interrupts. */
1489 WRT_REG_DWORD(®
->ictrl
, 0);
1490 RD_REG_DWORD(®
->ictrl
);
1492 /* Shadow registers. */
1493 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1494 RD_REG_DWORD(®
->iobase_addr
);
1495 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
1496 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1498 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
1499 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1501 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
1502 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1504 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
1505 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1507 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
1508 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1510 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
1511 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1513 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
1514 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1516 WRT_REG_DWORD(®
->iobase_select
, 0xB0700000);
1517 fw
->shadow_reg
[7] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1519 WRT_REG_DWORD(®
->iobase_select
, 0xB0800000);
1520 fw
->shadow_reg
[8] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1522 WRT_REG_DWORD(®
->iobase_select
, 0xB0900000);
1523 fw
->shadow_reg
[9] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1525 WRT_REG_DWORD(®
->iobase_select
, 0xB0A00000);
1526 fw
->shadow_reg
[10] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1528 /* RISC I/O register. */
1529 WRT_REG_DWORD(®
->iobase_addr
, 0x0010);
1530 fw
->risc_io_reg
= htonl(RD_REG_DWORD(®
->iobase_window
));
1532 /* Mailbox registers. */
1533 mbx_reg
= ®
->mailbox0
;
1534 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
1535 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
1537 /* Transfer sequence registers. */
1538 iter_reg
= fw
->xseq_gp_reg
;
1539 iter_reg
= qla24xx_read_window(reg
, 0xBF00, 16, iter_reg
);
1540 iter_reg
= qla24xx_read_window(reg
, 0xBF10, 16, iter_reg
);
1541 iter_reg
= qla24xx_read_window(reg
, 0xBF20, 16, iter_reg
);
1542 iter_reg
= qla24xx_read_window(reg
, 0xBF30, 16, iter_reg
);
1543 iter_reg
= qla24xx_read_window(reg
, 0xBF40, 16, iter_reg
);
1544 iter_reg
= qla24xx_read_window(reg
, 0xBF50, 16, iter_reg
);
1545 iter_reg
= qla24xx_read_window(reg
, 0xBF60, 16, iter_reg
);
1546 qla24xx_read_window(reg
, 0xBF70, 16, iter_reg
);
1548 iter_reg
= fw
->xseq_0_reg
;
1549 iter_reg
= qla24xx_read_window(reg
, 0xBFC0, 16, iter_reg
);
1550 iter_reg
= qla24xx_read_window(reg
, 0xBFD0, 16, iter_reg
);
1551 qla24xx_read_window(reg
, 0xBFE0, 16, iter_reg
);
1553 qla24xx_read_window(reg
, 0xBFF0, 16, fw
->xseq_1_reg
);
1555 /* Receive sequence registers. */
1556 iter_reg
= fw
->rseq_gp_reg
;
1557 iter_reg
= qla24xx_read_window(reg
, 0xFF00, 16, iter_reg
);
1558 iter_reg
= qla24xx_read_window(reg
, 0xFF10, 16, iter_reg
);
1559 iter_reg
= qla24xx_read_window(reg
, 0xFF20, 16, iter_reg
);
1560 iter_reg
= qla24xx_read_window(reg
, 0xFF30, 16, iter_reg
);
1561 iter_reg
= qla24xx_read_window(reg
, 0xFF40, 16, iter_reg
);
1562 iter_reg
= qla24xx_read_window(reg
, 0xFF50, 16, iter_reg
);
1563 iter_reg
= qla24xx_read_window(reg
, 0xFF60, 16, iter_reg
);
1564 qla24xx_read_window(reg
, 0xFF70, 16, iter_reg
);
1566 iter_reg
= fw
->rseq_0_reg
;
1567 iter_reg
= qla24xx_read_window(reg
, 0xFFC0, 16, iter_reg
);
1568 qla24xx_read_window(reg
, 0xFFD0, 16, iter_reg
);
1570 qla24xx_read_window(reg
, 0xFFE0, 16, fw
->rseq_1_reg
);
1571 qla24xx_read_window(reg
, 0xFFF0, 16, fw
->rseq_2_reg
);
1573 /* Auxiliary sequence registers. */
1574 iter_reg
= fw
->aseq_gp_reg
;
1575 iter_reg
= qla24xx_read_window(reg
, 0xB000, 16, iter_reg
);
1576 iter_reg
= qla24xx_read_window(reg
, 0xB010, 16, iter_reg
);
1577 iter_reg
= qla24xx_read_window(reg
, 0xB020, 16, iter_reg
);
1578 iter_reg
= qla24xx_read_window(reg
, 0xB030, 16, iter_reg
);
1579 iter_reg
= qla24xx_read_window(reg
, 0xB040, 16, iter_reg
);
1580 iter_reg
= qla24xx_read_window(reg
, 0xB050, 16, iter_reg
);
1581 iter_reg
= qla24xx_read_window(reg
, 0xB060, 16, iter_reg
);
1582 qla24xx_read_window(reg
, 0xB070, 16, iter_reg
);
1584 iter_reg
= fw
->aseq_0_reg
;
1585 iter_reg
= qla24xx_read_window(reg
, 0xB0C0, 16, iter_reg
);
1586 qla24xx_read_window(reg
, 0xB0D0, 16, iter_reg
);
1588 qla24xx_read_window(reg
, 0xB0E0, 16, fw
->aseq_1_reg
);
1589 qla24xx_read_window(reg
, 0xB0F0, 16, fw
->aseq_2_reg
);
1591 /* Command DMA registers. */
1592 qla24xx_read_window(reg
, 0x7100, 16, fw
->cmd_dma_reg
);
1595 iter_reg
= fw
->req0_dma_reg
;
1596 iter_reg
= qla24xx_read_window(reg
, 0x7200, 8, iter_reg
);
1597 dmp_reg
= ®
->iobase_q
;
1598 for (cnt
= 0; cnt
< 7; cnt
++)
1599 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1601 iter_reg
= fw
->resp0_dma_reg
;
1602 iter_reg
= qla24xx_read_window(reg
, 0x7300, 8, iter_reg
);
1603 dmp_reg
= ®
->iobase_q
;
1604 for (cnt
= 0; cnt
< 7; cnt
++)
1605 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1607 iter_reg
= fw
->req1_dma_reg
;
1608 iter_reg
= qla24xx_read_window(reg
, 0x7400, 8, iter_reg
);
1609 dmp_reg
= ®
->iobase_q
;
1610 for (cnt
= 0; cnt
< 7; cnt
++)
1611 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1613 /* Transmit DMA registers. */
1614 iter_reg
= fw
->xmt0_dma_reg
;
1615 iter_reg
= qla24xx_read_window(reg
, 0x7600, 16, iter_reg
);
1616 qla24xx_read_window(reg
, 0x7610, 16, iter_reg
);
1618 iter_reg
= fw
->xmt1_dma_reg
;
1619 iter_reg
= qla24xx_read_window(reg
, 0x7620, 16, iter_reg
);
1620 qla24xx_read_window(reg
, 0x7630, 16, iter_reg
);
1622 iter_reg
= fw
->xmt2_dma_reg
;
1623 iter_reg
= qla24xx_read_window(reg
, 0x7640, 16, iter_reg
);
1624 qla24xx_read_window(reg
, 0x7650, 16, iter_reg
);
1626 iter_reg
= fw
->xmt3_dma_reg
;
1627 iter_reg
= qla24xx_read_window(reg
, 0x7660, 16, iter_reg
);
1628 qla24xx_read_window(reg
, 0x7670, 16, iter_reg
);
1630 iter_reg
= fw
->xmt4_dma_reg
;
1631 iter_reg
= qla24xx_read_window(reg
, 0x7680, 16, iter_reg
);
1632 qla24xx_read_window(reg
, 0x7690, 16, iter_reg
);
1634 qla24xx_read_window(reg
, 0x76A0, 16, fw
->xmt_data_dma_reg
);
1636 /* Receive DMA registers. */
1637 iter_reg
= fw
->rcvt0_data_dma_reg
;
1638 iter_reg
= qla24xx_read_window(reg
, 0x7700, 16, iter_reg
);
1639 qla24xx_read_window(reg
, 0x7710, 16, iter_reg
);
1641 iter_reg
= fw
->rcvt1_data_dma_reg
;
1642 iter_reg
= qla24xx_read_window(reg
, 0x7720, 16, iter_reg
);
1643 qla24xx_read_window(reg
, 0x7730, 16, iter_reg
);
1645 /* RISC registers. */
1646 iter_reg
= fw
->risc_gp_reg
;
1647 iter_reg
= qla24xx_read_window(reg
, 0x0F00, 16, iter_reg
);
1648 iter_reg
= qla24xx_read_window(reg
, 0x0F10, 16, iter_reg
);
1649 iter_reg
= qla24xx_read_window(reg
, 0x0F20, 16, iter_reg
);
1650 iter_reg
= qla24xx_read_window(reg
, 0x0F30, 16, iter_reg
);
1651 iter_reg
= qla24xx_read_window(reg
, 0x0F40, 16, iter_reg
);
1652 iter_reg
= qla24xx_read_window(reg
, 0x0F50, 16, iter_reg
);
1653 iter_reg
= qla24xx_read_window(reg
, 0x0F60, 16, iter_reg
);
1654 qla24xx_read_window(reg
, 0x0F70, 16, iter_reg
);
1656 /* Local memory controller registers. */
1657 iter_reg
= fw
->lmc_reg
;
1658 iter_reg
= qla24xx_read_window(reg
, 0x3000, 16, iter_reg
);
1659 iter_reg
= qla24xx_read_window(reg
, 0x3010, 16, iter_reg
);
1660 iter_reg
= qla24xx_read_window(reg
, 0x3020, 16, iter_reg
);
1661 iter_reg
= qla24xx_read_window(reg
, 0x3030, 16, iter_reg
);
1662 iter_reg
= qla24xx_read_window(reg
, 0x3040, 16, iter_reg
);
1663 iter_reg
= qla24xx_read_window(reg
, 0x3050, 16, iter_reg
);
1664 iter_reg
= qla24xx_read_window(reg
, 0x3060, 16, iter_reg
);
1665 qla24xx_read_window(reg
, 0x3070, 16, iter_reg
);
1667 /* Fibre Protocol Module registers. */
1668 iter_reg
= fw
->fpm_hdw_reg
;
1669 iter_reg
= qla24xx_read_window(reg
, 0x4000, 16, iter_reg
);
1670 iter_reg
= qla24xx_read_window(reg
, 0x4010, 16, iter_reg
);
1671 iter_reg
= qla24xx_read_window(reg
, 0x4020, 16, iter_reg
);
1672 iter_reg
= qla24xx_read_window(reg
, 0x4030, 16, iter_reg
);
1673 iter_reg
= qla24xx_read_window(reg
, 0x4040, 16, iter_reg
);
1674 iter_reg
= qla24xx_read_window(reg
, 0x4050, 16, iter_reg
);
1675 iter_reg
= qla24xx_read_window(reg
, 0x4060, 16, iter_reg
);
1676 iter_reg
= qla24xx_read_window(reg
, 0x4070, 16, iter_reg
);
1677 iter_reg
= qla24xx_read_window(reg
, 0x4080, 16, iter_reg
);
1678 iter_reg
= qla24xx_read_window(reg
, 0x4090, 16, iter_reg
);
1679 iter_reg
= qla24xx_read_window(reg
, 0x40A0, 16, iter_reg
);
1680 iter_reg
= qla24xx_read_window(reg
, 0x40B0, 16, iter_reg
);
1681 iter_reg
= qla24xx_read_window(reg
, 0x40C0, 16, iter_reg
);
1682 qla24xx_read_window(reg
, 0x40D0, 16, iter_reg
);
1684 /* Frame Buffer registers. */
1685 iter_reg
= fw
->fb_hdw_reg
;
1686 iter_reg
= qla24xx_read_window(reg
, 0x6000, 16, iter_reg
);
1687 iter_reg
= qla24xx_read_window(reg
, 0x6010, 16, iter_reg
);
1688 iter_reg
= qla24xx_read_window(reg
, 0x6020, 16, iter_reg
);
1689 iter_reg
= qla24xx_read_window(reg
, 0x6030, 16, iter_reg
);
1690 iter_reg
= qla24xx_read_window(reg
, 0x6040, 16, iter_reg
);
1691 iter_reg
= qla24xx_read_window(reg
, 0x6100, 16, iter_reg
);
1692 iter_reg
= qla24xx_read_window(reg
, 0x6130, 16, iter_reg
);
1693 iter_reg
= qla24xx_read_window(reg
, 0x6150, 16, iter_reg
);
1694 iter_reg
= qla24xx_read_window(reg
, 0x6170, 16, iter_reg
);
1695 iter_reg
= qla24xx_read_window(reg
, 0x6190, 16, iter_reg
);
1696 iter_reg
= qla24xx_read_window(reg
, 0x61B0, 16, iter_reg
);
1697 iter_reg
= qla24xx_read_window(reg
, 0x61C0, 16, iter_reg
);
1698 qla24xx_read_window(reg
, 0x6F00, 16, iter_reg
);
1700 /* Multi queue registers */
1701 nxt_chain
= qla25xx_copy_mq(ha
, (void *)ha
->fw_dump
+ ha
->chain_offset
,
1704 rval
= qla24xx_soft_reset(ha
);
1705 if (rval
!= QLA_SUCCESS
)
1706 goto qla81xx_fw_dump_failed_0
;
1708 rval
= qla24xx_dump_memory(ha
, fw
->code_ram
, sizeof(fw
->code_ram
),
1710 if (rval
!= QLA_SUCCESS
)
1711 goto qla81xx_fw_dump_failed_0
;
1713 nxt
= qla2xxx_copy_queues(ha
, nxt
);
1715 nxt
= qla24xx_copy_eft(ha
, nxt
);
1717 /* Chain entries -- started with MQ. */
1718 nxt_chain
= qla25xx_copy_fce(ha
, nxt_chain
, &last_chain
);
1719 nxt_chain
= qla25xx_copy_mqueues(ha
, nxt_chain
, &last_chain
);
1721 ha
->fw_dump
->version
|= __constant_htonl(DUMP_CHAIN_VARIANT
);
1722 *last_chain
|= __constant_htonl(DUMP_CHAIN_LAST
);
1725 /* Adjust valid length. */
1726 ha
->fw_dump_len
= (nxt_chain
- (void *)ha
->fw_dump
);
1728 qla81xx_fw_dump_failed_0
:
1729 qla2xxx_dump_post_process(base_vha
, rval
);
1731 qla81xx_fw_dump_failed
:
1732 if (!hardware_locked
)
1733 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1737 qla83xx_fw_dump(scsi_qla_host_t
*vha
, int hardware_locked
)
1740 uint32_t cnt
, reg_data
;
1741 uint32_t risc_address
;
1742 struct qla_hw_data
*ha
= vha
->hw
;
1743 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1744 uint32_t __iomem
*dmp_reg
;
1746 uint16_t __iomem
*mbx_reg
;
1747 unsigned long flags
;
1748 struct qla83xx_fw_dump
*fw
;
1749 uint32_t ext_mem_cnt
;
1750 void *nxt
, *nxt_chain
;
1751 uint32_t *last_chain
= NULL
;
1752 struct scsi_qla_host
*base_vha
= pci_get_drvdata(ha
->pdev
);
1754 risc_address
= ext_mem_cnt
= 0;
1757 if (!hardware_locked
)
1758 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1761 ql_log(ql_log_warn
, vha
, 0xd00c,
1762 "No buffer available for dump!!!\n");
1763 goto qla83xx_fw_dump_failed
;
1766 if (ha
->fw_dumped
) {
1767 ql_log(ql_log_warn
, vha
, 0xd00d,
1768 "Firmware has been previously dumped (%p) -- ignoring "
1769 "request...\n", ha
->fw_dump
);
1770 goto qla83xx_fw_dump_failed
;
1772 fw
= &ha
->fw_dump
->isp
.isp83
;
1773 qla2xxx_prep_dump(ha
, ha
->fw_dump
);
1775 fw
->host_status
= htonl(RD_REG_DWORD(®
->host_status
));
1778 rval
= qla24xx_pause_risc(reg
);
1779 if (rval
!= QLA_SUCCESS
)
1780 goto qla83xx_fw_dump_failed_0
;
1782 WRT_REG_DWORD(®
->iobase_addr
, 0x6000);
1783 dmp_reg
= ®
->iobase_window
;
1784 reg_data
= RD_REG_DWORD(dmp_reg
);
1785 WRT_REG_DWORD(dmp_reg
, 0);
1787 dmp_reg
= ®
->unused_4_1
[0];
1788 reg_data
= RD_REG_DWORD(dmp_reg
);
1789 WRT_REG_DWORD(dmp_reg
, 0);
1791 WRT_REG_DWORD(®
->iobase_addr
, 0x6010);
1792 dmp_reg
= ®
->unused_4_1
[2];
1793 reg_data
= RD_REG_DWORD(dmp_reg
);
1794 WRT_REG_DWORD(dmp_reg
, 0);
1796 /* select PCR and disable ecc checking and correction */
1797 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1798 RD_REG_DWORD(®
->iobase_addr
);
1799 WRT_REG_DWORD(®
->iobase_select
, 0x60000000); /* write to F0h = PCR */
1801 /* Host/Risc registers. */
1802 iter_reg
= fw
->host_risc_reg
;
1803 iter_reg
= qla24xx_read_window(reg
, 0x7000, 16, iter_reg
);
1804 iter_reg
= qla24xx_read_window(reg
, 0x7010, 16, iter_reg
);
1805 qla24xx_read_window(reg
, 0x7040, 16, iter_reg
);
1807 /* PCIe registers. */
1808 WRT_REG_DWORD(®
->iobase_addr
, 0x7C00);
1809 RD_REG_DWORD(®
->iobase_addr
);
1810 WRT_REG_DWORD(®
->iobase_window
, 0x01);
1811 dmp_reg
= ®
->iobase_c4
;
1812 fw
->pcie_regs
[0] = htonl(RD_REG_DWORD(dmp_reg
++));
1813 fw
->pcie_regs
[1] = htonl(RD_REG_DWORD(dmp_reg
++));
1814 fw
->pcie_regs
[2] = htonl(RD_REG_DWORD(dmp_reg
));
1815 fw
->pcie_regs
[3] = htonl(RD_REG_DWORD(®
->iobase_window
));
1817 WRT_REG_DWORD(®
->iobase_window
, 0x00);
1818 RD_REG_DWORD(®
->iobase_window
);
1820 /* Host interface registers. */
1821 dmp_reg
= ®
->flash_addr
;
1822 for (cnt
= 0; cnt
< sizeof(fw
->host_reg
) / 4; cnt
++)
1823 fw
->host_reg
[cnt
] = htonl(RD_REG_DWORD(dmp_reg
++));
1825 /* Disable interrupts. */
1826 WRT_REG_DWORD(®
->ictrl
, 0);
1827 RD_REG_DWORD(®
->ictrl
);
1829 /* Shadow registers. */
1830 WRT_REG_DWORD(®
->iobase_addr
, 0x0F70);
1831 RD_REG_DWORD(®
->iobase_addr
);
1832 WRT_REG_DWORD(®
->iobase_select
, 0xB0000000);
1833 fw
->shadow_reg
[0] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1835 WRT_REG_DWORD(®
->iobase_select
, 0xB0100000);
1836 fw
->shadow_reg
[1] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1838 WRT_REG_DWORD(®
->iobase_select
, 0xB0200000);
1839 fw
->shadow_reg
[2] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1841 WRT_REG_DWORD(®
->iobase_select
, 0xB0300000);
1842 fw
->shadow_reg
[3] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1844 WRT_REG_DWORD(®
->iobase_select
, 0xB0400000);
1845 fw
->shadow_reg
[4] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1847 WRT_REG_DWORD(®
->iobase_select
, 0xB0500000);
1848 fw
->shadow_reg
[5] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1850 WRT_REG_DWORD(®
->iobase_select
, 0xB0600000);
1851 fw
->shadow_reg
[6] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1853 WRT_REG_DWORD(®
->iobase_select
, 0xB0700000);
1854 fw
->shadow_reg
[7] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1856 WRT_REG_DWORD(®
->iobase_select
, 0xB0800000);
1857 fw
->shadow_reg
[8] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1859 WRT_REG_DWORD(®
->iobase_select
, 0xB0900000);
1860 fw
->shadow_reg
[9] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1862 WRT_REG_DWORD(®
->iobase_select
, 0xB0A00000);
1863 fw
->shadow_reg
[10] = htonl(RD_REG_DWORD(®
->iobase_sdata
));
1865 /* RISC I/O register. */
1866 WRT_REG_DWORD(®
->iobase_addr
, 0x0010);
1867 fw
->risc_io_reg
= htonl(RD_REG_DWORD(®
->iobase_window
));
1869 /* Mailbox registers. */
1870 mbx_reg
= ®
->mailbox0
;
1871 for (cnt
= 0; cnt
< sizeof(fw
->mailbox_reg
) / 2; cnt
++)
1872 fw
->mailbox_reg
[cnt
] = htons(RD_REG_WORD(mbx_reg
++));
1874 /* Transfer sequence registers. */
1875 iter_reg
= fw
->xseq_gp_reg
;
1876 iter_reg
= qla24xx_read_window(reg
, 0xBE00, 16, iter_reg
);
1877 iter_reg
= qla24xx_read_window(reg
, 0xBE10, 16, iter_reg
);
1878 iter_reg
= qla24xx_read_window(reg
, 0xBE20, 16, iter_reg
);
1879 iter_reg
= qla24xx_read_window(reg
, 0xBE30, 16, iter_reg
);
1880 iter_reg
= qla24xx_read_window(reg
, 0xBE40, 16, iter_reg
);
1881 iter_reg
= qla24xx_read_window(reg
, 0xBE50, 16, iter_reg
);
1882 iter_reg
= qla24xx_read_window(reg
, 0xBE60, 16, iter_reg
);
1883 iter_reg
= qla24xx_read_window(reg
, 0xBE70, 16, iter_reg
);
1884 iter_reg
= qla24xx_read_window(reg
, 0xBF00, 16, iter_reg
);
1885 iter_reg
= qla24xx_read_window(reg
, 0xBF10, 16, iter_reg
);
1886 iter_reg
= qla24xx_read_window(reg
, 0xBF20, 16, iter_reg
);
1887 iter_reg
= qla24xx_read_window(reg
, 0xBF30, 16, iter_reg
);
1888 iter_reg
= qla24xx_read_window(reg
, 0xBF40, 16, iter_reg
);
1889 iter_reg
= qla24xx_read_window(reg
, 0xBF50, 16, iter_reg
);
1890 iter_reg
= qla24xx_read_window(reg
, 0xBF60, 16, iter_reg
);
1891 qla24xx_read_window(reg
, 0xBF70, 16, iter_reg
);
1893 iter_reg
= fw
->xseq_0_reg
;
1894 iter_reg
= qla24xx_read_window(reg
, 0xBFC0, 16, iter_reg
);
1895 iter_reg
= qla24xx_read_window(reg
, 0xBFD0, 16, iter_reg
);
1896 qla24xx_read_window(reg
, 0xBFE0, 16, iter_reg
);
1898 qla24xx_read_window(reg
, 0xBFF0, 16, fw
->xseq_1_reg
);
1900 qla24xx_read_window(reg
, 0xBEF0, 16, fw
->xseq_2_reg
);
1902 /* Receive sequence registers. */
1903 iter_reg
= fw
->rseq_gp_reg
;
1904 iter_reg
= qla24xx_read_window(reg
, 0xFE00, 16, iter_reg
);
1905 iter_reg
= qla24xx_read_window(reg
, 0xFE10, 16, iter_reg
);
1906 iter_reg
= qla24xx_read_window(reg
, 0xFE20, 16, iter_reg
);
1907 iter_reg
= qla24xx_read_window(reg
, 0xFE30, 16, iter_reg
);
1908 iter_reg
= qla24xx_read_window(reg
, 0xFE40, 16, iter_reg
);
1909 iter_reg
= qla24xx_read_window(reg
, 0xFE50, 16, iter_reg
);
1910 iter_reg
= qla24xx_read_window(reg
, 0xFE60, 16, iter_reg
);
1911 iter_reg
= qla24xx_read_window(reg
, 0xFE70, 16, iter_reg
);
1912 iter_reg
= qla24xx_read_window(reg
, 0xFF00, 16, iter_reg
);
1913 iter_reg
= qla24xx_read_window(reg
, 0xFF10, 16, iter_reg
);
1914 iter_reg
= qla24xx_read_window(reg
, 0xFF20, 16, iter_reg
);
1915 iter_reg
= qla24xx_read_window(reg
, 0xFF30, 16, iter_reg
);
1916 iter_reg
= qla24xx_read_window(reg
, 0xFF40, 16, iter_reg
);
1917 iter_reg
= qla24xx_read_window(reg
, 0xFF50, 16, iter_reg
);
1918 iter_reg
= qla24xx_read_window(reg
, 0xFF60, 16, iter_reg
);
1919 qla24xx_read_window(reg
, 0xFF70, 16, iter_reg
);
1921 iter_reg
= fw
->rseq_0_reg
;
1922 iter_reg
= qla24xx_read_window(reg
, 0xFFC0, 16, iter_reg
);
1923 qla24xx_read_window(reg
, 0xFFD0, 16, iter_reg
);
1925 qla24xx_read_window(reg
, 0xFFE0, 16, fw
->rseq_1_reg
);
1926 qla24xx_read_window(reg
, 0xFFF0, 16, fw
->rseq_2_reg
);
1927 qla24xx_read_window(reg
, 0xFEF0, 16, fw
->rseq_3_reg
);
1929 /* Auxiliary sequence registers. */
1930 iter_reg
= fw
->aseq_gp_reg
;
1931 iter_reg
= qla24xx_read_window(reg
, 0xB000, 16, iter_reg
);
1932 iter_reg
= qla24xx_read_window(reg
, 0xB010, 16, iter_reg
);
1933 iter_reg
= qla24xx_read_window(reg
, 0xB020, 16, iter_reg
);
1934 iter_reg
= qla24xx_read_window(reg
, 0xB030, 16, iter_reg
);
1935 iter_reg
= qla24xx_read_window(reg
, 0xB040, 16, iter_reg
);
1936 iter_reg
= qla24xx_read_window(reg
, 0xB050, 16, iter_reg
);
1937 iter_reg
= qla24xx_read_window(reg
, 0xB060, 16, iter_reg
);
1938 iter_reg
= qla24xx_read_window(reg
, 0xB070, 16, iter_reg
);
1939 iter_reg
= qla24xx_read_window(reg
, 0xB100, 16, iter_reg
);
1940 iter_reg
= qla24xx_read_window(reg
, 0xB110, 16, iter_reg
);
1941 iter_reg
= qla24xx_read_window(reg
, 0xB120, 16, iter_reg
);
1942 iter_reg
= qla24xx_read_window(reg
, 0xB130, 16, iter_reg
);
1943 iter_reg
= qla24xx_read_window(reg
, 0xB140, 16, iter_reg
);
1944 iter_reg
= qla24xx_read_window(reg
, 0xB150, 16, iter_reg
);
1945 iter_reg
= qla24xx_read_window(reg
, 0xB160, 16, iter_reg
);
1946 qla24xx_read_window(reg
, 0xB170, 16, iter_reg
);
1948 iter_reg
= fw
->aseq_0_reg
;
1949 iter_reg
= qla24xx_read_window(reg
, 0xB0C0, 16, iter_reg
);
1950 qla24xx_read_window(reg
, 0xB0D0, 16, iter_reg
);
1952 qla24xx_read_window(reg
, 0xB0E0, 16, fw
->aseq_1_reg
);
1953 qla24xx_read_window(reg
, 0xB0F0, 16, fw
->aseq_2_reg
);
1954 qla24xx_read_window(reg
, 0xB1F0, 16, fw
->aseq_3_reg
);
1956 /* Command DMA registers. */
1957 iter_reg
= fw
->cmd_dma_reg
;
1958 iter_reg
= qla24xx_read_window(reg
, 0x7100, 16, iter_reg
);
1959 iter_reg
= qla24xx_read_window(reg
, 0x7120, 16, iter_reg
);
1960 iter_reg
= qla24xx_read_window(reg
, 0x7130, 16, iter_reg
);
1961 qla24xx_read_window(reg
, 0x71F0, 16, iter_reg
);
1964 iter_reg
= fw
->req0_dma_reg
;
1965 iter_reg
= qla24xx_read_window(reg
, 0x7200, 8, iter_reg
);
1966 dmp_reg
= ®
->iobase_q
;
1967 for (cnt
= 0; cnt
< 7; cnt
++)
1968 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1970 iter_reg
= fw
->resp0_dma_reg
;
1971 iter_reg
= qla24xx_read_window(reg
, 0x7300, 8, iter_reg
);
1972 dmp_reg
= ®
->iobase_q
;
1973 for (cnt
= 0; cnt
< 7; cnt
++)
1974 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1976 iter_reg
= fw
->req1_dma_reg
;
1977 iter_reg
= qla24xx_read_window(reg
, 0x7400, 8, iter_reg
);
1978 dmp_reg
= ®
->iobase_q
;
1979 for (cnt
= 0; cnt
< 7; cnt
++)
1980 *iter_reg
++ = htonl(RD_REG_DWORD(dmp_reg
++));
1982 /* Transmit DMA registers. */
1983 iter_reg
= fw
->xmt0_dma_reg
;
1984 iter_reg
= qla24xx_read_window(reg
, 0x7600, 16, iter_reg
);
1985 qla24xx_read_window(reg
, 0x7610, 16, iter_reg
);
1987 iter_reg
= fw
->xmt1_dma_reg
;
1988 iter_reg
= qla24xx_read_window(reg
, 0x7620, 16, iter_reg
);
1989 qla24xx_read_window(reg
, 0x7630, 16, iter_reg
);
1991 iter_reg
= fw
->xmt2_dma_reg
;
1992 iter_reg
= qla24xx_read_window(reg
, 0x7640, 16, iter_reg
);
1993 qla24xx_read_window(reg
, 0x7650, 16, iter_reg
);
1995 iter_reg
= fw
->xmt3_dma_reg
;
1996 iter_reg
= qla24xx_read_window(reg
, 0x7660, 16, iter_reg
);
1997 qla24xx_read_window(reg
, 0x7670, 16, iter_reg
);
1999 iter_reg
= fw
->xmt4_dma_reg
;
2000 iter_reg
= qla24xx_read_window(reg
, 0x7680, 16, iter_reg
);
2001 qla24xx_read_window(reg
, 0x7690, 16, iter_reg
);
2003 qla24xx_read_window(reg
, 0x76A0, 16, fw
->xmt_data_dma_reg
);
2005 /* Receive DMA registers. */
2006 iter_reg
= fw
->rcvt0_data_dma_reg
;
2007 iter_reg
= qla24xx_read_window(reg
, 0x7700, 16, iter_reg
);
2008 qla24xx_read_window(reg
, 0x7710, 16, iter_reg
);
2010 iter_reg
= fw
->rcvt1_data_dma_reg
;
2011 iter_reg
= qla24xx_read_window(reg
, 0x7720, 16, iter_reg
);
2012 qla24xx_read_window(reg
, 0x7730, 16, iter_reg
);
2014 /* RISC registers. */
2015 iter_reg
= fw
->risc_gp_reg
;
2016 iter_reg
= qla24xx_read_window(reg
, 0x0F00, 16, iter_reg
);
2017 iter_reg
= qla24xx_read_window(reg
, 0x0F10, 16, iter_reg
);
2018 iter_reg
= qla24xx_read_window(reg
, 0x0F20, 16, iter_reg
);
2019 iter_reg
= qla24xx_read_window(reg
, 0x0F30, 16, iter_reg
);
2020 iter_reg
= qla24xx_read_window(reg
, 0x0F40, 16, iter_reg
);
2021 iter_reg
= qla24xx_read_window(reg
, 0x0F50, 16, iter_reg
);
2022 iter_reg
= qla24xx_read_window(reg
, 0x0F60, 16, iter_reg
);
2023 qla24xx_read_window(reg
, 0x0F70, 16, iter_reg
);
2025 /* Local memory controller registers. */
2026 iter_reg
= fw
->lmc_reg
;
2027 iter_reg
= qla24xx_read_window(reg
, 0x3000, 16, iter_reg
);
2028 iter_reg
= qla24xx_read_window(reg
, 0x3010, 16, iter_reg
);
2029 iter_reg
= qla24xx_read_window(reg
, 0x3020, 16, iter_reg
);
2030 iter_reg
= qla24xx_read_window(reg
, 0x3030, 16, iter_reg
);
2031 iter_reg
= qla24xx_read_window(reg
, 0x3040, 16, iter_reg
);
2032 iter_reg
= qla24xx_read_window(reg
, 0x3050, 16, iter_reg
);
2033 iter_reg
= qla24xx_read_window(reg
, 0x3060, 16, iter_reg
);
2034 qla24xx_read_window(reg
, 0x3070, 16, iter_reg
);
2036 /* Fibre Protocol Module registers. */
2037 iter_reg
= fw
->fpm_hdw_reg
;
2038 iter_reg
= qla24xx_read_window(reg
, 0x4000, 16, iter_reg
);
2039 iter_reg
= qla24xx_read_window(reg
, 0x4010, 16, iter_reg
);
2040 iter_reg
= qla24xx_read_window(reg
, 0x4020, 16, iter_reg
);
2041 iter_reg
= qla24xx_read_window(reg
, 0x4030, 16, iter_reg
);
2042 iter_reg
= qla24xx_read_window(reg
, 0x4040, 16, iter_reg
);
2043 iter_reg
= qla24xx_read_window(reg
, 0x4050, 16, iter_reg
);
2044 iter_reg
= qla24xx_read_window(reg
, 0x4060, 16, iter_reg
);
2045 iter_reg
= qla24xx_read_window(reg
, 0x4070, 16, iter_reg
);
2046 iter_reg
= qla24xx_read_window(reg
, 0x4080, 16, iter_reg
);
2047 iter_reg
= qla24xx_read_window(reg
, 0x4090, 16, iter_reg
);
2048 iter_reg
= qla24xx_read_window(reg
, 0x40A0, 16, iter_reg
);
2049 iter_reg
= qla24xx_read_window(reg
, 0x40B0, 16, iter_reg
);
2050 iter_reg
= qla24xx_read_window(reg
, 0x40C0, 16, iter_reg
);
2051 iter_reg
= qla24xx_read_window(reg
, 0x40D0, 16, iter_reg
);
2052 iter_reg
= qla24xx_read_window(reg
, 0x40E0, 16, iter_reg
);
2053 qla24xx_read_window(reg
, 0x40F0, 16, iter_reg
);
2055 /* RQ0 Array registers. */
2056 iter_reg
= fw
->rq0_array_reg
;
2057 iter_reg
= qla24xx_read_window(reg
, 0x5C00, 16, iter_reg
);
2058 iter_reg
= qla24xx_read_window(reg
, 0x5C10, 16, iter_reg
);
2059 iter_reg
= qla24xx_read_window(reg
, 0x5C20, 16, iter_reg
);
2060 iter_reg
= qla24xx_read_window(reg
, 0x5C30, 16, iter_reg
);
2061 iter_reg
= qla24xx_read_window(reg
, 0x5C40, 16, iter_reg
);
2062 iter_reg
= qla24xx_read_window(reg
, 0x5C50, 16, iter_reg
);
2063 iter_reg
= qla24xx_read_window(reg
, 0x5C60, 16, iter_reg
);
2064 iter_reg
= qla24xx_read_window(reg
, 0x5C70, 16, iter_reg
);
2065 iter_reg
= qla24xx_read_window(reg
, 0x5C80, 16, iter_reg
);
2066 iter_reg
= qla24xx_read_window(reg
, 0x5C90, 16, iter_reg
);
2067 iter_reg
= qla24xx_read_window(reg
, 0x5CA0, 16, iter_reg
);
2068 iter_reg
= qla24xx_read_window(reg
, 0x5CB0, 16, iter_reg
);
2069 iter_reg
= qla24xx_read_window(reg
, 0x5CC0, 16, iter_reg
);
2070 iter_reg
= qla24xx_read_window(reg
, 0x5CD0, 16, iter_reg
);
2071 iter_reg
= qla24xx_read_window(reg
, 0x5CE0, 16, iter_reg
);
2072 qla24xx_read_window(reg
, 0x5CF0, 16, iter_reg
);
2074 /* RQ1 Array registers. */
2075 iter_reg
= fw
->rq1_array_reg
;
2076 iter_reg
= qla24xx_read_window(reg
, 0x5D00, 16, iter_reg
);
2077 iter_reg
= qla24xx_read_window(reg
, 0x5D10, 16, iter_reg
);
2078 iter_reg
= qla24xx_read_window(reg
, 0x5D20, 16, iter_reg
);
2079 iter_reg
= qla24xx_read_window(reg
, 0x5D30, 16, iter_reg
);
2080 iter_reg
= qla24xx_read_window(reg
, 0x5D40, 16, iter_reg
);
2081 iter_reg
= qla24xx_read_window(reg
, 0x5D50, 16, iter_reg
);
2082 iter_reg
= qla24xx_read_window(reg
, 0x5D60, 16, iter_reg
);
2083 iter_reg
= qla24xx_read_window(reg
, 0x5D70, 16, iter_reg
);
2084 iter_reg
= qla24xx_read_window(reg
, 0x5D80, 16, iter_reg
);
2085 iter_reg
= qla24xx_read_window(reg
, 0x5D90, 16, iter_reg
);
2086 iter_reg
= qla24xx_read_window(reg
, 0x5DA0, 16, iter_reg
);
2087 iter_reg
= qla24xx_read_window(reg
, 0x5DB0, 16, iter_reg
);
2088 iter_reg
= qla24xx_read_window(reg
, 0x5DC0, 16, iter_reg
);
2089 iter_reg
= qla24xx_read_window(reg
, 0x5DD0, 16, iter_reg
);
2090 iter_reg
= qla24xx_read_window(reg
, 0x5DE0, 16, iter_reg
);
2091 qla24xx_read_window(reg
, 0x5DF0, 16, iter_reg
);
2093 /* RP0 Array registers. */
2094 iter_reg
= fw
->rp0_array_reg
;
2095 iter_reg
= qla24xx_read_window(reg
, 0x5E00, 16, iter_reg
);
2096 iter_reg
= qla24xx_read_window(reg
, 0x5E10, 16, iter_reg
);
2097 iter_reg
= qla24xx_read_window(reg
, 0x5E20, 16, iter_reg
);
2098 iter_reg
= qla24xx_read_window(reg
, 0x5E30, 16, iter_reg
);
2099 iter_reg
= qla24xx_read_window(reg
, 0x5E40, 16, iter_reg
);
2100 iter_reg
= qla24xx_read_window(reg
, 0x5E50, 16, iter_reg
);
2101 iter_reg
= qla24xx_read_window(reg
, 0x5E60, 16, iter_reg
);
2102 iter_reg
= qla24xx_read_window(reg
, 0x5E70, 16, iter_reg
);
2103 iter_reg
= qla24xx_read_window(reg
, 0x5E80, 16, iter_reg
);
2104 iter_reg
= qla24xx_read_window(reg
, 0x5E90, 16, iter_reg
);
2105 iter_reg
= qla24xx_read_window(reg
, 0x5EA0, 16, iter_reg
);
2106 iter_reg
= qla24xx_read_window(reg
, 0x5EB0, 16, iter_reg
);
2107 iter_reg
= qla24xx_read_window(reg
, 0x5EC0, 16, iter_reg
);
2108 iter_reg
= qla24xx_read_window(reg
, 0x5ED0, 16, iter_reg
);
2109 iter_reg
= qla24xx_read_window(reg
, 0x5EE0, 16, iter_reg
);
2110 qla24xx_read_window(reg
, 0x5EF0, 16, iter_reg
);
2112 /* RP1 Array registers. */
2113 iter_reg
= fw
->rp1_array_reg
;
2114 iter_reg
= qla24xx_read_window(reg
, 0x5F00, 16, iter_reg
);
2115 iter_reg
= qla24xx_read_window(reg
, 0x5F10, 16, iter_reg
);
2116 iter_reg
= qla24xx_read_window(reg
, 0x5F20, 16, iter_reg
);
2117 iter_reg
= qla24xx_read_window(reg
, 0x5F30, 16, iter_reg
);
2118 iter_reg
= qla24xx_read_window(reg
, 0x5F40, 16, iter_reg
);
2119 iter_reg
= qla24xx_read_window(reg
, 0x5F50, 16, iter_reg
);
2120 iter_reg
= qla24xx_read_window(reg
, 0x5F60, 16, iter_reg
);
2121 iter_reg
= qla24xx_read_window(reg
, 0x5F70, 16, iter_reg
);
2122 iter_reg
= qla24xx_read_window(reg
, 0x5F80, 16, iter_reg
);
2123 iter_reg
= qla24xx_read_window(reg
, 0x5F90, 16, iter_reg
);
2124 iter_reg
= qla24xx_read_window(reg
, 0x5FA0, 16, iter_reg
);
2125 iter_reg
= qla24xx_read_window(reg
, 0x5FB0, 16, iter_reg
);
2126 iter_reg
= qla24xx_read_window(reg
, 0x5FC0, 16, iter_reg
);
2127 iter_reg
= qla24xx_read_window(reg
, 0x5FD0, 16, iter_reg
);
2128 iter_reg
= qla24xx_read_window(reg
, 0x5FE0, 16, iter_reg
);
2129 qla24xx_read_window(reg
, 0x5FF0, 16, iter_reg
);
2131 iter_reg
= fw
->at0_array_reg
;
2132 iter_reg
= qla24xx_read_window(reg
, 0x7080, 16, iter_reg
);
2133 iter_reg
= qla24xx_read_window(reg
, 0x7090, 16, iter_reg
);
2134 iter_reg
= qla24xx_read_window(reg
, 0x70A0, 16, iter_reg
);
2135 iter_reg
= qla24xx_read_window(reg
, 0x70B0, 16, iter_reg
);
2136 iter_reg
= qla24xx_read_window(reg
, 0x70C0, 16, iter_reg
);
2137 iter_reg
= qla24xx_read_window(reg
, 0x70D0, 16, iter_reg
);
2138 iter_reg
= qla24xx_read_window(reg
, 0x70E0, 16, iter_reg
);
2139 qla24xx_read_window(reg
, 0x70F0, 16, iter_reg
);
2141 /* I/O Queue Control registers. */
2142 qla24xx_read_window(reg
, 0x7800, 16, fw
->queue_control_reg
);
2144 /* Frame Buffer registers. */
2145 iter_reg
= fw
->fb_hdw_reg
;
2146 iter_reg
= qla24xx_read_window(reg
, 0x6000, 16, iter_reg
);
2147 iter_reg
= qla24xx_read_window(reg
, 0x6010, 16, iter_reg
);
2148 iter_reg
= qla24xx_read_window(reg
, 0x6020, 16, iter_reg
);
2149 iter_reg
= qla24xx_read_window(reg
, 0x6030, 16, iter_reg
);
2150 iter_reg
= qla24xx_read_window(reg
, 0x6040, 16, iter_reg
);
2151 iter_reg
= qla24xx_read_window(reg
, 0x6060, 16, iter_reg
);
2152 iter_reg
= qla24xx_read_window(reg
, 0x6070, 16, iter_reg
);
2153 iter_reg
= qla24xx_read_window(reg
, 0x6100, 16, iter_reg
);
2154 iter_reg
= qla24xx_read_window(reg
, 0x6130, 16, iter_reg
);
2155 iter_reg
= qla24xx_read_window(reg
, 0x6150, 16, iter_reg
);
2156 iter_reg
= qla24xx_read_window(reg
, 0x6170, 16, iter_reg
);
2157 iter_reg
= qla24xx_read_window(reg
, 0x6190, 16, iter_reg
);
2158 iter_reg
= qla24xx_read_window(reg
, 0x61B0, 16, iter_reg
);
2159 iter_reg
= qla24xx_read_window(reg
, 0x61C0, 16, iter_reg
);
2160 iter_reg
= qla24xx_read_window(reg
, 0x6530, 16, iter_reg
);
2161 iter_reg
= qla24xx_read_window(reg
, 0x6540, 16, iter_reg
);
2162 iter_reg
= qla24xx_read_window(reg
, 0x6550, 16, iter_reg
);
2163 iter_reg
= qla24xx_read_window(reg
, 0x6560, 16, iter_reg
);
2164 iter_reg
= qla24xx_read_window(reg
, 0x6570, 16, iter_reg
);
2165 iter_reg
= qla24xx_read_window(reg
, 0x6580, 16, iter_reg
);
2166 iter_reg
= qla24xx_read_window(reg
, 0x6590, 16, iter_reg
);
2167 iter_reg
= qla24xx_read_window(reg
, 0x65A0, 16, iter_reg
);
2168 iter_reg
= qla24xx_read_window(reg
, 0x65B0, 16, iter_reg
);
2169 iter_reg
= qla24xx_read_window(reg
, 0x65C0, 16, iter_reg
);
2170 iter_reg
= qla24xx_read_window(reg
, 0x65D0, 16, iter_reg
);
2171 iter_reg
= qla24xx_read_window(reg
, 0x65E0, 16, iter_reg
);
2172 qla24xx_read_window(reg
, 0x6F00, 16, iter_reg
);
2174 /* Multi queue registers */
2175 nxt_chain
= qla25xx_copy_mq(ha
, (void *)ha
->fw_dump
+ ha
->chain_offset
,
2178 rval
= qla24xx_soft_reset(ha
);
2179 if (rval
!= QLA_SUCCESS
) {
2180 ql_log(ql_log_warn
, vha
, 0xd00e,
2181 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2184 ql_log(ql_log_warn
, vha
, 0xd00f, "try a bigger hammer!!!\n");
2186 WRT_REG_DWORD(®
->hccr
, HCCRX_SET_RISC_RESET
);
2187 RD_REG_DWORD(®
->hccr
);
2189 WRT_REG_DWORD(®
->hccr
, HCCRX_REL_RISC_PAUSE
);
2190 RD_REG_DWORD(®
->hccr
);
2192 WRT_REG_DWORD(®
->hccr
, HCCRX_CLR_RISC_RESET
);
2193 RD_REG_DWORD(®
->hccr
);
2195 for (cnt
= 30000; cnt
&& (RD_REG_WORD(®
->mailbox0
)); cnt
--)
2200 nxt
+= sizeof(fw
->code_ram
),
2201 nxt
+= (ha
->fw_memory_size
- 0x100000 + 1);
2204 ql_log(ql_log_warn
, vha
, 0xd010,
2205 "bigger hammer success?\n");
2208 rval
= qla24xx_dump_memory(ha
, fw
->code_ram
, sizeof(fw
->code_ram
),
2210 if (rval
!= QLA_SUCCESS
)
2211 goto qla83xx_fw_dump_failed_0
;
2214 nxt
= qla2xxx_copy_queues(ha
, nxt
);
2216 nxt
= qla24xx_copy_eft(ha
, nxt
);
2218 /* Chain entries -- started with MQ. */
2219 nxt_chain
= qla25xx_copy_fce(ha
, nxt_chain
, &last_chain
);
2220 nxt_chain
= qla25xx_copy_mqueues(ha
, nxt_chain
, &last_chain
);
2222 ha
->fw_dump
->version
|= __constant_htonl(DUMP_CHAIN_VARIANT
);
2223 *last_chain
|= __constant_htonl(DUMP_CHAIN_LAST
);
2226 /* Adjust valid length. */
2227 ha
->fw_dump_len
= (nxt_chain
- (void *)ha
->fw_dump
);
2229 qla83xx_fw_dump_failed_0
:
2230 qla2xxx_dump_post_process(base_vha
, rval
);
2232 qla83xx_fw_dump_failed
:
2233 if (!hardware_locked
)
2234 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
2237 /****************************************************************************/
2238 /* Driver Debug Functions. */
2239 /****************************************************************************/
2242 ql_mask_match(uint32_t level
)
2244 if (ql2xextended_error_logging
== 1)
2245 ql2xextended_error_logging
= QL_DBG_DEFAULT1_MASK
;
2246 return (level
& ql2xextended_error_logging
) == level
;
2250 * This function is for formatting and logging debug information.
2251 * It is to be used when vha is available. It formats the message
2252 * and logs it to the messages file.
2254 * level: The level of the debug messages to be printed.
2255 * If ql2xextended_error_logging value is correctly set,
2256 * this message will appear in the messages file.
2257 * vha: Pointer to the scsi_qla_host_t.
2258 * id: This is a unique identifier for the level. It identifies the
2259 * part of the code from where the message originated.
2260 * msg: The message to be displayed.
2263 ql_dbg(uint32_t level
, scsi_qla_host_t
*vha
, int32_t id
, const char *fmt
, ...)
2266 struct va_format vaf
;
2268 if (!ql_mask_match(level
))
2277 const struct pci_dev
*pdev
= vha
->hw
->pdev
;
2278 /* <module-name> <pci-name> <msg-id>:<host> Message */
2279 pr_warn("%s [%s]-%04x:%ld: %pV",
2280 QL_MSGHDR
, dev_name(&(pdev
->dev
)), id
+ ql_dbg_offset
,
2281 vha
->host_no
, &vaf
);
2283 pr_warn("%s [%s]-%04x: : %pV",
2284 QL_MSGHDR
, "0000:00:00.0", id
+ ql_dbg_offset
, &vaf
);
2292 * This function is for formatting and logging debug information.
2293 * It is to be used when vha is not available and pci is availble,
2294 * i.e., before host allocation. It formats the message and logs it
2295 * to the messages file.
2297 * level: The level of the debug messages to be printed.
2298 * If ql2xextended_error_logging value is correctly set,
2299 * this message will appear in the messages file.
2300 * pdev: Pointer to the struct pci_dev.
2301 * id: This is a unique id for the level. It identifies the part
2302 * of the code from where the message originated.
2303 * msg: The message to be displayed.
2306 ql_dbg_pci(uint32_t level
, struct pci_dev
*pdev
, int32_t id
,
2307 const char *fmt
, ...)
2310 struct va_format vaf
;
2314 if (!ql_mask_match(level
))
2322 /* <module-name> <dev-name>:<msg-id> Message */
2323 pr_warn("%s [%s]-%04x: : %pV",
2324 QL_MSGHDR
, dev_name(&(pdev
->dev
)), id
+ ql_dbg_offset
, &vaf
);
2330 * This function is for formatting and logging log messages.
2331 * It is to be used when vha is available. It formats the message
2332 * and logs it to the messages file. All the messages will be logged
2333 * irrespective of value of ql2xextended_error_logging.
2335 * level: The level of the log messages to be printed in the
2337 * vha: Pointer to the scsi_qla_host_t
2338 * id: This is a unique id for the level. It identifies the
2339 * part of the code from where the message originated.
2340 * msg: The message to be displayed.
2343 ql_log(uint32_t level
, scsi_qla_host_t
*vha
, int32_t id
, const char *fmt
, ...)
2346 struct va_format vaf
;
2349 if (level
> ql_errlev
)
2353 const struct pci_dev
*pdev
= vha
->hw
->pdev
;
2354 /* <module-name> <msg-id>:<host> Message */
2355 snprintf(pbuf
, sizeof(pbuf
), "%s [%s]-%04x:%ld: ",
2356 QL_MSGHDR
, dev_name(&(pdev
->dev
)), id
, vha
->host_no
);
2358 snprintf(pbuf
, sizeof(pbuf
), "%s [%s]-%04x: : ",
2359 QL_MSGHDR
, "0000:00:00.0", id
);
2361 pbuf
[sizeof(pbuf
) - 1] = 0;
2369 case ql_log_fatal
: /* FATAL LOG */
2370 pr_crit("%s%pV", pbuf
, &vaf
);
2373 pr_err("%s%pV", pbuf
, &vaf
);
2376 pr_warn("%s%pV", pbuf
, &vaf
);
2379 pr_info("%s%pV", pbuf
, &vaf
);
2387 * This function is for formatting and logging log messages.
2388 * It is to be used when vha is not available and pci is availble,
2389 * i.e., before host allocation. It formats the message and logs
2390 * it to the messages file. All the messages are logged irrespective
2391 * of the value of ql2xextended_error_logging.
2393 * level: The level of the log messages to be printed in the
2395 * pdev: Pointer to the struct pci_dev.
2396 * id: This is a unique id for the level. It identifies the
2397 * part of the code from where the message originated.
2398 * msg: The message to be displayed.
2401 ql_log_pci(uint32_t level
, struct pci_dev
*pdev
, int32_t id
,
2402 const char *fmt
, ...)
2405 struct va_format vaf
;
2410 if (level
> ql_errlev
)
2413 /* <module-name> <dev-name>:<msg-id> Message */
2414 snprintf(pbuf
, sizeof(pbuf
), "%s [%s]-%04x: : ",
2415 QL_MSGHDR
, dev_name(&(pdev
->dev
)), id
);
2416 pbuf
[sizeof(pbuf
) - 1] = 0;
2424 case ql_log_fatal
: /* FATAL LOG */
2425 pr_crit("%s%pV", pbuf
, &vaf
);
2428 pr_err("%s%pV", pbuf
, &vaf
);
2431 pr_warn("%s%pV", pbuf
, &vaf
);
2434 pr_info("%s%pV", pbuf
, &vaf
);
2442 ql_dump_regs(uint32_t level
, scsi_qla_host_t
*vha
, int32_t id
)
2445 struct qla_hw_data
*ha
= vha
->hw
;
2446 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2447 struct device_reg_24xx __iomem
*reg24
= &ha
->iobase
->isp24
;
2448 struct device_reg_82xx __iomem
*reg82
= &ha
->iobase
->isp82
;
2449 uint16_t __iomem
*mbx_reg
;
2451 if (!ql_mask_match(level
))
2455 mbx_reg
= ®82
->mailbox_in
[0];
2456 else if (IS_FWI2_CAPABLE(ha
))
2457 mbx_reg
= ®24
->mailbox0
;
2459 mbx_reg
= MAILBOX_REG(ha
, reg
, 0);
2461 ql_dbg(level
, vha
, id
, "Mailbox registers:\n");
2462 for (i
= 0; i
< 6; i
++)
2463 ql_dbg(level
, vha
, id
,
2464 "mbox[%d] 0x%04x\n", i
, RD_REG_WORD(mbx_reg
++));
2469 ql_dump_buffer(uint32_t level
, scsi_qla_host_t
*vha
, int32_t id
,
2470 uint8_t *b
, uint32_t size
)
2475 if (!ql_mask_match(level
))
2478 ql_dbg(level
, vha
, id
, " 0 1 2 3 4 5 6 7 8 "
2479 "9 Ah Bh Ch Dh Eh Fh\n");
2480 ql_dbg(level
, vha
, id
, "----------------------------------"
2481 "----------------------------\n");
2483 ql_dbg(level
, vha
, id
, " ");
2484 for (cnt
= 0; cnt
< size
;) {
2486 printk("%02x", (uint32_t) c
);
2494 ql_dbg(level
, vha
, id
, "\n");