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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / pm8001 / pm8001_hwi.h
1 /*
2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #ifndef _PMC8001_REG_H_
41 #define _PMC8001_REG_H_
42
43 #include <linux/types.h>
44 #include <scsi/libsas.h>
45
46
47 /* for Request Opcode of IOMB */
48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
54 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
55 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
56 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
57 #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
58 #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
59 #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
60 #define OPC_INB_SSP_ABORT 15 /* 0x00F */
61 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
62 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
63 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
64 /* SMP_RESPONSE is removed */
65 #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
66 #define OPC_INB_SMP_ABORT 20 /* 0x014 */
67 #define OPC_INB_REG_DEV 22 /* 0x016 */
68 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
69 #define OPC_INB_SATA_ABORT 24 /* 0x018 */
70 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
71 #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73 #define OPC_INB_GPIO 34 /* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76 #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
77 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
78 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
79 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
80 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
81 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
82 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
83 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
84 #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
85
86 /* for Response Opcode of IOMB */
87 #define OPC_OUB_ECHO 1 /* 0x001 */
88 #define OPC_OUB_HW_EVENT 4 /* 0x004 */
89 #define OPC_OUB_SSP_COMP 5 /* 0x005 */
90 #define OPC_OUB_SMP_COMP 6 /* 0x006 */
91 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
92 #define OPC_OUB_DEV_REGIST 10 /* 0x00A */
93 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
94 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
95 #define OPC_OUB_SATA_COMP 13 /* 0x00D */
96 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
97 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
98 #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
99 /* SMP_RECEIVED Notification is removed */
100 #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
101 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
102 #define OPC_OUB_DEV_INFO 19 /* 0x013 */
103 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
104 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
105 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
106 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
107 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
108 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
109 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
110 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
111 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
112 #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
113 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
114 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
115 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
116 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
117 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
118 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
119 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
120 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
121 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
122 #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
123
124 /* for phy start*/
125 #define SPINHOLD_DISABLE (0x00 << 14)
126 #define SPINHOLD_ENABLE (0x01 << 14)
127 #define LINKMODE_SAS (0x01 << 12)
128 #define LINKMODE_DSATA (0x02 << 12)
129 #define LINKMODE_AUTO (0x03 << 12)
130 #define LINKRATE_15 (0x01 << 8)
131 #define LINKRATE_30 (0x02 << 8)
132 #define LINKRATE_60 (0x04 << 8)
133
134 /* for new SPC controllers MEMBASE III is shared between BIOS and DATA */
135 #define GSM_SM_BASE 0x4F0000
136 struct mpi_msg_hdr{
137 __le32 header; /* Bits [11:0] - Message operation code */
138 /* Bits [15:12] - Message Category */
139 /* Bits [21:16] - Outboundqueue ID for the
140 operation completion message */
141 /* Bits [23:22] - Reserved */
142 /* Bits [28:24] - Buffer Count, indicates how
143 many buffer are allocated for the massage */
144 /* Bits [30:29] - Reserved */
145 /* Bits [31] - Message Valid bit */
146 } __attribute__((packed, aligned(4)));
147
148
149 /*
150 * brief the data structure of PHY Start Command
151 * use to describe enable the phy (64 bytes)
152 */
153 struct phy_start_req {
154 __le32 tag;
155 __le32 ase_sh_lm_slr_phyid;
156 struct sas_identify_frame sas_identify;
157 u32 reserved[5];
158 } __attribute__((packed, aligned(4)));
159
160
161 /*
162 * brief the data structure of PHY Start Command
163 * use to disable the phy (64 bytes)
164 */
165 struct phy_stop_req {
166 __le32 tag;
167 __le32 phy_id;
168 u32 reserved[13];
169 } __attribute__((packed, aligned(4)));
170
171
172 /* set device bits fis - device to host */
173 struct set_dev_bits_fis {
174 u8 fis_type; /* 0xA1*/
175 u8 n_i_pmport;
176 /* b7 : n Bit. Notification bit. If set device needs attention. */
177 /* b6 : i Bit. Interrupt Bit */
178 /* b5-b4: reserved2 */
179 /* b3-b0: PM Port */
180 u8 status;
181 u8 error;
182 u32 _r_a;
183 } __attribute__ ((packed));
184 /* PIO setup FIS - device to host */
185 struct pio_setup_fis {
186 u8 fis_type; /* 0x5f */
187 u8 i_d_pmPort;
188 /* b7 : reserved */
189 /* b6 : i bit. Interrupt bit */
190 /* b5 : d bit. data transfer direction. set to 1 for device to host
191 xfer */
192 /* b4 : reserved */
193 /* b3-b0: PM Port */
194 u8 status;
195 u8 error;
196 u8 lbal;
197 u8 lbam;
198 u8 lbah;
199 u8 device;
200 u8 lbal_exp;
201 u8 lbam_exp;
202 u8 lbah_exp;
203 u8 _r_a;
204 u8 sector_count;
205 u8 sector_count_exp;
206 u8 _r_b;
207 u8 e_status;
208 u8 _r_c[2];
209 u8 transfer_count;
210 } __attribute__ ((packed));
211
212 /*
213 * brief the data structure of SATA Completion Response
214 * use to describe the sata task response (64 bytes)
215 */
216 struct sata_completion_resp {
217 __le32 tag;
218 __le32 status;
219 __le32 param;
220 u32 sata_resp[12];
221 } __attribute__((packed, aligned(4)));
222
223
224 /*
225 * brief the data structure of SAS HW Event Notification
226 * use to alert the host about the hardware event(64 bytes)
227 */
228 struct hw_event_resp {
229 __le32 lr_evt_status_phyid_portid;
230 __le32 evt_param;
231 __le32 npip_portstate;
232 struct sas_identify_frame sas_identify;
233 struct dev_to_host_fis sata_fis;
234 } __attribute__((packed, aligned(4)));
235
236
237 /*
238 * brief the data structure of REGISTER DEVICE Command
239 * use to describe MPI REGISTER DEVICE Command (64 bytes)
240 */
241
242 struct reg_dev_req {
243 __le32 tag;
244 __le32 phyid_portid;
245 __le32 dtype_dlr_retry;
246 __le32 firstburstsize_ITNexustimeout;
247 u8 sas_addr[SAS_ADDR_SIZE];
248 __le32 upper_device_id;
249 u32 reserved[8];
250 } __attribute__((packed, aligned(4)));
251
252
253 /*
254 * brief the data structure of DEREGISTER DEVICE Command
255 * use to request spc to remove all internal resources associated
256 * with the device id (64 bytes)
257 */
258
259 struct dereg_dev_req {
260 __le32 tag;
261 __le32 device_id;
262 u32 reserved[13];
263 } __attribute__((packed, aligned(4)));
264
265
266 /*
267 * brief the data structure of DEVICE_REGISTRATION Response
268 * use to notify the completion of the device registration (64 bytes)
269 */
270
271 struct dev_reg_resp {
272 __le32 tag;
273 __le32 status;
274 __le32 device_id;
275 u32 reserved[12];
276 } __attribute__((packed, aligned(4)));
277
278
279 /*
280 * brief the data structure of Local PHY Control Command
281 * use to issue PHY CONTROL to local phy (64 bytes)
282 */
283 struct local_phy_ctl_req {
284 __le32 tag;
285 __le32 phyop_phyid;
286 u32 reserved1[13];
287 } __attribute__((packed, aligned(4)));
288
289
290 /**
291 * brief the data structure of Local Phy Control Response
292 * use to describe MPI Local Phy Control Response (64 bytes)
293 */
294 struct local_phy_ctl_resp {
295 __le32 tag;
296 __le32 phyop_phyid;
297 __le32 status;
298 u32 reserved[12];
299 } __attribute__((packed, aligned(4)));
300
301
302 #define OP_BITS 0x0000FF00
303 #define ID_BITS 0x000000FF
304
305 /*
306 * brief the data structure of PORT Control Command
307 * use to control port properties (64 bytes)
308 */
309
310 struct port_ctl_req {
311 __le32 tag;
312 __le32 portop_portid;
313 __le32 param0;
314 __le32 param1;
315 u32 reserved1[11];
316 } __attribute__((packed, aligned(4)));
317
318
319 /*
320 * brief the data structure of HW Event Ack Command
321 * use to acknowledge receive HW event (64 bytes)
322 */
323
324 struct hw_event_ack_req {
325 __le32 tag;
326 __le32 sea_phyid_portid;
327 __le32 param0;
328 __le32 param1;
329 u32 reserved1[11];
330 } __attribute__((packed, aligned(4)));
331
332
333 /*
334 * brief the data structure of SSP Completion Response
335 * use to indicate a SSP Completion (n bytes)
336 */
337 struct ssp_completion_resp {
338 __le32 tag;
339 __le32 status;
340 __le32 param;
341 __le32 ssptag_rescv_rescpad;
342 struct ssp_response_iu ssp_resp_iu;
343 __le32 residual_count;
344 } __attribute__((packed, aligned(4)));
345
346
347 #define SSP_RESCV_BIT 0x00010000
348
349 /*
350 * brief the data structure of SATA EVNET esponse
351 * use to indicate a SATA Completion (64 bytes)
352 */
353
354 struct sata_event_resp {
355 __le32 tag;
356 __le32 event;
357 __le32 port_id;
358 __le32 device_id;
359 u32 reserved[11];
360 } __attribute__((packed, aligned(4)));
361
362 /*
363 * brief the data structure of SSP EVNET esponse
364 * use to indicate a SSP Completion (64 bytes)
365 */
366
367 struct ssp_event_resp {
368 __le32 tag;
369 __le32 event;
370 __le32 port_id;
371 __le32 device_id;
372 u32 reserved[11];
373 } __attribute__((packed, aligned(4)));
374
375 /**
376 * brief the data structure of General Event Notification Response
377 * use to describe MPI General Event Notification Response (64 bytes)
378 */
379 struct general_event_resp {
380 __le32 status;
381 __le32 inb_IOMB_payload[14];
382 } __attribute__((packed, aligned(4)));
383
384
385 #define GENERAL_EVENT_PAYLOAD 14
386 #define OPCODE_BITS 0x00000fff
387
388 /*
389 * brief the data structure of SMP Request Command
390 * use to describe MPI SMP REQUEST Command (64 bytes)
391 */
392 struct smp_req {
393 __le32 tag;
394 __le32 device_id;
395 __le32 len_ip_ir;
396 /* Bits [0] - Indirect response */
397 /* Bits [1] - Indirect Payload */
398 /* Bits [15:2] - Reserved */
399 /* Bits [23:16] - direct payload Len */
400 /* Bits [31:24] - Reserved */
401 u8 smp_req16[16];
402 union {
403 u8 smp_req[32];
404 struct {
405 __le64 long_req_addr;/* sg dma address, LE */
406 __le32 long_req_size;/* LE */
407 u32 _r_a;
408 __le64 long_resp_addr;/* sg dma address, LE */
409 __le32 long_resp_size;/* LE */
410 u32 _r_b;
411 } long_smp_req;/* sequencer extension */
412 };
413 } __attribute__((packed, aligned(4)));
414 /*
415 * brief the data structure of SMP Completion Response
416 * use to describe MPI SMP Completion Response (64 bytes)
417 */
418 struct smp_completion_resp {
419 __le32 tag;
420 __le32 status;
421 __le32 param;
422 __le32 _r_a[12];
423 } __attribute__((packed, aligned(4)));
424
425 /*
426 *brief the data structure of SSP SMP SATA Abort Command
427 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
428 */
429 struct task_abort_req {
430 __le32 tag;
431 __le32 device_id;
432 __le32 tag_to_abort;
433 __le32 abort_all;
434 u32 reserved[11];
435 } __attribute__((packed, aligned(4)));
436
437 /* These flags used for SSP SMP & SATA Abort */
438 #define ABORT_MASK 0x3
439 #define ABORT_SINGLE 0x0
440 #define ABORT_ALL 0x1
441
442 /**
443 * brief the data structure of SSP SATA SMP Abort Response
444 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
445 */
446 struct task_abort_resp {
447 __le32 tag;
448 __le32 status;
449 __le32 scp;
450 u32 reserved[12];
451 } __attribute__((packed, aligned(4)));
452
453
454 /**
455 * brief the data structure of SAS Diagnostic Start/End Command
456 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
457 */
458 struct sas_diag_start_end_req {
459 __le32 tag;
460 __le32 operation_phyid;
461 u32 reserved[13];
462 } __attribute__((packed, aligned(4)));
463
464
465 /**
466 * brief the data structure of SAS Diagnostic Execute Command
467 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
468 */
469 struct sas_diag_execute_req{
470 __le32 tag;
471 __le32 cmdtype_cmddesc_phyid;
472 __le32 pat1_pat2;
473 __le32 threshold;
474 __le32 codepat_errmsk;
475 __le32 pmon;
476 __le32 pERF1CTL;
477 u32 reserved[8];
478 } __attribute__((packed, aligned(4)));
479
480
481 #define SAS_DIAG_PARAM_BYTES 24
482
483 /*
484 * brief the data structure of Set Device State Command
485 * use to describe MPI Set Device State Command (64 bytes)
486 */
487 struct set_dev_state_req {
488 __le32 tag;
489 __le32 device_id;
490 __le32 nds;
491 u32 reserved[12];
492 } __attribute__((packed, aligned(4)));
493
494 /*
495 * brief the data structure of sas_re_initialization
496 */
497 struct sas_re_initialization_req {
498
499 __le32 tag;
500 __le32 SSAHOLT;/* bit29-set max port;
501 ** bit28-set open reject cmd retries.
502 ** bit27-set open reject data retries.
503 ** bit26-set open reject option, remap:1 or not:0.
504 ** bit25-set sata head of line time out.
505 */
506 __le32 reserved_maxPorts;
507 __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16;
508 * data retries: bit15-bit0.
509 */
510 __le32 sata_hol_tmo;
511 u32 reserved1[10];
512 } __attribute__((packed, aligned(4)));
513
514 /*
515 * brief the data structure of SATA Start Command
516 * use to describe MPI SATA IO Start Command (64 bytes)
517 */
518
519 struct sata_start_req {
520 __le32 tag;
521 __le32 device_id;
522 __le32 data_len;
523 __le32 ncqtag_atap_dir_m;
524 struct host_to_dev_fis sata_fis;
525 u32 reserved1;
526 u32 reserved2;
527 u32 addr_low;
528 u32 addr_high;
529 __le32 len;
530 __le32 esgl;
531 } __attribute__((packed, aligned(4)));
532
533 /**
534 * brief the data structure of SSP INI TM Start Command
535 * use to describe MPI SSP INI TM Start Command (64 bytes)
536 */
537 struct ssp_ini_tm_start_req {
538 __le32 tag;
539 __le32 device_id;
540 __le32 relate_tag;
541 __le32 tmf;
542 u8 lun[8];
543 __le32 ds_ads_m;
544 u32 reserved[8];
545 } __attribute__((packed, aligned(4)));
546
547
548 struct ssp_info_unit {
549 u8 lun[8];/* SCSI Logical Unit Number */
550 u8 reserved1;/* reserved */
551 u8 efb_prio_attr;
552 /* B7 : enabledFirstBurst */
553 /* B6-3 : taskPriority */
554 /* B2-0 : taskAttribute */
555 u8 reserved2; /* reserved */
556 u8 additional_cdb_len;
557 /* B7-2 : additional_cdb_len */
558 /* B1-0 : reserved */
559 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
560 } __attribute__((packed, aligned(4)));
561
562
563 /**
564 * brief the data structure of SSP INI IO Start Command
565 * use to describe MPI SSP INI IO Start Command (64 bytes)
566 */
567 struct ssp_ini_io_start_req {
568 __le32 tag;
569 __le32 device_id;
570 __le32 data_len;
571 __le32 dir_m_tlr;
572 struct ssp_info_unit ssp_iu;
573 __le32 addr_low;
574 __le32 addr_high;
575 __le32 len;
576 __le32 esgl;
577 } __attribute__((packed, aligned(4)));
578
579
580 /**
581 * brief the data structure of Firmware download
582 * use to describe MPI FW DOWNLOAD Command (64 bytes)
583 */
584 struct fw_flash_Update_req {
585 __le32 tag;
586 __le32 cur_image_offset;
587 __le32 cur_image_len;
588 __le32 total_image_len;
589 u32 reserved0[7];
590 __le32 sgl_addr_lo;
591 __le32 sgl_addr_hi;
592 __le32 len;
593 __le32 ext_reserved;
594 } __attribute__((packed, aligned(4)));
595
596
597 #define FWFLASH_IOMB_RESERVED_LEN 0x07
598 /**
599 * brief the data structure of FW_FLASH_UPDATE Response
600 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
601 *
602 */
603 struct fw_flash_Update_resp {
604 __le32 tag;
605 __le32 status;
606 u32 reserved[13];
607 } __attribute__((packed, aligned(4)));
608
609
610 /**
611 * brief the data structure of Get NVM Data Command
612 * use to get data from NVM in HBA(64 bytes)
613 */
614 struct get_nvm_data_req {
615 __le32 tag;
616 __le32 len_ir_vpdd;
617 __le32 vpd_offset;
618 u32 reserved[8];
619 __le32 resp_addr_lo;
620 __le32 resp_addr_hi;
621 __le32 resp_len;
622 u32 reserved1;
623 } __attribute__((packed, aligned(4)));
624
625
626 struct set_nvm_data_req {
627 __le32 tag;
628 __le32 len_ir_vpdd;
629 __le32 vpd_offset;
630 __le32 reserved[8];
631 __le32 resp_addr_lo;
632 __le32 resp_addr_hi;
633 __le32 resp_len;
634 u32 reserved1;
635 } __attribute__((packed, aligned(4)));
636
637
638 #define TWI_DEVICE 0x0
639 #define C_SEEPROM 0x1
640 #define VPD_FLASH 0x4
641 #define AAP1_RDUMP 0x5
642 #define IOP_RDUMP 0x6
643 #define EXPAN_ROM 0x7
644
645 #define IPMode 0x80000000
646 #define NVMD_TYPE 0x0000000F
647 #define NVMD_STAT 0x0000FFFF
648 #define NVMD_LEN 0xFF000000
649 /**
650 * brief the data structure of Get NVMD Data Response
651 * use to describe MPI Get NVMD Data Response (64 bytes)
652 */
653 struct get_nvm_data_resp {
654 __le32 tag;
655 __le32 ir_tda_bn_dps_das_nvm;
656 __le32 dlen_status;
657 __le32 nvm_data[12];
658 } __attribute__((packed, aligned(4)));
659
660
661 /**
662 * brief the data structure of SAS Diagnostic Start/End Response
663 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
664 *
665 */
666 struct sas_diag_start_end_resp {
667 __le32 tag;
668 __le32 status;
669 u32 reserved[13];
670 } __attribute__((packed, aligned(4)));
671
672
673 /**
674 * brief the data structure of SAS Diagnostic Execute Response
675 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
676 *
677 */
678 struct sas_diag_execute_resp {
679 __le32 tag;
680 __le32 cmdtype_cmddesc_phyid;
681 __le32 Status;
682 __le32 ReportData;
683 u32 reserved[11];
684 } __attribute__((packed, aligned(4)));
685
686
687 /**
688 * brief the data structure of Set Device State Response
689 * use to describe MPI Set Device State Response (64 bytes)
690 *
691 */
692 struct set_dev_state_resp {
693 __le32 tag;
694 __le32 status;
695 __le32 device_id;
696 __le32 pds_nds;
697 u32 reserved[11];
698 } __attribute__((packed, aligned(4)));
699
700
701 #define NDS_BITS 0x0F
702 #define PDS_BITS 0xF0
703
704 /*
705 * HW Events type
706 */
707
708 #define HW_EVENT_RESET_START 0x01
709 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
710 #define HW_EVENT_PHY_STOP_STATUS 0x03
711 #define HW_EVENT_SAS_PHY_UP 0x04
712 #define HW_EVENT_SATA_PHY_UP 0x05
713 #define HW_EVENT_SATA_SPINUP_HOLD 0x06
714 #define HW_EVENT_PHY_DOWN 0x07
715 #define HW_EVENT_PORT_INVALID 0x08
716 #define HW_EVENT_BROADCAST_CHANGE 0x09
717 #define HW_EVENT_PHY_ERROR 0x0A
718 #define HW_EVENT_BROADCAST_SES 0x0B
719 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
720 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
721 #define HW_EVENT_MALFUNCTION 0x0E
722 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
723 #define HW_EVENT_BROADCAST_EXP 0x10
724 #define HW_EVENT_PHY_START_STATUS 0x11
725 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
726 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
727 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
728 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
729 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
730 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
731 #define HW_EVENT_PORT_RECOVER 0x18
732 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
733 #define HW_EVENT_PORT_RESET_COMPLETE 0x20
734 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
735
736 /* port state */
737 #define PORT_NOT_ESTABLISHED 0x00
738 #define PORT_VALID 0x01
739 #define PORT_LOSTCOMM 0x02
740 #define PORT_IN_RESET 0x04
741 #define PORT_INVALID 0x08
742
743 /*
744 * SSP/SMP/SATA IO Completion Status values
745 */
746
747 #define IO_SUCCESS 0x00
748 #define IO_ABORTED 0x01
749 #define IO_OVERFLOW 0x02
750 #define IO_UNDERFLOW 0x03
751 #define IO_FAILED 0x04
752 #define IO_ABORT_RESET 0x05
753 #define IO_NOT_VALID 0x06
754 #define IO_NO_DEVICE 0x07
755 #define IO_ILLEGAL_PARAMETER 0x08
756 #define IO_LINK_FAILURE 0x09
757 #define IO_PROG_ERROR 0x0A
758 #define IO_EDC_IN_ERROR 0x0B
759 #define IO_EDC_OUT_ERROR 0x0C
760 #define IO_ERROR_HW_TIMEOUT 0x0D
761 #define IO_XFER_ERROR_BREAK 0x0E
762 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
763 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
764 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
765 #define IO_OPEN_CNX_ERROR_BREAK 0x12
766 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
767 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
768 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
769 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
770 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
771 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
772 #define IO_XFER_ERROR_NAK_RECEIVED 0x19
773 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
774 #define IO_XFER_ERROR_PEER_ABORTED 0x1B
775 #define IO_XFER_ERROR_RX_FRAME 0x1C
776 #define IO_XFER_ERROR_DMA 0x1D
777 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
778 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
779 #define IO_XFER_ERROR_SATA 0x20
780 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
781 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
782 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
783 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
784 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
785 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
786 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
787 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
788
789 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
790 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
791 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
792
793 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
794 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
795 #define IO_XFER_CMD_FRAME_ISSUED 0x36
796 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
797 #define IO_PORT_IN_RESET 0x38
798 #define IO_DS_NON_OPERATIONAL 0x39
799 #define IO_DS_IN_RECOVERY 0x3A
800 #define IO_TM_TAG_NOT_FOUND 0x3B
801 #define IO_XFER_PIO_SETUP_ERROR 0x3C
802 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
803 #define IO_DS_IN_ERROR 0x3E
804 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
805 #define IO_ABORT_IN_PROGRESS 0x40
806 #define IO_ABORT_DELAYED 0x41
807 #define IO_INVALID_LENGTH 0x42
808
809 /* WARNING: This error code must always be the last number.
810 * If you add error code, modify this code also
811 * It is used as an index
812 */
813 #define IO_ERROR_UNKNOWN_GENERIC 0x43
814
815 /* MSGU CONFIGURATION TABLE*/
816
817 #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
818 #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
819 #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
820 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
821 #define MSGU_IBDB_SET 0x04
822 #define MSGU_HOST_INT_STATUS 0x08
823 #define MSGU_HOST_INT_MASK 0x0C
824 #define MSGU_IOPIB_INT_STATUS 0x18
825 #define MSGU_IOPIB_INT_MASK 0x1C
826 #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
827 #define MSGU_MSGU_CONTROL 0x24
828 #define MSGU_ODR 0x3C/* RevB */
829 #define MSGU_ODCR 0x40/* RevB */
830 #define MSGU_SCRATCH_PAD_0 0x44
831 #define MSGU_SCRATCH_PAD_1 0x48
832 #define MSGU_SCRATCH_PAD_2 0x4C
833 #define MSGU_SCRATCH_PAD_3 0x50
834 #define MSGU_HOST_SCRATCH_PAD_0 0x54
835 #define MSGU_HOST_SCRATCH_PAD_1 0x58
836 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
837 #define MSGU_HOST_SCRATCH_PAD_3 0x60
838 #define MSGU_HOST_SCRATCH_PAD_4 0x64
839 #define MSGU_HOST_SCRATCH_PAD_5 0x68
840 #define MSGU_HOST_SCRATCH_PAD_6 0x6C
841 #define MSGU_HOST_SCRATCH_PAD_7 0x70
842 #define MSGU_ODMR 0x74/* RevB */
843
844 /* bit definition for ODMR register */
845 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
846 interrupt vector */
847 #define ODMR_CLEAR_ALL 0/* clear all
848 interrupt vector */
849 /* bit definition for ODCR register */
850 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
851 interrupt vector*/
852 /* MSIX Interupts */
853 #define MSIX_TABLE_OFFSET 0x2000
854 #define MSIX_TABLE_ELEMENT_SIZE 0x10
855 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
856 #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
857 #define MSIX_INTERRUPT_DISABLE 0x1
858 #define MSIX_INTERRUPT_ENABLE 0x0
859
860
861 /* state definition for Scratch Pad1 register */
862 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
863 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
864 #define SCRATCH_PAD1_ERR 0x02 /* error state */
865 #define SCRATCH_PAD1_RDY 0x03 /* ready state */
866 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
867 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
868 #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
869 Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
870 #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
871 Reserved bit 3 to 9 */
872
873 /* state definition for Scratch Pad2 register */
874 #define SCRATCH_PAD2_POR 0x00 /* power on state */
875 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
876 #define SCRATCH_PAD2_ERR 0x02 /* error state */
877 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
878 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
879 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
880 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
881 Mask, bit1-0 State */
882 #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
883 Reserved bit 2 to 9 */
884
885 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
886 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
887
888 /* main configuration offset - byte offset */
889 #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
890 #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
891 #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
892 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
893 #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
894 #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
895 #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
896 #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
897 #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
898 #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
899 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
900 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
901 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
902 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
903 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
904 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
905 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
906 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
907 #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
908 #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
909 #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
910 #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
911 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
912 #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
913 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
914 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
915 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
916 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
917 #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
918 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
919 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
920 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
921 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
922 #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
923 #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
924
925 /* Gereral Status Table offset - byte offset */
926 #define GST_GSTLEN_MPIS_OFFSET 0x00
927 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
928 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
929 #define GST_MSGUTCNT_OFFSET 0x0C
930 #define GST_IOPTCNT_OFFSET 0x10
931 #define GST_PHYSTATE_OFFSET 0x18
932 #define GST_PHYSTATE0_OFFSET 0x18
933 #define GST_PHYSTATE1_OFFSET 0x1C
934 #define GST_PHYSTATE2_OFFSET 0x20
935 #define GST_PHYSTATE3_OFFSET 0x24
936 #define GST_PHYSTATE4_OFFSET 0x28
937 #define GST_PHYSTATE5_OFFSET 0x2C
938 #define GST_PHYSTATE6_OFFSET 0x30
939 #define GST_PHYSTATE7_OFFSET 0x34
940 #define GST_RERRINFO_OFFSET 0x44
941
942 /* General Status Table - MPI state */
943 #define GST_MPI_STATE_UNINIT 0x00
944 #define GST_MPI_STATE_INIT 0x01
945 #define GST_MPI_STATE_TERMINATION 0x02
946 #define GST_MPI_STATE_ERROR 0x03
947 #define GST_MPI_STATE_MASK 0x07
948
949 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
950 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
951 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
952 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
953 #define PCIE_EVENT_INTERRUPT 0x003044
954 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
955 #define PCIE_ERROR_INTERRUPT 0x00304C
956 /* signature definition for host scratch pad0 register */
957 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
958 /* Signature for Soft Reset */
959
960 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
961 #define SPC_REG_RESET 0x000000/* reset register */
962
963 /* bit difination for SPC_RESET register */
964 #define SPC_REG_RESET_OSSP 0x00000001
965 #define SPC_REG_RESET_RAAE 0x00000002
966 #define SPC_REG_RESET_PCS_SPBC 0x00000004
967 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
968 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
969 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
970 #define SPC_REG_RESET_PCS_LM 0x00000040
971 #define SPC_REG_RESET_PCS 0x00000080
972 #define SPC_REG_RESET_GSM 0x00000100
973 #define SPC_REG_RESET_DDR2 0x00010000
974 #define SPC_REG_RESET_BDMA_CORE 0x00020000
975 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
976 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
977 #define SPC_REG_RESET_PCIE_PWR 0x00100000
978 #define SPC_REG_RESET_PCIE_SFT 0x00200000
979 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
980 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
981 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
982 #define SPC_REG_RESET_PMIC_CORE 0x02000000
983 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
984 #define SPC_REG_RESET_DEVICE 0x80000000
985
986 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
987 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
988
989 #define MBIC_AAP1_ADDR_BASE 0x060000
990 #define MBIC_IOP_ADDR_BASE 0x070000
991 #define GSM_ADDR_BASE 0x0700000
992 /* Dynamic map through Bar4 - 0x00700000 */
993 #define GSM_CONFIG_RESET 0x00000000
994 #define RAM_ECC_DB_ERR 0x00000018
995 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
996 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
997 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
998 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
999 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
1000 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1001
1002 #define RB6_ACCESS_REG 0x6A0000
1003 #define HDAC_EXEC_CMD 0x0002
1004 #define HDA_C_PA 0xcb
1005 #define HDA_SEQ_ID_BITS 0x00ff0000
1006 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1007 #define MBIC_AAP1_ADDR_BASE 0x060000
1008 #define MBIC_IOP_ADDR_BASE 0x070000
1009 #define GSM_ADDR_BASE 0x0700000
1010 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1011 #define GSM_CONFIG_RESET_VALUE 0x00003b00
1012 #define GPIO_ADDR_BASE 0x00090000
1013 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1014
1015 /* RB6 offset */
1016 #define SPC_RB6_OFFSET 0x80C0
1017 /* Magic number of soft reset for RB6 */
1018 #define RB6_MAGIC_NUMBER_RST 0x1234
1019
1020 /* Device Register status */
1021 #define DEVREG_SUCCESS 0x00
1022 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1023 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1024 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1025 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1026 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1027 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1028 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07
1029
1030 #endif
1031
kernel source for telekom puls (alcatel/mediatek)