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Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / ips.c
1 /*****************************************************************************/
2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
7 /* */
8 /* Copyright (C) 2000 IBM Corporation */
9 /* Copyright (C) 2002,2003 Adaptec, Inc. */
10 /* */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
15 /* */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
20 /* */
21 /* NO WARRANTY */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
31 /* */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40 /* */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44 /* */
45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */
46 /* ipslinux@adaptec.com */
47 /* */
48 /* For system support issues, contact your local IBM Customer support. */
49 /* Directions to find IBM Customer Support for each country can be found at: */
50 /* http://www.ibm.com/planetwide/ */
51 /* */
52 /*****************************************************************************/
53
54 /*****************************************************************************/
55 /* Change Log */
56 /* */
57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58 /* 0.99.03 - Make interrupt routine handle all completed request on the */
59 /* adapter not just the first one */
60 /* - Make sure passthru commands get woken up if we run out of */
61 /* SCBs */
62 /* - Send all of the commands on the queue at once rather than */
63 /* one at a time since the card will support it. */
64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65 /* the interface to the utilities to change */
66 /* - Fix error recovery code */
67 /* 0.99.05 - Fix an oops when we get certain passthru commands */
68 /* 1.00.00 - Initial Public Release */
69 /* Functionally equivalent to 0.99.05 */
70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71 /* - Change version to 3.60 to coincide with release numbering. */
72 /* 3.60.01 - Remove bogus error check in passthru routine */
73 /* 3.60.02 - Make DCDB direction based on lookup table */
74 /* - Only allow one DCDB command to a SCSI ID at a time */
75 /* 4.00.00 - Add support for ServeRAID 4 */
76 /* 4.00.01 - Add support for First Failure Data Capture */
77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */
78 /* 4.00.03 - Add alternative passthru interface */
79 /* - Add ability to flash BIOS */
80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81 /* 4.00.05 - Remove wish_block from init routine */
82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83 /* 2.3.18 and later */
84 /* - Sync with other changes from the 2.3 kernels */
85 /* 4.00.06 - Fix timeout with initial FFDC command */
86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87 /* 4.10.00 - Add support for ServeRAID 4M/4L */
88 /* 4.10.13 - Fix for dynamic unload and proc file system */
89 /* 4.20.03 - Rename version to coincide with new release schedules */
90 /* Performance fixes */
91 /* Fix truncation of /proc files with cat */
92 /* Merge in changes through kernel 2.4.0test1ac21 */
93 /* 4.20.13 - Fix some failure cases / reset code */
94 /* - Hook into the reboot_notifier to flush the controller cache */
95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97 /* - Add IPSSEND Flash Support */
98 /* - Set Sense Data for Unknown SCSI Command */
99 /* - Use Slot Number from NVRAM Page 5 */
100 /* - Restore caller's DCDB Structure */
101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103 /* - Don't release HA Lock in ips_next() until SC taken off queue */
104 /* - Unregister SCSI device in ips_release() */
105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107 /* Code Clean-Up for 2.4.x kernel */
108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110 /* - Don't Issue Internal FFDC Command if there are Active Commands */
111 /* - Close Window for getting too many IOCTL's active */
112 /* 4.80.00 - Make ia64 Safe */
113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114 /* - Adjustments to Device Queue Depth */
115 /* 4.80.14 - Take all semaphores off stack */
116 /* - Clean Up New_IOCTL path */
117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118 /* - 5 second delay needed after resetting an i960 adapter */
119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124 /* 4.90.11 - Don't actually RESET unless it's physically required */
125 /* - Remove unused compile options */
126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127 /* - Get rid on IOCTL_NEW_COMMAND code */
128 /* - Add Extended DCDB Commands for Tape Support in 5I */
129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130 /* 5.10.15 - remove unused code (sem, macros, etc.) */
131 /* 5.30.00 - use __devexit_p() */
132 /* 6.00.00 - Add 6x Adapters and Battery Flash */
133 /* 6.10.00 - Remove 1G Addressing Limitations */
134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136 /* 7.10.xx - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138 /* - Fix sort order of 7k */
139 /* - Remove 3 unused "inline" functions */
140 /*****************************************************************************/
141
142 /*
143 * Conditional Compilation directives for this driver:
144 *
145 * IPS_DEBUG - Turn on debugging info
146 *
147 * Parameters:
148 *
149 * debug:<number> - Set debug level to <number>
150 * NOTE: only works when IPS_DEBUG compile directive is used.
151 * 1 - Normal debug messages
152 * 2 - Verbose debug messages
153 * 11 - Method trace (non interrupt)
154 * 12 - Method trace (includes interrupt)
155 *
156 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
157 * nommap - Don't use memory mapped I/O
158 * ioctlsize - Initial size of the IOCTL buffer
159 */
160
161 #include <asm/io.h>
162 #include <asm/byteorder.h>
163 #include <asm/page.h>
164 #include <linux/stddef.h>
165 #include <linux/version.h>
166 #include <linux/string.h>
167 #include <linux/errno.h>
168 #include <linux/kernel.h>
169 #include <linux/ioport.h>
170 #include <linux/slab.h>
171 #include <linux/delay.h>
172 #include <linux/pci.h>
173 #include <linux/proc_fs.h>
174 #include <linux/reboot.h>
175 #include <linux/interrupt.h>
176
177 #include <linux/blkdev.h>
178 #include <linux/types.h>
179
180 #include <scsi/sg.h>
181
182 #include "scsi.h"
183
184 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
185 #include "hosts.h"
186 #else
187 #include <scsi/scsi_host.h>
188 #endif
189
190 #include "ips.h"
191
192 #include <linux/module.h>
193
194 #include <linux/stat.h>
195 #include <linux/config.h>
196
197 #include <linux/spinlock.h>
198 #include <linux/init.h>
199
200 #include <linux/smp.h>
201
202 #ifdef MODULE
203 static char *ips = NULL;
204 module_param(ips, charp, 0);
205 #endif
206
207 /*
208 * DRIVER_VER
209 */
210 #define IPS_VERSION_HIGH "7.10"
211 #define IPS_VERSION_LOW ".18 "
212
213 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
214 #warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
215 #endif
216
217 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
218 #include <linux/blk.h>
219 #include "sd.h"
220 #define IPS_SG_ADDRESS(sg) ((sg)->address)
221 #define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags)
222 #define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags)
223 #ifndef __devexit_p
224 #define __devexit_p(x) x
225 #endif
226 #else
227 #define IPS_SG_ADDRESS(sg) (page_address((sg)->page) ? \
228 page_address((sg)->page)+(sg)->offset : NULL)
229 #define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0)
230 #define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0)
231 #endif
232
233 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
234 SCSI_DATA_NONE == scb->scsi_cmd->sc_data_direction) ? \
235 PCI_DMA_BIDIRECTIONAL : \
236 scsi_to_pci_dma_dir(scb->scsi_cmd->sc_data_direction))
237
238 #ifdef IPS_DEBUG
239 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
240 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
241 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
242 #else
243 #define METHOD_TRACE(s, i)
244 #define DEBUG(i, s)
245 #define DEBUG_VAR(i, s, v...)
246 #endif
247
248 /*
249 * Function prototypes
250 */
251 static int ips_detect(Scsi_Host_Template *);
252 static int ips_release(struct Scsi_Host *);
253 static int ips_eh_abort(Scsi_Cmnd *);
254 static int ips_eh_reset(Scsi_Cmnd *);
255 static int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *));
256 static const char *ips_info(struct Scsi_Host *);
257 static irqreturn_t do_ipsintr(int, void *, struct pt_regs *);
258 static int ips_hainit(ips_ha_t *);
259 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
260 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
261 static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
262 static int ips_online(ips_ha_t *, ips_scb_t *);
263 static int ips_inquiry(ips_ha_t *, ips_scb_t *);
264 static int ips_rdcap(ips_ha_t *, ips_scb_t *);
265 static int ips_msense(ips_ha_t *, ips_scb_t *);
266 static int ips_reqsen(ips_ha_t *, ips_scb_t *);
267 static int ips_deallocatescbs(ips_ha_t *, int);
268 static int ips_allocatescbs(ips_ha_t *);
269 static int ips_reset_copperhead(ips_ha_t *);
270 static int ips_reset_copperhead_memio(ips_ha_t *);
271 static int ips_reset_morpheus(ips_ha_t *);
272 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
273 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
274 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
275 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
276 static int ips_isintr_copperhead(ips_ha_t *);
277 static int ips_isintr_copperhead_memio(ips_ha_t *);
278 static int ips_isintr_morpheus(ips_ha_t *);
279 static int ips_wait(ips_ha_t *, int, int);
280 static int ips_write_driver_status(ips_ha_t *, int);
281 static int ips_read_adapter_status(ips_ha_t *, int);
282 static int ips_read_subsystem_parameters(ips_ha_t *, int);
283 static int ips_read_config(ips_ha_t *, int);
284 static int ips_clear_adapter(ips_ha_t *, int);
285 static int ips_readwrite_page5(ips_ha_t *, int, int);
286 static int ips_init_copperhead(ips_ha_t *);
287 static int ips_init_copperhead_memio(ips_ha_t *);
288 static int ips_init_morpheus(ips_ha_t *);
289 static int ips_isinit_copperhead(ips_ha_t *);
290 static int ips_isinit_copperhead_memio(ips_ha_t *);
291 static int ips_isinit_morpheus(ips_ha_t *);
292 static int ips_erase_bios(ips_ha_t *);
293 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
294 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
295 static int ips_erase_bios_memio(ips_ha_t *);
296 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
297 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
298 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
299 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
300 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
301 static void ips_free_flash_copperhead(ips_ha_t * ha);
302 static void ips_get_bios_version(ips_ha_t *, int);
303 static void ips_identify_controller(ips_ha_t *);
304 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
305 static void ips_enable_int_copperhead(ips_ha_t *);
306 static void ips_enable_int_copperhead_memio(ips_ha_t *);
307 static void ips_enable_int_morpheus(ips_ha_t *);
308 static int ips_intr_copperhead(ips_ha_t *);
309 static int ips_intr_morpheus(ips_ha_t *);
310 static void ips_next(ips_ha_t *, int);
311 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
312 static void ipsintr_done(ips_ha_t *, struct ips_scb *);
313 static void ips_done(ips_ha_t *, ips_scb_t *);
314 static void ips_free(ips_ha_t *);
315 static void ips_init_scb(ips_ha_t *, ips_scb_t *);
316 static void ips_freescb(ips_ha_t *, ips_scb_t *);
317 static void ips_setup_funclist(ips_ha_t *);
318 static void ips_statinit(ips_ha_t *);
319 static void ips_statinit_memio(ips_ha_t *);
320 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
321 static void ips_ffdc_reset(ips_ha_t *, int);
322 static void ips_ffdc_time(ips_ha_t *);
323 static uint32_t ips_statupd_copperhead(ips_ha_t *);
324 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
325 static uint32_t ips_statupd_morpheus(ips_ha_t *);
326 static ips_scb_t *ips_getscb(ips_ha_t *);
327 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
328 static void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *);
329 static void ips_putq_copp_tail(ips_copp_queue_t *,
330 ips_copp_wait_item_t *);
331 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
332 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
333 static Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
334 static Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *);
335 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
336 ips_copp_wait_item_t *);
337 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
338
339 static int ips_is_passthru(Scsi_Cmnd *);
340 static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int);
341 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
342 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
343 static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data,
344 unsigned int count);
345 static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count);
346
347 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
348 static int ips_host_info(ips_ha_t *, char *, off_t, int);
349 static void copy_mem_info(IPS_INFOSTR *, char *, int);
350 static int copy_info(IPS_INFOSTR *, char *, ...);
351 static int ips_get_version_info(ips_ha_t * ha, dma_addr_t, int intr);
352 static void ips_version_check(ips_ha_t * ha, int intr);
353 static int ips_abort_init(ips_ha_t * ha, int index);
354 static int ips_init_phase2(int index);
355
356 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
357 static int ips_register_scsi(int index);
358
359 /*
360 * global variables
361 */
362 static const char ips_name[] = "ips";
363 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
364 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
365 static unsigned int ips_next_controller;
366 static unsigned int ips_num_controllers;
367 static unsigned int ips_released_controllers;
368 static int ips_hotplug;
369 static int ips_cmd_timeout = 60;
370 static int ips_reset_timeout = 60 * 5;
371 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
372 static int ips_force_i2o = 1; /* Always use I2O command delivery */
373 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
374 static int ips_cd_boot; /* Booting from Manager CD */
375 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
376 static dma_addr_t ips_flashbusaddr;
377 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
378 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
379 static Scsi_Host_Template ips_driver_template = {
380 .detect = ips_detect,
381 .release = ips_release,
382 .info = ips_info,
383 .queuecommand = ips_queue,
384 .eh_abort_handler = ips_eh_abort,
385 .eh_host_reset_handler = ips_eh_reset,
386 .proc_name = "ips",
387 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
388 .proc_info = ips_proc_info,
389 .slave_configure = ips_slave_configure,
390 #else
391 .proc_info = ips_proc24_info,
392 .select_queue_depths = ips_select_queue_depth,
393 #endif
394 .bios_param = ips_biosparam,
395 .this_id = -1,
396 .sg_tablesize = IPS_MAX_SG,
397 .cmd_per_lun = 3,
398 .use_clustering = ENABLE_CLUSTERING,
399 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
400 .use_new_eh_code = 1,
401 #endif
402 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
403 .highmem_io = 1,
404 #endif
405 };
406
407 static IPS_DEFINE_COMPAT_TABLE( Compatable ); /* Version Compatability Table */
408
409
410 /* This table describes all ServeRAID Adapters */
411 static struct pci_device_id ips_pci_table[] = {
412 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
413 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
414 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
415 { 0, }
416 };
417
418 MODULE_DEVICE_TABLE( pci, ips_pci_table );
419
420 static char ips_hot_plug_name[] = "ips";
421
422 static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
423 static void __devexit ips_remove_device(struct pci_dev *pci_dev);
424
425 static struct pci_driver ips_pci_driver = {
426 .name = ips_hot_plug_name,
427 .id_table = ips_pci_table,
428 .probe = ips_insert_device,
429 .remove = __devexit_p(ips_remove_device),
430 };
431
432
433 /*
434 * Necessary forward function protoypes
435 */
436 static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
437
438 #define MAX_ADAPTER_NAME 15
439
440 static char ips_adapter_name[][30] = {
441 "ServeRAID",
442 "ServeRAID II",
443 "ServeRAID on motherboard",
444 "ServeRAID on motherboard",
445 "ServeRAID 3H",
446 "ServeRAID 3L",
447 "ServeRAID 4H",
448 "ServeRAID 4M",
449 "ServeRAID 4L",
450 "ServeRAID 4Mx",
451 "ServeRAID 4Lx",
452 "ServeRAID 5i",
453 "ServeRAID 5i",
454 "ServeRAID 6M",
455 "ServeRAID 6i",
456 "ServeRAID 7t",
457 "ServeRAID 7k",
458 "ServeRAID 7M"
459 };
460
461 static struct notifier_block ips_notifier = {
462 ips_halt, NULL, 0
463 };
464
465 /*
466 * Direction table
467 */
468 static char ips_command_direction[] = {
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
470 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
473 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
474 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
475 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
476 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
478 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
479 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
480 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
481 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
482 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
483 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
484 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
487 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
490 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
491 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
492 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
493 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
494 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
495 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
496 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
497 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
498 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
499 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
500 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
501 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
502 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
503 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
504 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
505 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
506 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
507 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
508 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
509 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
510 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
511 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
512 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
513 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
514 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
515 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
516 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
517 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
518 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
519 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
520 };
521
522
523 /****************************************************************************/
524 /* */
525 /* Routine Name: ips_setup */
526 /* */
527 /* Routine Description: */
528 /* */
529 /* setup parameters to the driver */
530 /* */
531 /****************************************************************************/
532 static int
533 ips_setup(char *ips_str)
534 {
535
536 int i;
537 char *key;
538 char *value;
539 IPS_OPTION options[] = {
540 {"noi2o", &ips_force_i2o, 0},
541 {"nommap", &ips_force_memio, 0},
542 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
543 {"cdboot", &ips_cd_boot, 0},
544 {"maxcmds", &MaxLiteCmds, 32},
545 };
546
547 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
548 /* Search for value */
549 while ((key = strsep(&ips_str, ",."))) {
550 if (!*key)
551 continue;
552 value = strchr(key, ':');
553 if (value)
554 *value++ = '\0';
555 /*
556 * We now have key/value pairs.
557 * Update the variables
558 */
559 for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) {
560 if (strnicmp
561 (key, options[i].option_name,
562 strlen(options[i].option_name)) == 0) {
563 if (value)
564 *options[i].option_flag =
565 simple_strtoul(value, NULL, 0);
566 else
567 *options[i].option_flag =
568 options[i].option_value;
569 break;
570 }
571 }
572 }
573
574 return (1);
575 }
576
577 __setup("ips=", ips_setup);
578
579 /****************************************************************************/
580 /* */
581 /* Routine Name: ips_detect */
582 /* */
583 /* Routine Description: */
584 /* */
585 /* Detect and initialize the driver */
586 /* */
587 /* NOTE: this routine is called under the io_request_lock spinlock */
588 /* */
589 /****************************************************************************/
590 static int
591 ips_detect(Scsi_Host_Template * SHT)
592 {
593 int i;
594
595 METHOD_TRACE("ips_detect", 1);
596
597 #ifdef MODULE
598 if (ips)
599 ips_setup(ips);
600 #endif
601
602 for (i = 0; i < ips_num_controllers; i++) {
603 if (ips_register_scsi(i))
604 ips_free(ips_ha[i]);
605 ips_released_controllers++;
606 }
607 ips_hotplug = 1;
608 return (ips_num_controllers);
609 }
610
611 /****************************************************************************/
612 /* configure the function pointers to use the functions that will work */
613 /* with the found version of the adapter */
614 /****************************************************************************/
615 static void
616 ips_setup_funclist(ips_ha_t * ha)
617 {
618
619 /*
620 * Setup Functions
621 */
622 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
623 /* morpheus / marco / sebring */
624 ha->func.isintr = ips_isintr_morpheus;
625 ha->func.isinit = ips_isinit_morpheus;
626 ha->func.issue = ips_issue_i2o_memio;
627 ha->func.init = ips_init_morpheus;
628 ha->func.statupd = ips_statupd_morpheus;
629 ha->func.reset = ips_reset_morpheus;
630 ha->func.intr = ips_intr_morpheus;
631 ha->func.enableint = ips_enable_int_morpheus;
632 } else if (IPS_USE_MEMIO(ha)) {
633 /* copperhead w/MEMIO */
634 ha->func.isintr = ips_isintr_copperhead_memio;
635 ha->func.isinit = ips_isinit_copperhead_memio;
636 ha->func.init = ips_init_copperhead_memio;
637 ha->func.statupd = ips_statupd_copperhead_memio;
638 ha->func.statinit = ips_statinit_memio;
639 ha->func.reset = ips_reset_copperhead_memio;
640 ha->func.intr = ips_intr_copperhead;
641 ha->func.erasebios = ips_erase_bios_memio;
642 ha->func.programbios = ips_program_bios_memio;
643 ha->func.verifybios = ips_verify_bios_memio;
644 ha->func.enableint = ips_enable_int_copperhead_memio;
645 if (IPS_USE_I2O_DELIVER(ha))
646 ha->func.issue = ips_issue_i2o_memio;
647 else
648 ha->func.issue = ips_issue_copperhead_memio;
649 } else {
650 /* copperhead */
651 ha->func.isintr = ips_isintr_copperhead;
652 ha->func.isinit = ips_isinit_copperhead;
653 ha->func.init = ips_init_copperhead;
654 ha->func.statupd = ips_statupd_copperhead;
655 ha->func.statinit = ips_statinit;
656 ha->func.reset = ips_reset_copperhead;
657 ha->func.intr = ips_intr_copperhead;
658 ha->func.erasebios = ips_erase_bios;
659 ha->func.programbios = ips_program_bios;
660 ha->func.verifybios = ips_verify_bios;
661 ha->func.enableint = ips_enable_int_copperhead;
662
663 if (IPS_USE_I2O_DELIVER(ha))
664 ha->func.issue = ips_issue_i2o;
665 else
666 ha->func.issue = ips_issue_copperhead;
667 }
668 }
669
670 /****************************************************************************/
671 /* */
672 /* Routine Name: ips_release */
673 /* */
674 /* Routine Description: */
675 /* */
676 /* Remove a driver */
677 /* */
678 /****************************************************************************/
679 static int
680 ips_release(struct Scsi_Host *sh)
681 {
682 ips_scb_t *scb;
683 ips_ha_t *ha;
684 int i;
685
686 METHOD_TRACE("ips_release", 1);
687
688 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
689
690 if (i == IPS_MAX_ADAPTERS) {
691 printk(KERN_WARNING
692 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
693 BUG();
694 return (FALSE);
695 }
696
697 ha = IPS_HA(sh);
698
699 if (!ha)
700 return (FALSE);
701
702 /* flush the cache on the controller */
703 scb = &ha->scbs[ha->max_cmds - 1];
704
705 ips_init_scb(ha, scb);
706
707 scb->timeout = ips_cmd_timeout;
708 scb->cdb[0] = IPS_CMD_FLUSH;
709
710 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
711 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
712 scb->cmd.flush_cache.state = IPS_NORM_STATE;
713 scb->cmd.flush_cache.reserved = 0;
714 scb->cmd.flush_cache.reserved2 = 0;
715 scb->cmd.flush_cache.reserved3 = 0;
716 scb->cmd.flush_cache.reserved4 = 0;
717
718 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
719
720 /* send command */
721 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
722 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
723
724 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
725
726 ips_sh[i] = NULL;
727 ips_ha[i] = NULL;
728
729 /* free extra memory */
730 ips_free(ha);
731
732 /* Free I/O Region */
733 if (ha->io_addr)
734 release_region(ha->io_addr, ha->io_len);
735
736 /* free IRQ */
737 free_irq(ha->irq, ha);
738
739 IPS_REMOVE_HOST(sh);
740 scsi_host_put(sh);
741
742 ips_released_controllers++;
743
744 return (FALSE);
745 }
746
747 /****************************************************************************/
748 /* */
749 /* Routine Name: ips_halt */
750 /* */
751 /* Routine Description: */
752 /* */
753 /* Perform cleanup when the system reboots */
754 /* */
755 /****************************************************************************/
756 static int
757 ips_halt(struct notifier_block *nb, ulong event, void *buf)
758 {
759 ips_scb_t *scb;
760 ips_ha_t *ha;
761 int i;
762
763 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
764 (event != SYS_POWER_OFF))
765 return (NOTIFY_DONE);
766
767 for (i = 0; i < ips_next_controller; i++) {
768 ha = (ips_ha_t *) ips_ha[i];
769
770 if (!ha)
771 continue;
772
773 if (!ha->active)
774 continue;
775
776 /* flush the cache on the controller */
777 scb = &ha->scbs[ha->max_cmds - 1];
778
779 ips_init_scb(ha, scb);
780
781 scb->timeout = ips_cmd_timeout;
782 scb->cdb[0] = IPS_CMD_FLUSH;
783
784 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
785 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
786 scb->cmd.flush_cache.state = IPS_NORM_STATE;
787 scb->cmd.flush_cache.reserved = 0;
788 scb->cmd.flush_cache.reserved2 = 0;
789 scb->cmd.flush_cache.reserved3 = 0;
790 scb->cmd.flush_cache.reserved4 = 0;
791
792 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
793
794 /* send command */
795 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
796 IPS_FAILURE)
797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
798 "Incomplete Flush.\n");
799 else
800 IPS_PRINTK(KERN_WARNING, ha->pcidev,
801 "Flushing Complete.\n");
802 }
803
804 return (NOTIFY_OK);
805 }
806
807 /****************************************************************************/
808 /* */
809 /* Routine Name: ips_eh_abort */
810 /* */
811 /* Routine Description: */
812 /* */
813 /* Abort a command (using the new error code stuff) */
814 /* Note: this routine is called under the io_request_lock */
815 /****************************************************************************/
816 int
817 ips_eh_abort(Scsi_Cmnd * SC)
818 {
819 ips_ha_t *ha;
820 ips_copp_wait_item_t *item;
821 int ret;
822
823 METHOD_TRACE("ips_eh_abort", 1);
824
825 if (!SC)
826 return (FAILED);
827
828 ha = (ips_ha_t *) SC->device->host->hostdata;
829
830 if (!ha)
831 return (FAILED);
832
833 if (!ha->active)
834 return (FAILED);
835
836 if (SC->serial_number != SC->serial_number_at_timeout) {
837 /* HMM, looks like a bogus command */
838 DEBUG(1, "Abort called with bogus scsi command");
839
840 return (FAILED);
841 }
842
843 /* See if the command is on the copp queue */
844 item = ha->copp_waitlist.head;
845 while ((item) && (item->scsi_cmd != SC))
846 item = item->next;
847
848 if (item) {
849 /* Found it */
850 ips_removeq_copp(&ha->copp_waitlist, item);
851 ret = (SUCCESS);
852
853 /* See if the command is on the wait queue */
854 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
855 /* command not sent yet */
856 ret = (SUCCESS);
857 } else {
858 /* command must have already been sent */
859 ret = (FAILED);
860 }
861 return ret;
862 }
863
864 /****************************************************************************/
865 /* */
866 /* Routine Name: ips_eh_reset */
867 /* */
868 /* Routine Description: */
869 /* */
870 /* Reset the controller (with new eh error code) */
871 /* */
872 /* NOTE: this routine is called under the io_request_lock spinlock */
873 /* */
874 /****************************************************************************/
875 static int
876 ips_eh_reset(Scsi_Cmnd * SC)
877 {
878 int ret;
879 int i;
880 ips_ha_t *ha;
881 ips_scb_t *scb;
882 ips_copp_wait_item_t *item;
883
884 METHOD_TRACE("ips_eh_reset", 1);
885
886 #ifdef NO_IPS_RESET
887 return (FAILED);
888 #else
889
890 if (!SC) {
891 DEBUG(1, "Reset called with NULL scsi command");
892
893 return (FAILED);
894 }
895
896 ha = (ips_ha_t *) SC->device->host->hostdata;
897
898 if (!ha) {
899 DEBUG(1, "Reset called with NULL ha struct");
900
901 return (FAILED);
902 }
903
904 if (!ha->active)
905 return (FAILED);
906
907 /* See if the command is on the copp queue */
908 item = ha->copp_waitlist.head;
909 while ((item) && (item->scsi_cmd != SC))
910 item = item->next;
911
912 if (item) {
913 /* Found it */
914 ips_removeq_copp(&ha->copp_waitlist, item);
915 return (SUCCESS);
916 }
917
918 /* See if the command is on the wait queue */
919 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
920 /* command not sent yet */
921 return (SUCCESS);
922 }
923
924 /* An explanation for the casual observer: */
925 /* Part of the function of a RAID controller is automatic error */
926 /* detection and recovery. As such, the only problem that physically */
927 /* resetting an adapter will ever fix is when, for some reason, */
928 /* the driver is not successfully communicating with the adapter. */
929 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
930 /* then there's no real purpose in a physical reset. This will complete */
931 /* much faster and avoids any problems that might be caused by a */
932 /* physical reset ( such as having to fail all the outstanding I/O's ). */
933
934 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
935 scb = &ha->scbs[ha->max_cmds - 1];
936
937 ips_init_scb(ha, scb);
938
939 scb->timeout = ips_cmd_timeout;
940 scb->cdb[0] = IPS_CMD_FLUSH;
941
942 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
943 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
944 scb->cmd.flush_cache.state = IPS_NORM_STATE;
945 scb->cmd.flush_cache.reserved = 0;
946 scb->cmd.flush_cache.reserved2 = 0;
947 scb->cmd.flush_cache.reserved3 = 0;
948 scb->cmd.flush_cache.reserved4 = 0;
949
950 /* Attempt the flush command */
951 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
952 if (ret == IPS_SUCCESS) {
953 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
954 "Reset Request - Flushed Cache\n");
955 return (SUCCESS);
956 }
957 }
958
959 /* Either we can't communicate with the adapter or it's an IOCTL request */
960 /* from a utility. A physical reset is needed at this point. */
961
962 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
963
964 /*
965 * command must have already been sent
966 * reset the controller
967 */
968 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
969 ret = (*ha->func.reset) (ha);
970
971 if (!ret) {
972 Scsi_Cmnd *scsi_cmd;
973
974 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
975 "Controller reset failed - controller now offline.\n");
976
977 /* Now fail all of the active commands */
978 DEBUG_VAR(1, "(%s%d) Failing active commands",
979 ips_name, ha->host_num);
980
981 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
982 scb->scsi_cmd->result = DID_ERROR << 16;
983 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
984 ips_freescb(ha, scb);
985 }
986
987 /* Now fail all of the pending commands */
988 DEBUG_VAR(1, "(%s%d) Failing pending commands",
989 ips_name, ha->host_num);
990
991 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
992 scsi_cmd->result = DID_ERROR;
993 scsi_cmd->scsi_done(scsi_cmd);
994 }
995
996 ha->active = FALSE;
997 return (FAILED);
998 }
999
1000 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
1001 Scsi_Cmnd *scsi_cmd;
1002
1003 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
1004 "Controller reset failed - controller now offline.\n");
1005
1006 /* Now fail all of the active commands */
1007 DEBUG_VAR(1, "(%s%d) Failing active commands",
1008 ips_name, ha->host_num);
1009
1010 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1011 scb->scsi_cmd->result = DID_ERROR << 16;
1012 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1013 ips_freescb(ha, scb);
1014 }
1015
1016 /* Now fail all of the pending commands */
1017 DEBUG_VAR(1, "(%s%d) Failing pending commands",
1018 ips_name, ha->host_num);
1019
1020 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
1021 scsi_cmd->result = DID_ERROR << 16;
1022 scsi_cmd->scsi_done(scsi_cmd);
1023 }
1024
1025 ha->active = FALSE;
1026 return (FAILED);
1027 }
1028
1029 /* FFDC */
1030 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
1031 struct timeval tv;
1032
1033 do_gettimeofday(&tv);
1034 ha->last_ffdc = tv.tv_sec;
1035 ha->reset_count++;
1036 ips_ffdc_reset(ha, IPS_INTR_IORL);
1037 }
1038
1039 /* Now fail all of the active commands */
1040 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1041
1042 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1043 scb->scsi_cmd->result =
1044 (DID_RESET << 16) | (SUGGEST_RETRY << 24);
1045 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1046 ips_freescb(ha, scb);
1047 }
1048
1049 /* Reset DCDB active command bits */
1050 for (i = 1; i < ha->nbus; i++)
1051 ha->dcdb_active[i - 1] = 0;
1052
1053 /* Reset the number of active IOCTLs */
1054 ha->num_ioctl = 0;
1055
1056 ips_next(ha, IPS_INTR_IORL);
1057
1058 return (SUCCESS);
1059 #endif /* NO_IPS_RESET */
1060
1061 }
1062
1063 /****************************************************************************/
1064 /* */
1065 /* Routine Name: ips_queue */
1066 /* */
1067 /* Routine Description: */
1068 /* */
1069 /* Send a command to the controller */
1070 /* */
1071 /* NOTE: */
1072 /* Linux obtains io_request_lock before calling this function */
1073 /* */
1074 /****************************************************************************/
1075 static int
1076 ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *))
1077 {
1078 ips_ha_t *ha;
1079 ips_passthru_t *pt;
1080
1081 METHOD_TRACE("ips_queue", 1);
1082
1083 ha = (ips_ha_t *) SC->device->host->hostdata;
1084
1085 if (!ha)
1086 return (1);
1087
1088 if (!ha->active)
1089 return (DID_ERROR);
1090
1091 if (ips_is_passthru(SC)) {
1092 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1093 SC->result = DID_BUS_BUSY << 16;
1094 done(SC);
1095
1096 return (0);
1097 }
1098 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1099 SC->result = DID_BUS_BUSY << 16;
1100 done(SC);
1101
1102 return (0);
1103 }
1104
1105 SC->scsi_done = done;
1106
1107 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1108 ips_name,
1109 ha->host_num,
1110 SC->cmnd[0],
1111 SC->device->channel, SC->device->id, SC->device->lun);
1112
1113 /* Check for command to initiator IDs */
1114 if ((SC->device->channel > 0)
1115 && (SC->device->id == ha->ha_id[SC->device->channel])) {
1116 SC->result = DID_NO_CONNECT << 16;
1117 done(SC);
1118
1119 return (0);
1120 }
1121
1122 if (ips_is_passthru(SC)) {
1123
1124 ips_copp_wait_item_t *scratch;
1125
1126 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1127 /* There can never be any system activity ( network or disk ), but check */
1128 /* anyway just as a good practice. */
1129 pt = (ips_passthru_t *) SC->request_buffer;
1130 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1131 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1132 if (ha->scb_activelist.count != 0) {
1133 SC->result = DID_BUS_BUSY << 16;
1134 done(SC);
1135 return (0);
1136 }
1137 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1138 ips_eh_reset(SC);
1139 SC->result = DID_OK << 16;
1140 SC->scsi_done(SC);
1141 return (0);
1142 }
1143
1144 /* allocate space for the scribble */
1145 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1146
1147 if (!scratch) {
1148 SC->result = DID_ERROR << 16;
1149 done(SC);
1150
1151 return (0);
1152 }
1153
1154 scratch->scsi_cmd = SC;
1155 scratch->next = NULL;
1156
1157 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1158 } else {
1159 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1160 }
1161
1162 ips_next(ha, IPS_INTR_IORL);
1163
1164 return (0);
1165 }
1166
1167 /****************************************************************************/
1168 /* */
1169 /* Routine Name: ips_biosparam */
1170 /* */
1171 /* Routine Description: */
1172 /* */
1173 /* Set bios geometry for the controller */
1174 /* */
1175 /****************************************************************************/
1176 static int
1177 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1178 ips_biosparam(Disk * disk, kdev_t dev, int geom[])
1179 {
1180 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata;
1181 unsigned long capacity = disk->capacity;
1182 #else
1183 ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1184 sector_t capacity, int geom[])
1185 {
1186 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1187 #endif
1188 int heads;
1189 int sectors;
1190 int cylinders;
1191
1192 METHOD_TRACE("ips_biosparam", 1);
1193
1194 if (!ha)
1195 /* ?!?! host adater info invalid */
1196 return (0);
1197
1198 if (!ha->active)
1199 return (0);
1200
1201 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1202 /* ?!?! Enquiry command failed */
1203 return (0);
1204
1205 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1206 heads = IPS_NORM_HEADS;
1207 sectors = IPS_NORM_SECTORS;
1208 } else {
1209 heads = IPS_COMP_HEADS;
1210 sectors = IPS_COMP_SECTORS;
1211 }
1212
1213 cylinders = (unsigned long) capacity / (heads * sectors);
1214
1215 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1216 heads, sectors, cylinders);
1217
1218 geom[0] = heads;
1219 geom[1] = sectors;
1220 geom[2] = cylinders;
1221
1222 return (0);
1223 }
1224
1225 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1226
1227 /* ips_proc24_info is a wrapper around ips_proc_info *
1228 * for compatibility with the 2.4 scsi parameters */
1229 static int
1230 ips_proc24_info(char *buffer, char **start, off_t offset, int length,
1231 int hostno, int func)
1232 {
1233 int i;
1234
1235 for (i = 0; i < ips_next_controller; i++) {
1236 if (ips_sh[i] && ips_sh[i]->host_no == hostno) {
1237 return ips_proc_info(ips_sh[i], buffer, start,
1238 offset, length, func);
1239 }
1240 }
1241 return -EINVAL;
1242 }
1243
1244 /****************************************************************************/
1245 /* */
1246 /* Routine Name: ips_select_queue_depth */
1247 /* */
1248 /* Routine Description: */
1249 /* */
1250 /* Select queue depths for the devices on the contoller */
1251 /* */
1252 /****************************************************************************/
1253 static void
1254 ips_select_queue_depth(struct Scsi_Host *host, Scsi_Device * scsi_devs)
1255 {
1256 Scsi_Device *device;
1257 ips_ha_t *ha;
1258 int count = 0;
1259 int min;
1260
1261 ha = IPS_HA(host);
1262 min = ha->max_cmds / 4;
1263
1264 for (device = scsi_devs; device; device = device->next) {
1265 if (device->host == host) {
1266 if ((device->channel == 0) && (device->type == 0))
1267 count++;
1268 }
1269 }
1270
1271 for (device = scsi_devs; device; device = device->next) {
1272 if (device->host == host) {
1273 if ((device->channel == 0) && (device->type == 0)) {
1274 device->queue_depth =
1275 (ha->max_cmds - 1) / count;
1276 if (device->queue_depth < min)
1277 device->queue_depth = min;
1278 } else {
1279 device->queue_depth = 2;
1280 }
1281
1282 if (device->queue_depth < 2)
1283 device->queue_depth = 2;
1284 }
1285 }
1286 }
1287
1288 #else
1289 /****************************************************************************/
1290 /* */
1291 /* Routine Name: ips_slave_configure */
1292 /* */
1293 /* Routine Description: */
1294 /* */
1295 /* Set queue depths on devices once scan is complete */
1296 /* */
1297 /****************************************************************************/
1298 static int
1299 ips_slave_configure(Scsi_Device * SDptr)
1300 {
1301 ips_ha_t *ha;
1302 int min;
1303
1304 ha = IPS_HA(SDptr->host);
1305 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1306 min = ha->max_cmds / 2;
1307 if (ha->enq->ucLogDriveCount <= 2)
1308 min = ha->max_cmds - 1;
1309 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1310 }
1311 return 0;
1312 }
1313 #endif
1314
1315 /****************************************************************************/
1316 /* */
1317 /* Routine Name: do_ipsintr */
1318 /* */
1319 /* Routine Description: */
1320 /* */
1321 /* Wrapper for the interrupt handler */
1322 /* */
1323 /****************************************************************************/
1324 static irqreturn_t
1325 do_ipsintr(int irq, void *dev_id, struct pt_regs * regs)
1326 {
1327 ips_ha_t *ha;
1328 unsigned long cpu_flags;
1329 struct Scsi_Host *host;
1330 int irqstatus;
1331
1332 METHOD_TRACE("do_ipsintr", 2);
1333
1334 ha = (ips_ha_t *) dev_id;
1335 if (!ha)
1336 return IRQ_NONE;
1337 host = ips_sh[ha->host_num];
1338 /* interrupt during initialization */
1339 if (!host) {
1340 (*ha->func.intr) (ha);
1341 return IRQ_HANDLED;
1342 }
1343
1344 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
1345
1346 if (!ha->active) {
1347 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1348 return IRQ_HANDLED;
1349 }
1350
1351 irqstatus = (*ha->func.intr) (ha);
1352
1353 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1354
1355 /* start the next command */
1356 ips_next(ha, IPS_INTR_ON);
1357 return IRQ_RETVAL(irqstatus);
1358 }
1359
1360 /****************************************************************************/
1361 /* */
1362 /* Routine Name: ips_intr_copperhead */
1363 /* */
1364 /* Routine Description: */
1365 /* */
1366 /* Polling interrupt handler */
1367 /* */
1368 /* ASSUMES interrupts are disabled */
1369 /* */
1370 /****************************************************************************/
1371 int
1372 ips_intr_copperhead(ips_ha_t * ha)
1373 {
1374 ips_stat_t *sp;
1375 ips_scb_t *scb;
1376 IPS_STATUS cstatus;
1377 int intrstatus;
1378
1379 METHOD_TRACE("ips_intr", 2);
1380
1381 if (!ha)
1382 return 0;
1383
1384 if (!ha->active)
1385 return 0;
1386
1387 intrstatus = (*ha->func.isintr) (ha);
1388
1389 if (!intrstatus) {
1390 /*
1391 * Unexpected/Shared interrupt
1392 */
1393
1394 return 0;
1395 }
1396
1397 while (TRUE) {
1398 sp = &ha->sp;
1399
1400 intrstatus = (*ha->func.isintr) (ha);
1401
1402 if (!intrstatus)
1403 break;
1404 else
1405 cstatus.value = (*ha->func.statupd) (ha);
1406
1407 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1408 /* Spurious Interupt ? */
1409 continue;
1410 }
1411
1412 ips_chkstatus(ha, &cstatus);
1413 scb = (ips_scb_t *) sp->scb_addr;
1414
1415 /*
1416 * use the callback function to finish things up
1417 * NOTE: interrupts are OFF for this
1418 */
1419 (*scb->callback) (ha, scb);
1420 } /* end while */
1421 return 1;
1422 }
1423
1424 /****************************************************************************/
1425 /* */
1426 /* Routine Name: ips_intr_morpheus */
1427 /* */
1428 /* Routine Description: */
1429 /* */
1430 /* Polling interrupt handler */
1431 /* */
1432 /* ASSUMES interrupts are disabled */
1433 /* */
1434 /****************************************************************************/
1435 int
1436 ips_intr_morpheus(ips_ha_t * ha)
1437 {
1438 ips_stat_t *sp;
1439 ips_scb_t *scb;
1440 IPS_STATUS cstatus;
1441 int intrstatus;
1442
1443 METHOD_TRACE("ips_intr_morpheus", 2);
1444
1445 if (!ha)
1446 return 0;
1447
1448 if (!ha->active)
1449 return 0;
1450
1451 intrstatus = (*ha->func.isintr) (ha);
1452
1453 if (!intrstatus) {
1454 /*
1455 * Unexpected/Shared interrupt
1456 */
1457
1458 return 0;
1459 }
1460
1461 while (TRUE) {
1462 sp = &ha->sp;
1463
1464 intrstatus = (*ha->func.isintr) (ha);
1465
1466 if (!intrstatus)
1467 break;
1468 else
1469 cstatus.value = (*ha->func.statupd) (ha);
1470
1471 if (cstatus.value == 0xffffffff)
1472 /* No more to process */
1473 break;
1474
1475 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1476 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1477 "Spurious interrupt; no ccb.\n");
1478
1479 continue;
1480 }
1481
1482 ips_chkstatus(ha, &cstatus);
1483 scb = (ips_scb_t *) sp->scb_addr;
1484
1485 /*
1486 * use the callback function to finish things up
1487 * NOTE: interrupts are OFF for this
1488 */
1489 (*scb->callback) (ha, scb);
1490 } /* end while */
1491 return 1;
1492 }
1493
1494 /****************************************************************************/
1495 /* */
1496 /* Routine Name: ips_info */
1497 /* */
1498 /* Routine Description: */
1499 /* */
1500 /* Return info about the driver */
1501 /* */
1502 /****************************************************************************/
1503 static const char *
1504 ips_info(struct Scsi_Host *SH)
1505 {
1506 static char buffer[256];
1507 char *bp;
1508 ips_ha_t *ha;
1509
1510 METHOD_TRACE("ips_info", 1);
1511
1512 ha = IPS_HA(SH);
1513
1514 if (!ha)
1515 return (NULL);
1516
1517 bp = &buffer[0];
1518 memset(bp, 0, sizeof (buffer));
1519
1520 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1521 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1522
1523 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1524 strcat(bp, " <");
1525 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1526 strcat(bp, ">");
1527 }
1528
1529 return (bp);
1530 }
1531
1532 /****************************************************************************/
1533 /* */
1534 /* Routine Name: ips_proc_info */
1535 /* */
1536 /* Routine Description: */
1537 /* */
1538 /* The passthru interface for the driver */
1539 /* */
1540 /****************************************************************************/
1541 static int
1542 ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1543 int length, int func)
1544 {
1545 int i;
1546 int ret;
1547 ips_ha_t *ha = NULL;
1548
1549 METHOD_TRACE("ips_proc_info", 1);
1550
1551 /* Find our host structure */
1552 for (i = 0; i < ips_next_controller; i++) {
1553 if (ips_sh[i]) {
1554 if (ips_sh[i] == host) {
1555 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1556 break;
1557 }
1558 }
1559 }
1560
1561 if (!ha)
1562 return (-EINVAL);
1563
1564 if (func) {
1565 /* write */
1566 return (0);
1567 } else {
1568 /* read */
1569 if (start)
1570 *start = buffer;
1571
1572 ret = ips_host_info(ha, buffer, offset, length);
1573
1574 return (ret);
1575 }
1576 }
1577
1578 /*--------------------------------------------------------------------------*/
1579 /* Helper Functions */
1580 /*--------------------------------------------------------------------------*/
1581
1582 /****************************************************************************/
1583 /* */
1584 /* Routine Name: ips_is_passthru */
1585 /* */
1586 /* Routine Description: */
1587 /* */
1588 /* Determine if the specified SCSI command is really a passthru command */
1589 /* */
1590 /****************************************************************************/
1591 static int
1592 ips_is_passthru(Scsi_Cmnd * SC)
1593 {
1594 METHOD_TRACE("ips_is_passthru", 1);
1595
1596 if (!SC)
1597 return (0);
1598
1599 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1600 (SC->device->channel == 0) &&
1601 (SC->device->id == IPS_ADAPTER_ID) &&
1602 (SC->device->lun == 0) && SC->request_buffer) {
1603 if ((!SC->use_sg) && SC->request_bufflen &&
1604 (((char *) SC->request_buffer)[0] == 'C') &&
1605 (((char *) SC->request_buffer)[1] == 'O') &&
1606 (((char *) SC->request_buffer)[2] == 'P') &&
1607 (((char *) SC->request_buffer)[3] == 'P'))
1608 return 1;
1609 else if (SC->use_sg) {
1610 struct scatterlist *sg = SC->request_buffer;
1611 char *buffer = IPS_SG_ADDRESS(sg);
1612 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1613 buffer[2] == 'P' && buffer[3] == 'P')
1614 return 1;
1615 }
1616 }
1617 return 0;
1618 }
1619
1620 /****************************************************************************/
1621 /* */
1622 /* Routine Name: ips_alloc_passthru_buffer */
1623 /* */
1624 /* Routine Description: */
1625 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1626 /* is too small or doesn't exist */
1627 /****************************************************************************/
1628 static int
1629 ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1630 {
1631 void *bigger_buf;
1632 dma_addr_t dma_busaddr;
1633
1634 if (ha->ioctl_data && length <= ha->ioctl_len)
1635 return 0;
1636 /* there is no buffer or it's not big enough, allocate a new one */
1637 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1638 if (bigger_buf) {
1639 /* free the old memory */
1640 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1641 ha->ioctl_busaddr);
1642 /* use the new memory */
1643 ha->ioctl_data = (char *) bigger_buf;
1644 ha->ioctl_len = length;
1645 ha->ioctl_busaddr = dma_busaddr;
1646 } else {
1647 return -1;
1648 }
1649 return 0;
1650 }
1651
1652 /****************************************************************************/
1653 /* */
1654 /* Routine Name: ips_make_passthru */
1655 /* */
1656 /* Routine Description: */
1657 /* */
1658 /* Make a passthru command out of the info in the Scsi block */
1659 /* */
1660 /****************************************************************************/
1661 static int
1662 ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr)
1663 {
1664 ips_passthru_t *pt;
1665 int length = 0;
1666 int ret;
1667
1668 METHOD_TRACE("ips_make_passthru", 1);
1669
1670 if (!SC->use_sg) {
1671 length = SC->request_bufflen;
1672 } else {
1673 struct scatterlist *sg = SC->request_buffer;
1674 int i;
1675 for (i = 0; i < SC->use_sg; i++)
1676 length += sg[i].length;
1677 }
1678 if (length < sizeof (ips_passthru_t)) {
1679 /* wrong size */
1680 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1681 ips_name, ha->host_num);
1682 return (IPS_FAILURE);
1683 }
1684 if (ips_alloc_passthru_buffer(ha, length)) {
1685 /* allocation failure! If ha->ioctl_data exists, use it to return
1686 some error codes. Return a failed command to the scsi layer. */
1687 if (ha->ioctl_data) {
1688 pt = (ips_passthru_t *) ha->ioctl_data;
1689 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1690 pt->BasicStatus = 0x0B;
1691 pt->ExtendedStatus = 0x00;
1692 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1693 }
1694 return IPS_FAILURE;
1695 }
1696 ha->ioctl_datasize = length;
1697
1698 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1699 pt = (ips_passthru_t *) ha->ioctl_data;
1700
1701 /*
1702 * Some notes about the passthru interface used
1703 *
1704 * IF the scsi op_code == 0x0d then we assume
1705 * that the data came along with/goes with the
1706 * packet we received from the sg driver. In this
1707 * case the CmdBSize field of the pt structure is
1708 * used for the size of the buffer.
1709 */
1710
1711 switch (pt->CoppCmd) {
1712 case IPS_NUMCTRLS:
1713 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1714 &ips_num_controllers, sizeof (int));
1715 ips_scmd_buf_write(SC, ha->ioctl_data,
1716 sizeof (ips_passthru_t) + sizeof (int));
1717 SC->result = DID_OK << 16;
1718
1719 return (IPS_SUCCESS_IMM);
1720
1721 case IPS_COPPUSRCMD:
1722 case IPS_COPPIOCCMD:
1723 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1724 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1725 /* wrong size */
1726 DEBUG_VAR(1,
1727 "(%s%d) Passthru structure wrong size",
1728 ips_name, ha->host_num);
1729
1730 return (IPS_FAILURE);
1731 }
1732
1733 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
1734 pt->CoppCP.cmd.flashfw.op_code ==
1735 IPS_CMD_RW_BIOSFW) {
1736 ret = ips_flash_copperhead(ha, pt, scb);
1737 ips_scmd_buf_write(SC, ha->ioctl_data,
1738 sizeof (ips_passthru_t));
1739 return ret;
1740 }
1741 if (ips_usrcmd(ha, pt, scb))
1742 return (IPS_SUCCESS);
1743 else
1744 return (IPS_FAILURE);
1745 }
1746
1747 break;
1748
1749 } /* end switch */
1750
1751 return (IPS_FAILURE);
1752 }
1753
1754 /****************************************************************************/
1755 /* Routine Name: ips_flash_copperhead */
1756 /* Routine Description: */
1757 /* Flash the BIOS/FW on a Copperhead style controller */
1758 /****************************************************************************/
1759 static int
1760 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1761 {
1762 int datasize;
1763
1764 /* Trombone is the only copperhead that can do packet flash, but only
1765 * for firmware. No one said it had to make sence. */
1766 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1767 if (ips_usrcmd(ha, pt, scb))
1768 return IPS_SUCCESS;
1769 else
1770 return IPS_FAILURE;
1771 }
1772 pt->BasicStatus = 0x0B;
1773 pt->ExtendedStatus = 0;
1774 scb->scsi_cmd->result = DID_OK << 16;
1775 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1776 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1777 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1778 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1779 pt->BasicStatus = 0;
1780 return ips_flash_bios(ha, pt, scb);
1781 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1782 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1783 ha->flash_data = ips_FlashData;
1784 ha->flash_busaddr = ips_flashbusaddr;
1785 ha->flash_len = PAGE_SIZE << 7;
1786 ha->flash_datasize = 0;
1787 } else if (!ha->flash_data) {
1788 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1789 pt->CoppCP.cmd.flashfw.count;
1790 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1791 datasize,
1792 &ha->flash_busaddr);
1793 if (!ha->flash_data){
1794 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1795 return IPS_FAILURE;
1796 }
1797 ha->flash_datasize = 0;
1798 ha->flash_len = datasize;
1799 } else
1800 return IPS_FAILURE;
1801 } else {
1802 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1803 ha->flash_len) {
1804 ips_free_flash_copperhead(ha);
1805 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1806 "failed size sanity check\n");
1807 return IPS_FAILURE;
1808 }
1809 }
1810 if (!ha->flash_data)
1811 return IPS_FAILURE;
1812 pt->BasicStatus = 0;
1813 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1814 pt->CoppCP.cmd.flashfw.count);
1815 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1816 if (pt->CoppCP.cmd.flashfw.packet_num ==
1817 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1818 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1819 return ips_flash_bios(ha, pt, scb);
1820 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1821 return ips_flash_firmware(ha, pt, scb);
1822 }
1823 return IPS_SUCCESS_IMM;
1824 }
1825
1826 /****************************************************************************/
1827 /* Routine Name: ips_flash_bios */
1828 /* Routine Description: */
1829 /* flashes the bios of a copperhead adapter */
1830 /****************************************************************************/
1831 static int
1832 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1833 {
1834
1835 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1836 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1837 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1838 (!ha->func.verifybios))
1839 goto error;
1840 if ((*ha->func.erasebios) (ha)) {
1841 DEBUG_VAR(1,
1842 "(%s%d) flash bios failed - unable to erase flash",
1843 ips_name, ha->host_num);
1844 goto error;
1845 } else
1846 if ((*ha->func.programbios) (ha,
1847 ha->flash_data +
1848 IPS_BIOS_HEADER,
1849 ha->flash_datasize -
1850 IPS_BIOS_HEADER, 0)) {
1851 DEBUG_VAR(1,
1852 "(%s%d) flash bios failed - unable to flash",
1853 ips_name, ha->host_num);
1854 goto error;
1855 } else
1856 if ((*ha->func.verifybios) (ha,
1857 ha->flash_data +
1858 IPS_BIOS_HEADER,
1859 ha->flash_datasize -
1860 IPS_BIOS_HEADER, 0)) {
1861 DEBUG_VAR(1,
1862 "(%s%d) flash bios failed - unable to verify flash",
1863 ips_name, ha->host_num);
1864 goto error;
1865 }
1866 ips_free_flash_copperhead(ha);
1867 return IPS_SUCCESS_IMM;
1868 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1869 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1870 if (!ha->func.erasebios)
1871 goto error;
1872 if ((*ha->func.erasebios) (ha)) {
1873 DEBUG_VAR(1,
1874 "(%s%d) flash bios failed - unable to erase flash",
1875 ips_name, ha->host_num);
1876 goto error;
1877 }
1878 return IPS_SUCCESS_IMM;
1879 }
1880 error:
1881 pt->BasicStatus = 0x0B;
1882 pt->ExtendedStatus = 0x00;
1883 ips_free_flash_copperhead(ha);
1884 return IPS_FAILURE;
1885 }
1886
1887 /****************************************************************************/
1888 /* */
1889 /* Routine Name: ips_fill_scb_sg_single */
1890 /* */
1891 /* Routine Description: */
1892 /* Fill in a single scb sg_list element from an address */
1893 /* return a -1 if a breakup occurred */
1894 /****************************************************************************/
1895 static int
1896 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1897 ips_scb_t * scb, int indx, unsigned int e_len)
1898 {
1899
1900 int ret_val = 0;
1901
1902 if ((scb->data_len + e_len) > ha->max_xfer) {
1903 e_len = ha->max_xfer - scb->data_len;
1904 scb->breakup = indx;
1905 ++scb->sg_break;
1906 ret_val = -1;
1907 } else {
1908 scb->breakup = 0;
1909 scb->sg_break = 0;
1910 }
1911 if (IPS_USE_ENH_SGLIST(ha)) {
1912 scb->sg_list.enh_list[indx].address_lo =
1913 cpu_to_le32(pci_dma_lo32(busaddr));
1914 scb->sg_list.enh_list[indx].address_hi =
1915 cpu_to_le32(pci_dma_hi32(busaddr));
1916 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1917 } else {
1918 scb->sg_list.std_list[indx].address =
1919 cpu_to_le32(pci_dma_lo32(busaddr));
1920 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1921 }
1922
1923 ++scb->sg_len;
1924 scb->data_len += e_len;
1925 return ret_val;
1926 }
1927
1928 /****************************************************************************/
1929 /* Routine Name: ips_flash_firmware */
1930 /* Routine Description: */
1931 /* flashes the firmware of a copperhead adapter */
1932 /****************************************************************************/
1933 static int
1934 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1935 {
1936 IPS_SG_LIST sg_list;
1937 uint32_t cmd_busaddr;
1938
1939 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1940 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1941 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1942 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1943 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1944 } else {
1945 pt->BasicStatus = 0x0B;
1946 pt->ExtendedStatus = 0x00;
1947 ips_free_flash_copperhead(ha);
1948 return IPS_FAILURE;
1949 }
1950 /* Save the S/G list pointer so it doesn't get clobbered */
1951 sg_list.list = scb->sg_list.list;
1952 cmd_busaddr = scb->scb_busaddr;
1953 /* copy in the CP */
1954 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1955 /* FIX stuff that might be wrong */
1956 scb->sg_list.list = sg_list.list;
1957 scb->scb_busaddr = cmd_busaddr;
1958 scb->bus = scb->scsi_cmd->device->channel;
1959 scb->target_id = scb->scsi_cmd->device->id;
1960 scb->lun = scb->scsi_cmd->device->lun;
1961 scb->sg_len = 0;
1962 scb->data_len = 0;
1963 scb->flags = 0;
1964 scb->op_code = 0;
1965 scb->callback = ipsintr_done;
1966 scb->timeout = ips_cmd_timeout;
1967
1968 scb->data_len = ha->flash_datasize;
1969 scb->data_busaddr =
1970 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1971 IPS_DMA_DIR(scb));
1972 scb->flags |= IPS_SCB_MAP_SINGLE;
1973 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1974 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1975 if (pt->TimeOut)
1976 scb->timeout = pt->TimeOut;
1977 scb->scsi_cmd->result = DID_OK << 16;
1978 return IPS_SUCCESS;
1979 }
1980
1981 /****************************************************************************/
1982 /* Routine Name: ips_free_flash_copperhead */
1983 /* Routine Description: */
1984 /* release the memory resources used to hold the flash image */
1985 /****************************************************************************/
1986 static void
1987 ips_free_flash_copperhead(ips_ha_t * ha)
1988 {
1989 if (ha->flash_data == ips_FlashData)
1990 test_and_clear_bit(0, &ips_FlashDataInUse);
1991 else if (ha->flash_data)
1992 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1993 ha->flash_busaddr);
1994 ha->flash_data = NULL;
1995 }
1996
1997 /****************************************************************************/
1998 /* */
1999 /* Routine Name: ips_usrcmd */
2000 /* */
2001 /* Routine Description: */
2002 /* */
2003 /* Process a user command and make it ready to send */
2004 /* */
2005 /****************************************************************************/
2006 static int
2007 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
2008 {
2009 IPS_SG_LIST sg_list;
2010 uint32_t cmd_busaddr;
2011
2012 METHOD_TRACE("ips_usrcmd", 1);
2013
2014 if ((!scb) || (!pt) || (!ha))
2015 return (0);
2016
2017 /* Save the S/G list pointer so it doesn't get clobbered */
2018 sg_list.list = scb->sg_list.list;
2019 cmd_busaddr = scb->scb_busaddr;
2020 /* copy in the CP */
2021 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
2022 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
2023
2024 /* FIX stuff that might be wrong */
2025 scb->sg_list.list = sg_list.list;
2026 scb->scb_busaddr = cmd_busaddr;
2027 scb->bus = scb->scsi_cmd->device->channel;
2028 scb->target_id = scb->scsi_cmd->device->id;
2029 scb->lun = scb->scsi_cmd->device->lun;
2030 scb->sg_len = 0;
2031 scb->data_len = 0;
2032 scb->flags = 0;
2033 scb->op_code = 0;
2034 scb->callback = ipsintr_done;
2035 scb->timeout = ips_cmd_timeout;
2036 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
2037
2038 /* we don't support DCDB/READ/WRITE Scatter Gather */
2039 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
2040 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
2041 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
2042 return (0);
2043
2044 if (pt->CmdBSize) {
2045 scb->data_len = pt->CmdBSize;
2046 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
2047 } else {
2048 scb->data_busaddr = 0L;
2049 }
2050
2051 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2052 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
2053 (unsigned long) &scb->
2054 dcdb -
2055 (unsigned long) scb);
2056
2057 if (pt->CmdBSize) {
2058 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2059 scb->dcdb.buffer_pointer =
2060 cpu_to_le32(scb->data_busaddr);
2061 else
2062 scb->cmd.basic_io.sg_addr =
2063 cpu_to_le32(scb->data_busaddr);
2064 }
2065
2066 /* set timeouts */
2067 if (pt->TimeOut) {
2068 scb->timeout = pt->TimeOut;
2069
2070 if (pt->TimeOut <= 10)
2071 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
2072 else if (pt->TimeOut <= 60)
2073 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
2074 else
2075 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
2076 }
2077
2078 /* assume success */
2079 scb->scsi_cmd->result = DID_OK << 16;
2080
2081 /* success */
2082 return (1);
2083 }
2084
2085 /****************************************************************************/
2086 /* */
2087 /* Routine Name: ips_cleanup_passthru */
2088 /* */
2089 /* Routine Description: */
2090 /* */
2091 /* Cleanup after a passthru command */
2092 /* */
2093 /****************************************************************************/
2094 static void
2095 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2096 {
2097 ips_passthru_t *pt;
2098
2099 METHOD_TRACE("ips_cleanup_passthru", 1);
2100
2101 if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) {
2102 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2103 ips_name, ha->host_num);
2104
2105 return;
2106 }
2107 pt = (ips_passthru_t *) ha->ioctl_data;
2108
2109 /* Copy data back to the user */
2110 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2111 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2112
2113 pt->BasicStatus = scb->basic_status;
2114 pt->ExtendedStatus = scb->extended_status;
2115 pt->AdapterType = ha->ad_type;
2116
2117 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
2118 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2119 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2120 ips_free_flash_copperhead(ha);
2121
2122 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2123 }
2124
2125 /****************************************************************************/
2126 /* */
2127 /* Routine Name: ips_host_info */
2128 /* */
2129 /* Routine Description: */
2130 /* */
2131 /* The passthru interface for the driver */
2132 /* */
2133 /****************************************************************************/
2134 static int
2135 ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2136 {
2137 IPS_INFOSTR info;
2138
2139 METHOD_TRACE("ips_host_info", 1);
2140
2141 info.buffer = ptr;
2142 info.length = len;
2143 info.offset = offset;
2144 info.pos = 0;
2145 info.localpos = 0;
2146
2147 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2148
2149 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2150 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2151 copy_info(&info, "\tController Type : %s\n",
2152 ips_adapter_name[ha->ad_type - 1]);
2153 else
2154 copy_info(&info,
2155 "\tController Type : Unknown\n");
2156
2157 if (ha->io_addr)
2158 copy_info(&info,
2159 "\tIO region : 0x%lx (%d bytes)\n",
2160 ha->io_addr, ha->io_len);
2161
2162 if (ha->mem_addr) {
2163 copy_info(&info,
2164 "\tMemory region : 0x%lx (%d bytes)\n",
2165 ha->mem_addr, ha->mem_len);
2166 copy_info(&info,
2167 "\tShared memory address : 0x%lx\n",
2168 ha->mem_ptr);
2169 }
2170
2171 copy_info(&info, "\tIRQ number : %d\n", ha->irq);
2172
2173 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2174 /* That keeps everything happy for "text" operations on the proc file. */
2175
2176 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2177 if (ha->nvram->bios_low[3] == 0) {
2178 copy_info(&info,
2179 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2180 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2181 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2182 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2183 ha->nvram->bios_low[2]);
2184
2185 } else {
2186 copy_info(&info,
2187 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2188 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2189 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2190 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2191 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2192 }
2193
2194 }
2195
2196 if (ha->enq->CodeBlkVersion[7] == 0) {
2197 copy_info(&info,
2198 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2199 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2200 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2201 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2202 ha->enq->CodeBlkVersion[6]);
2203 } else {
2204 copy_info(&info,
2205 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2206 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2207 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2208 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2209 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2210 }
2211
2212 if (ha->enq->BootBlkVersion[7] == 0) {
2213 copy_info(&info,
2214 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2215 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2216 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2217 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2218 ha->enq->BootBlkVersion[6]);
2219 } else {
2220 copy_info(&info,
2221 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2222 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2223 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2224 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2225 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2226 }
2227
2228 copy_info(&info, "\tDriver Version : %s%s\n",
2229 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2230
2231 copy_info(&info, "\tDriver Build : %d\n",
2232 IPS_BUILD_IDENT);
2233
2234 copy_info(&info, "\tMax Physical Devices : %d\n",
2235 ha->enq->ucMaxPhysicalDevices);
2236 copy_info(&info, "\tMax Active Commands : %d\n",
2237 ha->max_cmds);
2238 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2239 ha->scb_waitlist.count);
2240 copy_info(&info, "\tCurrent Active Commands : %d\n",
2241 ha->scb_activelist.count - ha->num_ioctl);
2242 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2243 ha->copp_waitlist.count);
2244 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2245 ha->num_ioctl);
2246
2247 copy_info(&info, "\n");
2248
2249 return (info.localpos);
2250 }
2251
2252 /****************************************************************************/
2253 /* */
2254 /* Routine Name: copy_mem_info */
2255 /* */
2256 /* Routine Description: */
2257 /* */
2258 /* Copy data into an IPS_INFOSTR structure */
2259 /* */
2260 /****************************************************************************/
2261 static void
2262 copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2263 {
2264 METHOD_TRACE("copy_mem_info", 1);
2265
2266 if (info->pos + len < info->offset) {
2267 info->pos += len;
2268 return;
2269 }
2270
2271 if (info->pos < info->offset) {
2272 data += (info->offset - info->pos);
2273 len -= (info->offset - info->pos);
2274 info->pos += (info->offset - info->pos);
2275 }
2276
2277 if (info->localpos + len > info->length)
2278 len = info->length - info->localpos;
2279
2280 if (len > 0) {
2281 memcpy(info->buffer + info->localpos, data, len);
2282 info->pos += len;
2283 info->localpos += len;
2284 }
2285 }
2286
2287 /****************************************************************************/
2288 /* */
2289 /* Routine Name: copy_info */
2290 /* */
2291 /* Routine Description: */
2292 /* */
2293 /* printf style wrapper for an info structure */
2294 /* */
2295 /****************************************************************************/
2296 static int
2297 copy_info(IPS_INFOSTR * info, char *fmt, ...)
2298 {
2299 va_list args;
2300 char buf[128];
2301 int len;
2302
2303 METHOD_TRACE("copy_info", 1);
2304
2305 va_start(args, fmt);
2306 len = vsprintf(buf, fmt, args);
2307 va_end(args);
2308
2309 copy_mem_info(info, buf, len);
2310
2311 return (len);
2312 }
2313
2314 /****************************************************************************/
2315 /* */
2316 /* Routine Name: ips_identify_controller */
2317 /* */
2318 /* Routine Description: */
2319 /* */
2320 /* Identify this controller */
2321 /* */
2322 /****************************************************************************/
2323 static void
2324 ips_identify_controller(ips_ha_t * ha)
2325 {
2326 METHOD_TRACE("ips_identify_controller", 1);
2327
2328 switch (ha->device_id) {
2329 case IPS_DEVICEID_COPPERHEAD:
2330 if (ha->revision_id <= IPS_REVID_SERVERAID) {
2331 ha->ad_type = IPS_ADTYPE_SERVERAID;
2332 } else if (ha->revision_id == IPS_REVID_SERVERAID2) {
2333 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2334 } else if (ha->revision_id == IPS_REVID_NAVAJO) {
2335 ha->ad_type = IPS_ADTYPE_NAVAJO;
2336 } else if ((ha->revision_id == IPS_REVID_SERVERAID2)
2337 && (ha->slot_num == 0)) {
2338 ha->ad_type = IPS_ADTYPE_KIOWA;
2339 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
2340 (ha->revision_id <= IPS_REVID_CLARINETP3)) {
2341 if (ha->enq->ucMaxPhysicalDevices == 15)
2342 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2343 else
2344 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2345 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
2346 (ha->revision_id <= IPS_REVID_TROMBONE64)) {
2347 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2348 }
2349 break;
2350
2351 case IPS_DEVICEID_MORPHEUS:
2352 switch (ha->subdevice_id) {
2353 case IPS_SUBDEVICEID_4L:
2354 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2355 break;
2356
2357 case IPS_SUBDEVICEID_4M:
2358 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2359 break;
2360
2361 case IPS_SUBDEVICEID_4MX:
2362 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2363 break;
2364
2365 case IPS_SUBDEVICEID_4LX:
2366 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2367 break;
2368
2369 case IPS_SUBDEVICEID_5I2:
2370 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2371 break;
2372
2373 case IPS_SUBDEVICEID_5I1:
2374 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2375 break;
2376 }
2377
2378 break;
2379
2380 case IPS_DEVICEID_MARCO:
2381 switch (ha->subdevice_id) {
2382 case IPS_SUBDEVICEID_6M:
2383 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2384 break;
2385 case IPS_SUBDEVICEID_6I:
2386 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2387 break;
2388 case IPS_SUBDEVICEID_7k:
2389 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2390 break;
2391 case IPS_SUBDEVICEID_7M:
2392 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2393 break;
2394 }
2395 break;
2396 }
2397 }
2398
2399 /****************************************************************************/
2400 /* */
2401 /* Routine Name: ips_get_bios_version */
2402 /* */
2403 /* Routine Description: */
2404 /* */
2405 /* Get the BIOS revision number */
2406 /* */
2407 /****************************************************************************/
2408 static void
2409 ips_get_bios_version(ips_ha_t * ha, int intr)
2410 {
2411 ips_scb_t *scb;
2412 int ret;
2413 uint8_t major;
2414 uint8_t minor;
2415 uint8_t subminor;
2416 uint8_t *buffer;
2417 char hexDigits[] =
2418 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2419 'D', 'E', 'F' };
2420
2421 METHOD_TRACE("ips_get_bios_version", 1);
2422
2423 major = 0;
2424 minor = 0;
2425
2426 strncpy(ha->bios_version, " ?", 8);
2427
2428 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
2429 if (IPS_USE_MEMIO(ha)) {
2430 /* Memory Mapped I/O */
2431
2432 /* test 1st byte */
2433 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2434 if (ha->revision_id == IPS_REVID_TROMBONE64)
2435 udelay(25); /* 25 us */
2436
2437 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2438 return;
2439
2440 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2441 if (ha->revision_id == IPS_REVID_TROMBONE64)
2442 udelay(25); /* 25 us */
2443
2444 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2445 return;
2446
2447 /* Get Major version */
2448 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2449 if (ha->revision_id == IPS_REVID_TROMBONE64)
2450 udelay(25); /* 25 us */
2451
2452 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2453
2454 /* Get Minor version */
2455 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2456 if (ha->revision_id == IPS_REVID_TROMBONE64)
2457 udelay(25); /* 25 us */
2458 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2459
2460 /* Get SubMinor version */
2461 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2462 if (ha->revision_id == IPS_REVID_TROMBONE64)
2463 udelay(25); /* 25 us */
2464 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2465
2466 } else {
2467 /* Programmed I/O */
2468
2469 /* test 1st byte */
2470 outl(0, ha->io_addr + IPS_REG_FLAP);
2471 if (ha->revision_id == IPS_REVID_TROMBONE64)
2472 udelay(25); /* 25 us */
2473
2474 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2475 return;
2476
2477 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2478 if (ha->revision_id == IPS_REVID_TROMBONE64)
2479 udelay(25); /* 25 us */
2480
2481 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2482 return;
2483
2484 /* Get Major version */
2485 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2486 if (ha->revision_id == IPS_REVID_TROMBONE64)
2487 udelay(25); /* 25 us */
2488
2489 major = inb(ha->io_addr + IPS_REG_FLDP);
2490
2491 /* Get Minor version */
2492 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2493 if (ha->revision_id == IPS_REVID_TROMBONE64)
2494 udelay(25); /* 25 us */
2495
2496 minor = inb(ha->io_addr + IPS_REG_FLDP);
2497
2498 /* Get SubMinor version */
2499 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2500 if (ha->revision_id == IPS_REVID_TROMBONE64)
2501 udelay(25); /* 25 us */
2502
2503 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2504
2505 }
2506 } else {
2507 /* Morpheus Family - Send Command to the card */
2508
2509 buffer = ha->ioctl_data;
2510
2511 memset(buffer, 0, 0x1000);
2512
2513 scb = &ha->scbs[ha->max_cmds - 1];
2514
2515 ips_init_scb(ha, scb);
2516
2517 scb->timeout = ips_cmd_timeout;
2518 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2519
2520 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2521 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2522 scb->cmd.flashfw.type = 1;
2523 scb->cmd.flashfw.direction = 0;
2524 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2525 scb->cmd.flashfw.total_packets = 1;
2526 scb->cmd.flashfw.packet_num = 0;
2527 scb->data_len = 0x1000;
2528 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2529
2530 /* issue the command */
2531 if (((ret =
2532 ips_send_wait(ha, scb, ips_cmd_timeout,
2533 intr)) == IPS_FAILURE)
2534 || (ret == IPS_SUCCESS_IMM)
2535 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2536 /* Error occurred */
2537
2538 return;
2539 }
2540
2541 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2542 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2543 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2544 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2545 } else {
2546 return;
2547 }
2548 }
2549
2550 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2551 ha->bios_version[1] = '.';
2552 ha->bios_version[2] = hexDigits[major & 0x0F];
2553 ha->bios_version[3] = hexDigits[subminor];
2554 ha->bios_version[4] = '.';
2555 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2556 ha->bios_version[6] = hexDigits[minor & 0x0F];
2557 ha->bios_version[7] = 0;
2558 }
2559
2560 /****************************************************************************/
2561 /* */
2562 /* Routine Name: ips_hainit */
2563 /* */
2564 /* Routine Description: */
2565 /* */
2566 /* Initialize the controller */
2567 /* */
2568 /* NOTE: Assumes to be called from with a lock */
2569 /* */
2570 /****************************************************************************/
2571 static int
2572 ips_hainit(ips_ha_t * ha)
2573 {
2574 int i;
2575 struct timeval tv;
2576
2577 METHOD_TRACE("ips_hainit", 1);
2578
2579 if (!ha)
2580 return (0);
2581
2582 if (ha->func.statinit)
2583 (*ha->func.statinit) (ha);
2584
2585 if (ha->func.enableint)
2586 (*ha->func.enableint) (ha);
2587
2588 /* Send FFDC */
2589 ha->reset_count = 1;
2590 do_gettimeofday(&tv);
2591 ha->last_ffdc = tv.tv_sec;
2592 ips_ffdc_reset(ha, IPS_INTR_IORL);
2593
2594 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2595 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2596 "unable to read config from controller.\n");
2597
2598 return (0);
2599 }
2600 /* end if */
2601 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2602 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2603 "unable to read controller status.\n");
2604
2605 return (0);
2606 }
2607
2608 /* Identify this controller */
2609 ips_identify_controller(ha);
2610
2611 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2612 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2613 "unable to read subsystem parameters.\n");
2614
2615 return (0);
2616 }
2617
2618 /* write nvram user page 5 */
2619 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2620 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2621 "unable to write driver info to controller.\n");
2622
2623 return (0);
2624 }
2625
2626 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2627 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2628 ips_clear_adapter(ha, IPS_INTR_IORL);
2629
2630 /* set limits on SID, LUN, BUS */
2631 ha->ntargets = IPS_MAX_TARGETS + 1;
2632 ha->nlun = 1;
2633 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2634
2635 switch (ha->conf->logical_drive[0].ucStripeSize) {
2636 case 4:
2637 ha->max_xfer = 0x10000;
2638 break;
2639
2640 case 5:
2641 ha->max_xfer = 0x20000;
2642 break;
2643
2644 case 6:
2645 ha->max_xfer = 0x40000;
2646 break;
2647
2648 case 7:
2649 default:
2650 ha->max_xfer = 0x80000;
2651 break;
2652 }
2653
2654 /* setup max concurrent commands */
2655 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2656 /* Use the new method */
2657 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2658 } else {
2659 /* use the old method */
2660 switch (ha->conf->logical_drive[0].ucStripeSize) {
2661 case 4:
2662 ha->max_cmds = 32;
2663 break;
2664
2665 case 5:
2666 ha->max_cmds = 16;
2667 break;
2668
2669 case 6:
2670 ha->max_cmds = 8;
2671 break;
2672
2673 case 7:
2674 default:
2675 ha->max_cmds = 4;
2676 break;
2677 }
2678 }
2679
2680 /* Limit the Active Commands on a Lite Adapter */
2681 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2682 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2683 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2684 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2685 ha->max_cmds = MaxLiteCmds;
2686 }
2687
2688 /* set controller IDs */
2689 ha->ha_id[0] = IPS_ADAPTER_ID;
2690 for (i = 1; i < ha->nbus; i++) {
2691 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2692 ha->dcdb_active[i - 1] = 0;
2693 }
2694
2695 return (1);
2696 }
2697
2698 /****************************************************************************/
2699 /* */
2700 /* Routine Name: ips_next */
2701 /* */
2702 /* Routine Description: */
2703 /* */
2704 /* Take the next command off the queue and send it to the controller */
2705 /* */
2706 /****************************************************************************/
2707 static void
2708 ips_next(ips_ha_t * ha, int intr)
2709 {
2710 ips_scb_t *scb;
2711 Scsi_Cmnd *SC;
2712 Scsi_Cmnd *p;
2713 Scsi_Cmnd *q;
2714 ips_copp_wait_item_t *item;
2715 int ret;
2716 unsigned long cpu_flags = 0;
2717 struct Scsi_Host *host;
2718 METHOD_TRACE("ips_next", 1);
2719
2720 if (!ha)
2721 return;
2722 host = ips_sh[ha->host_num];
2723 /*
2724 * Block access to the queue function so
2725 * this command won't time out
2726 */
2727 if (intr == IPS_INTR_ON)
2728 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2729
2730 if ((ha->subsys->param[3] & 0x300000)
2731 && (ha->scb_activelist.count == 0)) {
2732 struct timeval tv;
2733
2734 do_gettimeofday(&tv);
2735
2736 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2737 ha->last_ffdc = tv.tv_sec;
2738 ips_ffdc_time(ha);
2739 }
2740 }
2741
2742 /*
2743 * Send passthru commands
2744 * These have priority over normal I/O
2745 * but shouldn't affect performance too much
2746 * since we limit the number that can be active
2747 * on the card at any one time
2748 */
2749 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2750 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2751
2752 item = ips_removeq_copp_head(&ha->copp_waitlist);
2753 ha->num_ioctl++;
2754 if (intr == IPS_INTR_ON)
2755 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2756 scb->scsi_cmd = item->scsi_cmd;
2757 kfree(item);
2758
2759 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2760
2761 if (intr == IPS_INTR_ON)
2762 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2763 switch (ret) {
2764 case IPS_FAILURE:
2765 if (scb->scsi_cmd) {
2766 scb->scsi_cmd->result = DID_ERROR << 16;
2767 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2768 }
2769
2770 ips_freescb(ha, scb);
2771 break;
2772 case IPS_SUCCESS_IMM:
2773 if (scb->scsi_cmd) {
2774 scb->scsi_cmd->result = DID_OK << 16;
2775 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2776 }
2777
2778 ips_freescb(ha, scb);
2779 break;
2780 default:
2781 break;
2782 } /* end case */
2783
2784 if (ret != IPS_SUCCESS) {
2785 ha->num_ioctl--;
2786 continue;
2787 }
2788
2789 ret = ips_send_cmd(ha, scb);
2790
2791 if (ret == IPS_SUCCESS)
2792 ips_putq_scb_head(&ha->scb_activelist, scb);
2793 else
2794 ha->num_ioctl--;
2795
2796 switch (ret) {
2797 case IPS_FAILURE:
2798 if (scb->scsi_cmd) {
2799 scb->scsi_cmd->result = DID_ERROR << 16;
2800 }
2801
2802 ips_freescb(ha, scb);
2803 break;
2804 case IPS_SUCCESS_IMM:
2805 ips_freescb(ha, scb);
2806 break;
2807 default:
2808 break;
2809 } /* end case */
2810
2811 }
2812
2813 /*
2814 * Send "Normal" I/O commands
2815 */
2816
2817 p = ha->scb_waitlist.head;
2818 while ((p) && (scb = ips_getscb(ha))) {
2819 if ((p->device->channel > 0)
2820 && (ha->
2821 dcdb_active[p->device->channel -
2822 1] & (1 << p->device->id))) {
2823 ips_freescb(ha, scb);
2824 p = (Scsi_Cmnd *) p->host_scribble;
2825 continue;
2826 }
2827
2828 q = p;
2829 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2830
2831 if (intr == IPS_INTR_ON)
2832 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */
2833
2834 SC->result = DID_OK;
2835 SC->host_scribble = NULL;
2836
2837 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
2838
2839 scb->target_id = SC->device->id;
2840 scb->lun = SC->device->lun;
2841 scb->bus = SC->device->channel;
2842 scb->scsi_cmd = SC;
2843 scb->breakup = 0;
2844 scb->data_len = 0;
2845 scb->callback = ipsintr_done;
2846 scb->timeout = ips_cmd_timeout;
2847 memset(&scb->cmd, 0, 16);
2848
2849 /* copy in the CDB */
2850 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2851
2852 /* Now handle the data buffer */
2853 if (SC->use_sg) {
2854 struct scatterlist *sg;
2855 int i;
2856
2857 sg = SC->request_buffer;
2858 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
2859 scsi_to_pci_dma_dir(SC->
2860 sc_data_direction));
2861 scb->flags |= IPS_SCB_MAP_SG;
2862 for (i = 0; i < scb->sg_count; i++) {
2863 if (ips_fill_scb_sg_single
2864 (ha, sg_dma_address(&sg[i]), scb, i,
2865 sg_dma_len(&sg[i])) < 0)
2866 break;
2867 }
2868 scb->dcdb.transfer_length = scb->data_len;
2869 } else {
2870 if (SC->request_bufflen) {
2871 scb->data_busaddr =
2872 pci_map_single(ha->pcidev,
2873 SC->request_buffer,
2874 SC->request_bufflen,
2875 scsi_to_pci_dma_dir(SC->
2876 sc_data_direction));
2877 scb->flags |= IPS_SCB_MAP_SINGLE;
2878 ips_fill_scb_sg_single(ha, scb->data_busaddr,
2879 scb, 0,
2880 SC->request_bufflen);
2881 scb->dcdb.transfer_length = scb->data_len;
2882 } else {
2883 scb->data_busaddr = 0L;
2884 scb->sg_len = 0;
2885 scb->data_len = 0;
2886 scb->dcdb.transfer_length = 0;
2887 }
2888
2889 }
2890
2891 scb->dcdb.cmd_attribute =
2892 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2893
2894 /* Allow a WRITE BUFFER Command to Have no Data */
2895 /* This is Used by Tape Flash Utilites */
2896 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0))
2897 scb->dcdb.cmd_attribute = 0;
2898
2899 if (!(scb->dcdb.cmd_attribute & 0x3))
2900 scb->dcdb.transfer_length = 0;
2901
2902 if (scb->data_len >= IPS_MAX_XFER) {
2903 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2904 scb->dcdb.transfer_length = 0;
2905 }
2906 if (intr == IPS_INTR_ON)
2907 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2908
2909 ret = ips_send_cmd(ha, scb);
2910
2911 switch (ret) {
2912 case IPS_SUCCESS:
2913 ips_putq_scb_head(&ha->scb_activelist, scb);
2914 break;
2915 case IPS_FAILURE:
2916 if (scb->scsi_cmd) {
2917 scb->scsi_cmd->result = DID_ERROR << 16;
2918 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2919 }
2920
2921 if (scb->bus)
2922 ha->dcdb_active[scb->bus - 1] &=
2923 ~(1 << scb->target_id);
2924
2925 ips_freescb(ha, scb);
2926 break;
2927 case IPS_SUCCESS_IMM:
2928 if (scb->scsi_cmd)
2929 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2930
2931 if (scb->bus)
2932 ha->dcdb_active[scb->bus - 1] &=
2933 ~(1 << scb->target_id);
2934
2935 ips_freescb(ha, scb);
2936 break;
2937 default:
2938 break;
2939 } /* end case */
2940
2941 p = (Scsi_Cmnd *) p->host_scribble;
2942
2943 } /* end while */
2944
2945 if (intr == IPS_INTR_ON)
2946 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2947 }
2948
2949 /****************************************************************************/
2950 /* */
2951 /* Routine Name: ips_putq_scb_head */
2952 /* */
2953 /* Routine Description: */
2954 /* */
2955 /* Add an item to the head of the queue */
2956 /* */
2957 /* ASSUMED to be called from within the HA lock */
2958 /* */
2959 /****************************************************************************/
2960 static void
2961 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2962 {
2963 METHOD_TRACE("ips_putq_scb_head", 1);
2964
2965 if (!item)
2966 return;
2967
2968 item->q_next = queue->head;
2969 queue->head = item;
2970
2971 if (!queue->tail)
2972 queue->tail = item;
2973
2974 queue->count++;
2975 }
2976
2977 /****************************************************************************/
2978 /* */
2979 /* Routine Name: ips_removeq_scb_head */
2980 /* */
2981 /* Routine Description: */
2982 /* */
2983 /* Remove the head of the queue */
2984 /* */
2985 /* ASSUMED to be called from within the HA lock */
2986 /* */
2987 /****************************************************************************/
2988 static ips_scb_t *
2989 ips_removeq_scb_head(ips_scb_queue_t * queue)
2990 {
2991 ips_scb_t *item;
2992
2993 METHOD_TRACE("ips_removeq_scb_head", 1);
2994
2995 item = queue->head;
2996
2997 if (!item) {
2998 return (NULL);
2999 }
3000
3001 queue->head = item->q_next;
3002 item->q_next = NULL;
3003
3004 if (queue->tail == item)
3005 queue->tail = NULL;
3006
3007 queue->count--;
3008
3009 return (item);
3010 }
3011
3012 /****************************************************************************/
3013 /* */
3014 /* Routine Name: ips_removeq_scb */
3015 /* */
3016 /* Routine Description: */
3017 /* */
3018 /* Remove an item from a queue */
3019 /* */
3020 /* ASSUMED to be called from within the HA lock */
3021 /* */
3022 /****************************************************************************/
3023 static ips_scb_t *
3024 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
3025 {
3026 ips_scb_t *p;
3027
3028 METHOD_TRACE("ips_removeq_scb", 1);
3029
3030 if (!item)
3031 return (NULL);
3032
3033 if (item == queue->head) {
3034 return (ips_removeq_scb_head(queue));
3035 }
3036
3037 p = queue->head;
3038
3039 while ((p) && (item != p->q_next))
3040 p = p->q_next;
3041
3042 if (p) {
3043 /* found a match */
3044 p->q_next = item->q_next;
3045
3046 if (!item->q_next)
3047 queue->tail = p;
3048
3049 item->q_next = NULL;
3050 queue->count--;
3051
3052 return (item);
3053 }
3054
3055 return (NULL);
3056 }
3057
3058 /****************************************************************************/
3059 /* */
3060 /* Routine Name: ips_putq_wait_tail */
3061 /* */
3062 /* Routine Description: */
3063 /* */
3064 /* Add an item to the tail of the queue */
3065 /* */
3066 /* ASSUMED to be called from within the HA lock */
3067 /* */
3068 /****************************************************************************/
3069 static void
3070 ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3071 {
3072 METHOD_TRACE("ips_putq_wait_tail", 1);
3073
3074 if (!item)
3075 return;
3076
3077 item->host_scribble = NULL;
3078
3079 if (queue->tail)
3080 queue->tail->host_scribble = (char *) item;
3081
3082 queue->tail = item;
3083
3084 if (!queue->head)
3085 queue->head = item;
3086
3087 queue->count++;
3088 }
3089
3090 /****************************************************************************/
3091 /* */
3092 /* Routine Name: ips_removeq_wait_head */
3093 /* */
3094 /* Routine Description: */
3095 /* */
3096 /* Remove the head of the queue */
3097 /* */
3098 /* ASSUMED to be called from within the HA lock */
3099 /* */
3100 /****************************************************************************/
3101 static Scsi_Cmnd *
3102 ips_removeq_wait_head(ips_wait_queue_t * queue)
3103 {
3104 Scsi_Cmnd *item;
3105
3106 METHOD_TRACE("ips_removeq_wait_head", 1);
3107
3108 item = queue->head;
3109
3110 if (!item) {
3111 return (NULL);
3112 }
3113
3114 queue->head = (Scsi_Cmnd *) item->host_scribble;
3115 item->host_scribble = NULL;
3116
3117 if (queue->tail == item)
3118 queue->tail = NULL;
3119
3120 queue->count--;
3121
3122 return (item);
3123 }
3124
3125 /****************************************************************************/
3126 /* */
3127 /* Routine Name: ips_removeq_wait */
3128 /* */
3129 /* Routine Description: */
3130 /* */
3131 /* Remove an item from a queue */
3132 /* */
3133 /* ASSUMED to be called from within the HA lock */
3134 /* */
3135 /****************************************************************************/
3136 static Scsi_Cmnd *
3137 ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3138 {
3139 Scsi_Cmnd *p;
3140
3141 METHOD_TRACE("ips_removeq_wait", 1);
3142
3143 if (!item)
3144 return (NULL);
3145
3146 if (item == queue->head) {
3147 return (ips_removeq_wait_head(queue));
3148 }
3149
3150 p = queue->head;
3151
3152 while ((p) && (item != (Scsi_Cmnd *) p->host_scribble))
3153 p = (Scsi_Cmnd *) p->host_scribble;
3154
3155 if (p) {
3156 /* found a match */
3157 p->host_scribble = item->host_scribble;
3158
3159 if (!item->host_scribble)
3160 queue->tail = p;
3161
3162 item->host_scribble = NULL;
3163 queue->count--;
3164
3165 return (item);
3166 }
3167
3168 return (NULL);
3169 }
3170
3171 /****************************************************************************/
3172 /* */
3173 /* Routine Name: ips_putq_copp_tail */
3174 /* */
3175 /* Routine Description: */
3176 /* */
3177 /* Add an item to the tail of the queue */
3178 /* */
3179 /* ASSUMED to be called from within the HA lock */
3180 /* */
3181 /****************************************************************************/
3182 static void
3183 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3184 {
3185 METHOD_TRACE("ips_putq_copp_tail", 1);
3186
3187 if (!item)
3188 return;
3189
3190 item->next = NULL;
3191
3192 if (queue->tail)
3193 queue->tail->next = item;
3194
3195 queue->tail = item;
3196
3197 if (!queue->head)
3198 queue->head = item;
3199
3200 queue->count++;
3201 }
3202
3203 /****************************************************************************/
3204 /* */
3205 /* Routine Name: ips_removeq_copp_head */
3206 /* */
3207 /* Routine Description: */
3208 /* */
3209 /* Remove the head of the queue */
3210 /* */
3211 /* ASSUMED to be called from within the HA lock */
3212 /* */
3213 /****************************************************************************/
3214 static ips_copp_wait_item_t *
3215 ips_removeq_copp_head(ips_copp_queue_t * queue)
3216 {
3217 ips_copp_wait_item_t *item;
3218
3219 METHOD_TRACE("ips_removeq_copp_head", 1);
3220
3221 item = queue->head;
3222
3223 if (!item) {
3224 return (NULL);
3225 }
3226
3227 queue->head = item->next;
3228 item->next = NULL;
3229
3230 if (queue->tail == item)
3231 queue->tail = NULL;
3232
3233 queue->count--;
3234
3235 return (item);
3236 }
3237
3238 /****************************************************************************/
3239 /* */
3240 /* Routine Name: ips_removeq_copp */
3241 /* */
3242 /* Routine Description: */
3243 /* */
3244 /* Remove an item from a queue */
3245 /* */
3246 /* ASSUMED to be called from within the HA lock */
3247 /* */
3248 /****************************************************************************/
3249 static ips_copp_wait_item_t *
3250 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3251 {
3252 ips_copp_wait_item_t *p;
3253
3254 METHOD_TRACE("ips_removeq_copp", 1);
3255
3256 if (!item)
3257 return (NULL);
3258
3259 if (item == queue->head) {
3260 return (ips_removeq_copp_head(queue));
3261 }
3262
3263 p = queue->head;
3264
3265 while ((p) && (item != p->next))
3266 p = p->next;
3267
3268 if (p) {
3269 /* found a match */
3270 p->next = item->next;
3271
3272 if (!item->next)
3273 queue->tail = p;
3274
3275 item->next = NULL;
3276 queue->count--;
3277
3278 return (item);
3279 }
3280
3281 return (NULL);
3282 }
3283
3284 /****************************************************************************/
3285 /* */
3286 /* Routine Name: ipsintr_blocking */
3287 /* */
3288 /* Routine Description: */
3289 /* */
3290 /* Finalize an interrupt for internal commands */
3291 /* */
3292 /****************************************************************************/
3293 static void
3294 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3295 {
3296 METHOD_TRACE("ipsintr_blocking", 2);
3297
3298 ips_freescb(ha, scb);
3299 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3300 ha->waitflag = FALSE;
3301
3302 return;
3303 }
3304 }
3305
3306 /****************************************************************************/
3307 /* */
3308 /* Routine Name: ipsintr_done */
3309 /* */
3310 /* Routine Description: */
3311 /* */
3312 /* Finalize an interrupt for non-internal commands */
3313 /* */
3314 /****************************************************************************/
3315 static void
3316 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3317 {
3318 METHOD_TRACE("ipsintr_done", 2);
3319
3320 if (!scb) {
3321 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3322 "Spurious interrupt; scb NULL.\n");
3323
3324 return;
3325 }
3326
3327 if (scb->scsi_cmd == NULL) {
3328 /* unexpected interrupt */
3329 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3330 "Spurious interrupt; scsi_cmd not set.\n");
3331
3332 return;
3333 }
3334
3335 ips_done(ha, scb);
3336 }
3337
3338 /****************************************************************************/
3339 /* */
3340 /* Routine Name: ips_done */
3341 /* */
3342 /* Routine Description: */
3343 /* */
3344 /* Do housekeeping on completed commands */
3345 /* ASSUMED to be called form within the request lock */
3346 /****************************************************************************/
3347 static void
3348 ips_done(ips_ha_t * ha, ips_scb_t * scb)
3349 {
3350 int ret;
3351
3352 METHOD_TRACE("ips_done", 1);
3353
3354 if (!scb)
3355 return;
3356
3357 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3358 ips_cleanup_passthru(ha, scb);
3359 ha->num_ioctl--;
3360 } else {
3361 /*
3362 * Check to see if this command had too much
3363 * data and had to be broke up. If so, queue
3364 * the rest of the data and continue.
3365 */
3366 if ((scb->breakup) || (scb->sg_break)) {
3367 /* we had a data breakup */
3368 scb->data_len = 0;
3369
3370 if (scb->sg_count) {
3371 /* S/G request */
3372 struct scatterlist *sg;
3373 int ips_sg_index = 0;
3374 int sg_dma_index;
3375
3376 sg = scb->scsi_cmd->request_buffer;
3377
3378 /* Spin forward to last dma chunk */
3379 sg_dma_index = scb->breakup;
3380
3381 /* Take care of possible partial on last chunk */
3382 ips_fill_scb_sg_single(ha,
3383 sg_dma_address(&sg
3384 [sg_dma_index]),
3385 scb, ips_sg_index++,
3386 sg_dma_len(&sg
3387 [sg_dma_index]));
3388
3389 for (; sg_dma_index < scb->sg_count;
3390 sg_dma_index++) {
3391 if (ips_fill_scb_sg_single
3392 (ha,
3393 sg_dma_address(&sg[sg_dma_index]),
3394 scb, ips_sg_index++,
3395 sg_dma_len(&sg[sg_dma_index])) < 0)
3396 break;
3397
3398 }
3399
3400 } else {
3401 /* Non S/G Request */
3402 (void) ips_fill_scb_sg_single(ha,
3403 scb->
3404 data_busaddr +
3405 (scb->sg_break *
3406 ha->max_xfer),
3407 scb, 0,
3408 scb->scsi_cmd->
3409 request_bufflen -
3410 (scb->sg_break *
3411 ha->max_xfer));
3412 }
3413
3414 scb->dcdb.transfer_length = scb->data_len;
3415 scb->dcdb.cmd_attribute |=
3416 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3417
3418 if (!(scb->dcdb.cmd_attribute & 0x3))
3419 scb->dcdb.transfer_length = 0;
3420
3421 if (scb->data_len >= IPS_MAX_XFER) {
3422 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3423 scb->dcdb.transfer_length = 0;
3424 }
3425
3426 ret = ips_send_cmd(ha, scb);
3427
3428 switch (ret) {
3429 case IPS_FAILURE:
3430 if (scb->scsi_cmd) {
3431 scb->scsi_cmd->result = DID_ERROR << 16;
3432 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3433 }
3434
3435 ips_freescb(ha, scb);
3436 break;
3437 case IPS_SUCCESS_IMM:
3438 if (scb->scsi_cmd) {
3439 scb->scsi_cmd->result = DID_ERROR << 16;
3440 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3441 }
3442
3443 ips_freescb(ha, scb);
3444 break;
3445 default:
3446 break;
3447 } /* end case */
3448
3449 return;
3450 }
3451 } /* end if passthru */
3452
3453 if (scb->bus) {
3454 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3455 }
3456
3457 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3458
3459 ips_freescb(ha, scb);
3460 }
3461
3462 /****************************************************************************/
3463 /* */
3464 /* Routine Name: ips_map_status */
3465 /* */
3466 /* Routine Description: */
3467 /* */
3468 /* Map Controller Error codes to Linux Error Codes */
3469 /* */
3470 /****************************************************************************/
3471 static int
3472 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3473 {
3474 int errcode;
3475 int device_error;
3476 uint32_t transfer_len;
3477 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3478
3479 METHOD_TRACE("ips_map_status", 1);
3480
3481 if (scb->bus) {
3482 DEBUG_VAR(2,
3483 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3484 ips_name, ha->host_num,
3485 scb->scsi_cmd->device->channel,
3486 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3487 scb->basic_status, scb->extended_status,
3488 scb->extended_status ==
3489 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3490 scb->extended_status ==
3491 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3492 scb->extended_status ==
3493 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3494 }
3495
3496 /* default driver error */
3497 errcode = DID_ERROR;
3498 device_error = 0;
3499
3500 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3501 case IPS_CMD_TIMEOUT:
3502 errcode = DID_TIME_OUT;
3503 break;
3504
3505 case IPS_INVAL_OPCO:
3506 case IPS_INVAL_CMD_BLK:
3507 case IPS_INVAL_PARM_BLK:
3508 case IPS_LD_ERROR:
3509 case IPS_CMD_CMPLT_WERROR:
3510 break;
3511
3512 case IPS_PHYS_DRV_ERROR:
3513 switch (scb->extended_status) {
3514 case IPS_ERR_SEL_TO:
3515 if (scb->bus)
3516 errcode = DID_NO_CONNECT;
3517
3518 break;
3519
3520 case IPS_ERR_OU_RUN:
3521 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3522 (scb->cmd.dcdb.op_code ==
3523 IPS_CMD_EXTENDED_DCDB_SG)) {
3524 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3525 transfer_len = tapeDCDB->transfer_length;
3526 } else {
3527 transfer_len =
3528 (uint32_t) scb->dcdb.transfer_length;
3529 }
3530
3531 if ((scb->bus) && (transfer_len < scb->data_len)) {
3532 /* Underrun - set default to no error */
3533 errcode = DID_OK;
3534
3535 /* Restrict access to physical DASD */
3536 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
3537 ((((char *) scb->scsi_cmd->
3538 buffer)[0] & 0x1f) == TYPE_DISK)) {
3539 /* underflow -- no error */
3540 /* restrict access to physical DASD */
3541 errcode = DID_TIME_OUT;
3542 break;
3543 }
3544 } else
3545 errcode = DID_ERROR;
3546
3547 break;
3548
3549 case IPS_ERR_RECOVERY:
3550 /* don't fail recovered errors */
3551 if (scb->bus)
3552 errcode = DID_OK;
3553
3554 break;
3555
3556 case IPS_ERR_HOST_RESET:
3557 case IPS_ERR_DEV_RESET:
3558 errcode = DID_RESET;
3559 break;
3560
3561 case IPS_ERR_CKCOND:
3562 if (scb->bus) {
3563 if ((scb->cmd.dcdb.op_code ==
3564 IPS_CMD_EXTENDED_DCDB)
3565 || (scb->cmd.dcdb.op_code ==
3566 IPS_CMD_EXTENDED_DCDB_SG)) {
3567 tapeDCDB =
3568 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3569 memcpy(scb->scsi_cmd->sense_buffer,
3570 tapeDCDB->sense_info,
3571 sizeof (scb->scsi_cmd->
3572 sense_buffer));
3573 } else {
3574 memcpy(scb->scsi_cmd->sense_buffer,
3575 scb->dcdb.sense_info,
3576 sizeof (scb->scsi_cmd->
3577 sense_buffer));
3578 }
3579 device_error = 2; /* check condition */
3580 }
3581
3582 errcode = DID_OK;
3583
3584 break;
3585
3586 default:
3587 errcode = DID_ERROR;
3588 break;
3589
3590 } /* end switch */
3591 } /* end switch */
3592
3593 scb->scsi_cmd->result = device_error | (errcode << 16);
3594
3595 return (1);
3596 }
3597
3598 /****************************************************************************/
3599 /* */
3600 /* Routine Name: ips_send_wait */
3601 /* */
3602 /* Routine Description: */
3603 /* */
3604 /* Send a command to the controller and wait for it to return */
3605 /* */
3606 /* The FFDC Time Stamp use this function for the callback, but doesn't */
3607 /* actually need to wait. */
3608 /****************************************************************************/
3609 static int
3610 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3611 {
3612 int ret;
3613
3614 METHOD_TRACE("ips_send_wait", 1);
3615
3616 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3617 ha->waitflag = TRUE;
3618 ha->cmd_in_progress = scb->cdb[0];
3619 }
3620 scb->callback = ipsintr_blocking;
3621 ret = ips_send_cmd(ha, scb);
3622
3623 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3624 return (ret);
3625
3626 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3627 ret = ips_wait(ha, timeout, intr);
3628
3629 return (ret);
3630 }
3631
3632 /****************************************************************************/
3633 /* */
3634 /* Routine Name: ips_scmd_buf_write */
3635 /* */
3636 /* Routine Description: */
3637 /* Write data to Scsi_Cmnd request_buffer at proper offsets */
3638 /****************************************************************************/
3639 static void
3640 ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned
3641 int count)
3642 {
3643 if (scmd->use_sg) {
3644 int i;
3645 unsigned int min_cnt, xfer_cnt;
3646 char *cdata = (char *) data;
3647 struct scatterlist *sg = scmd->request_buffer;
3648 for (i = 0, xfer_cnt = 0;
3649 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3650 if (!IPS_SG_ADDRESS(&sg[i]))
3651 return;
3652 min_cnt = min(count - xfer_cnt, sg[i].length);
3653 memcpy(IPS_SG_ADDRESS(&sg[i]), &cdata[xfer_cnt],
3654 min_cnt);
3655 xfer_cnt += min_cnt;
3656 }
3657
3658 } else {
3659 unsigned int min_cnt = min(count, scmd->request_bufflen);
3660 memcpy(scmd->request_buffer, data, min_cnt);
3661 }
3662 }
3663
3664 /****************************************************************************/
3665 /* */
3666 /* Routine Name: ips_scmd_buf_read */
3667 /* */
3668 /* Routine Description: */
3669 /* Copy data from a Scsi_Cmnd to a new, linear buffer */
3670 /****************************************************************************/
3671 static void
3672 ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned
3673 int count)
3674 {
3675 if (scmd->use_sg) {
3676 int i;
3677 unsigned int min_cnt, xfer_cnt;
3678 char *cdata = (char *) data;
3679 struct scatterlist *sg = scmd->request_buffer;
3680 for (i = 0, xfer_cnt = 0;
3681 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3682 if (!IPS_SG_ADDRESS(&sg[i]))
3683 return;
3684 min_cnt = min(count - xfer_cnt, sg[i].length);
3685 memcpy(&cdata[xfer_cnt], IPS_SG_ADDRESS(&sg[i]),
3686 min_cnt);
3687 xfer_cnt += min_cnt;
3688 }
3689
3690 } else {
3691 unsigned int min_cnt = min(count, scmd->request_bufflen);
3692 memcpy(data, scmd->request_buffer, min_cnt);
3693 }
3694 }
3695
3696 /****************************************************************************/
3697 /* */
3698 /* Routine Name: ips_send_cmd */
3699 /* */
3700 /* Routine Description: */
3701 /* */
3702 /* Map SCSI commands to ServeRAID commands for logical drives */
3703 /* */
3704 /****************************************************************************/
3705 static int
3706 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3707 {
3708 int ret;
3709 char *sp;
3710 int device_error;
3711 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3712 int TimeOut;
3713
3714 METHOD_TRACE("ips_send_cmd", 1);
3715
3716 ret = IPS_SUCCESS;
3717
3718 if (!scb->scsi_cmd) {
3719 /* internal command */
3720
3721 if (scb->bus > 0) {
3722 /* Controller commands can't be issued */
3723 /* to real devices -- fail them */
3724 if ((ha->waitflag == TRUE) &&
3725 (ha->cmd_in_progress == scb->cdb[0])) {
3726 ha->waitflag = FALSE;
3727 }
3728
3729 return (1);
3730 }
3731 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3732 /* command to logical bus -- interpret */
3733 ret = IPS_SUCCESS_IMM;
3734
3735 switch (scb->scsi_cmd->cmnd[0]) {
3736 case ALLOW_MEDIUM_REMOVAL:
3737 case REZERO_UNIT:
3738 case ERASE:
3739 case WRITE_FILEMARKS:
3740 case SPACE:
3741 scb->scsi_cmd->result = DID_ERROR << 16;
3742 break;
3743
3744 case START_STOP:
3745 scb->scsi_cmd->result = DID_OK << 16;
3746
3747 case TEST_UNIT_READY:
3748 case INQUIRY:
3749 if (scb->target_id == IPS_ADAPTER_ID) {
3750 /*
3751 * Either we have a TUR
3752 * or we have a SCSI inquiry
3753 */
3754 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3755 scb->scsi_cmd->result = DID_OK << 16;
3756
3757 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3758 IPS_SCSI_INQ_DATA inquiry;
3759
3760 memset(&inquiry, 0,
3761 sizeof (IPS_SCSI_INQ_DATA));
3762
3763 inquiry.DeviceType =
3764 IPS_SCSI_INQ_TYPE_PROCESSOR;
3765 inquiry.DeviceTypeQualifier =
3766 IPS_SCSI_INQ_LU_CONNECTED;
3767 inquiry.Version = IPS_SCSI_INQ_REV2;
3768 inquiry.ResponseDataFormat =
3769 IPS_SCSI_INQ_RD_REV2;
3770 inquiry.AdditionalLength = 31;
3771 inquiry.Flags[0] =
3772 IPS_SCSI_INQ_Address16;
3773 inquiry.Flags[1] =
3774 IPS_SCSI_INQ_WBus16 |
3775 IPS_SCSI_INQ_Sync;
3776 strncpy(inquiry.VendorId, "IBM ",
3777 8);
3778 strncpy(inquiry.ProductId,
3779 "SERVERAID ", 16);
3780 strncpy(inquiry.ProductRevisionLevel,
3781 "1.00", 4);
3782
3783 ips_scmd_buf_write(scb->scsi_cmd,
3784 &inquiry,
3785 sizeof (inquiry));
3786
3787 scb->scsi_cmd->result = DID_OK << 16;
3788 }
3789 } else {
3790 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3791 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3792 scb->cmd.logical_info.reserved = 0;
3793 scb->cmd.logical_info.reserved2 = 0;
3794 scb->data_len = sizeof (IPS_LD_INFO);
3795 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3796 scb->flags = 0;
3797 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3798 ret = IPS_SUCCESS;
3799 }
3800
3801 break;
3802
3803 case REQUEST_SENSE:
3804 ips_reqsen(ha, scb);
3805 scb->scsi_cmd->result = DID_OK << 16;
3806 break;
3807
3808 case READ_6:
3809 case WRITE_6:
3810 if (!scb->sg_len) {
3811 scb->cmd.basic_io.op_code =
3812 (scb->scsi_cmd->cmnd[0] ==
3813 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3814 scb->cmd.basic_io.enhanced_sg = 0;
3815 scb->cmd.basic_io.sg_addr =
3816 cpu_to_le32(scb->data_busaddr);
3817 } else {
3818 scb->cmd.basic_io.op_code =
3819 (scb->scsi_cmd->cmnd[0] ==
3820 READ_6) ? IPS_CMD_READ_SG :
3821 IPS_CMD_WRITE_SG;
3822 scb->cmd.basic_io.enhanced_sg =
3823 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3824 scb->cmd.basic_io.sg_addr =
3825 cpu_to_le32(scb->sg_busaddr);
3826 }
3827
3828 scb->cmd.basic_io.segment_4G = 0;
3829 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3830 scb->cmd.basic_io.log_drv = scb->target_id;
3831 scb->cmd.basic_io.sg_count = scb->sg_len;
3832
3833 if (scb->cmd.basic_io.lba)
3834 scb->cmd.basic_io.lba =
3835 cpu_to_le32(le32_to_cpu
3836 (scb->cmd.basic_io.lba) +
3837 le16_to_cpu(scb->cmd.basic_io.
3838 sector_count));
3839 else
3840 scb->cmd.basic_io.lba =
3841 (((scb->scsi_cmd->
3842 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3843 cmnd[2] << 8) |
3844 (scb->scsi_cmd->cmnd[3]));
3845
3846 scb->cmd.basic_io.sector_count =
3847 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3848
3849 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3850 scb->cmd.basic_io.sector_count =
3851 cpu_to_le16(256);
3852
3853 ret = IPS_SUCCESS;
3854 break;
3855
3856 case READ_10:
3857 case WRITE_10:
3858 if (!scb->sg_len) {
3859 scb->cmd.basic_io.op_code =
3860 (scb->scsi_cmd->cmnd[0] ==
3861 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3862 scb->cmd.basic_io.enhanced_sg = 0;
3863 scb->cmd.basic_io.sg_addr =
3864 cpu_to_le32(scb->data_busaddr);
3865 } else {
3866 scb->cmd.basic_io.op_code =
3867 (scb->scsi_cmd->cmnd[0] ==
3868 READ_10) ? IPS_CMD_READ_SG :
3869 IPS_CMD_WRITE_SG;
3870 scb->cmd.basic_io.enhanced_sg =
3871 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3872 scb->cmd.basic_io.sg_addr =
3873 cpu_to_le32(scb->sg_busaddr);
3874 }
3875
3876 scb->cmd.basic_io.segment_4G = 0;
3877 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3878 scb->cmd.basic_io.log_drv = scb->target_id;
3879 scb->cmd.basic_io.sg_count = scb->sg_len;
3880
3881 if (scb->cmd.basic_io.lba)
3882 scb->cmd.basic_io.lba =
3883 cpu_to_le32(le32_to_cpu
3884 (scb->cmd.basic_io.lba) +
3885 le16_to_cpu(scb->cmd.basic_io.
3886 sector_count));
3887 else
3888 scb->cmd.basic_io.lba =
3889 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3890 scsi_cmd->
3891 cmnd[3]
3892 << 16) |
3893 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3894 scsi_cmd->cmnd[5]);
3895
3896 scb->cmd.basic_io.sector_count =
3897 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3898
3899 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3900 /*
3901 * This is a null condition
3902 * we don't have to do anything
3903 * so just return
3904 */
3905 scb->scsi_cmd->result = DID_OK << 16;
3906 } else
3907 ret = IPS_SUCCESS;
3908
3909 break;
3910
3911 case RESERVE:
3912 case RELEASE:
3913 scb->scsi_cmd->result = DID_OK << 16;
3914 break;
3915
3916 case MODE_SENSE:
3917 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3918 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3919 scb->cmd.basic_io.segment_4G = 0;
3920 scb->cmd.basic_io.enhanced_sg = 0;
3921 scb->data_len = sizeof (*ha->enq);
3922 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3923 ret = IPS_SUCCESS;
3924 break;
3925
3926 case READ_CAPACITY:
3927 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3928 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3929 scb->cmd.logical_info.reserved = 0;
3930 scb->cmd.logical_info.reserved2 = 0;
3931 scb->cmd.logical_info.reserved3 = 0;
3932 scb->data_len = sizeof (IPS_LD_INFO);
3933 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3934 scb->flags = 0;
3935 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3936 ret = IPS_SUCCESS;
3937 break;
3938
3939 case SEND_DIAGNOSTIC:
3940 case REASSIGN_BLOCKS:
3941 case FORMAT_UNIT:
3942 case SEEK_10:
3943 case VERIFY:
3944 case READ_DEFECT_DATA:
3945 case READ_BUFFER:
3946 case WRITE_BUFFER:
3947 scb->scsi_cmd->result = DID_OK << 16;
3948 break;
3949
3950 default:
3951 /* Set the Return Info to appear like the Command was */
3952 /* attempted, a Check Condition occurred, and Sense */
3953 /* Data indicating an Invalid CDB OpCode is returned. */
3954 sp = (char *) scb->scsi_cmd->sense_buffer;
3955 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
3956
3957 sp[0] = 0x70; /* Error Code */
3958 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3959 sp[7] = 0x0A; /* Additional Sense Length */
3960 sp[12] = 0x20; /* ASC = Invalid OpCode */
3961 sp[13] = 0x00; /* ASCQ */
3962
3963 device_error = 2; /* Indicate Check Condition */
3964 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3965 break;
3966 } /* end switch */
3967 }
3968 /* end if */
3969 if (ret == IPS_SUCCESS_IMM)
3970 return (ret);
3971
3972 /* setup DCDB */
3973 if (scb->bus > 0) {
3974
3975 /* If we already know the Device is Not there, no need to attempt a Command */
3976 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3977 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3978 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3979 return (IPS_SUCCESS_IMM);
3980 }
3981
3982 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3983 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3984 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3985 (unsigned long) &scb->
3986 dcdb -
3987 (unsigned long) scb);
3988 scb->cmd.dcdb.reserved = 0;
3989 scb->cmd.dcdb.reserved2 = 0;
3990 scb->cmd.dcdb.reserved3 = 0;
3991 scb->cmd.dcdb.segment_4G = 0;
3992 scb->cmd.dcdb.enhanced_sg = 0;
3993
3994 TimeOut = scb->scsi_cmd->timeout_per_command;
3995
3996 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3997 if (!scb->sg_len) {
3998 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3999 } else {
4000 scb->cmd.dcdb.op_code =
4001 IPS_CMD_EXTENDED_DCDB_SG;
4002 scb->cmd.dcdb.enhanced_sg =
4003 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4004 }
4005
4006 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
4007 tapeDCDB->device_address =
4008 ((scb->bus - 1) << 4) | scb->target_id;
4009 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4010 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
4011
4012 if (TimeOut) {
4013 if (TimeOut < (10 * HZ))
4014 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4015 else if (TimeOut < (60 * HZ))
4016 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4017 else if (TimeOut < (1200 * HZ))
4018 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4019 }
4020
4021 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
4022 tapeDCDB->reserved_for_LUN = 0;
4023 tapeDCDB->transfer_length = scb->data_len;
4024 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
4025 tapeDCDB->buffer_pointer =
4026 cpu_to_le32(scb->sg_busaddr);
4027 else
4028 tapeDCDB->buffer_pointer =
4029 cpu_to_le32(scb->data_busaddr);
4030 tapeDCDB->sg_count = scb->sg_len;
4031 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
4032 tapeDCDB->scsi_status = 0;
4033 tapeDCDB->reserved = 0;
4034 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
4035 scb->scsi_cmd->cmd_len);
4036 } else {
4037 if (!scb->sg_len) {
4038 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
4039 } else {
4040 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
4041 scb->cmd.dcdb.enhanced_sg =
4042 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4043 }
4044
4045 scb->dcdb.device_address =
4046 ((scb->bus - 1) << 4) | scb->target_id;
4047 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4048
4049 if (TimeOut) {
4050 if (TimeOut < (10 * HZ))
4051 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4052 else if (TimeOut < (60 * HZ))
4053 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4054 else if (TimeOut < (1200 * HZ))
4055 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4056 }
4057
4058 scb->dcdb.transfer_length = scb->data_len;
4059 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
4060 scb->dcdb.transfer_length = 0;
4061 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
4062 scb->dcdb.buffer_pointer =
4063 cpu_to_le32(scb->sg_busaddr);
4064 else
4065 scb->dcdb.buffer_pointer =
4066 cpu_to_le32(scb->data_busaddr);
4067 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
4068 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
4069 scb->dcdb.sg_count = scb->sg_len;
4070 scb->dcdb.reserved = 0;
4071 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
4072 scb->scsi_cmd->cmd_len);
4073 scb->dcdb.scsi_status = 0;
4074 scb->dcdb.reserved2[0] = 0;
4075 scb->dcdb.reserved2[1] = 0;
4076 scb->dcdb.reserved2[2] = 0;
4077 }
4078 }
4079
4080 return ((*ha->func.issue) (ha, scb));
4081 }
4082
4083 /****************************************************************************/
4084 /* */
4085 /* Routine Name: ips_chk_status */
4086 /* */
4087 /* Routine Description: */
4088 /* */
4089 /* Check the status of commands to logical drives */
4090 /* Assumed to be called with the HA lock */
4091 /****************************************************************************/
4092 static void
4093 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4094 {
4095 ips_scb_t *scb;
4096 ips_stat_t *sp;
4097 uint8_t basic_status;
4098 uint8_t ext_status;
4099 int errcode;
4100
4101 METHOD_TRACE("ips_chkstatus", 1);
4102
4103 scb = &ha->scbs[pstatus->fields.command_id];
4104 scb->basic_status = basic_status =
4105 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
4106 scb->extended_status = ext_status = pstatus->fields.extended_status;
4107
4108 sp = &ha->sp;
4109 sp->residue_len = 0;
4110 sp->scb_addr = (void *) scb;
4111
4112 /* Remove the item from the active queue */
4113 ips_removeq_scb(&ha->scb_activelist, scb);
4114
4115 if (!scb->scsi_cmd)
4116 /* internal commands are handled in do_ipsintr */
4117 return;
4118
4119 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
4120 ips_name,
4121 ha->host_num,
4122 scb->cdb[0],
4123 scb->cmd.basic_io.command_id,
4124 scb->bus, scb->target_id, scb->lun);
4125
4126 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
4127 /* passthru - just returns the raw result */
4128 return;
4129
4130 errcode = DID_OK;
4131
4132 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
4133 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
4134
4135 if (scb->bus == 0) {
4136 if ((basic_status & IPS_GSC_STATUS_MASK) ==
4137 IPS_CMD_RECOVERED_ERROR) {
4138 DEBUG_VAR(1,
4139 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4140 ips_name, ha->host_num,
4141 scb->cmd.basic_io.op_code,
4142 basic_status, ext_status);
4143 }
4144
4145 switch (scb->scsi_cmd->cmnd[0]) {
4146 case ALLOW_MEDIUM_REMOVAL:
4147 case REZERO_UNIT:
4148 case ERASE:
4149 case WRITE_FILEMARKS:
4150 case SPACE:
4151 errcode = DID_ERROR;
4152 break;
4153
4154 case START_STOP:
4155 break;
4156
4157 case TEST_UNIT_READY:
4158 if (!ips_online(ha, scb)) {
4159 errcode = DID_TIME_OUT;
4160 }
4161 break;
4162
4163 case INQUIRY:
4164 if (ips_online(ha, scb)) {
4165 ips_inquiry(ha, scb);
4166 } else {
4167 errcode = DID_TIME_OUT;
4168 }
4169 break;
4170
4171 case REQUEST_SENSE:
4172 ips_reqsen(ha, scb);
4173 break;
4174
4175 case READ_6:
4176 case WRITE_6:
4177 case READ_10:
4178 case WRITE_10:
4179 case RESERVE:
4180 case RELEASE:
4181 break;
4182
4183 case MODE_SENSE:
4184 if (!ips_online(ha, scb)
4185 || !ips_msense(ha, scb)) {
4186 errcode = DID_ERROR;
4187 }
4188 break;
4189
4190 case READ_CAPACITY:
4191 if (ips_online(ha, scb))
4192 ips_rdcap(ha, scb);
4193 else {
4194 errcode = DID_TIME_OUT;
4195 }
4196 break;
4197
4198 case SEND_DIAGNOSTIC:
4199 case REASSIGN_BLOCKS:
4200 break;
4201
4202 case FORMAT_UNIT:
4203 errcode = DID_ERROR;
4204 break;
4205
4206 case SEEK_10:
4207 case VERIFY:
4208 case READ_DEFECT_DATA:
4209 case READ_BUFFER:
4210 case WRITE_BUFFER:
4211 break;
4212
4213 default:
4214 errcode = DID_ERROR;
4215 } /* end switch */
4216
4217 scb->scsi_cmd->result = errcode << 16;
4218 } else { /* bus == 0 */
4219 /* restrict access to physical drives */
4220 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
4221 ((((char *) scb->scsi_cmd->buffer)[0] & 0x1f) ==
4222 TYPE_DISK)) {
4223
4224 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4225 }
4226 } /* else */
4227 } else { /* recovered error / success */
4228 if (scb->bus == 0) {
4229 DEBUG_VAR(1,
4230 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4231 ips_name, ha->host_num,
4232 scb->cmd.basic_io.op_code, basic_status,
4233 ext_status);
4234 }
4235
4236 ips_map_status(ha, scb, sp);
4237 } /* else */
4238 }
4239
4240 /****************************************************************************/
4241 /* */
4242 /* Routine Name: ips_online */
4243 /* */
4244 /* Routine Description: */
4245 /* */
4246 /* Determine if a logical drive is online */
4247 /* */
4248 /****************************************************************************/
4249 static int
4250 ips_online(ips_ha_t * ha, ips_scb_t * scb)
4251 {
4252 METHOD_TRACE("ips_online", 1);
4253
4254 if (scb->target_id >= IPS_MAX_LD)
4255 return (0);
4256
4257 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4258 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4259 return (0);
4260 }
4261
4262 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4263 IPS_LD_OFFLINE
4264 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4265 IPS_LD_FREE
4266 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4267 IPS_LD_CRS
4268 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4269 IPS_LD_SYS)
4270 return (1);
4271 else
4272 return (0);
4273 }
4274
4275 /****************************************************************************/
4276 /* */
4277 /* Routine Name: ips_inquiry */
4278 /* */
4279 /* Routine Description: */
4280 /* */
4281 /* Simulate an inquiry command to a logical drive */
4282 /* */
4283 /****************************************************************************/
4284 static int
4285 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4286 {
4287 IPS_SCSI_INQ_DATA inquiry;
4288
4289 METHOD_TRACE("ips_inquiry", 1);
4290
4291 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4292
4293 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4294 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4295 inquiry.Version = IPS_SCSI_INQ_REV2;
4296 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4297 inquiry.AdditionalLength = 31;
4298 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4299 inquiry.Flags[1] =
4300 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4301 strncpy(inquiry.VendorId, "IBM ", 8);
4302 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4303 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4304
4305 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4306
4307 return (1);
4308 }
4309
4310 /****************************************************************************/
4311 /* */
4312 /* Routine Name: ips_rdcap */
4313 /* */
4314 /* Routine Description: */
4315 /* */
4316 /* Simulate a read capacity command to a logical drive */
4317 /* */
4318 /****************************************************************************/
4319 static int
4320 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4321 {
4322 IPS_SCSI_CAPACITY cap;
4323
4324 METHOD_TRACE("ips_rdcap", 1);
4325
4326 if (scb->scsi_cmd->bufflen < 8)
4327 return (0);
4328
4329 cap.lba =
4330 cpu_to_be32(le32_to_cpu
4331 (ha->logical_drive_info->
4332 drive_info[scb->target_id].sector_count) - 1);
4333 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4334
4335 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4336
4337 return (1);
4338 }
4339
4340 /****************************************************************************/
4341 /* */
4342 /* Routine Name: ips_msense */
4343 /* */
4344 /* Routine Description: */
4345 /* */
4346 /* Simulate a mode sense command to a logical drive */
4347 /* */
4348 /****************************************************************************/
4349 static int
4350 ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4351 {
4352 uint16_t heads;
4353 uint16_t sectors;
4354 uint32_t cylinders;
4355 IPS_SCSI_MODE_PAGE_DATA mdata;
4356
4357 METHOD_TRACE("ips_msense", 1);
4358
4359 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4360 (ha->enq->ucMiscFlag & 0x8) == 0) {
4361 heads = IPS_NORM_HEADS;
4362 sectors = IPS_NORM_SECTORS;
4363 } else {
4364 heads = IPS_COMP_HEADS;
4365 sectors = IPS_COMP_SECTORS;
4366 }
4367
4368 cylinders =
4369 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4370 1) / (heads * sectors);
4371
4372 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4373
4374 mdata.hdr.BlockDescLength = 8;
4375
4376 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4377 case 0x03: /* page 3 */
4378 mdata.pdata.pg3.PageCode = 3;
4379 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4380 mdata.hdr.DataLength =
4381 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4382 mdata.pdata.pg3.TracksPerZone = 0;
4383 mdata.pdata.pg3.AltSectorsPerZone = 0;
4384 mdata.pdata.pg3.AltTracksPerZone = 0;
4385 mdata.pdata.pg3.AltTracksPerVolume = 0;
4386 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4387 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4388 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4389 mdata.pdata.pg3.TrackSkew = 0;
4390 mdata.pdata.pg3.CylinderSkew = 0;
4391 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4392 break;
4393
4394 case 0x4:
4395 mdata.pdata.pg4.PageCode = 4;
4396 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4397 mdata.hdr.DataLength =
4398 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4399 mdata.pdata.pg4.CylindersHigh =
4400 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4401 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4402 mdata.pdata.pg4.Heads = heads;
4403 mdata.pdata.pg4.WritePrecompHigh = 0;
4404 mdata.pdata.pg4.WritePrecompLow = 0;
4405 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4406 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4407 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4408 mdata.pdata.pg4.LandingZoneHigh = 0;
4409 mdata.pdata.pg4.LandingZoneLow = 0;
4410 mdata.pdata.pg4.flags = 0;
4411 mdata.pdata.pg4.RotationalOffset = 0;
4412 mdata.pdata.pg4.MediumRotationRate = 0;
4413 break;
4414 case 0x8:
4415 mdata.pdata.pg8.PageCode = 8;
4416 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4417 mdata.hdr.DataLength =
4418 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4419 /* everything else is left set to 0 */
4420 break;
4421
4422 default:
4423 return (0);
4424 } /* end switch */
4425
4426 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4427
4428 return (1);
4429 }
4430
4431 /****************************************************************************/
4432 /* */
4433 /* Routine Name: ips_reqsen */
4434 /* */
4435 /* Routine Description: */
4436 /* */
4437 /* Simulate a request sense command to a logical drive */
4438 /* */
4439 /****************************************************************************/
4440 static int
4441 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4442 {
4443 IPS_SCSI_REQSEN reqsen;
4444
4445 METHOD_TRACE("ips_reqsen", 1);
4446
4447 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4448
4449 reqsen.ResponseCode =
4450 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4451 reqsen.AdditionalLength = 10;
4452 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4453 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4454
4455 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4456
4457 return (1);
4458 }
4459
4460 /****************************************************************************/
4461 /* */
4462 /* Routine Name: ips_free */
4463 /* */
4464 /* Routine Description: */
4465 /* */
4466 /* Free any allocated space for this controller */
4467 /* */
4468 /****************************************************************************/
4469 static void
4470 ips_free(ips_ha_t * ha)
4471 {
4472
4473 METHOD_TRACE("ips_free", 1);
4474
4475 if (ha) {
4476 if (ha->enq) {
4477 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4478 ha->enq, ha->enq_busaddr);
4479 ha->enq = NULL;
4480 }
4481
4482 if (ha->conf) {
4483 kfree(ha->conf);
4484 ha->conf = NULL;
4485 }
4486
4487 if (ha->adapt) {
4488 pci_free_consistent(ha->pcidev,
4489 sizeof (IPS_ADAPTER) +
4490 sizeof (IPS_IO_CMD), ha->adapt,
4491 ha->adapt->hw_status_start);
4492 ha->adapt = NULL;
4493 }
4494
4495 if (ha->logical_drive_info) {
4496 pci_free_consistent(ha->pcidev,
4497 sizeof (IPS_LD_INFO),
4498 ha->logical_drive_info,
4499 ha->logical_drive_info_dma_addr);
4500 ha->logical_drive_info = NULL;
4501 }
4502
4503 if (ha->nvram) {
4504 kfree(ha->nvram);
4505 ha->nvram = NULL;
4506 }
4507
4508 if (ha->subsys) {
4509 kfree(ha->subsys);
4510 ha->subsys = NULL;
4511 }
4512
4513 if (ha->ioctl_data) {
4514 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4515 ha->ioctl_data, ha->ioctl_busaddr);
4516 ha->ioctl_data = NULL;
4517 ha->ioctl_datasize = 0;
4518 ha->ioctl_len = 0;
4519 }
4520 ips_deallocatescbs(ha, ha->max_cmds);
4521
4522 /* free memory mapped (if applicable) */
4523 if (ha->mem_ptr) {
4524 iounmap(ha->ioremap_ptr);
4525 ha->ioremap_ptr = NULL;
4526 ha->mem_ptr = NULL;
4527 }
4528
4529 if (ha->mem_addr)
4530 release_mem_region(ha->mem_addr, ha->mem_len);
4531 ha->mem_addr = 0;
4532
4533 }
4534 }
4535
4536 /****************************************************************************/
4537 /* */
4538 /* Routine Name: ips_deallocatescbs */
4539 /* */
4540 /* Routine Description: */
4541 /* */
4542 /* Free the command blocks */
4543 /* */
4544 /****************************************************************************/
4545 static int
4546 ips_deallocatescbs(ips_ha_t * ha, int cmds)
4547 {
4548 if (ha->scbs) {
4549 pci_free_consistent(ha->pcidev,
4550 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4551 ha->scbs->sg_list.list,
4552 ha->scbs->sg_busaddr);
4553 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4554 ha->scbs, ha->scbs->scb_busaddr);
4555 ha->scbs = NULL;
4556 } /* end if */
4557 return 1;
4558 }
4559
4560 /****************************************************************************/
4561 /* */
4562 /* Routine Name: ips_allocatescbs */
4563 /* */
4564 /* Routine Description: */
4565 /* */
4566 /* Allocate the command blocks */
4567 /* */
4568 /****************************************************************************/
4569 static int
4570 ips_allocatescbs(ips_ha_t * ha)
4571 {
4572 ips_scb_t *scb_p;
4573 IPS_SG_LIST ips_sg;
4574 int i;
4575 dma_addr_t command_dma, sg_dma;
4576
4577 METHOD_TRACE("ips_allocatescbs", 1);
4578
4579 /* Allocate memory for the SCBs */
4580 ha->scbs =
4581 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4582 &command_dma);
4583 if (ha->scbs == NULL)
4584 return 0;
4585 ips_sg.list =
4586 pci_alloc_consistent(ha->pcidev,
4587 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4588 ha->max_cmds, &sg_dma);
4589 if (ips_sg.list == NULL) {
4590 pci_free_consistent(ha->pcidev,
4591 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4592 command_dma);
4593 return 0;
4594 }
4595
4596 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4597
4598 for (i = 0; i < ha->max_cmds; i++) {
4599 scb_p = &ha->scbs[i];
4600 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4601 /* set up S/G list */
4602 if (IPS_USE_ENH_SGLIST(ha)) {
4603 scb_p->sg_list.enh_list =
4604 ips_sg.enh_list + i * IPS_MAX_SG;
4605 scb_p->sg_busaddr =
4606 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4607 } else {
4608 scb_p->sg_list.std_list =
4609 ips_sg.std_list + i * IPS_MAX_SG;
4610 scb_p->sg_busaddr =
4611 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4612 }
4613
4614 /* add to the free list */
4615 if (i < ha->max_cmds - 1) {
4616 scb_p->q_next = ha->scb_freelist;
4617 ha->scb_freelist = scb_p;
4618 }
4619 }
4620
4621 /* success */
4622 return (1);
4623 }
4624
4625 /****************************************************************************/
4626 /* */
4627 /* Routine Name: ips_init_scb */
4628 /* */
4629 /* Routine Description: */
4630 /* */
4631 /* Initialize a CCB to default values */
4632 /* */
4633 /****************************************************************************/
4634 static void
4635 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4636 {
4637 IPS_SG_LIST sg_list;
4638 uint32_t cmd_busaddr, sg_busaddr;
4639 METHOD_TRACE("ips_init_scb", 1);
4640
4641 if (scb == NULL)
4642 return;
4643
4644 sg_list.list = scb->sg_list.list;
4645 cmd_busaddr = scb->scb_busaddr;
4646 sg_busaddr = scb->sg_busaddr;
4647 /* zero fill */
4648 memset(scb, 0, sizeof (ips_scb_t));
4649 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4650
4651 /* Initialize dummy command bucket */
4652 ha->dummy->op_code = 0xFF;
4653 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4654 + sizeof (IPS_ADAPTER));
4655 ha->dummy->command_id = IPS_MAX_CMDS;
4656
4657 /* set bus address of scb */
4658 scb->scb_busaddr = cmd_busaddr;
4659 scb->sg_busaddr = sg_busaddr;
4660 scb->sg_list.list = sg_list.list;
4661
4662 /* Neptune Fix */
4663 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4664 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4665 + sizeof (IPS_ADAPTER));
4666 }
4667
4668 /****************************************************************************/
4669 /* */
4670 /* Routine Name: ips_get_scb */
4671 /* */
4672 /* Routine Description: */
4673 /* */
4674 /* Initialize a CCB to default values */
4675 /* */
4676 /* ASSUMED to be callled from within a lock */
4677 /* */
4678 /****************************************************************************/
4679 static ips_scb_t *
4680 ips_getscb(ips_ha_t * ha)
4681 {
4682 ips_scb_t *scb;
4683
4684 METHOD_TRACE("ips_getscb", 1);
4685
4686 if ((scb = ha->scb_freelist) == NULL) {
4687
4688 return (NULL);
4689 }
4690
4691 ha->scb_freelist = scb->q_next;
4692 scb->flags = 0;
4693 scb->q_next = NULL;
4694
4695 ips_init_scb(ha, scb);
4696
4697 return (scb);
4698 }
4699
4700 /****************************************************************************/
4701 /* */
4702 /* Routine Name: ips_free_scb */
4703 /* */
4704 /* Routine Description: */
4705 /* */
4706 /* Return an unused CCB back to the free list */
4707 /* */
4708 /* ASSUMED to be called from within a lock */
4709 /* */
4710 /****************************************************************************/
4711 static void
4712 ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4713 {
4714
4715 METHOD_TRACE("ips_freescb", 1);
4716 if (scb->flags & IPS_SCB_MAP_SG)
4717 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
4718 scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb));
4719 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4720 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4721 IPS_DMA_DIR(scb));
4722
4723 /* check to make sure this is not our "special" scb */
4724 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4725 scb->q_next = ha->scb_freelist;
4726 ha->scb_freelist = scb;
4727 }
4728 }
4729
4730 /****************************************************************************/
4731 /* */
4732 /* Routine Name: ips_isinit_copperhead */
4733 /* */
4734 /* Routine Description: */
4735 /* */
4736 /* Is controller initialized ? */
4737 /* */
4738 /****************************************************************************/
4739 static int
4740 ips_isinit_copperhead(ips_ha_t * ha)
4741 {
4742 uint8_t scpr;
4743 uint8_t isr;
4744
4745 METHOD_TRACE("ips_isinit_copperhead", 1);
4746
4747 isr = inb(ha->io_addr + IPS_REG_HISR);
4748 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4749
4750 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4751 return (0);
4752 else
4753 return (1);
4754 }
4755
4756 /****************************************************************************/
4757 /* */
4758 /* Routine Name: ips_isinit_copperhead_memio */
4759 /* */
4760 /* Routine Description: */
4761 /* */
4762 /* Is controller initialized ? */
4763 /* */
4764 /****************************************************************************/
4765 static int
4766 ips_isinit_copperhead_memio(ips_ha_t * ha)
4767 {
4768 uint8_t isr = 0;
4769 uint8_t scpr;
4770
4771 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4772
4773 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4774 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4775
4776 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4777 return (0);
4778 else
4779 return (1);
4780 }
4781
4782 /****************************************************************************/
4783 /* */
4784 /* Routine Name: ips_isinit_morpheus */
4785 /* */
4786 /* Routine Description: */
4787 /* */
4788 /* Is controller initialized ? */
4789 /* */
4790 /****************************************************************************/
4791 static int
4792 ips_isinit_morpheus(ips_ha_t * ha)
4793 {
4794 uint32_t post;
4795 uint32_t bits;
4796
4797 METHOD_TRACE("ips_is_init_morpheus", 1);
4798
4799 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4800 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4801
4802 if (post == 0)
4803 return (0);
4804 else if (bits & 0x3)
4805 return (0);
4806 else
4807 return (1);
4808 }
4809
4810 /****************************************************************************/
4811 /* */
4812 /* Routine Name: ips_enable_int_copperhead */
4813 /* */
4814 /* Routine Description: */
4815 /* Turn on interrupts */
4816 /* */
4817 /****************************************************************************/
4818 static void
4819 ips_enable_int_copperhead(ips_ha_t * ha)
4820 {
4821 METHOD_TRACE("ips_enable_int_copperhead", 1);
4822
4823 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4824 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4825 }
4826
4827 /****************************************************************************/
4828 /* */
4829 /* Routine Name: ips_enable_int_copperhead_memio */
4830 /* */
4831 /* Routine Description: */
4832 /* Turn on interrupts */
4833 /* */
4834 /****************************************************************************/
4835 static void
4836 ips_enable_int_copperhead_memio(ips_ha_t * ha)
4837 {
4838 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4839
4840 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4841 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4842 }
4843
4844 /****************************************************************************/
4845 /* */
4846 /* Routine Name: ips_enable_int_morpheus */
4847 /* */
4848 /* Routine Description: */
4849 /* Turn on interrupts */
4850 /* */
4851 /****************************************************************************/
4852 static void
4853 ips_enable_int_morpheus(ips_ha_t * ha)
4854 {
4855 uint32_t Oimr;
4856
4857 METHOD_TRACE("ips_enable_int_morpheus", 1);
4858
4859 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4860 Oimr &= ~0x08;
4861 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4862 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4863 }
4864
4865 /****************************************************************************/
4866 /* */
4867 /* Routine Name: ips_init_copperhead */
4868 /* */
4869 /* Routine Description: */
4870 /* */
4871 /* Initialize a copperhead controller */
4872 /* */
4873 /****************************************************************************/
4874 static int
4875 ips_init_copperhead(ips_ha_t * ha)
4876 {
4877 uint8_t Isr;
4878 uint8_t Cbsp;
4879 uint8_t PostByte[IPS_MAX_POST_BYTES];
4880 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4881 int i, j;
4882
4883 METHOD_TRACE("ips_init_copperhead", 1);
4884
4885 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4886 for (j = 0; j < 45; j++) {
4887 Isr = inb(ha->io_addr + IPS_REG_HISR);
4888 if (Isr & IPS_BIT_GHI)
4889 break;
4890
4891 /* Delay for 1 Second */
4892 MDELAY(IPS_ONE_SEC);
4893 }
4894
4895 if (j >= 45)
4896 /* error occurred */
4897 return (0);
4898
4899 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4900 outb(Isr, ha->io_addr + IPS_REG_HISR);
4901 }
4902
4903 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4904 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4905 "reset controller fails (post status %x %x).\n",
4906 PostByte[0], PostByte[1]);
4907
4908 return (0);
4909 }
4910
4911 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4912 for (j = 0; j < 240; j++) {
4913 Isr = inb(ha->io_addr + IPS_REG_HISR);
4914 if (Isr & IPS_BIT_GHI)
4915 break;
4916
4917 /* Delay for 1 Second */
4918 MDELAY(IPS_ONE_SEC);
4919 }
4920
4921 if (j >= 240)
4922 /* error occurred */
4923 return (0);
4924
4925 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4926 outb(Isr, ha->io_addr + IPS_REG_HISR);
4927 }
4928
4929 for (i = 0; i < 240; i++) {
4930 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4931
4932 if ((Cbsp & IPS_BIT_OP) == 0)
4933 break;
4934
4935 /* Delay for 1 Second */
4936 MDELAY(IPS_ONE_SEC);
4937 }
4938
4939 if (i >= 240)
4940 /* reset failed */
4941 return (0);
4942
4943 /* setup CCCR */
4944 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
4945
4946 /* Enable busmastering */
4947 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4948
4949 if (ha->revision_id == IPS_REVID_TROMBONE64)
4950 /* fix for anaconda64 */
4951 outl(0, ha->io_addr + IPS_REG_NDAE);
4952
4953 /* Enable interrupts */
4954 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4955
4956 return (1);
4957 }
4958
4959 /****************************************************************************/
4960 /* */
4961 /* Routine Name: ips_init_copperhead_memio */
4962 /* */
4963 /* Routine Description: */
4964 /* */
4965 /* Initialize a copperhead controller with memory mapped I/O */
4966 /* */
4967 /****************************************************************************/
4968 static int
4969 ips_init_copperhead_memio(ips_ha_t * ha)
4970 {
4971 uint8_t Isr = 0;
4972 uint8_t Cbsp;
4973 uint8_t PostByte[IPS_MAX_POST_BYTES];
4974 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4975 int i, j;
4976
4977 METHOD_TRACE("ips_init_copperhead_memio", 1);
4978
4979 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4980 for (j = 0; j < 45; j++) {
4981 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4982 if (Isr & IPS_BIT_GHI)
4983 break;
4984
4985 /* Delay for 1 Second */
4986 MDELAY(IPS_ONE_SEC);
4987 }
4988
4989 if (j >= 45)
4990 /* error occurred */
4991 return (0);
4992
4993 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4994 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4995 }
4996
4997 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4998 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4999 "reset controller fails (post status %x %x).\n",
5000 PostByte[0], PostByte[1]);
5001
5002 return (0);
5003 }
5004
5005 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
5006 for (j = 0; j < 240; j++) {
5007 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5008 if (Isr & IPS_BIT_GHI)
5009 break;
5010
5011 /* Delay for 1 Second */
5012 MDELAY(IPS_ONE_SEC);
5013 }
5014
5015 if (j >= 240)
5016 /* error occurred */
5017 return (0);
5018
5019 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5020 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5021 }
5022
5023 for (i = 0; i < 240; i++) {
5024 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
5025
5026 if ((Cbsp & IPS_BIT_OP) == 0)
5027 break;
5028
5029 /* Delay for 1 Second */
5030 MDELAY(IPS_ONE_SEC);
5031 }
5032
5033 if (i >= 240)
5034 /* error occurred */
5035 return (0);
5036
5037 /* setup CCCR */
5038 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
5039
5040 /* Enable busmastering */
5041 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
5042
5043 if (ha->revision_id == IPS_REVID_TROMBONE64)
5044 /* fix for anaconda64 */
5045 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5046
5047 /* Enable interrupts */
5048 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
5049
5050 /* if we get here then everything went OK */
5051 return (1);
5052 }
5053
5054 /****************************************************************************/
5055 /* */
5056 /* Routine Name: ips_init_morpheus */
5057 /* */
5058 /* Routine Description: */
5059 /* */
5060 /* Initialize a morpheus controller */
5061 /* */
5062 /****************************************************************************/
5063 static int
5064 ips_init_morpheus(ips_ha_t * ha)
5065 {
5066 uint32_t Post;
5067 uint32_t Config;
5068 uint32_t Isr;
5069 uint32_t Oimr;
5070 int i;
5071
5072 METHOD_TRACE("ips_init_morpheus", 1);
5073
5074 /* Wait up to 45 secs for Post */
5075 for (i = 0; i < 45; i++) {
5076 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5077
5078 if (Isr & IPS_BIT_I960_MSG0I)
5079 break;
5080
5081 /* Delay for 1 Second */
5082 MDELAY(IPS_ONE_SEC);
5083 }
5084
5085 if (i >= 45) {
5086 /* error occurred */
5087 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5088 "timeout waiting for post.\n");
5089
5090 return (0);
5091 }
5092
5093 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5094
5095 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5096 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5097 "Flashing Battery PIC, Please wait ...\n");
5098
5099 /* Clear the interrupt bit */
5100 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5101 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5102
5103 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5104 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5105 if (Post != 0x4F00)
5106 break;
5107 /* Delay for 1 Second */
5108 MDELAY(IPS_ONE_SEC);
5109 }
5110
5111 if (i >= 120) {
5112 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5113 "timeout waiting for Battery PIC Flash\n");
5114 return (0);
5115 }
5116
5117 }
5118
5119 /* Clear the interrupt bit */
5120 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5121 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5122
5123 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5124 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5125 "reset controller fails (post status %x).\n", Post);
5126
5127 return (0);
5128 }
5129
5130 /* Wait up to 240 secs for config bytes */
5131 for (i = 0; i < 240; i++) {
5132 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5133
5134 if (Isr & IPS_BIT_I960_MSG1I)
5135 break;
5136
5137 /* Delay for 1 Second */
5138 MDELAY(IPS_ONE_SEC);
5139 }
5140
5141 if (i >= 240) {
5142 /* error occurred */
5143 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5144 "timeout waiting for config.\n");
5145
5146 return (0);
5147 }
5148
5149 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5150
5151 /* Clear interrupt bit */
5152 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5153 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5154
5155 /* Turn on the interrupts */
5156 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5157 Oimr &= ~0x8;
5158 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5159
5160 /* if we get here then everything went OK */
5161
5162 /* Since we did a RESET, an EraseStripeLock may be needed */
5163 if (Post == 0xEF10) {
5164 if ((Config == 0x000F) || (Config == 0x0009))
5165 ha->requires_esl = 1;
5166 }
5167
5168 return (1);
5169 }
5170
5171 /****************************************************************************/
5172 /* */
5173 /* Routine Name: ips_reset_copperhead */
5174 /* */
5175 /* Routine Description: */
5176 /* */
5177 /* Reset the controller */
5178 /* */
5179 /****************************************************************************/
5180 static int
5181 ips_reset_copperhead(ips_ha_t * ha)
5182 {
5183 int reset_counter;
5184
5185 METHOD_TRACE("ips_reset_copperhead", 1);
5186
5187 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5188 ips_name, ha->host_num, ha->io_addr, ha->irq);
5189
5190 reset_counter = 0;
5191
5192 while (reset_counter < 2) {
5193 reset_counter++;
5194
5195 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5196
5197 /* Delay for 1 Second */
5198 MDELAY(IPS_ONE_SEC);
5199
5200 outb(0, ha->io_addr + IPS_REG_SCPR);
5201
5202 /* Delay for 1 Second */
5203 MDELAY(IPS_ONE_SEC);
5204
5205 if ((*ha->func.init) (ha))
5206 break;
5207 else if (reset_counter >= 2) {
5208
5209 return (0);
5210 }
5211 }
5212
5213 return (1);
5214 }
5215
5216 /****************************************************************************/
5217 /* */
5218 /* Routine Name: ips_reset_copperhead_memio */
5219 /* */
5220 /* Routine Description: */
5221 /* */
5222 /* Reset the controller */
5223 /* */
5224 /****************************************************************************/
5225 static int
5226 ips_reset_copperhead_memio(ips_ha_t * ha)
5227 {
5228 int reset_counter;
5229
5230 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5231
5232 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5233 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5234
5235 reset_counter = 0;
5236
5237 while (reset_counter < 2) {
5238 reset_counter++;
5239
5240 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5241
5242 /* Delay for 1 Second */
5243 MDELAY(IPS_ONE_SEC);
5244
5245 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5246
5247 /* Delay for 1 Second */
5248 MDELAY(IPS_ONE_SEC);
5249
5250 if ((*ha->func.init) (ha))
5251 break;
5252 else if (reset_counter >= 2) {
5253
5254 return (0);
5255 }
5256 }
5257
5258 return (1);
5259 }
5260
5261 /****************************************************************************/
5262 /* */
5263 /* Routine Name: ips_reset_morpheus */
5264 /* */
5265 /* Routine Description: */
5266 /* */
5267 /* Reset the controller */
5268 /* */
5269 /****************************************************************************/
5270 static int
5271 ips_reset_morpheus(ips_ha_t * ha)
5272 {
5273 int reset_counter;
5274 uint8_t junk;
5275
5276 METHOD_TRACE("ips_reset_morpheus", 1);
5277
5278 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5279 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5280
5281 reset_counter = 0;
5282
5283 while (reset_counter < 2) {
5284 reset_counter++;
5285
5286 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5287
5288 /* Delay for 5 Seconds */
5289 MDELAY(5 * IPS_ONE_SEC);
5290
5291 /* Do a PCI config read to wait for adapter */
5292 pci_read_config_byte(ha->pcidev, 4, &junk);
5293
5294 if ((*ha->func.init) (ha))
5295 break;
5296 else if (reset_counter >= 2) {
5297
5298 return (0);
5299 }
5300 }
5301
5302 return (1);
5303 }
5304
5305 /****************************************************************************/
5306 /* */
5307 /* Routine Name: ips_statinit */
5308 /* */
5309 /* Routine Description: */
5310 /* */
5311 /* Initialize the status queues on the controller */
5312 /* */
5313 /****************************************************************************/
5314 static void
5315 ips_statinit(ips_ha_t * ha)
5316 {
5317 uint32_t phys_status_start;
5318
5319 METHOD_TRACE("ips_statinit", 1);
5320
5321 ha->adapt->p_status_start = ha->adapt->status;
5322 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5323 ha->adapt->p_status_tail = ha->adapt->status;
5324
5325 phys_status_start = ha->adapt->hw_status_start;
5326 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5327 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
5328 ha->io_addr + IPS_REG_SQER);
5329 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
5330 ha->io_addr + IPS_REG_SQHR);
5331 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5332
5333 ha->adapt->hw_status_tail = phys_status_start;
5334 }
5335
5336 /****************************************************************************/
5337 /* */
5338 /* Routine Name: ips_statinit_memio */
5339 /* */
5340 /* Routine Description: */
5341 /* */
5342 /* Initialize the status queues on the controller */
5343 /* */
5344 /****************************************************************************/
5345 static void
5346 ips_statinit_memio(ips_ha_t * ha)
5347 {
5348 uint32_t phys_status_start;
5349
5350 METHOD_TRACE("ips_statinit_memio", 1);
5351
5352 ha->adapt->p_status_start = ha->adapt->status;
5353 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5354 ha->adapt->p_status_tail = ha->adapt->status;
5355
5356 phys_status_start = ha->adapt->hw_status_start;
5357 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5358 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5359 ha->mem_ptr + IPS_REG_SQER);
5360 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5361 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5362
5363 ha->adapt->hw_status_tail = phys_status_start;
5364 }
5365
5366 /****************************************************************************/
5367 /* */
5368 /* Routine Name: ips_statupd_copperhead */
5369 /* */
5370 /* Routine Description: */
5371 /* */
5372 /* Remove an element from the status queue */
5373 /* */
5374 /****************************************************************************/
5375 static uint32_t
5376 ips_statupd_copperhead(ips_ha_t * ha)
5377 {
5378 METHOD_TRACE("ips_statupd_copperhead", 1);
5379
5380 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5381 ha->adapt->p_status_tail++;
5382 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5383 } else {
5384 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5385 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5386 }
5387
5388 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5389 ha->io_addr + IPS_REG_SQTR);
5390
5391 return (ha->adapt->p_status_tail->value);
5392 }
5393
5394 /****************************************************************************/
5395 /* */
5396 /* Routine Name: ips_statupd_copperhead_memio */
5397 /* */
5398 /* Routine Description: */
5399 /* */
5400 /* Remove an element from the status queue */
5401 /* */
5402 /****************************************************************************/
5403 static uint32_t
5404 ips_statupd_copperhead_memio(ips_ha_t * ha)
5405 {
5406 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5407
5408 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5409 ha->adapt->p_status_tail++;
5410 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5411 } else {
5412 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5413 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5414 }
5415
5416 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5417
5418 return (ha->adapt->p_status_tail->value);
5419 }
5420
5421 /****************************************************************************/
5422 /* */
5423 /* Routine Name: ips_statupd_morpheus */
5424 /* */
5425 /* Routine Description: */
5426 /* */
5427 /* Remove an element from the status queue */
5428 /* */
5429 /****************************************************************************/
5430 static uint32_t
5431 ips_statupd_morpheus(ips_ha_t * ha)
5432 {
5433 uint32_t val;
5434
5435 METHOD_TRACE("ips_statupd_morpheus", 1);
5436
5437 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5438
5439 return (val);
5440 }
5441
5442 /****************************************************************************/
5443 /* */
5444 /* Routine Name: ips_issue_copperhead */
5445 /* */
5446 /* Routine Description: */
5447 /* */
5448 /* Send a command down to the controller */
5449 /* */
5450 /****************************************************************************/
5451 static int
5452 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5453 {
5454 uint32_t TimeOut;
5455 uint32_t val;
5456
5457 METHOD_TRACE("ips_issue_copperhead", 1);
5458
5459 if (scb->scsi_cmd) {
5460 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5461 ips_name,
5462 ha->host_num,
5463 scb->cdb[0],
5464 scb->cmd.basic_io.command_id,
5465 scb->bus, scb->target_id, scb->lun);
5466 } else {
5467 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5468 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5469 }
5470
5471 TimeOut = 0;
5472
5473 while ((val =
5474 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5475 udelay(1000);
5476
5477 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5478 if (!(val & IPS_BIT_START_STOP))
5479 break;
5480
5481 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5482 "ips_issue val [0x%x].\n", val);
5483 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5484 "ips_issue semaphore chk timeout.\n");
5485
5486 return (IPS_FAILURE);
5487 } /* end if */
5488 } /* end while */
5489
5490 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5491 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5492
5493 return (IPS_SUCCESS);
5494 }
5495
5496 /****************************************************************************/
5497 /* */
5498 /* Routine Name: ips_issue_copperhead_memio */
5499 /* */
5500 /* Routine Description: */
5501 /* */
5502 /* Send a command down to the controller */
5503 /* */
5504 /****************************************************************************/
5505 static int
5506 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5507 {
5508 uint32_t TimeOut;
5509 uint32_t val;
5510
5511 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5512
5513 if (scb->scsi_cmd) {
5514 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5515 ips_name,
5516 ha->host_num,
5517 scb->cdb[0],
5518 scb->cmd.basic_io.command_id,
5519 scb->bus, scb->target_id, scb->lun);
5520 } else {
5521 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5522 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5523 }
5524
5525 TimeOut = 0;
5526
5527 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5528 udelay(1000);
5529
5530 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5531 if (!(val & IPS_BIT_START_STOP))
5532 break;
5533
5534 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5535 "ips_issue val [0x%x].\n", val);
5536 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5537 "ips_issue semaphore chk timeout.\n");
5538
5539 return (IPS_FAILURE);
5540 } /* end if */
5541 } /* end while */
5542
5543 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5544 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5545
5546 return (IPS_SUCCESS);
5547 }
5548
5549 /****************************************************************************/
5550 /* */
5551 /* Routine Name: ips_issue_i2o */
5552 /* */
5553 /* Routine Description: */
5554 /* */
5555 /* Send a command down to the controller */
5556 /* */
5557 /****************************************************************************/
5558 static int
5559 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5560 {
5561
5562 METHOD_TRACE("ips_issue_i2o", 1);
5563
5564 if (scb->scsi_cmd) {
5565 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5566 ips_name,
5567 ha->host_num,
5568 scb->cdb[0],
5569 scb->cmd.basic_io.command_id,
5570 scb->bus, scb->target_id, scb->lun);
5571 } else {
5572 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5573 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5574 }
5575
5576 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5577
5578 return (IPS_SUCCESS);
5579 }
5580
5581 /****************************************************************************/
5582 /* */
5583 /* Routine Name: ips_issue_i2o_memio */
5584 /* */
5585 /* Routine Description: */
5586 /* */
5587 /* Send a command down to the controller */
5588 /* */
5589 /****************************************************************************/
5590 static int
5591 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5592 {
5593
5594 METHOD_TRACE("ips_issue_i2o_memio", 1);
5595
5596 if (scb->scsi_cmd) {
5597 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5598 ips_name,
5599 ha->host_num,
5600 scb->cdb[0],
5601 scb->cmd.basic_io.command_id,
5602 scb->bus, scb->target_id, scb->lun);
5603 } else {
5604 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5605 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5606 }
5607
5608 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5609
5610 return (IPS_SUCCESS);
5611 }
5612
5613 /****************************************************************************/
5614 /* */
5615 /* Routine Name: ips_isintr_copperhead */
5616 /* */
5617 /* Routine Description: */
5618 /* */
5619 /* Test to see if an interrupt is for us */
5620 /* */
5621 /****************************************************************************/
5622 static int
5623 ips_isintr_copperhead(ips_ha_t * ha)
5624 {
5625 uint8_t Isr;
5626
5627 METHOD_TRACE("ips_isintr_copperhead", 2);
5628
5629 Isr = inb(ha->io_addr + IPS_REG_HISR);
5630
5631 if (Isr == 0xFF)
5632 /* ?!?! Nothing really there */
5633 return (0);
5634
5635 if (Isr & IPS_BIT_SCE)
5636 return (1);
5637 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5638 /* status queue overflow or GHI */
5639 /* just clear the interrupt */
5640 outb(Isr, ha->io_addr + IPS_REG_HISR);
5641 }
5642
5643 return (0);
5644 }
5645
5646 /****************************************************************************/
5647 /* */
5648 /* Routine Name: ips_isintr_copperhead_memio */
5649 /* */
5650 /* Routine Description: */
5651 /* */
5652 /* Test to see if an interrupt is for us */
5653 /* */
5654 /****************************************************************************/
5655 static int
5656 ips_isintr_copperhead_memio(ips_ha_t * ha)
5657 {
5658 uint8_t Isr;
5659
5660 METHOD_TRACE("ips_isintr_memio", 2);
5661
5662 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5663
5664 if (Isr == 0xFF)
5665 /* ?!?! Nothing really there */
5666 return (0);
5667
5668 if (Isr & IPS_BIT_SCE)
5669 return (1);
5670 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5671 /* status queue overflow or GHI */
5672 /* just clear the interrupt */
5673 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5674 }
5675
5676 return (0);
5677 }
5678
5679 /****************************************************************************/
5680 /* */
5681 /* Routine Name: ips_isintr_morpheus */
5682 /* */
5683 /* Routine Description: */
5684 /* */
5685 /* Test to see if an interrupt is for us */
5686 /* */
5687 /****************************************************************************/
5688 static int
5689 ips_isintr_morpheus(ips_ha_t * ha)
5690 {
5691 uint32_t Isr;
5692
5693 METHOD_TRACE("ips_isintr_morpheus", 2);
5694
5695 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5696
5697 if (Isr & IPS_BIT_I2O_OPQI)
5698 return (1);
5699 else
5700 return (0);
5701 }
5702
5703 /****************************************************************************/
5704 /* */
5705 /* Routine Name: ips_wait */
5706 /* */
5707 /* Routine Description: */
5708 /* */
5709 /* Wait for a command to complete */
5710 /* */
5711 /****************************************************************************/
5712 static int
5713 ips_wait(ips_ha_t * ha, int time, int intr)
5714 {
5715 int ret;
5716 int done;
5717
5718 METHOD_TRACE("ips_wait", 1);
5719
5720 ret = IPS_FAILURE;
5721 done = FALSE;
5722
5723 time *= IPS_ONE_SEC; /* convert seconds */
5724
5725 while ((time > 0) && (!done)) {
5726 if (intr == IPS_INTR_ON) {
5727 if (ha->waitflag == FALSE) {
5728 ret = IPS_SUCCESS;
5729 done = TRUE;
5730 break;
5731 }
5732 } else if (intr == IPS_INTR_IORL) {
5733 if (ha->waitflag == FALSE) {
5734 /*
5735 * controller generated an interrupt to
5736 * acknowledge completion of the command
5737 * and ips_intr() has serviced the interrupt.
5738 */
5739 ret = IPS_SUCCESS;
5740 done = TRUE;
5741 break;
5742 }
5743
5744 /*
5745 * NOTE: we already have the io_request_lock so
5746 * even if we get an interrupt it won't get serviced
5747 * until after we finish.
5748 */
5749
5750 (*ha->func.intr) (ha);
5751 }
5752
5753 /* This looks like a very evil loop, but it only does this during start-up */
5754 udelay(1000);
5755 time--;
5756 }
5757
5758 return (ret);
5759 }
5760
5761 /****************************************************************************/
5762 /* */
5763 /* Routine Name: ips_write_driver_status */
5764 /* */
5765 /* Routine Description: */
5766 /* */
5767 /* Write OS/Driver version to Page 5 of the nvram on the controller */
5768 /* */
5769 /****************************************************************************/
5770 static int
5771 ips_write_driver_status(ips_ha_t * ha, int intr)
5772 {
5773 METHOD_TRACE("ips_write_driver_status", 1);
5774
5775 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5776 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5777 "unable to read NVRAM page 5.\n");
5778
5779 return (0);
5780 }
5781
5782 /* check to make sure the page has a valid */
5783 /* signature */
5784 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5785 DEBUG_VAR(1,
5786 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5787 ips_name, ha->host_num, ha->nvram->signature);
5788 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5789 }
5790
5791 DEBUG_VAR(2,
5792 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5793 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5794 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5795 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5796 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5797 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5798 ha->nvram->bios_low[3]);
5799
5800 ips_get_bios_version(ha, intr);
5801
5802 /* change values (as needed) */
5803 ha->nvram->operating_system = IPS_OS_LINUX;
5804 ha->nvram->adapter_type = ha->ad_type;
5805 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5806 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5807 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5808 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5809
5810 ips_version_check(ha, intr); /* Check BIOS/FW/Driver Versions */
5811
5812 /* now update the page */
5813 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5814 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5815 "unable to write NVRAM page 5.\n");
5816
5817 return (0);
5818 }
5819
5820 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5821 ha->slot_num = ha->nvram->adapter_slot;
5822
5823 return (1);
5824 }
5825
5826 /****************************************************************************/
5827 /* */
5828 /* Routine Name: ips_read_adapter_status */
5829 /* */
5830 /* Routine Description: */
5831 /* */
5832 /* Do an Inquiry command to the adapter */
5833 /* */
5834 /****************************************************************************/
5835 static int
5836 ips_read_adapter_status(ips_ha_t * ha, int intr)
5837 {
5838 ips_scb_t *scb;
5839 int ret;
5840
5841 METHOD_TRACE("ips_read_adapter_status", 1);
5842
5843 scb = &ha->scbs[ha->max_cmds - 1];
5844
5845 ips_init_scb(ha, scb);
5846
5847 scb->timeout = ips_cmd_timeout;
5848 scb->cdb[0] = IPS_CMD_ENQUIRY;
5849
5850 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5851 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5852 scb->cmd.basic_io.sg_count = 0;
5853 scb->cmd.basic_io.lba = 0;
5854 scb->cmd.basic_io.sector_count = 0;
5855 scb->cmd.basic_io.log_drv = 0;
5856 scb->data_len = sizeof (*ha->enq);
5857 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5858
5859 /* send command */
5860 if (((ret =
5861 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5862 || (ret == IPS_SUCCESS_IMM)
5863 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5864 return (0);
5865
5866 return (1);
5867 }
5868
5869 /****************************************************************************/
5870 /* */
5871 /* Routine Name: ips_read_subsystem_parameters */
5872 /* */
5873 /* Routine Description: */
5874 /* */
5875 /* Read subsystem parameters from the adapter */
5876 /* */
5877 /****************************************************************************/
5878 static int
5879 ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5880 {
5881 ips_scb_t *scb;
5882 int ret;
5883
5884 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5885
5886 scb = &ha->scbs[ha->max_cmds - 1];
5887
5888 ips_init_scb(ha, scb);
5889
5890 scb->timeout = ips_cmd_timeout;
5891 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5892
5893 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5894 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5895 scb->cmd.basic_io.sg_count = 0;
5896 scb->cmd.basic_io.lba = 0;
5897 scb->cmd.basic_io.sector_count = 0;
5898 scb->cmd.basic_io.log_drv = 0;
5899 scb->data_len = sizeof (*ha->subsys);
5900 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5901
5902 /* send command */
5903 if (((ret =
5904 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5905 || (ret == IPS_SUCCESS_IMM)
5906 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5907 return (0);
5908
5909 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5910 return (1);
5911 }
5912
5913 /****************************************************************************/
5914 /* */
5915 /* Routine Name: ips_read_config */
5916 /* */
5917 /* Routine Description: */
5918 /* */
5919 /* Read the configuration on the adapter */
5920 /* */
5921 /****************************************************************************/
5922 static int
5923 ips_read_config(ips_ha_t * ha, int intr)
5924 {
5925 ips_scb_t *scb;
5926 int i;
5927 int ret;
5928
5929 METHOD_TRACE("ips_read_config", 1);
5930
5931 /* set defaults for initiator IDs */
5932 for (i = 0; i < 4; i++)
5933 ha->conf->init_id[i] = 7;
5934
5935 scb = &ha->scbs[ha->max_cmds - 1];
5936
5937 ips_init_scb(ha, scb);
5938
5939 scb->timeout = ips_cmd_timeout;
5940 scb->cdb[0] = IPS_CMD_READ_CONF;
5941
5942 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5943 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5944 scb->data_len = sizeof (*ha->conf);
5945 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5946
5947 /* send command */
5948 if (((ret =
5949 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5950 || (ret == IPS_SUCCESS_IMM)
5951 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5952
5953 memset(ha->conf, 0, sizeof (IPS_CONF));
5954
5955 /* reset initiator IDs */
5956 for (i = 0; i < 4; i++)
5957 ha->conf->init_id[i] = 7;
5958
5959 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5960 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5961 IPS_CMD_CMPLT_WERROR)
5962 return (1);
5963
5964 return (0);
5965 }
5966
5967 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5968 return (1);
5969 }
5970
5971 /****************************************************************************/
5972 /* */
5973 /* Routine Name: ips_readwrite_page5 */
5974 /* */
5975 /* Routine Description: */
5976 /* */
5977 /* Read nvram page 5 from the adapter */
5978 /* */
5979 /****************************************************************************/
5980 static int
5981 ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5982 {
5983 ips_scb_t *scb;
5984 int ret;
5985
5986 METHOD_TRACE("ips_readwrite_page5", 1);
5987
5988 scb = &ha->scbs[ha->max_cmds - 1];
5989
5990 ips_init_scb(ha, scb);
5991
5992 scb->timeout = ips_cmd_timeout;
5993 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5994
5995 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5996 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5997 scb->cmd.nvram.page = 5;
5998 scb->cmd.nvram.write = write;
5999 scb->cmd.nvram.reserved = 0;
6000 scb->cmd.nvram.reserved2 = 0;
6001 scb->data_len = sizeof (*ha->nvram);
6002 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
6003 if (write)
6004 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
6005
6006 /* issue the command */
6007 if (((ret =
6008 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6009 || (ret == IPS_SUCCESS_IMM)
6010 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
6011
6012 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
6013
6014 return (0);
6015 }
6016 if (!write)
6017 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
6018 return (1);
6019 }
6020
6021 /****************************************************************************/
6022 /* */
6023 /* Routine Name: ips_clear_adapter */
6024 /* */
6025 /* Routine Description: */
6026 /* */
6027 /* Clear the stripe lock tables */
6028 /* */
6029 /****************************************************************************/
6030 static int
6031 ips_clear_adapter(ips_ha_t * ha, int intr)
6032 {
6033 ips_scb_t *scb;
6034 int ret;
6035
6036 METHOD_TRACE("ips_clear_adapter", 1);
6037
6038 scb = &ha->scbs[ha->max_cmds - 1];
6039
6040 ips_init_scb(ha, scb);
6041
6042 scb->timeout = ips_reset_timeout;
6043 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
6044
6045 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
6046 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
6047 scb->cmd.config_sync.channel = 0;
6048 scb->cmd.config_sync.source_target = IPS_POCL;
6049 scb->cmd.config_sync.reserved = 0;
6050 scb->cmd.config_sync.reserved2 = 0;
6051 scb->cmd.config_sync.reserved3 = 0;
6052
6053 /* issue command */
6054 if (((ret =
6055 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6056 || (ret == IPS_SUCCESS_IMM)
6057 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6058 return (0);
6059
6060 /* send unlock stripe command */
6061 ips_init_scb(ha, scb);
6062
6063 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
6064 scb->timeout = ips_reset_timeout;
6065
6066 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
6067 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6068 scb->cmd.unlock_stripe.log_drv = 0;
6069 scb->cmd.unlock_stripe.control = IPS_CSL;
6070 scb->cmd.unlock_stripe.reserved = 0;
6071 scb->cmd.unlock_stripe.reserved2 = 0;
6072 scb->cmd.unlock_stripe.reserved3 = 0;
6073
6074 /* issue command */
6075 if (((ret =
6076 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6077 || (ret == IPS_SUCCESS_IMM)
6078 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6079 return (0);
6080
6081 return (1);
6082 }
6083
6084 /****************************************************************************/
6085 /* */
6086 /* Routine Name: ips_ffdc_reset */
6087 /* */
6088 /* Routine Description: */
6089 /* */
6090 /* FFDC: write reset info */
6091 /* */
6092 /****************************************************************************/
6093 static void
6094 ips_ffdc_reset(ips_ha_t * ha, int intr)
6095 {
6096 ips_scb_t *scb;
6097
6098 METHOD_TRACE("ips_ffdc_reset", 1);
6099
6100 scb = &ha->scbs[ha->max_cmds - 1];
6101
6102 ips_init_scb(ha, scb);
6103
6104 scb->timeout = ips_cmd_timeout;
6105 scb->cdb[0] = IPS_CMD_FFDC;
6106 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6107 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6108 scb->cmd.ffdc.reset_count = ha->reset_count;
6109 scb->cmd.ffdc.reset_type = 0x80;
6110
6111 /* convert time to what the card wants */
6112 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6113
6114 /* issue command */
6115 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6116 }
6117
6118 /****************************************************************************/
6119 /* */
6120 /* Routine Name: ips_ffdc_time */
6121 /* */
6122 /* Routine Description: */
6123 /* */
6124 /* FFDC: write time info */
6125 /* */
6126 /****************************************************************************/
6127 static void
6128 ips_ffdc_time(ips_ha_t * ha)
6129 {
6130 ips_scb_t *scb;
6131
6132 METHOD_TRACE("ips_ffdc_time", 1);
6133
6134 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6135
6136 scb = &ha->scbs[ha->max_cmds - 1];
6137
6138 ips_init_scb(ha, scb);
6139
6140 scb->timeout = ips_cmd_timeout;
6141 scb->cdb[0] = IPS_CMD_FFDC;
6142 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6143 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6144 scb->cmd.ffdc.reset_count = 0;
6145 scb->cmd.ffdc.reset_type = 0;
6146
6147 /* convert time to what the card wants */
6148 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6149
6150 /* issue command */
6151 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6152 }
6153
6154 /****************************************************************************/
6155 /* */
6156 /* Routine Name: ips_fix_ffdc_time */
6157 /* */
6158 /* Routine Description: */
6159 /* Adjust time_t to what the card wants */
6160 /* */
6161 /****************************************************************************/
6162 static void
6163 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6164 {
6165 long days;
6166 long rem;
6167 int i;
6168 int year;
6169 int yleap;
6170 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6171 int month_lengths[12][2] = { {31, 31},
6172 {28, 29},
6173 {31, 31},
6174 {30, 30},
6175 {31, 31},
6176 {30, 30},
6177 {31, 31},
6178 {31, 31},
6179 {30, 30},
6180 {31, 31},
6181 {30, 30},
6182 {31, 31}
6183 };
6184
6185 METHOD_TRACE("ips_fix_ffdc_time", 1);
6186
6187 days = current_time / IPS_SECS_DAY;
6188 rem = current_time % IPS_SECS_DAY;
6189
6190 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6191 rem = rem % IPS_SECS_HOUR;
6192 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6193 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6194
6195 year = IPS_EPOCH_YEAR;
6196 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6197 int newy;
6198
6199 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6200 if (days < 0)
6201 --newy;
6202 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6203 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6204 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6205 year = newy;
6206 }
6207
6208 scb->cmd.ffdc.yearH = year / 100;
6209 scb->cmd.ffdc.yearL = year % 100;
6210
6211 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6212 days -= month_lengths[i][yleap];
6213
6214 scb->cmd.ffdc.month = i + 1;
6215 scb->cmd.ffdc.day = days + 1;
6216 }
6217
6218 /****************************************************************************
6219 * BIOS Flash Routines *
6220 ****************************************************************************/
6221
6222 /****************************************************************************/
6223 /* */
6224 /* Routine Name: ips_erase_bios */
6225 /* */
6226 /* Routine Description: */
6227 /* Erase the BIOS on the adapter */
6228 /* */
6229 /****************************************************************************/
6230 static int
6231 ips_erase_bios(ips_ha_t * ha)
6232 {
6233 int timeout;
6234 uint8_t status = 0;
6235
6236 METHOD_TRACE("ips_erase_bios", 1);
6237
6238 status = 0;
6239
6240 /* Clear the status register */
6241 outl(0, ha->io_addr + IPS_REG_FLAP);
6242 if (ha->revision_id == IPS_REVID_TROMBONE64)
6243 udelay(25); /* 25 us */
6244
6245 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6246 if (ha->revision_id == IPS_REVID_TROMBONE64)
6247 udelay(25); /* 25 us */
6248
6249 /* Erase Setup */
6250 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6251 if (ha->revision_id == IPS_REVID_TROMBONE64)
6252 udelay(25); /* 25 us */
6253
6254 /* Erase Confirm */
6255 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6256 if (ha->revision_id == IPS_REVID_TROMBONE64)
6257 udelay(25); /* 25 us */
6258
6259 /* Erase Status */
6260 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6261 if (ha->revision_id == IPS_REVID_TROMBONE64)
6262 udelay(25); /* 25 us */
6263
6264 timeout = 80000; /* 80 seconds */
6265
6266 while (timeout > 0) {
6267 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6268 outl(0, ha->io_addr + IPS_REG_FLAP);
6269 udelay(25); /* 25 us */
6270 }
6271
6272 status = inb(ha->io_addr + IPS_REG_FLDP);
6273
6274 if (status & 0x80)
6275 break;
6276
6277 MDELAY(1);
6278 timeout--;
6279 }
6280
6281 /* check for timeout */
6282 if (timeout <= 0) {
6283 /* timeout */
6284
6285 /* try to suspend the erase */
6286 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6287 if (ha->revision_id == IPS_REVID_TROMBONE64)
6288 udelay(25); /* 25 us */
6289
6290 /* wait for 10 seconds */
6291 timeout = 10000;
6292 while (timeout > 0) {
6293 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6294 outl(0, ha->io_addr + IPS_REG_FLAP);
6295 udelay(25); /* 25 us */
6296 }
6297
6298 status = inb(ha->io_addr + IPS_REG_FLDP);
6299
6300 if (status & 0xC0)
6301 break;
6302
6303 MDELAY(1);
6304 timeout--;
6305 }
6306
6307 return (1);
6308 }
6309
6310 /* check for valid VPP */
6311 if (status & 0x08)
6312 /* VPP failure */
6313 return (1);
6314
6315 /* check for succesful flash */
6316 if (status & 0x30)
6317 /* sequence error */
6318 return (1);
6319
6320 /* Otherwise, we were successful */
6321 /* clear status */
6322 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6323 if (ha->revision_id == IPS_REVID_TROMBONE64)
6324 udelay(25); /* 25 us */
6325
6326 /* enable reads */
6327 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6328 if (ha->revision_id == IPS_REVID_TROMBONE64)
6329 udelay(25); /* 25 us */
6330
6331 return (0);
6332 }
6333
6334 /****************************************************************************/
6335 /* */
6336 /* Routine Name: ips_erase_bios_memio */
6337 /* */
6338 /* Routine Description: */
6339 /* Erase the BIOS on the adapter */
6340 /* */
6341 /****************************************************************************/
6342 static int
6343 ips_erase_bios_memio(ips_ha_t * ha)
6344 {
6345 int timeout;
6346 uint8_t status;
6347
6348 METHOD_TRACE("ips_erase_bios_memio", 1);
6349
6350 status = 0;
6351
6352 /* Clear the status register */
6353 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6354 if (ha->revision_id == IPS_REVID_TROMBONE64)
6355 udelay(25); /* 25 us */
6356
6357 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6358 if (ha->revision_id == IPS_REVID_TROMBONE64)
6359 udelay(25); /* 25 us */
6360
6361 /* Erase Setup */
6362 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6363 if (ha->revision_id == IPS_REVID_TROMBONE64)
6364 udelay(25); /* 25 us */
6365
6366 /* Erase Confirm */
6367 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6368 if (ha->revision_id == IPS_REVID_TROMBONE64)
6369 udelay(25); /* 25 us */
6370
6371 /* Erase Status */
6372 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6373 if (ha->revision_id == IPS_REVID_TROMBONE64)
6374 udelay(25); /* 25 us */
6375
6376 timeout = 80000; /* 80 seconds */
6377
6378 while (timeout > 0) {
6379 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6380 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6381 udelay(25); /* 25 us */
6382 }
6383
6384 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6385
6386 if (status & 0x80)
6387 break;
6388
6389 MDELAY(1);
6390 timeout--;
6391 }
6392
6393 /* check for timeout */
6394 if (timeout <= 0) {
6395 /* timeout */
6396
6397 /* try to suspend the erase */
6398 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6399 if (ha->revision_id == IPS_REVID_TROMBONE64)
6400 udelay(25); /* 25 us */
6401
6402 /* wait for 10 seconds */
6403 timeout = 10000;
6404 while (timeout > 0) {
6405 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6406 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6407 udelay(25); /* 25 us */
6408 }
6409
6410 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6411
6412 if (status & 0xC0)
6413 break;
6414
6415 MDELAY(1);
6416 timeout--;
6417 }
6418
6419 return (1);
6420 }
6421
6422 /* check for valid VPP */
6423 if (status & 0x08)
6424 /* VPP failure */
6425 return (1);
6426
6427 /* check for succesful flash */
6428 if (status & 0x30)
6429 /* sequence error */
6430 return (1);
6431
6432 /* Otherwise, we were successful */
6433 /* clear status */
6434 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6435 if (ha->revision_id == IPS_REVID_TROMBONE64)
6436 udelay(25); /* 25 us */
6437
6438 /* enable reads */
6439 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6440 if (ha->revision_id == IPS_REVID_TROMBONE64)
6441 udelay(25); /* 25 us */
6442
6443 return (0);
6444 }
6445
6446 /****************************************************************************/
6447 /* */
6448 /* Routine Name: ips_program_bios */
6449 /* */
6450 /* Routine Description: */
6451 /* Program the BIOS on the adapter */
6452 /* */
6453 /****************************************************************************/
6454 static int
6455 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6456 uint32_t offset)
6457 {
6458 int i;
6459 int timeout;
6460 uint8_t status = 0;
6461
6462 METHOD_TRACE("ips_program_bios", 1);
6463
6464 status = 0;
6465
6466 for (i = 0; i < buffersize; i++) {
6467 /* write a byte */
6468 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6469 if (ha->revision_id == IPS_REVID_TROMBONE64)
6470 udelay(25); /* 25 us */
6471
6472 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6473 if (ha->revision_id == IPS_REVID_TROMBONE64)
6474 udelay(25); /* 25 us */
6475
6476 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6477 if (ha->revision_id == IPS_REVID_TROMBONE64)
6478 udelay(25); /* 25 us */
6479
6480 /* wait up to one second */
6481 timeout = 1000;
6482 while (timeout > 0) {
6483 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6484 outl(0, ha->io_addr + IPS_REG_FLAP);
6485 udelay(25); /* 25 us */
6486 }
6487
6488 status = inb(ha->io_addr + IPS_REG_FLDP);
6489
6490 if (status & 0x80)
6491 break;
6492
6493 MDELAY(1);
6494 timeout--;
6495 }
6496
6497 if (timeout == 0) {
6498 /* timeout error */
6499 outl(0, ha->io_addr + IPS_REG_FLAP);
6500 if (ha->revision_id == IPS_REVID_TROMBONE64)
6501 udelay(25); /* 25 us */
6502
6503 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6504 if (ha->revision_id == IPS_REVID_TROMBONE64)
6505 udelay(25); /* 25 us */
6506
6507 return (1);
6508 }
6509
6510 /* check the status */
6511 if (status & 0x18) {
6512 /* programming error */
6513 outl(0, ha->io_addr + IPS_REG_FLAP);
6514 if (ha->revision_id == IPS_REVID_TROMBONE64)
6515 udelay(25); /* 25 us */
6516
6517 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6518 if (ha->revision_id == IPS_REVID_TROMBONE64)
6519 udelay(25); /* 25 us */
6520
6521 return (1);
6522 }
6523 } /* end for */
6524
6525 /* Enable reading */
6526 outl(0, ha->io_addr + IPS_REG_FLAP);
6527 if (ha->revision_id == IPS_REVID_TROMBONE64)
6528 udelay(25); /* 25 us */
6529
6530 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6531 if (ha->revision_id == IPS_REVID_TROMBONE64)
6532 udelay(25); /* 25 us */
6533
6534 return (0);
6535 }
6536
6537 /****************************************************************************/
6538 /* */
6539 /* Routine Name: ips_program_bios_memio */
6540 /* */
6541 /* Routine Description: */
6542 /* Program the BIOS on the adapter */
6543 /* */
6544 /****************************************************************************/
6545 static int
6546 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6547 uint32_t offset)
6548 {
6549 int i;
6550 int timeout;
6551 uint8_t status = 0;
6552
6553 METHOD_TRACE("ips_program_bios_memio", 1);
6554
6555 status = 0;
6556
6557 for (i = 0; i < buffersize; i++) {
6558 /* write a byte */
6559 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6560 if (ha->revision_id == IPS_REVID_TROMBONE64)
6561 udelay(25); /* 25 us */
6562
6563 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6564 if (ha->revision_id == IPS_REVID_TROMBONE64)
6565 udelay(25); /* 25 us */
6566
6567 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6568 if (ha->revision_id == IPS_REVID_TROMBONE64)
6569 udelay(25); /* 25 us */
6570
6571 /* wait up to one second */
6572 timeout = 1000;
6573 while (timeout > 0) {
6574 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6575 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6576 udelay(25); /* 25 us */
6577 }
6578
6579 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6580
6581 if (status & 0x80)
6582 break;
6583
6584 MDELAY(1);
6585 timeout--;
6586 }
6587
6588 if (timeout == 0) {
6589 /* timeout error */
6590 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6591 if (ha->revision_id == IPS_REVID_TROMBONE64)
6592 udelay(25); /* 25 us */
6593
6594 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6595 if (ha->revision_id == IPS_REVID_TROMBONE64)
6596 udelay(25); /* 25 us */
6597
6598 return (1);
6599 }
6600
6601 /* check the status */
6602 if (status & 0x18) {
6603 /* programming error */
6604 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6605 if (ha->revision_id == IPS_REVID_TROMBONE64)
6606 udelay(25); /* 25 us */
6607
6608 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6609 if (ha->revision_id == IPS_REVID_TROMBONE64)
6610 udelay(25); /* 25 us */
6611
6612 return (1);
6613 }
6614 } /* end for */
6615
6616 /* Enable reading */
6617 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6618 if (ha->revision_id == IPS_REVID_TROMBONE64)
6619 udelay(25); /* 25 us */
6620
6621 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6622 if (ha->revision_id == IPS_REVID_TROMBONE64)
6623 udelay(25); /* 25 us */
6624
6625 return (0);
6626 }
6627
6628 /****************************************************************************/
6629 /* */
6630 /* Routine Name: ips_verify_bios */
6631 /* */
6632 /* Routine Description: */
6633 /* Verify the BIOS on the adapter */
6634 /* */
6635 /****************************************************************************/
6636 static int
6637 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6638 uint32_t offset)
6639 {
6640 uint8_t checksum;
6641 int i;
6642
6643 METHOD_TRACE("ips_verify_bios", 1);
6644
6645 /* test 1st byte */
6646 outl(0, ha->io_addr + IPS_REG_FLAP);
6647 if (ha->revision_id == IPS_REVID_TROMBONE64)
6648 udelay(25); /* 25 us */
6649
6650 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6651 return (1);
6652
6653 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6654 if (ha->revision_id == IPS_REVID_TROMBONE64)
6655 udelay(25); /* 25 us */
6656 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6657 return (1);
6658
6659 checksum = 0xff;
6660 for (i = 2; i < buffersize; i++) {
6661
6662 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6663 if (ha->revision_id == IPS_REVID_TROMBONE64)
6664 udelay(25); /* 25 us */
6665
6666 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6667 }
6668
6669 if (checksum != 0)
6670 /* failure */
6671 return (1);
6672 else
6673 /* success */
6674 return (0);
6675 }
6676
6677 /****************************************************************************/
6678 /* */
6679 /* Routine Name: ips_verify_bios_memio */
6680 /* */
6681 /* Routine Description: */
6682 /* Verify the BIOS on the adapter */
6683 /* */
6684 /****************************************************************************/
6685 static int
6686 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6687 uint32_t offset)
6688 {
6689 uint8_t checksum;
6690 int i;
6691
6692 METHOD_TRACE("ips_verify_bios_memio", 1);
6693
6694 /* test 1st byte */
6695 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6696 if (ha->revision_id == IPS_REVID_TROMBONE64)
6697 udelay(25); /* 25 us */
6698
6699 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6700 return (1);
6701
6702 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6703 if (ha->revision_id == IPS_REVID_TROMBONE64)
6704 udelay(25); /* 25 us */
6705 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6706 return (1);
6707
6708 checksum = 0xff;
6709 for (i = 2; i < buffersize; i++) {
6710
6711 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6712 if (ha->revision_id == IPS_REVID_TROMBONE64)
6713 udelay(25); /* 25 us */
6714
6715 checksum =
6716 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6717 }
6718
6719 if (checksum != 0)
6720 /* failure */
6721 return (1);
6722 else
6723 /* success */
6724 return (0);
6725 }
6726
6727 /*---------------------------------------------------------------------------*/
6728 /* Routine Name: ips_version_check */
6729 /* */
6730 /* Dependencies: */
6731 /* Assumes that ips_read_adapter_status() is called first filling in */
6732 /* the data for SubSystem Parameters. */
6733 /* Called from ips_write_driver_status() so it also assumes NVRAM Page 5 */
6734 /* Data is available. */
6735 /* */
6736 /*---------------------------------------------------------------------------*/
6737 static void
6738 ips_version_check(ips_ha_t * ha, int intr)
6739 {
6740 IPS_VERSION_DATA *VersionInfo;
6741 uint8_t FirmwareVersion[IPS_COMPAT_ID_LENGTH + 1];
6742 uint8_t BiosVersion[IPS_COMPAT_ID_LENGTH + 1];
6743 int MatchError;
6744 int rc;
6745 char BiosString[10];
6746 char FirmwareString[10];
6747
6748 METHOD_TRACE("ips_version_check", 1);
6749
6750 VersionInfo = ( IPS_VERSION_DATA * ) ha->ioctl_data;
6751
6752 memset(FirmwareVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6753 memset(BiosVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6754
6755 /* Get the Compatible BIOS Version from NVRAM Page 5 */
6756 memcpy(BiosVersion, ha->nvram->BiosCompatibilityID,
6757 IPS_COMPAT_ID_LENGTH);
6758
6759 rc = IPS_FAILURE;
6760 if (ha->subsys->param[4] & IPS_GET_VERSION_SUPPORT) { /* If Versioning is Supported */
6761 /* Get the Version Info with a Get Version Command */
6762 memset( VersionInfo, 0, sizeof (IPS_VERSION_DATA));
6763 rc = ips_get_version_info(ha, ha->ioctl_busaddr, intr);
6764 if (rc == IPS_SUCCESS)
6765 memcpy(FirmwareVersion, VersionInfo->compatibilityId,
6766 IPS_COMPAT_ID_LENGTH);
6767 }
6768
6769 if (rc != IPS_SUCCESS) { /* If Data Not Obtainable from a GetVersion Command */
6770 /* Get the Firmware Version from Enquiry Data */
6771 memcpy(FirmwareVersion, ha->enq->CodeBlkVersion,
6772 IPS_COMPAT_ID_LENGTH);
6773 }
6774
6775 /* printk(KERN_WARNING "Adapter's BIOS Version = %s\n", BiosVersion); */
6776 /* printk(KERN_WARNING "BIOS Compatible Version = %s\n", IPS_COMPAT_BIOS); */
6777 /* printk(KERN_WARNING "Adapter's Firmware Version = %s\n", FirmwareVersion); */
6778 /* printk(KERN_WARNING "Firmware Compatible Version = %s \n", Compatable[ ha->nvram->adapter_type ]); */
6779
6780 MatchError = 0;
6781
6782 if (strncmp
6783 (FirmwareVersion, Compatable[ha->nvram->adapter_type],
6784 IPS_COMPAT_ID_LENGTH) != 0)
6785 MatchError = 1;
6786
6787 if (strncmp(BiosVersion, IPS_COMPAT_BIOS, IPS_COMPAT_ID_LENGTH) != 0)
6788 MatchError = 1;
6789
6790 ha->nvram->versioning = 1; /* Indicate the Driver Supports Versioning */
6791
6792 if (MatchError) {
6793 ha->nvram->version_mismatch = 1;
6794 if (ips_cd_boot == 0) {
6795 strncpy(&BiosString[0], ha->nvram->bios_high, 4);
6796 strncpy(&BiosString[4], ha->nvram->bios_low, 4);
6797 BiosString[8] = 0;
6798
6799 strncpy(&FirmwareString[0], ha->enq->CodeBlkVersion, 8);
6800 FirmwareString[8] = 0;
6801
6802 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6803 "Warning ! ! ! ServeRAID Version Mismatch\n");
6804 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6805 "Bios = %s, Firmware = %s, Device Driver = %s%s\n",
6806 BiosString, FirmwareString, IPS_VERSION_HIGH,
6807 IPS_VERSION_LOW);
6808 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6809 "These levels should match to avoid possible compatibility problems.\n");
6810 }
6811 } else {
6812 ha->nvram->version_mismatch = 0;
6813 }
6814
6815 return;
6816 }
6817
6818 /*---------------------------------------------------------------------------*/
6819 /* Routine Name: ips_get_version_info */
6820 /* */
6821 /* Routine Description: */
6822 /* Issue an internal GETVERSION Command */
6823 /* */
6824 /* Return Value: */
6825 /* 0 if Successful, else non-zero */
6826 /*---------------------------------------------------------------------------*/
6827 static int
6828 ips_get_version_info(ips_ha_t * ha, dma_addr_t Buffer, int intr)
6829 {
6830 ips_scb_t *scb;
6831 int rc;
6832
6833 METHOD_TRACE("ips_get_version_info", 1);
6834
6835 scb = &ha->scbs[ha->max_cmds - 1];
6836
6837 ips_init_scb(ha, scb);
6838
6839 scb->timeout = ips_cmd_timeout;
6840 scb->cdb[0] = IPS_CMD_GET_VERSION_INFO;
6841 scb->cmd.version_info.op_code = IPS_CMD_GET_VERSION_INFO;
6842 scb->cmd.version_info.command_id = IPS_COMMAND_ID(ha, scb);
6843 scb->cmd.version_info.reserved = 0;
6844 scb->cmd.version_info.count = sizeof (IPS_VERSION_DATA);
6845 scb->cmd.version_info.reserved2 = 0;
6846 scb->data_len = sizeof (IPS_VERSION_DATA);
6847 scb->data_busaddr = Buffer;
6848 scb->cmd.version_info.buffer_addr = Buffer;
6849 scb->flags = 0;
6850
6851 /* issue command */
6852 rc = ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6853 return (rc);
6854 }
6855
6856 /****************************************************************************/
6857 /* */
6858 /* Routine Name: ips_abort_init */
6859 /* */
6860 /* Routine Description: */
6861 /* cleanup routine for a failed adapter initialization */
6862 /****************************************************************************/
6863 static int
6864 ips_abort_init(ips_ha_t * ha, int index)
6865 {
6866 ha->active = 0;
6867 ips_free(ha);
6868 ips_ha[index] = NULL;
6869 ips_sh[index] = NULL;
6870 return -1;
6871 }
6872
6873 /****************************************************************************/
6874 /* */
6875 /* Routine Name: ips_shift_controllers */
6876 /* */
6877 /* Routine Description: */
6878 /* helper function for ordering adapters */
6879 /****************************************************************************/
6880 static void
6881 ips_shift_controllers(int lowindex, int highindex)
6882 {
6883 ips_ha_t *ha_sav = ips_ha[highindex];
6884 struct Scsi_Host *sh_sav = ips_sh[highindex];
6885 int i;
6886
6887 for (i = highindex; i > lowindex; i--) {
6888 ips_ha[i] = ips_ha[i - 1];
6889 ips_sh[i] = ips_sh[i - 1];
6890 ips_ha[i]->host_num = i;
6891 }
6892 ha_sav->host_num = lowindex;
6893 ips_ha[lowindex] = ha_sav;
6894 ips_sh[lowindex] = sh_sav;
6895 }
6896
6897 /****************************************************************************/
6898 /* */
6899 /* Routine Name: ips_order_controllers */
6900 /* */
6901 /* Routine Description: */
6902 /* place controllers is the "proper" boot order */
6903 /****************************************************************************/
6904 static void
6905 ips_order_controllers(void)
6906 {
6907 int i, j, tmp, position = 0;
6908 IPS_NVRAM_P5 *nvram;
6909 if (!ips_ha[0])
6910 return;
6911 nvram = ips_ha[0]->nvram;
6912
6913 if (nvram->adapter_order[0]) {
6914 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6915 for (j = position; j < ips_num_controllers; j++) {
6916 switch (ips_ha[j]->ad_type) {
6917 case IPS_ADTYPE_SERVERAID6M:
6918 case IPS_ADTYPE_SERVERAID7M:
6919 if (nvram->adapter_order[i] == 'M') {
6920 ips_shift_controllers(position,
6921 j);
6922 position++;
6923 }
6924 break;
6925 case IPS_ADTYPE_SERVERAID4L:
6926 case IPS_ADTYPE_SERVERAID4M:
6927 case IPS_ADTYPE_SERVERAID4MX:
6928 case IPS_ADTYPE_SERVERAID4LX:
6929 if (nvram->adapter_order[i] == 'N') {
6930 ips_shift_controllers(position,
6931 j);
6932 position++;
6933 }
6934 break;
6935 case IPS_ADTYPE_SERVERAID6I:
6936 case IPS_ADTYPE_SERVERAID5I2:
6937 case IPS_ADTYPE_SERVERAID5I1:
6938 case IPS_ADTYPE_SERVERAID7k:
6939 if (nvram->adapter_order[i] == 'S') {
6940 ips_shift_controllers(position,
6941 j);
6942 position++;
6943 }
6944 break;
6945 case IPS_ADTYPE_SERVERAID:
6946 case IPS_ADTYPE_SERVERAID2:
6947 case IPS_ADTYPE_NAVAJO:
6948 case IPS_ADTYPE_KIOWA:
6949 case IPS_ADTYPE_SERVERAID3L:
6950 case IPS_ADTYPE_SERVERAID3:
6951 case IPS_ADTYPE_SERVERAID4H:
6952 if (nvram->adapter_order[i] == 'A') {
6953 ips_shift_controllers(position,
6954 j);
6955 position++;
6956 }
6957 break;
6958 default:
6959 break;
6960 }
6961 }
6962 }
6963 /* if adapter_order[0], then ordering is complete */
6964 return;
6965 }
6966 /* old bios, use older ordering */
6967 tmp = 0;
6968 for (i = position; i < ips_num_controllers; i++) {
6969 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6970 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6971 ips_shift_controllers(position, i);
6972 position++;
6973 tmp = 1;
6974 }
6975 }
6976 /* if there were no 5I cards, then don't do any extra ordering */
6977 if (!tmp)
6978 return;
6979 for (i = position; i < ips_num_controllers; i++) {
6980 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6981 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6982 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6983 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6984 ips_shift_controllers(position, i);
6985 position++;
6986 }
6987 }
6988
6989 return;
6990 }
6991
6992 /****************************************************************************/
6993 /* */
6994 /* Routine Name: ips_register_scsi */
6995 /* */
6996 /* Routine Description: */
6997 /* perform any registration and setup with the scsi layer */
6998 /****************************************************************************/
6999 static int
7000 ips_register_scsi(int index)
7001 {
7002 struct Scsi_Host *sh;
7003 ips_ha_t *ha, *oldha = ips_ha[index];
7004 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
7005 if (!sh) {
7006 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
7007 "Unable to register controller with SCSI subsystem\n");
7008 return -1;
7009 }
7010 ha = IPS_HA(sh);
7011 memcpy(ha, oldha, sizeof (ips_ha_t));
7012 free_irq(oldha->irq, oldha);
7013 /* Install the interrupt handler with the new ha */
7014 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7015 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7016 "Unable to install interrupt handler\n");
7017 scsi_host_put(sh);
7018 return -1;
7019 }
7020
7021 kfree(oldha);
7022 ips_sh[index] = sh;
7023 ips_ha[index] = ha;
7024 IPS_SCSI_SET_DEVICE(sh, ha);
7025
7026 /* Store away needed values for later use */
7027 sh->io_port = ha->io_addr;
7028 sh->n_io_port = ha->io_addr ? 255 : 0;
7029 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
7030 sh->irq = ha->irq;
7031 sh->sg_tablesize = sh->hostt->sg_tablesize;
7032 sh->can_queue = sh->hostt->can_queue;
7033 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
7034 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
7035 sh->use_clustering = sh->hostt->use_clustering;
7036
7037 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7)
7038 sh->max_sectors = 128;
7039 #endif
7040
7041 sh->max_id = ha->ntargets;
7042 sh->max_lun = ha->nlun;
7043 sh->max_channel = ha->nbus - 1;
7044 sh->can_queue = ha->max_cmds - 1;
7045
7046 IPS_ADD_HOST(sh, NULL);
7047 return 0;
7048 }
7049
7050 /*---------------------------------------------------------------------------*/
7051 /* Routine Name: ips_remove_device */
7052 /* */
7053 /* Routine Description: */
7054 /* Remove one Adapter ( Hot Plugging ) */
7055 /*---------------------------------------------------------------------------*/
7056 static void __devexit
7057 ips_remove_device(struct pci_dev *pci_dev)
7058 {
7059 int i;
7060 struct Scsi_Host *sh;
7061 ips_ha_t *ha;
7062
7063 for (i = 0; i < IPS_MAX_ADAPTERS; i++) {
7064 ha = ips_ha[i];
7065 if (ha) {
7066 if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
7067 (pci_dev->devfn == ha->pcidev->devfn)) {
7068 sh = ips_sh[i];
7069 ips_release(sh);
7070 }
7071 }
7072 }
7073 }
7074
7075 /****************************************************************************/
7076 /* */
7077 /* Routine Name: ips_module_init */
7078 /* */
7079 /* Routine Description: */
7080 /* function called on module load */
7081 /****************************************************************************/
7082 static int __init
7083 ips_module_init(void)
7084 {
7085 if (pci_module_init(&ips_pci_driver) < 0)
7086 return -ENODEV;
7087 ips_driver_template.module = THIS_MODULE;
7088 ips_order_controllers();
7089 if (IPS_REGISTER_HOSTS(&ips_driver_template)) {
7090 pci_unregister_driver(&ips_pci_driver);
7091 return -ENODEV;
7092 }
7093 register_reboot_notifier(&ips_notifier);
7094 return 0;
7095 }
7096
7097 /****************************************************************************/
7098 /* */
7099 /* Routine Name: ips_module_exit */
7100 /* */
7101 /* Routine Description: */
7102 /* function called on module unload */
7103 /****************************************************************************/
7104 static void __exit
7105 ips_module_exit(void)
7106 {
7107 IPS_UNREGISTER_HOSTS(&ips_driver_template);
7108 pci_unregister_driver(&ips_pci_driver);
7109 unregister_reboot_notifier(&ips_notifier);
7110 }
7111
7112 module_init(ips_module_init);
7113 module_exit(ips_module_exit);
7114
7115 /*---------------------------------------------------------------------------*/
7116 /* Routine Name: ips_insert_device */
7117 /* */
7118 /* Routine Description: */
7119 /* Add One Adapter ( Hot Plug ) */
7120 /* */
7121 /* Return Value: */
7122 /* 0 if Successful, else non-zero */
7123 /*---------------------------------------------------------------------------*/
7124 static int __devinit
7125 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
7126 {
7127 int index;
7128 int rc;
7129
7130 METHOD_TRACE("ips_insert_device", 1);
7131 if (pci_enable_device(pci_dev))
7132 return -1;
7133
7134 rc = ips_init_phase1(pci_dev, &index);
7135 if (rc == SUCCESS)
7136 rc = ips_init_phase2(index);
7137
7138 if (ips_hotplug)
7139 if (ips_register_scsi(index)) {
7140 ips_free(ips_ha[index]);
7141 rc = -1;
7142 }
7143
7144 if (rc == SUCCESS)
7145 ips_num_controllers++;
7146
7147 ips_next_controller = ips_num_controllers;
7148 return rc;
7149 }
7150
7151 /*---------------------------------------------------------------------------*/
7152 /* Routine Name: ips_init_phase1 */
7153 /* */
7154 /* Routine Description: */
7155 /* Adapter Initialization */
7156 /* */
7157 /* Return Value: */
7158 /* 0 if Successful, else non-zero */
7159 /*---------------------------------------------------------------------------*/
7160 static int
7161 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7162 {
7163 ips_ha_t *ha;
7164 uint32_t io_addr;
7165 uint32_t mem_addr;
7166 uint32_t io_len;
7167 uint32_t mem_len;
7168 uint8_t revision_id;
7169 uint8_t bus;
7170 uint8_t func;
7171 uint8_t irq;
7172 uint16_t subdevice_id;
7173 int j;
7174 int index;
7175 dma_addr_t dma_address;
7176 char __iomem *ioremap_ptr;
7177 char __iomem *mem_ptr;
7178 uint32_t IsDead;
7179
7180 METHOD_TRACE("ips_init_phase1", 1);
7181 index = IPS_MAX_ADAPTERS;
7182 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7183 if (ips_ha[j] == 0) {
7184 index = j;
7185 break;
7186 }
7187 }
7188
7189 if (index >= IPS_MAX_ADAPTERS)
7190 return -1;
7191
7192 /* stuff that we get in dev */
7193 irq = pci_dev->irq;
7194 bus = pci_dev->bus->number;
7195 func = pci_dev->devfn;
7196
7197 /* Init MEM/IO addresses to 0 */
7198 mem_addr = 0;
7199 io_addr = 0;
7200 mem_len = 0;
7201 io_len = 0;
7202
7203 for (j = 0; j < 2; j++) {
7204 if (!pci_resource_start(pci_dev, j))
7205 break;
7206
7207 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
7208 io_addr = pci_resource_start(pci_dev, j);
7209 io_len = pci_resource_len(pci_dev, j);
7210 } else {
7211 mem_addr = pci_resource_start(pci_dev, j);
7212 mem_len = pci_resource_len(pci_dev, j);
7213 }
7214 }
7215
7216 /* setup memory mapped area (if applicable) */
7217 if (mem_addr) {
7218 uint32_t base;
7219 uint32_t offs;
7220
7221 if (!request_mem_region(mem_addr, mem_len, "ips")) {
7222 IPS_PRINTK(KERN_WARNING, pci_dev,
7223 "Couldn't allocate IO Memory space %x len %d.\n",
7224 mem_addr, mem_len);
7225 return -1;
7226 }
7227
7228 base = mem_addr & PAGE_MASK;
7229 offs = mem_addr - base;
7230 ioremap_ptr = ioremap(base, PAGE_SIZE);
7231 mem_ptr = ioremap_ptr + offs;
7232 } else {
7233 ioremap_ptr = NULL;
7234 mem_ptr = NULL;
7235 }
7236
7237 /* setup I/O mapped area (if applicable) */
7238 if (io_addr) {
7239 if (!request_region(io_addr, io_len, "ips")) {
7240 IPS_PRINTK(KERN_WARNING, pci_dev,
7241 "Couldn't allocate IO space %x len %d.\n",
7242 io_addr, io_len);
7243 return -1;
7244 }
7245 }
7246
7247 /* get the revision ID */
7248 if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
7249 IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n");
7250 return -1;
7251 }
7252
7253 subdevice_id = pci_dev->subsystem_device;
7254
7255 /* found a controller */
7256 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
7257 if (ha == NULL) {
7258 IPS_PRINTK(KERN_WARNING, pci_dev,
7259 "Unable to allocate temporary ha struct\n");
7260 return -1;
7261 }
7262
7263 memset(ha, 0, sizeof (ips_ha_t));
7264
7265 ips_sh[index] = NULL;
7266 ips_ha[index] = ha;
7267 ha->active = 1;
7268
7269 /* Store info in HA structure */
7270 ha->irq = irq;
7271 ha->io_addr = io_addr;
7272 ha->io_len = io_len;
7273 ha->mem_addr = mem_addr;
7274 ha->mem_len = mem_len;
7275 ha->mem_ptr = mem_ptr;
7276 ha->ioremap_ptr = ioremap_ptr;
7277 ha->host_num = (uint32_t) index;
7278 ha->revision_id = revision_id;
7279 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7280 ha->device_id = pci_dev->device;
7281 ha->subdevice_id = subdevice_id;
7282 ha->pcidev = pci_dev;
7283
7284 /*
7285 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7286 * addressing so don't enable it if the adapter can't support
7287 * it! Also, don't use 64bit addressing if dma addresses
7288 * are guaranteed to be < 4G.
7289 */
7290 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7291 !pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) {
7292 (ha)->flags |= IPS_HA_ENH_SG;
7293 } else {
7294 if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) {
7295 printk(KERN_WARNING "Unable to set DMA Mask\n");
7296 return ips_abort_init(ha, index);
7297 }
7298 }
7299 if(ips_cd_boot && !ips_FlashData){
7300 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7301 &ips_flashbusaddr);
7302 }
7303
7304 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7305 &ha->enq_busaddr);
7306 if (!ha->enq) {
7307 IPS_PRINTK(KERN_WARNING, pci_dev,
7308 "Unable to allocate host inquiry structure\n");
7309 return ips_abort_init(ha, index);
7310 }
7311
7312 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7313 sizeof (IPS_IO_CMD), &dma_address);
7314 if (!ha->adapt) {
7315 IPS_PRINTK(KERN_WARNING, pci_dev,
7316 "Unable to allocate host adapt & dummy structures\n");
7317 return ips_abort_init(ha, index);
7318 }
7319 ha->adapt->hw_status_start = dma_address;
7320 ha->dummy = (void *) (ha->adapt + 1);
7321
7322
7323
7324 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7325 if (!ha->logical_drive_info) {
7326 IPS_PRINTK(KERN_WARNING, pci_dev,
7327 "Unable to allocate logical drive info structure\n");
7328 return ips_abort_init(ha, index);
7329 }
7330 ha->logical_drive_info_dma_addr = dma_address;
7331
7332
7333 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7334
7335 if (!ha->conf) {
7336 IPS_PRINTK(KERN_WARNING, pci_dev,
7337 "Unable to allocate host conf structure\n");
7338 return ips_abort_init(ha, index);
7339 }
7340
7341 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7342
7343 if (!ha->nvram) {
7344 IPS_PRINTK(KERN_WARNING, pci_dev,
7345 "Unable to allocate host NVRAM structure\n");
7346 return ips_abort_init(ha, index);
7347 }
7348
7349 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7350
7351 if (!ha->subsys) {
7352 IPS_PRINTK(KERN_WARNING, pci_dev,
7353 "Unable to allocate host subsystem structure\n");
7354 return ips_abort_init(ha, index);
7355 }
7356
7357 /* the ioctl buffer is now used during adapter initialization, so its
7358 * successful allocation is now required */
7359 if (ips_ioctlsize < PAGE_SIZE)
7360 ips_ioctlsize = PAGE_SIZE;
7361
7362 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7363 &ha->ioctl_busaddr);
7364 ha->ioctl_len = ips_ioctlsize;
7365 if (!ha->ioctl_data) {
7366 IPS_PRINTK(KERN_WARNING, pci_dev,
7367 "Unable to allocate IOCTL data\n");
7368 return ips_abort_init(ha, index);
7369 }
7370
7371 /*
7372 * Setup Functions
7373 */
7374 ips_setup_funclist(ha);
7375
7376 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7377 /* If Morpheus appears dead, reset it */
7378 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7379 if (IsDead == 0xDEADBEEF) {
7380 ips_reset_morpheus(ha);
7381 }
7382 }
7383
7384 /*
7385 * Initialize the card if it isn't already
7386 */
7387
7388 if (!(*ha->func.isinit) (ha)) {
7389 if (!(*ha->func.init) (ha)) {
7390 /*
7391 * Initialization failed
7392 */
7393 IPS_PRINTK(KERN_WARNING, pci_dev,
7394 "Unable to initialize controller\n");
7395 return ips_abort_init(ha, index);
7396 }
7397 }
7398
7399 *indexPtr = index;
7400 return SUCCESS;
7401 }
7402
7403 /*---------------------------------------------------------------------------*/
7404 /* Routine Name: ips_init_phase2 */
7405 /* */
7406 /* Routine Description: */
7407 /* Adapter Initialization Phase 2 */
7408 /* */
7409 /* Return Value: */
7410 /* 0 if Successful, else non-zero */
7411 /*---------------------------------------------------------------------------*/
7412 static int
7413 ips_init_phase2(int index)
7414 {
7415 ips_ha_t *ha;
7416
7417 ha = ips_ha[index];
7418
7419 METHOD_TRACE("ips_init_phase2", 1);
7420 if (!ha->active) {
7421 ips_ha[index] = NULL;
7422 return -1;
7423 }
7424
7425 /* Install the interrupt handler */
7426 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7427 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7428 "Unable to install interrupt handler\n");
7429 return ips_abort_init(ha, index);
7430 }
7431
7432 /*
7433 * Allocate a temporary SCB for initialization
7434 */
7435 ha->max_cmds = 1;
7436 if (!ips_allocatescbs(ha)) {
7437 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7438 "Unable to allocate a CCB\n");
7439 free_irq(ha->irq, ha);
7440 return ips_abort_init(ha, index);
7441 }
7442
7443 if (!ips_hainit(ha)) {
7444 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7445 "Unable to initialize controller\n");
7446 free_irq(ha->irq, ha);
7447 return ips_abort_init(ha, index);
7448 }
7449 /* Free the temporary SCB */
7450 ips_deallocatescbs(ha, 1);
7451
7452 /* allocate CCBs */
7453 if (!ips_allocatescbs(ha)) {
7454 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7455 "Unable to allocate CCBs\n");
7456 free_irq(ha->irq, ha);
7457 return ips_abort_init(ha, index);
7458 }
7459
7460 return SUCCESS;
7461 }
7462
7463 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9)
7464 MODULE_LICENSE("GPL");
7465 #endif
7466
7467 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7468
7469 #ifdef MODULE_VERSION
7470 MODULE_VERSION(IPS_VER_STRING);
7471 #endif
7472
7473
7474 /*
7475 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7476 * Emacs will notice this stuff at the end of the file and automatically
7477 * adjust the settings for this buffer only. This must remain at the end
7478 * of the file.
7479 * ---------------------------------------------------------------------------
7480 * Local variables:
7481 * c-indent-level: 2
7482 * c-brace-imaginary-offset: 0
7483 * c-brace-offset: -2
7484 * c-argdecl-indent: 2
7485 * c-label-offset: -2
7486 * c-continued-statement-offset: 2
7487 * c-continued-brace-offset: 0
7488 * indent-tabs-mode: nil
7489 * tab-width: 8
7490 * End:
7491 */
kernel source for telekom puls (alcatel/mediatek)