1 /**************************************************************************
2 * Initio 9100 device driver for Linux.
4 * Copyright (c) 1994-1998 Initio Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 * --------------------------------------------------------------------------
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions, and the following disclaimer,
28 * without modification, immediately at the beginning of the file.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
35 * Where this Software is combined with software released under the terms of
36 * the GNU General Public License ("GPL") and the terms of the GPL would require the
37 * combined work to also be released under the terms of the GPL, the terms
38 * and conditions of this License will apply in addition to those of the
39 * GPL with the exception of any terms or conditions of this License that
40 * conflict with, or are expressly prohibited by, the GPL.
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
46 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 **************************************************************************/
57 #include <linux/config.h>
58 #include <linux/types.h>
60 #define ULONG unsigned long
61 #define USHORT unsigned short
62 #define UCHAR unsigned char
63 #define BYTE unsigned char
64 #define WORD unsigned short
65 #define DWORD unsigned long
66 #define UBYTE unsigned char
67 #define UWORD unsigned short
68 #define UDWORD unsigned long
71 #define TOTAL_SG_ENTRY 32
72 #define MAX_SUPPORTED_ADAPTERS 8
74 #define MAX_TARGETS 16
81 /***************************************/
82 /* Tulip Configuration Register Set */
83 /***************************************/
84 #define TUL_PVID 0x00 /* Vendor ID */
85 #define TUL_PDID 0x02 /* Device ID */
86 #define TUL_PCMD 0x04 /* Command */
87 #define TUL_PSTUS 0x06 /* Status */
88 #define TUL_PRID 0x08 /* Revision number */
89 #define TUL_PPI 0x09 /* Programming interface */
90 #define TUL_PSC 0x0A /* Sub Class */
91 #define TUL_PBC 0x0B /* Base Class */
92 #define TUL_PCLS 0x0C /* Cache line size */
93 #define TUL_PLTR 0x0D /* Latency timer */
94 #define TUL_PHDT 0x0E /* Header type */
95 #define TUL_PBIST 0x0F /* BIST */
96 #define TUL_PBAD 0x10 /* Base address */
97 #define TUL_PBAD1 0x14 /* Base address */
98 #define TUL_PBAD2 0x18 /* Base address */
99 #define TUL_PBAD3 0x1C /* Base address */
100 #define TUL_PBAD4 0x20 /* Base address */
101 #define TUL_PBAD5 0x24 /* Base address */
102 #define TUL_PRSVD 0x28 /* Reserved */
103 #define TUL_PRSVD1 0x2C /* Reserved */
104 #define TUL_PRAD 0x30 /* Expansion ROM base address */
105 #define TUL_PRSVD2 0x34 /* Reserved */
106 #define TUL_PRSVD3 0x38 /* Reserved */
107 #define TUL_PINTL 0x3C /* Interrupt line */
108 #define TUL_PINTP 0x3D /* Interrupt pin */
109 #define TUL_PIGNT 0x3E /* MIN_GNT */
110 #define TUL_PMGNT 0x3F /* MAX_GNT */
112 /************************/
113 /* Jasmin Register Set */
114 /************************/
115 #define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */
116 #define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */
117 #define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */
119 #define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */
120 #define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */
121 #define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */
122 #define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */
124 #define TUL_GINTS 0x50 /* Global Interrupt Status Register */
125 #define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */
126 #define TUL_GCTRL 0x54 /* Global Control Register */
127 #define TUL_GCTRL_EEPROM_BIT 0x04
128 #define TUL_GCTRL1 0x55 /* Global Control Register */
129 #define TUL_DMACFG 0x5B /* DMA configuration */
130 #define TUL_NVRAM 0x5D /* Non-volatile RAM port */
132 #define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */
133 #define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */
134 #define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */
135 #define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */
136 #define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */
137 #define TUL_SInt 0x84 /* 04 R Interrupt Register */
138 #define TUL_SCtrl0 0x85 /* 05 W Control 0 */
139 #define TUL_SStatus0 0x85 /* 05 R Status 0 */
140 #define TUL_SCtrl1 0x86 /* 06 W Control 1 */
141 #define TUL_SStatus1 0x86 /* 06 R Status 1 */
142 #define TUL_SConfig 0x87 /* 07 W Configuration */
143 #define TUL_SStatus2 0x87 /* 07 R Status 2 */
144 #define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */
145 #define TUL_SOffset 0x88 /* 08 R Offset */
146 #define TUL_SScsiId 0x89 /* 09 W SCSI ID */
147 #define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */
148 #define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */
149 #define TUL_SIdent 0x8A /* 0A R Identify Message Register */
150 #define TUL_SAvail 0x8A /* 0A R Availiable Counter Register */
151 #define TUL_SData 0x8B /* 0B R/W SCSI data in/out */
152 #define TUL_SFifo 0x8C /* 0C R/W FIFO */
153 #define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */
154 #define TUL_SCmd 0x91 /* 11 R/W Command */
155 #define TUL_STest0 0x92 /* 12 R/W Test0 */
156 #define TUL_STest1 0x93 /* 13 R/W Test1 */
157 #define TUL_SCFG1 0x94 /* 14 R/W Configuration */
159 #define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */
160 #define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */
161 #define TUL_XCntH 0xD0 /*DMA Transfer Counter */
162 #define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */
163 #define TUL_XCmd 0xD8 /*DMA Command Register */
164 #define TUL_Int 0xDC /*Interrupt Register */
165 #define TUL_XStatus 0xDD /*DMA status Register */
166 #define TUL_Mask 0xE0 /*Interrupt Mask Register */
167 #define TUL_XCtrl 0xE4 /*DMA Control Register */
168 #define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */
169 #define TUL_XFifo 0xE8 /*DMA FIFO */
171 #define TUL_WCtrl 0xF7 /*Bus master wait state control */
172 #define TUL_DCtrl 0xFB /*DMA delay control */
174 /*----------------------------------------------------------------------*/
175 /* bit definition for Command register of Configuration Space Header */
176 /*----------------------------------------------------------------------*/
177 #define BUSMS 0x04 /* BUS MASTER Enable */
178 #define IOSPA 0x01 /* IO Space Enable */
180 /*----------------------------------------------------------------------*/
181 /* Command Codes of Tulip SCSI Command register */
182 /*----------------------------------------------------------------------*/
183 #define TSC_EN_RESEL 0x80 /* Enable Reselection */
184 #define TSC_CMD_COMP 0x84 /* Command Complete Sequence */
185 #define TSC_SEL 0x01 /* Select Without ATN Sequence */
186 #define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */
187 #define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */
188 #define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */
189 #define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */
190 #define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */
192 #define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */
193 #define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */
194 #define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */
195 #define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */
196 #define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Infomation out */
197 #define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Infomation in */
199 #define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Infomation out */
200 #define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Infomation in */
201 #define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Infomation out */
202 #define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Infomation in */
204 #define TSC_MSG_ACCEPT 0x0F /* Message Accept */
206 /*----------------------------------------------------------------------*/
207 /* bit definition for Tulip SCSI Control 0 Register */
208 /*----------------------------------------------------------------------*/
209 #define TSC_RST_SEQ 0x20 /* Reset sequence counter */
210 #define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */
211 #define TSC_ABT_CMD 0x04 /* Abort command (sequence) */
212 #define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */
213 #define TSC_RST_BUS 0x01 /* Reset SCSI Bus */
215 /*----------------------------------------------------------------------*/
216 /* bit definition for Tulip SCSI Control 1 Register */
217 /*----------------------------------------------------------------------*/
218 #define TSC_EN_SCAM 0x80 /* Enable SCAM */
219 #define TSC_TIMER 0x40 /* Select timeout unit */
220 #define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */
221 #define TSC_PWDN 0x10 /* Power down mode */
222 #define TSC_WIDE_CPU 0x08 /* Wide CPU */
223 #define TSC_HW_RESELECT 0x04 /* Enable HW reselect */
224 #define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */
225 #define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */
227 /*----------------------------------------------------------------------*/
228 /* bit definition for Tulip SCSI Configuration Register */
229 /*----------------------------------------------------------------------*/
230 #define TSC_EN_LATCH 0x80 /* Enable phase latch */
231 #define TSC_INITIATOR 0x40 /* Initiator mode */
232 #define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */
233 #define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */
234 #define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */
235 #define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */
236 #define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */
237 #define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */
239 #define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST)
241 #define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */
243 /*----------------------------------------------------------------------*/
244 /* bit definition for Tulip SCSI signal Register */
245 /*----------------------------------------------------------------------*/
246 #define TSC_RST_ACK 0x00 /* Release ACK signal */
247 #define TSC_RST_ATN 0x00 /* Release ATN signal */
248 #define TSC_RST_BSY 0x00 /* Release BSY signal */
250 #define TSC_SET_ACK 0x40 /* ACK signal */
251 #define TSC_SET_ATN 0x08 /* ATN signal */
253 #define TSC_REQI 0x80 /* REQ signal */
254 #define TSC_ACKI 0x40 /* ACK signal */
255 #define TSC_BSYI 0x20 /* BSY signal */
256 #define TSC_SELI 0x10 /* SEL signal */
257 #define TSC_ATNI 0x08 /* ATN signal */
258 #define TSC_MSGI 0x04 /* MSG signal */
259 #define TSC_CDI 0x02 /* C/D signal */
260 #define TSC_IOI 0x01 /* I/O signal */
263 /*----------------------------------------------------------------------*/
264 /* bit definition for Tulip SCSI Status 0 Register */
265 /*----------------------------------------------------------------------*/
266 #define TSS_INT_PENDING 0x80 /* Interrupt pending */
267 #define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */
268 #define TSS_XFER_CNT 0x20 /* Transfer counter zero */
269 #define TSS_FIFO_EMPTY 0x10 /* FIFO empty */
270 #define TSS_PAR_ERROR 0x08 /* SCSI parity error */
271 #define TSS_PH_MASK 0x07 /* SCSI phase mask */
273 /*----------------------------------------------------------------------*/
274 /* bit definition for Tulip SCSI Status 1 Register */
275 /*----------------------------------------------------------------------*/
276 #define TSS_STATUS_RCV 0x08 /* Status received */
277 #define TSS_MSG_SEND 0x40 /* Message sent */
278 #define TSS_CMD_PH_CMP 0x20 /* command phase done */
279 #define TSS_DATA_PH_CMP 0x10 /* Data phase done */
280 #define TSS_STATUS_SEND 0x08 /* Status sent */
281 #define TSS_XFER_CMP 0x04 /* Transfer completed */
282 #define TSS_SEL_CMP 0x02 /* Selection completed */
283 #define TSS_ARB_CMP 0x01 /* Arbitration completed */
285 /*----------------------------------------------------------------------*/
286 /* bit definition for Tulip SCSI Status 2 Register */
287 /*----------------------------------------------------------------------*/
288 #define TSS_CMD_ABTED 0x80 /* Command aborted */
289 #define TSS_OFFSET_0 0x40 /* Offset counter zero */
290 #define TSS_FIFO_FULL 0x20 /* FIFO full */
291 #define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */
292 #define TSS_BUSY_RLS 0x08 /* Busy release */
293 #define TSS_PH_MISMATCH 0x04 /* Phase mismatch */
294 #define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */
295 #define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */
297 /*----------------------------------------------------------------------*/
298 /* bit definition for Tulip SCSI Interrupt Register */
299 /*----------------------------------------------------------------------*/
300 #define TSS_RESEL_INT 0x80 /* Reselected interrupt */
301 #define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */
302 #define TSS_BUS_SERV 0x20
303 #define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */
304 #define TSS_DISC_INT 0x08 /* Disconnected interrupt */
305 #define TSS_SEL_INT 0x04 /* Select interrupt */
306 #define TSS_SCAM_SEL 0x02 /* SCAM selected */
307 #define TSS_FUNC_COMP 0x01
309 /*----------------------------------------------------------------------*/
310 /* SCSI Phase Codes. */
311 /*----------------------------------------------------------------------*/
313 #define DATA_IN 1 /* 4 */
315 #define STATUS_IN 3 /* 6 */
316 #define MSG_OUT 6 /* 3 */
321 /*----------------------------------------------------------------------*/
322 /* Command Codes of Tulip xfer Command register */
323 /*----------------------------------------------------------------------*/
324 #define TAX_X_FORC 0x02
325 #define TAX_X_ABT 0x04
326 #define TAX_X_CLR_FIFO 0x08
328 #define TAX_X_IN 0x21
329 #define TAX_X_OUT 0x01
330 #define TAX_SG_IN 0xA1
331 #define TAX_SG_OUT 0x81
333 /*----------------------------------------------------------------------*/
334 /* Tulip Interrupt Register */
335 /*----------------------------------------------------------------------*/
343 /*----------------------------------------------------------------------*/
344 /* Tulip DMA Status Register */
345 /*----------------------------------------------------------------------*/
346 #define XPEND 0x01 /* Transfer pending */
347 #define FEMPTY 0x02 /* FIFO empty */
351 /*----------------------------------------------------------------------*/
352 /* bit definition for TUL_GCTRL */
353 /*----------------------------------------------------------------------*/
360 /*----------------------------------------------------------------------*/
361 /* bit definition for TUL_NVRAM */
362 /*----------------------------------------------------------------------*/
369 /************************************************************************/
370 /* Scatter-Gather Element Structure */
371 /************************************************************************/
372 typedef struct SG_Struc
{
373 U32 SG_Ptr
; /* Data Pointer */
374 U32 SG_Len
; /* Data Length */
377 /***********************************************************************
379 ************************************************************************/
380 typedef struct Scsi_Ctrl_Blk
{
381 struct Scsi_Ctrl_Blk
*SCB_NxtScb
;
382 UBYTE SCB_Status
; /*4 */
383 UBYTE SCB_NxtStat
; /*5 */
384 UBYTE SCB_Mode
; /*6 */
385 UBYTE SCB_Msgin
; /*7 SCB_Res0 */
386 UWORD SCB_SGIdx
; /*8 */
387 UWORD SCB_SGMax
; /*A */
389 U32 SCB_Reserved
[2]; /*C */
391 U32 SCB_Reserved
[3]; /*C */
394 U32 SCB_XferLen
; /*18 Current xfer len */
395 U32 SCB_TotXLen
; /*1C Total xfer len */
396 U32 SCB_PAddr
; /*20 SCB phy. Addr. */
398 UBYTE SCB_Opcode
; /*24 SCB command code */
399 UBYTE SCB_Flags
; /*25 SCB Flags */
400 UBYTE SCB_Target
; /*26 Target Id */
401 UBYTE SCB_Lun
; /*27 Lun */
402 U32 SCB_BufPtr
; /*28 Data Buffer Pointer */
403 U32 SCB_BufLen
; /*2C Data Allocation Length */
404 UBYTE SCB_SGLen
; /*30 SG list # */
405 UBYTE SCB_SenseLen
; /*31 Sense Allocation Length */
406 UBYTE SCB_HaStat
; /*32 */
407 UBYTE SCB_TaStat
; /*33 */
408 UBYTE SCB_CDBLen
; /*34 CDB Length */
409 UBYTE SCB_Ident
; /*35 Identify */
410 UBYTE SCB_TagMsg
; /*36 Tag Message */
411 UBYTE SCB_TagId
; /*37 Queue Tag */
412 UBYTE SCB_CDB
[12]; /*38 */
413 U32 SCB_SGPAddr
; /*44 SG List/Sense Buf phy. Addr. */
414 U32 SCB_SensePtr
; /*48 Sense data pointer */
415 void (*SCB_Post
) (BYTE
*, BYTE
*); /*4C POST routine */
416 struct scsi_cmnd
*SCB_Srb
; /*50 SRB Pointer */
417 SG SCB_SGList
[TOTAL_SG_ENTRY
]; /*54 Start of SG list */
420 /* Bit Definition for SCB_Status */
421 #define SCB_RENT 0x01
422 #define SCB_PEND 0x02
423 #define SCB_CONTIG 0x04 /* Contigent Allegiance */
424 #define SCB_SELECT 0x08
425 #define SCB_BUSY 0x10
426 #define SCB_DONE 0x20
429 /* Opcodes of SCB_Opcode */
431 #define BusDevRst 0x2
435 /* Bit Definition for SCB_Mode */
436 #define SCM_RSENS 0x01 /* request sense mode */
439 /* Bit Definition for SCB_Flags */
440 #define SCF_DONE 0x01
441 #define SCF_POST 0x02
442 #define SCF_SENSE 0x04
444 #define SCF_NO_DCHK 0x00
446 #define SCF_DOUT 0x10
447 #define SCF_NO_XF 0x18
448 #define SCF_WR_VF 0x20 /* Write verify turn on */
449 #define SCF_POLL 0x40
452 /* Error Codes for SCB_HaStat */
453 #define HOST_SEL_TOUT 0x11
454 #define HOST_DO_DU 0x12
455 #define HOST_BUS_FREE 0x13
456 #define HOST_BAD_PHAS 0x14
457 #define HOST_INV_CMD 0x16
458 #define HOST_ABORTED 0x1A /* 07/21/98 */
459 #define HOST_SCSI_RST 0x1B
460 #define HOST_DEV_RST 0x1C
462 /* Error Codes for SCB_TaStat */
463 #define TARGET_CHKCOND 0x02
464 #define TARGET_BUSY 0x08
465 #define INI_QUEUE_FULL 0x28
468 #define MSG_COMP 0x00
469 #define MSG_EXTEND 0x01
471 #define MSG_RESTORE 0x03
472 #define MSG_DISC 0x04
474 #define MSG_ABORT 0x06
477 #define MSG_PARITY 0x09
478 #define MSG_LINK_COMP 0x0A
479 #define MSG_LINK_FLAG 0x0B
480 #define MSG_DEVRST 0x0C
481 #define MSG_ABORT_TAG 0x0D
483 /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
484 #define MSG_STAG 0x20
485 #define MSG_HTAG 0x21
486 #define MSG_OTAG 0x22
488 #define MSG_IGNOREWIDE 0x23
490 #define MSG_IDENT 0x80
492 /***********************************************************************
493 Target Device Control Structure
494 **********************************************************************/
496 typedef struct Tar_Ctrl_Struc
{
497 UWORD TCS_Flags
; /* 0 */
498 UBYTE TCS_JS_Period
; /* 2 */
499 UBYTE TCS_SConfig0
; /* 3 */
501 UWORD TCS_DrvFlags
; /* 4 */
502 UBYTE TCS_DrvHead
; /* 6 */
503 UBYTE TCS_DrvSector
; /* 7 */
506 /***********************************************************************
507 Target Device Control Structure
508 **********************************************************************/
510 /* Bit Definition for TCF_Flags */
511 #define TCF_SCSI_RATE 0x0007
512 #define TCF_EN_DISC 0x0008
513 #define TCF_NO_SYNC_NEGO 0x0010
514 #define TCF_NO_WDTR 0x0020
515 #define TCF_EN_255 0x0040
516 #define TCF_EN_START 0x0080
517 #define TCF_WDTR_DONE 0x0100
518 #define TCF_SYNC_DONE 0x0200
519 #define TCF_BUSY 0x0400
522 /* Bit Definition for TCF_DrvFlags */
523 #define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */
524 #define TCF_DRV_EN_TAG 0x0800
525 #define TCF_DRV_255_63 0x0400
527 typedef struct I91u_Adpt_Struc
{
528 UWORD ADPT_BIOS
; /* 0 */
529 UWORD ADPT_BASE
; /* 1 */
530 UBYTE ADPT_Bus
; /* 2 */
531 UBYTE ADPT_Device
; /* 3 */
532 UBYTE ADPT_INTR
; /* 4 */
536 /***********************************************************************
537 Host Adapter Control Structure
538 ************************************************************************/
539 typedef struct Ha_Ctrl_Struc
{
540 UWORD HCS_Base
; /* 00 */
541 UWORD HCS_BIOS
; /* 02 */
542 UBYTE HCS_Intr
; /* 04 */
543 UBYTE HCS_SCSI_ID
; /* 05 */
544 UBYTE HCS_MaxTar
; /* 06 */
545 UBYTE HCS_NumScbs
; /* 07 */
547 UBYTE HCS_Flags
; /* 08 */
548 UBYTE HCS_Index
; /* 09 */
549 UBYTE HCS_HaId
; /* 0A */
550 UBYTE HCS_Config
; /* 0B */
551 UWORD HCS_IdMask
; /* 0C */
552 UBYTE HCS_Semaph
; /* 0E */
553 UBYTE HCS_Phase
; /* 0F */
554 UBYTE HCS_JSStatus0
; /* 10 */
555 UBYTE HCS_JSInt
; /* 11 */
556 UBYTE HCS_JSStatus1
; /* 12 */
557 UBYTE HCS_SConf1
; /* 13 */
559 UBYTE HCS_Msg
[8]; /* 14 */
560 SCB
*HCS_NxtAvail
; /* 1C */
561 SCB
*HCS_Scb
; /* 20 */
562 SCB
*HCS_ScbEnd
; /* 24 */
563 SCB
*HCS_NxtPend
; /* 28 */
564 SCB
*HCS_NxtContig
; /* 2C */
565 SCB
*HCS_ActScb
; /* 30 */
566 TCS
*HCS_ActTcs
; /* 34 */
568 SCB
*HCS_FirstAvail
; /* 38 */
569 SCB
*HCS_LastAvail
; /* 3C */
570 SCB
*HCS_FirstPend
; /* 40 */
571 SCB
*HCS_LastPend
; /* 44 */
572 SCB
*HCS_FirstBusy
; /* 48 */
573 SCB
*HCS_LastBusy
; /* 4C */
574 SCB
*HCS_FirstDone
; /* 50 */
575 SCB
*HCS_LastDone
; /* 54 */
576 UBYTE HCS_MaxTags
[16]; /* 58 */
577 UBYTE HCS_ActTags
[16]; /* 68 */
578 TCS HCS_Tcs
[MAX_TARGETS
]; /* 78 */
579 spinlock_t HCS_AvailLock
;
580 spinlock_t HCS_SemaphLock
;
581 struct pci_dev
*pci_dev
;
584 /* Bit Definition for HCB_Config */
585 #define HCC_SCSI_RESET 0x01
586 #define HCC_EN_PAR 0x02
587 #define HCC_ACT_TERM1 0x04
588 #define HCC_ACT_TERM2 0x08
589 #define HCC_AUTO_TERM 0x10
590 #define HCC_EN_PWR 0x80
592 /* Bit Definition for HCB_Flags */
593 #define HCF_EXPECT_DISC 0x01
594 #define HCF_EXPECT_SELECT 0x02
595 #define HCF_EXPECT_RESET 0x10
596 #define HCF_EXPECT_DONE_DISC 0x20
598 /******************************************************************
600 *******************************************************************/
602 typedef struct _NVRAM_SCSI
{ /* SCSI channel configuration */
603 UCHAR NVM_ChSCSIID
; /* 0Ch -> Channel SCSI ID */
604 UCHAR NVM_ChConfig1
; /* 0Dh -> Channel config 1 */
605 UCHAR NVM_ChConfig2
; /* 0Eh -> Channel config 2 */
606 UCHAR NVM_NumOfTarg
; /* 0Fh -> Number of SCSI target */
607 /* SCSI target configuration */
608 UCHAR NVM_Targ0Config
; /* 10h -> Target 0 configuration */
609 UCHAR NVM_Targ1Config
; /* 11h -> Target 1 configuration */
610 UCHAR NVM_Targ2Config
; /* 12h -> Target 2 configuration */
611 UCHAR NVM_Targ3Config
; /* 13h -> Target 3 configuration */
612 UCHAR NVM_Targ4Config
; /* 14h -> Target 4 configuration */
613 UCHAR NVM_Targ5Config
; /* 15h -> Target 5 configuration */
614 UCHAR NVM_Targ6Config
; /* 16h -> Target 6 configuration */
615 UCHAR NVM_Targ7Config
; /* 17h -> Target 7 configuration */
616 UCHAR NVM_Targ8Config
; /* 18h -> Target 8 configuration */
617 UCHAR NVM_Targ9Config
; /* 19h -> Target 9 configuration */
618 UCHAR NVM_TargAConfig
; /* 1Ah -> Target A configuration */
619 UCHAR NVM_TargBConfig
; /* 1Bh -> Target B configuration */
620 UCHAR NVM_TargCConfig
; /* 1Ch -> Target C configuration */
621 UCHAR NVM_TargDConfig
; /* 1Dh -> Target D configuration */
622 UCHAR NVM_TargEConfig
; /* 1Eh -> Target E configuration */
623 UCHAR NVM_TargFConfig
; /* 1Fh -> Target F configuration */
626 typedef struct _NVRAM
{
627 /*----------header ---------------*/
628 USHORT NVM_Signature
; /* 0,1: Signature */
629 UCHAR NVM_Size
; /* 2: Size of data structure */
630 UCHAR NVM_Revision
; /* 3: Revision of data structure */
631 /* ----Host Adapter Structure ---- */
632 UCHAR NVM_ModelByte0
; /* 4: Model number (byte 0) */
633 UCHAR NVM_ModelByte1
; /* 5: Model number (byte 1) */
634 UCHAR NVM_ModelInfo
; /* 6: Model information */
635 UCHAR NVM_NumOfCh
; /* 7: Number of SCSI channel */
636 UCHAR NVM_BIOSConfig1
; /* 8: BIOS configuration 1 */
637 UCHAR NVM_BIOSConfig2
; /* 9: BIOS configuration 2 */
638 UCHAR NVM_HAConfig1
; /* A: Hoat adapter configuration 1 */
639 UCHAR NVM_HAConfig2
; /* B: Hoat adapter configuration 2 */
640 NVRAM_SCSI NVM_SCSIInfo
[2];
641 UCHAR NVM_reserved
[10];
642 /* ---------- CheckSum ---------- */
643 USHORT NVM_CheckSum
; /* 0x3E, 0x3F: Checksum of NVRam */
646 /* Bios Configuration for nvram->BIOSConfig1 */
647 #define NBC1_ENABLE 0x01 /* BIOS enable */
648 #define NBC1_8DRIVE 0x02 /* Support more than 2 drives */
649 #define NBC1_REMOVABLE 0x04 /* Support removable drive */
650 #define NBC1_INT19 0x08 /* Intercept int 19h */
651 #define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */
652 #define NBC1_LUNSUPPORT 0x40 /* Support LUN */
654 /* HA Configuration Byte 1 */
655 #define NHC1_BOOTIDMASK 0x0F /* Boot ID number */
656 #define NHC1_LUNMASK 0x70 /* Boot LUN number */
657 #define NHC1_CHANMASK 0x80 /* Boot Channel number */
659 /* Bit definition for nvram->SCSIconfig1 */
660 #define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */
661 #define NCC1_PARITYCHK 0x02 /* SCSI parity enable */
662 #define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */
663 #define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */
664 #define NCC1_AUTOTERM 0x10 /* Enable auto terminator */
665 #define NCC1_PWRMGR 0x80 /* Enable power management */
667 /* Bit definition for SCSI Target configuration byte */
668 #define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */
669 #define NTC_SYNC 0x10 /* SYNC_NEGO */
670 #define NTC_NO_WDTR 0x20 /* SYNC_NEGO */
671 #define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */
672 #define NTC_SPINUP 0x80 /* Start disk drive */
674 /* Default NVRam values */
675 #define INI_SIGNATURE 0xC925
676 #define NBC1_DEFAULT (NBC1_ENABLE)
677 #define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK)
678 #define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT)
680 /* SCSI related definition */
681 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
682 #define DISC_ALLOW 0xC0 /* Disconnect is allowed */
683 #define SCSICMD_RequestSense 0x03
685 typedef struct _HCSinfo
{
688 UCHAR bios
; /* High byte of BIOS address */
689 USHORT BaseAndBios
; /* high byte: pHcsInfo->bios,low byte:pHcsInfo->base */
692 #define TUL_RD(x,y) (UCHAR)(inb( (int)((ULONG)(x+y)) ))
693 #define TUL_RDLONG(x,y) (ULONG)(inl((int)((ULONG)(x+y)) ))
694 #define TUL_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
695 #define TUL_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
696 #define TUL_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
698 #define SCSI_ABORT_SNOOZE 0
699 #define SCSI_ABORT_SUCCESS 1
700 #define SCSI_ABORT_PENDING 2
701 #define SCSI_ABORT_BUSY 3
702 #define SCSI_ABORT_NOT_RUNNING 4
703 #define SCSI_ABORT_ERROR 5
705 #define SCSI_RESET_SNOOZE 0
706 #define SCSI_RESET_PUNT 1
707 #define SCSI_RESET_SUCCESS 2
708 #define SCSI_RESET_PENDING 3
709 #define SCSI_RESET_WAKEUP 4
710 #define SCSI_RESET_NOT_RUNNING 5
711 #define SCSI_RESET_ERROR 6
713 #define SCSI_RESET_SYNCHRONOUS 0x01
714 #define SCSI_RESET_ASYNCHRONOUS 0x02
715 #define SCSI_RESET_SUGGEST_BUS_RESET 0x04
716 #define SCSI_RESET_SUGGEST_HOST_RESET 0x08
718 #define SCSI_RESET_BUS_RESET 0x100
719 #define SCSI_RESET_HOST_RESET 0x200
720 #define SCSI_RESET_ACTION 0xff
722 extern void init_i91uAdapter_table(void);
723 extern int Addi91u_into_Adapter_table(WORD
, WORD
, BYTE
, BYTE
, BYTE
);
724 extern int tul_ReturnNumberOfAdapters(void);
725 extern void get_tulipPCIConfig(HCS
* pHCB
, int iChannel_index
);
726 extern int init_tulip(HCS
* pHCB
, SCB
* pSCB
, int tul_num_scb
, BYTE
* pbBiosAdr
, int reset_time
);
727 extern SCB
*tul_alloc_scb(HCS
* pHCB
);
728 extern int tul_abort_srb(HCS
* pHCB
, struct scsi_cmnd
* pSRB
);
729 extern void tul_exec_scb(HCS
* pHCB
, SCB
* pSCB
);
730 extern void tul_release_scb(HCS
* pHCB
, SCB
* pSCB
);
731 extern void tul_stop_bm(HCS
* pHCB
);
732 extern int tul_reset_scsi(HCS
* pCurHcb
, int seconds
);
733 extern int tul_isr(HCS
* pHCB
);
734 extern int tul_reset(HCS
* pHCB
, struct scsi_cmnd
* pSRB
, unsigned char target
);
735 extern int tul_reset_scsi_bus(HCS
* pCurHcb
);
736 extern int tul_device_reset(HCS
* pCurHcb
, struct scsi_cmnd
*pSrb
,
737 unsigned int target
, unsigned int ResetFlags
);
738 /* ---- EXTERNAL VARIABLES ---- */
739 extern HCS tul_hcs
[];
projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / blob