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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / gdth.c
1 /************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
8 * Copyright (C) 2002-04 Intel Corporation *
9 * Copyright (C) 2003-06 Adaptec Inc. *
10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
30 * Linux kernel 2.4.x, 2.6.x supported *
31 * *
32 * $Log: gdth.c,v $
33 * Revision 1.74 2006/04/10 13:44:47 achim
34 * Community changes for 2.6.x
35 * Kernel 2.2.x no longer supported
36 * scsi_request interface removed, thanks to Christoph Hellwig
37 *
38 * Revision 1.73 2004/03/31 13:33:03 achim
39 * Special command 0xfd implemented to detect 64-bit DMA support
40 *
41 * Revision 1.72 2004/03/17 08:56:04 achim
42 * 64-bit DMA only enabled if FW >= x.43
43 *
44 * Revision 1.71 2004/03/05 15:51:29 achim
45 * Screen service: separate message buffer, bugfixes
46 *
47 * Revision 1.70 2004/02/27 12:19:07 achim
48 * Bugfix: Reset bit in config (0xfe) call removed
49 *
50 * Revision 1.69 2004/02/20 09:50:24 achim
51 * Compatibility changes for kernels < 2.4.20
52 * Bugfix screen service command size
53 * pci_set_dma_mask() error handling added
54 *
55 * Revision 1.68 2004/02/19 15:46:54 achim
56 * 64-bit DMA bugfixes
57 * Drive size bugfix for drives > 1TB
58 *
59 * Revision 1.67 2004/01/14 13:11:57 achim
60 * Tool access over /proc no longer supported
61 * Bugfixes IOCTLs
62 *
63 * Revision 1.66 2003/12/19 15:04:06 achim
64 * Bugfixes support for drives > 2TB
65 *
66 * Revision 1.65 2003/12/15 11:21:56 achim
67 * 64-bit DMA support added
68 * Support for drives > 2 TB implemented
69 * Kernels 2.2.x, 2.4.x, 2.6.x supported
70 *
71 * Revision 1.64 2003/09/17 08:30:26 achim
72 * EISA/ISA controller scan disabled
73 * Command line switch probe_eisa_isa added
74 *
75 * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
76 * Minor cleanups in gdth_ioctl.
77 *
78 * Revision 1.62 2003/02/27 15:01:59 achim
79 * Dynamic DMA mapping implemented
80 * New (character device) IOCTL interface added
81 * Other controller related changes made
82 *
83 * Revision 1.61 2002/11/08 13:09:52 boji
84 * Added support for XSCALE based RAID Controllers
85 * Fixed SCREENSERVICE initialization in SMP cases
86 * Added checks for gdth_polling before GDTH_HA_LOCK
87 *
88 * Revision 1.60 2002/02/05 09:35:22 achim
89 * MODULE_LICENSE only if kernel >= 2.4.11
90 *
91 * Revision 1.59 2002/01/30 09:46:33 achim
92 * Small changes
93 *
94 * Revision 1.58 2002/01/29 15:30:02 achim
95 * Set default value of shared_access to Y
96 * New status S_CACHE_RESERV for clustering added
97 *
98 * Revision 1.57 2001/08/21 11:16:35 achim
99 * Bugfix free_irq()
100 *
101 * Revision 1.56 2001/08/09 11:19:39 achim
102 * Scsi_Host_Template changes
103 *
104 * Revision 1.55 2001/08/09 10:11:28 achim
105 * Command HOST_UNFREEZE_IO before cache service init.
106 *
107 * Revision 1.54 2001/07/20 13:48:12 achim
108 * Expand: gdth_analyse_hdrive() removed
109 *
110 * Revision 1.53 2001/07/17 09:52:49 achim
111 * Small OEM related change
112 *
113 * Revision 1.52 2001/06/19 15:06:20 achim
114 * New host command GDT_UNFREEZE_IO added
115 *
116 * Revision 1.51 2001/05/22 06:42:37 achim
117 * PCI: Subdevice ID added
118 *
119 * Revision 1.50 2001/05/17 13:42:16 achim
120 * Support for Intel Storage RAID Controllers added
121 *
122 * Revision 1.50 2001/05/17 12:12:34 achim
123 * Support for Intel Storage RAID Controllers added
124 *
125 * Revision 1.49 2001/03/15 15:07:17 achim
126 * New __setup interface for boot command line options added
127 *
128 * Revision 1.48 2001/02/06 12:36:28 achim
129 * Bugfix Cluster protocol
130 *
131 * Revision 1.47 2001/01/10 14:42:06 achim
132 * New switch shared_access added
133 *
134 * Revision 1.46 2001/01/09 08:11:35 achim
135 * gdth_command() removed
136 * meaning of Scsi_Pointer members changed
137 *
138 * Revision 1.45 2000/11/16 12:02:24 achim
139 * Changes for kernel 2.4
140 *
141 * Revision 1.44 2000/10/11 08:44:10 achim
142 * Clustering changes: New flag media_changed added
143 *
144 * Revision 1.43 2000/09/20 12:59:01 achim
145 * DPMEM remap functions for all PCI controller types implemented
146 * Small changes for ia64 platform
147 *
148 * Revision 1.42 2000/07/20 09:04:50 achim
149 * Small changes for kernel 2.4
150 *
151 * Revision 1.41 2000/07/04 14:11:11 achim
152 * gdth_analyse_hdrive() added to rescan drives after online expansion
153 *
154 * Revision 1.40 2000/06/27 11:24:16 achim
155 * Changes Clustering, Screenservice
156 *
157 * Revision 1.39 2000/06/15 13:09:04 achim
158 * Changes for gdth_do_cmd()
159 *
160 * Revision 1.38 2000/06/15 12:08:43 achim
161 * Bugfix gdth_sync_event(), service SCREENSERVICE
162 * Data direction for command 0xc2 changed to DOU
163 *
164 * Revision 1.37 2000/05/25 13:50:10 achim
165 * New driver parameter virt_ctr added
166 *
167 * Revision 1.36 2000/05/04 08:50:46 achim
168 * Event buffer now in gdth_ha_str
169 *
170 * Revision 1.35 2000/03/03 10:44:08 achim
171 * New event_string only valid for the RP controller family
172 *
173 * Revision 1.34 2000/03/02 14:55:29 achim
174 * New mechanism for async. event handling implemented
175 *
176 * Revision 1.33 2000/02/21 15:37:37 achim
177 * Bugfix Alpha platform + DPMEM above 4GB
178 *
179 * Revision 1.32 2000/02/14 16:17:37 achim
180 * Bugfix sense_buffer[] + raw devices
181 *
182 * Revision 1.31 2000/02/10 10:29:00 achim
183 * Delete sense_buffer[0], if command OK
184 *
185 * Revision 1.30 1999/11/02 13:42:39 achim
186 * ARRAY_DRV_LIST2 implemented
187 * Now 255 log. and 100 host drives supported
188 *
189 * Revision 1.29 1999/10/05 13:28:47 achim
190 * GDT_CLUST_RESET added
191 *
192 * Revision 1.28 1999/08/12 13:44:54 achim
193 * MOUNTALL removed
194 * Cluster drives -> removeable drives
195 *
196 * Revision 1.27 1999/06/22 07:22:38 achim
197 * Small changes
198 *
199 * Revision 1.26 1999/06/10 16:09:12 achim
200 * Cluster Host Drive support: Bugfixes
201 *
202 * Revision 1.25 1999/06/01 16:03:56 achim
203 * gdth_init_pci(): Manipulate config. space to start RP controller
204 *
205 * Revision 1.24 1999/05/26 11:53:06 achim
206 * Cluster Host Drive support added
207 *
208 * Revision 1.23 1999/03/26 09:12:31 achim
209 * Default value for hdr_channel set to 0
210 *
211 * Revision 1.22 1999/03/22 16:27:16 achim
212 * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
213 *
214 * Revision 1.21 1999/03/16 13:40:34 achim
215 * Problems with reserved drives solved
216 * gdth_eh_bus_reset() implemented
217 *
218 * Revision 1.20 1999/03/10 09:08:13 achim
219 * Bugfix: Corrections in gdth_direction_tab[] made
220 * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
221 *
222 * Revision 1.19 1999/03/05 14:38:16 achim
223 * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
224 * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
225 * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
226 * with BIOS disabled and memory test set to Intensive
227 * Enhanced /proc support
228 *
229 * Revision 1.18 1999/02/24 09:54:33 achim
230 * Command line parameter hdr_channel implemented
231 * Bugfix for EISA controllers + Linux 2.2.x
232 *
233 * Revision 1.17 1998/12/17 15:58:11 achim
234 * Command line parameters implemented
235 * Changes for Alpha platforms
236 * PCI controller scan changed
237 * SMP support improved (spin_lock_irqsave(),...)
238 * New async. events, new scan/reserve commands included
239 *
240 * Revision 1.16 1998/09/28 16:08:46 achim
241 * GDT_PCIMPR: DPMEM remapping, if required
242 * mdelay() added
243 *
244 * Revision 1.15 1998/06/03 14:54:06 achim
245 * gdth_delay(), gdth_flush() implemented
246 * Bugfix: gdth_release() changed
247 *
248 * Revision 1.14 1998/05/22 10:01:17 achim
249 * mj: pcibios_strerror() removed
250 * Improved SMP support (if version >= 2.1.95)
251 * gdth_halt(): halt_called flag added (if version < 2.1)
252 *
253 * Revision 1.13 1998/04/16 09:14:57 achim
254 * Reserve drives (for raw service) implemented
255 * New error handling code enabled
256 * Get controller name from board_info() IOCTL
257 * Final round of PCI device driver patches by Martin Mares
258 *
259 * Revision 1.12 1998/03/03 09:32:37 achim
260 * Fibre channel controller support added
261 *
262 * Revision 1.11 1998/01/27 16:19:14 achim
263 * SA_SHIRQ added
264 * add_timer()/del_timer() instead of GDTH_TIMER
265 * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
266 * New error handling included
267 *
268 * Revision 1.10 1997/10/31 12:29:57 achim
269 * Read heads/sectors from host drive
270 *
271 * Revision 1.9 1997/09/04 10:07:25 achim
272 * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
273 * register_reboot_notifier() to get a notify on shutown used
274 *
275 * Revision 1.8 1997/04/02 12:14:30 achim
276 * Version 1.00 (see gdth.h), tested with kernel 2.0.29
277 *
278 * Revision 1.7 1997/03/12 13:33:37 achim
279 * gdth_reset() changed, new async. events
280 *
281 * Revision 1.6 1997/03/04 14:01:11 achim
282 * Shutdown routine gdth_halt() implemented
283 *
284 * Revision 1.5 1997/02/21 09:08:36 achim
285 * New controller included (RP, RP1, RP2 series)
286 * IOCTL interface implemented
287 *
288 * Revision 1.4 1996/07/05 12:48:55 achim
289 * Function gdth_bios_param() implemented
290 * New constant GDTH_MAXC_P_L inserted
291 * GDT_WRITE_THR, GDT_EXT_INFO implemented
292 * Function gdth_reset() changed
293 *
294 * Revision 1.3 1996/05/10 09:04:41 achim
295 * Small changes for Linux 1.2.13
296 *
297 * Revision 1.2 1996/05/09 12:45:27 achim
298 * Loadable module support implemented
299 * /proc support corrections made
300 *
301 * Revision 1.1 1996/04/11 07:35:57 achim
302 * Initial revision
303 *
304 ************************************************************************/
305
306 /* All GDT Disk Array Controllers are fully supported by this driver.
307 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
308 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
309 * list of all controller types.
310 *
311 * If you have one or more GDT3000/3020 EISA controllers with
312 * controller BIOS disabled, you have to set the IRQ values with the
313 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
314 * the IRQ values for the EISA controllers.
315 *
316 * After the optional list of IRQ values, other possible
317 * command line options are:
318 * disable:Y disable driver
319 * disable:N enable driver
320 * reserve_mode:0 reserve no drives for the raw service
321 * reserve_mode:1 reserve all not init., removable drives
322 * reserve_mode:2 reserve all not init. drives
323 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
324 * h- controller no., b- channel no.,
325 * t- target ID, l- LUN
326 * reverse_scan:Y reverse scan order for PCI controllers
327 * reverse_scan:N scan PCI controllers like BIOS
328 * max_ids:x x - target ID count per channel (1..MAXID)
329 * rescan:Y rescan all channels/IDs
330 * rescan:N use all devices found until now
331 * virt_ctr:Y map every channel to a virtual controller
332 * virt_ctr:N use multi channel support
333 * hdr_channel:x x - number of virtual bus for host drives
334 * shared_access:Y disable driver reserve/release protocol to
335 * access a shared resource from several nodes,
336 * appropriate controller firmware required
337 * shared_access:N enable driver reserve/release protocol
338 * probe_eisa_isa:Y scan for EISA/ISA controllers
339 * probe_eisa_isa:N do not scan for EISA/ISA controllers
340 * force_dma32:Y use only 32 bit DMA mode
341 * force_dma32:N use 64 bit DMA mode, if supported
342 *
343 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
344 * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
345 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
346 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
347 *
348 * When loading the gdth driver as a module, the same options are available.
349 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
350 * options changes slightly. You must replace all ',' between options
351 * with ' ' and all ':' with '=' and you must use
352 * '1' in place of 'Y' and '0' in place of 'N'.
353 *
354 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
355 * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
356 * probe_eisa_isa=0 force_dma32=0"
357 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
358 */
359
360 /* The meaning of the Scsi_Pointer members in this driver is as follows:
361 * ptr: Chaining
362 * this_residual: Command priority
363 * buffer: phys. DMA sense buffer
364 * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
365 * buffers_residual: Timeout value
366 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
367 * Message: Additional info (gdth_do_cmd()), DMA direction
368 * have_data_in: Flag for gdth_wait_completion()
369 * sent_command: Opcode special command
370 * phase: Service/parameter/return code special command
371 */
372
373
374 /* interrupt coalescing */
375 /* #define INT_COAL */
376
377 /* statistics */
378 #define GDTH_STATISTICS
379
380 #include <linux/module.h>
381
382 #include <linux/version.h>
383 #include <linux/kernel.h>
384 #include <linux/types.h>
385 #include <linux/pci.h>
386 #include <linux/string.h>
387 #include <linux/ctype.h>
388 #include <linux/ioport.h>
389 #include <linux/delay.h>
390 #include <linux/sched.h>
391 #include <linux/interrupt.h>
392 #include <linux/in.h>
393 #include <linux/proc_fs.h>
394 #include <linux/time.h>
395 #include <linux/timer.h>
396 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
397 #include <linux/dma-mapping.h>
398 #else
399 #define DMA_32BIT_MASK 0x00000000ffffffffULL
400 #define DMA_64BIT_MASK 0xffffffffffffffffULL
401 #endif
402
403 #ifdef GDTH_RTC
404 #include <linux/mc146818rtc.h>
405 #endif
406 #include <linux/reboot.h>
407
408 #include <asm/dma.h>
409 #include <asm/system.h>
410 #include <asm/io.h>
411 #include <asm/uaccess.h>
412 #include <linux/spinlock.h>
413 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
414 #include <linux/blkdev.h>
415 #else
416 #include <linux/blk.h>
417 #include "sd.h"
418 #endif
419
420 #include "scsi.h"
421 #include <scsi/scsi_host.h>
422 #include "gdth_kcompat.h"
423 #include "gdth.h"
424
425 static void gdth_delay(int milliseconds);
426 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
427 static irqreturn_t gdth_interrupt(int irq, void *dev_id);
428 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
429 static int gdth_async_event(int hanum);
430 static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
431
432 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
433 static void gdth_next(int hanum);
434 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
435 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
436 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
437 ushort idx, gdth_evt_data *evt);
438 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
439 static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
440 gdth_evt_str *estr);
441 static void gdth_clear_events(void);
442
443 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
444 char *buffer,ushort count);
445 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
446 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
447
448 static int gdth_search_eisa(ushort eisa_adr);
449 static int gdth_search_isa(ulong32 bios_adr);
450 static int gdth_search_pci(gdth_pci_str *pcistr);
451 static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
452 ushort vendor, ushort dev);
453 static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
454 static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
455 static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
456 static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
457
458 static void gdth_enable_int(int hanum);
459 static int gdth_get_status(unchar *pIStatus,int irq);
460 static int gdth_test_busy(int hanum);
461 static int gdth_get_cmd_index(int hanum);
462 static void gdth_release_event(int hanum);
463 static int gdth_wait(int hanum,int index,ulong32 time);
464 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
465 ulong64 p2,ulong64 p3);
466 static int gdth_search_drives(int hanum);
467 static int gdth_analyse_hdrive(int hanum, ushort hdrive);
468
469 static const char *gdth_ctr_name(int hanum);
470
471 static int gdth_open(struct inode *inode, struct file *filep);
472 static int gdth_close(struct inode *inode, struct file *filep);
473 static int gdth_ioctl(struct inode *inode, struct file *filep,
474 unsigned int cmd, unsigned long arg);
475
476 static void gdth_flush(int hanum);
477 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
478 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
479 static void gdth_scsi_done(struct scsi_cmnd *scp);
480
481 #ifdef DEBUG_GDTH
482 static unchar DebugState = DEBUG_GDTH;
483
484 #ifdef __SERIAL__
485 #define MAX_SERBUF 160
486 static void ser_init(void);
487 static void ser_puts(char *str);
488 static void ser_putc(char c);
489 static int ser_printk(const char *fmt, ...);
490 static char strbuf[MAX_SERBUF+1];
491 #ifdef __COM2__
492 #define COM_BASE 0x2f8
493 #else
494 #define COM_BASE 0x3f8
495 #endif
496 static void ser_init()
497 {
498 unsigned port=COM_BASE;
499
500 outb(0x80,port+3);
501 outb(0,port+1);
502 /* 19200 Baud, if 9600: outb(12,port) */
503 outb(6, port);
504 outb(3,port+3);
505 outb(0,port+1);
506 /*
507 ser_putc('I');
508 ser_putc(' ');
509 */
510 }
511
512 static void ser_puts(char *str)
513 {
514 char *ptr;
515
516 ser_init();
517 for (ptr=str;*ptr;++ptr)
518 ser_putc(*ptr);
519 }
520
521 static void ser_putc(char c)
522 {
523 unsigned port=COM_BASE;
524
525 while ((inb(port+5) & 0x20)==0);
526 outb(c,port);
527 if (c==0x0a)
528 {
529 while ((inb(port+5) & 0x20)==0);
530 outb(0x0d,port);
531 }
532 }
533
534 static int ser_printk(const char *fmt, ...)
535 {
536 va_list args;
537 int i;
538
539 va_start(args,fmt);
540 i = vsprintf(strbuf,fmt,args);
541 ser_puts(strbuf);
542 va_end(args);
543 return i;
544 }
545
546 #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
547 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
548 #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
549
550 #else /* !__SERIAL__ */
551 #define TRACE(a) {if (DebugState==1) {printk a;}}
552 #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
553 #define TRACE3(a) {if (DebugState!=0) {printk a;}}
554 #endif
555
556 #else /* !DEBUG */
557 #define TRACE(a)
558 #define TRACE2(a)
559 #define TRACE3(a)
560 #endif
561
562 #ifdef GDTH_STATISTICS
563 static ulong32 max_rq=0, max_index=0, max_sg=0;
564 #ifdef INT_COAL
565 static ulong32 max_int_coal=0;
566 #endif
567 static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
568 static struct timer_list gdth_timer;
569 #endif
570
571 #define PTR2USHORT(a) (ushort)(ulong)(a)
572 #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
573 #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
574
575 #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
576 #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
577 #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
578
579 #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
580
581 #define gdth_readb(addr) readb(addr)
582 #define gdth_readw(addr) readw(addr)
583 #define gdth_readl(addr) readl(addr)
584 #define gdth_writeb(b,addr) writeb((b),(addr))
585 #define gdth_writew(b,addr) writew((b),(addr))
586 #define gdth_writel(b,addr) writel((b),(addr))
587
588 static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
589 static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
590 static unchar gdth_polling; /* polling if TRUE */
591 static unchar gdth_from_wait = FALSE; /* gdth_wait() */
592 static int wait_index,wait_hanum; /* gdth_wait() */
593 static int gdth_ctr_count = 0; /* controller count */
594 static int gdth_ctr_vcount = 0; /* virt. ctr. count */
595 static int gdth_ctr_released = 0; /* gdth_release() */
596 static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
597 static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
598 static unchar gdth_write_through = FALSE; /* write through */
599 static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
600 static int elastidx;
601 static int eoldidx;
602 static int major;
603
604 #define DIN 1 /* IN data direction */
605 #define DOU 2 /* OUT data direction */
606 #define DNO DIN /* no data transfer */
607 #define DUN DIN /* unknown data direction */
608 static unchar gdth_direction_tab[0x100] = {
609 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
610 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
611 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
612 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
613 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
614 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
615 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
616 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
617 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
618 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
619 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
620 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
621 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
622 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
623 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
624 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
625 };
626
627 /* LILO and modprobe/insmod parameters */
628 /* IRQ list for GDT3000/3020 EISA controllers */
629 static int irq[MAXHA] __initdata =
630 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
631 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
632 /* disable driver flag */
633 static int disable __initdata = 0;
634 /* reserve flag */
635 static int reserve_mode = 1;
636 /* reserve list */
637 static int reserve_list[MAX_RES_ARGS] =
638 {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
639 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
640 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
641 /* scan order for PCI controllers */
642 static int reverse_scan = 0;
643 /* virtual channel for the host drives */
644 static int hdr_channel = 0;
645 /* max. IDs per channel */
646 static int max_ids = MAXID;
647 /* rescan all IDs */
648 static int rescan = 0;
649 /* map channels to virtual controllers */
650 static int virt_ctr = 0;
651 /* shared access */
652 static int shared_access = 1;
653 /* enable support for EISA and ISA controllers */
654 static int probe_eisa_isa = 0;
655 /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
656 static int force_dma32 = 0;
657
658 /* parameters for modprobe/insmod */
659 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
660 module_param_array(irq, int, NULL, 0);
661 module_param(disable, int, 0);
662 module_param(reserve_mode, int, 0);
663 module_param_array(reserve_list, int, NULL, 0);
664 module_param(reverse_scan, int, 0);
665 module_param(hdr_channel, int, 0);
666 module_param(max_ids, int, 0);
667 module_param(rescan, int, 0);
668 module_param(virt_ctr, int, 0);
669 module_param(shared_access, int, 0);
670 module_param(probe_eisa_isa, int, 0);
671 module_param(force_dma32, int, 0);
672 #else
673 MODULE_PARM(irq, "i");
674 MODULE_PARM(disable, "i");
675 MODULE_PARM(reserve_mode, "i");
676 MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
677 MODULE_PARM(reverse_scan, "i");
678 MODULE_PARM(hdr_channel, "i");
679 MODULE_PARM(max_ids, "i");
680 MODULE_PARM(rescan, "i");
681 MODULE_PARM(virt_ctr, "i");
682 MODULE_PARM(shared_access, "i");
683 MODULE_PARM(probe_eisa_isa, "i");
684 MODULE_PARM(force_dma32, "i");
685 #endif
686 MODULE_AUTHOR("Achim Leubner");
687 MODULE_LICENSE("GPL");
688
689 /* ioctl interface */
690 static struct file_operations gdth_fops = {
691 .ioctl = gdth_ioctl,
692 .open = gdth_open,
693 .release = gdth_close,
694 };
695
696 #include "gdth_proc.h"
697 #include "gdth_proc.c"
698
699 /* notifier block to get a notify on system shutdown/halt/reboot */
700 static struct notifier_block gdth_notifier = {
701 gdth_halt, NULL, 0
702 };
703 static int notifier_disabled = 0;
704
705 static void gdth_delay(int milliseconds)
706 {
707 if (milliseconds == 0) {
708 udelay(1);
709 } else {
710 mdelay(milliseconds);
711 }
712 }
713
714 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
715 static void gdth_scsi_done(struct scsi_cmnd *scp)
716 {
717 TRACE2(("gdth_scsi_done()\n"));
718
719 if (scp->request)
720 complete((struct completion *)scp->request);
721 }
722
723 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
724 int timeout, u32 *info)
725 {
726 Scsi_Cmnd *scp;
727 DECLARE_COMPLETION_ONSTACK(wait);
728 int rval;
729
730 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
731 if (!scp)
732 return -ENOMEM;
733 memset(scp, 0, sizeof(*scp));
734 scp->device = sdev;
735 /* use request field to save the ptr. to completion struct. */
736 scp->request = (struct request *)&wait;
737 scp->timeout_per_command = timeout*HZ;
738 scp->request_buffer = gdtcmd;
739 scp->cmd_len = 12;
740 memcpy(scp->cmnd, cmnd, 12);
741 scp->SCp.this_residual = IOCTL_PRI; /* priority */
742 scp->done = gdth_scsi_done; /* some fn. test this */
743 gdth_queuecommand(scp, gdth_scsi_done);
744 wait_for_completion(&wait);
745
746 rval = scp->SCp.Status;
747 if (info)
748 *info = scp->SCp.Message;
749 kfree(scp);
750 return rval;
751 }
752 #else
753 static void gdth_scsi_done(Scsi_Cmnd *scp)
754 {
755 TRACE2(("gdth_scsi_done()\n"));
756
757 scp->request.rq_status = RQ_SCSI_DONE;
758 if (scp->request.waiting)
759 complete(scp->request.waiting);
760 }
761
762 int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
763 int timeout, u32 *info)
764 {
765 Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
766 unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
767 DECLARE_COMPLETION_ONSTACK(wait);
768 int rval;
769
770 if (!scp)
771 return -ENOMEM;
772 scp->cmd_len = 12;
773 scp->use_sg = 0;
774 scp->SCp.this_residual = IOCTL_PRI; /* priority */
775 scp->request.rq_status = RQ_SCSI_BUSY;
776 scp->request.waiting = &wait;
777 scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
778 wait_for_completion(&wait);
779
780 rval = scp->SCp.Status;
781 if (info)
782 *info = scp->SCp.Message;
783
784 scsi_release_command(scp);
785 return rval;
786 }
787 #endif
788
789 int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
790 int timeout, u32 *info)
791 {
792 struct scsi_device *sdev = scsi_get_host_dev(shost);
793 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
794
795 scsi_free_host_dev(sdev);
796 return rval;
797 }
798
799 static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
800 {
801 *cyls = size /HEADS/SECS;
802 if (*cyls <= MAXCYLS) {
803 *heads = HEADS;
804 *secs = SECS;
805 } else { /* too high for 64*32 */
806 *cyls = size /MEDHEADS/MEDSECS;
807 if (*cyls <= MAXCYLS) {
808 *heads = MEDHEADS;
809 *secs = MEDSECS;
810 } else { /* too high for 127*63 */
811 *cyls = size /BIGHEADS/BIGSECS;
812 *heads = BIGHEADS;
813 *secs = BIGSECS;
814 }
815 }
816 }
817
818 /* controller search and initialization functions */
819
820 static int __init gdth_search_eisa(ushort eisa_adr)
821 {
822 ulong32 id;
823
824 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
825 id = inl(eisa_adr+ID0REG);
826 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
827 if ((inb(eisa_adr+EISAREG) & 8) == 0)
828 return 0; /* not EISA configured */
829 return 1;
830 }
831 if (id == GDT3_ID) /* GDT3000 */
832 return 1;
833
834 return 0;
835 }
836
837
838 static int __init gdth_search_isa(ulong32 bios_adr)
839 {
840 void __iomem *addr;
841 ulong32 id;
842
843 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
844 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
845 id = gdth_readl(addr);
846 iounmap(addr);
847 if (id == GDT2_ID) /* GDT2000 */
848 return 1;
849 }
850 return 0;
851 }
852
853
854 static int __init gdth_search_pci(gdth_pci_str *pcistr)
855 {
856 ushort device, cnt;
857
858 TRACE(("gdth_search_pci()\n"));
859
860 cnt = 0;
861 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
862 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
863 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
864 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
865 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
866 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
867 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
868 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
869 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
870 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
871 PCI_DEVICE_ID_INTEL_SRC);
872 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
873 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
874 return cnt;
875 }
876
877 /* Vortex only makes RAID controllers.
878 * We do not really want to specify all 550 ids here, so wildcard match.
879 */
880 static struct pci_device_id gdthtable[] __attribute_used__ = {
881 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
882 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
883 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
884 {0}
885 };
886 MODULE_DEVICE_TABLE(pci,gdthtable);
887
888 static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
889 ushort vendor, ushort device)
890 {
891 ulong base0, base1, base2;
892 struct pci_dev *pdev;
893
894 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
895 *cnt, vendor, device));
896
897 pdev = NULL;
898 while ((pdev = pci_find_device(vendor, device, pdev))
899 != NULL) {
900 if (pci_enable_device(pdev))
901 continue;
902 if (*cnt >= MAXHA)
903 return;
904 /* GDT PCI controller found, resources are already in pdev */
905 pcistr[*cnt].pdev = pdev;
906 pcistr[*cnt].vendor_id = vendor;
907 pcistr[*cnt].device_id = device;
908 pcistr[*cnt].subdevice_id = pdev->subsystem_device;
909 pcistr[*cnt].bus = pdev->bus->number;
910 pcistr[*cnt].device_fn = pdev->devfn;
911 pcistr[*cnt].irq = pdev->irq;
912 base0 = pci_resource_flags(pdev, 0);
913 base1 = pci_resource_flags(pdev, 1);
914 base2 = pci_resource_flags(pdev, 2);
915 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
916 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
917 if (!(base0 & IORESOURCE_MEM))
918 continue;
919 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
920 } else { /* GDT6110, GDT6120, .. */
921 if (!(base0 & IORESOURCE_MEM) ||
922 !(base2 & IORESOURCE_MEM) ||
923 !(base1 & IORESOURCE_IO))
924 continue;
925 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
926 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
927 pcistr[*cnt].io = pci_resource_start(pdev, 1);
928 }
929 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
930 pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
931 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
932 (*cnt)++;
933 }
934 }
935
936
937 static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
938 {
939 gdth_pci_str temp;
940 int i, changed;
941
942 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
943 if (cnt == 0)
944 return;
945
946 do {
947 changed = FALSE;
948 for (i = 0; i < cnt-1; ++i) {
949 if (!reverse_scan) {
950 if ((pcistr[i].bus > pcistr[i+1].bus) ||
951 (pcistr[i].bus == pcistr[i+1].bus &&
952 PCI_SLOT(pcistr[i].device_fn) >
953 PCI_SLOT(pcistr[i+1].device_fn))) {
954 temp = pcistr[i];
955 pcistr[i] = pcistr[i+1];
956 pcistr[i+1] = temp;
957 changed = TRUE;
958 }
959 } else {
960 if ((pcistr[i].bus < pcistr[i+1].bus) ||
961 (pcistr[i].bus == pcistr[i+1].bus &&
962 PCI_SLOT(pcistr[i].device_fn) <
963 PCI_SLOT(pcistr[i+1].device_fn))) {
964 temp = pcistr[i];
965 pcistr[i] = pcistr[i+1];
966 pcistr[i+1] = temp;
967 changed = TRUE;
968 }
969 }
970 }
971 } while (changed);
972 }
973
974
975 static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
976 {
977 ulong32 retries,id;
978 unchar prot_ver,eisacf,i,irq_found;
979
980 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
981
982 /* disable board interrupts, deinitialize services */
983 outb(0xff,eisa_adr+EDOORREG);
984 outb(0x00,eisa_adr+EDENABREG);
985 outb(0x00,eisa_adr+EINTENABREG);
986
987 outb(0xff,eisa_adr+LDOORREG);
988 retries = INIT_RETRIES;
989 gdth_delay(20);
990 while (inb(eisa_adr+EDOORREG) != 0xff) {
991 if (--retries == 0) {
992 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
993 return 0;
994 }
995 gdth_delay(1);
996 TRACE2(("wait for DEINIT: retries=%d\n",retries));
997 }
998 prot_ver = inb(eisa_adr+MAILBOXREG);
999 outb(0xff,eisa_adr+EDOORREG);
1000 if (prot_ver != PROTOCOL_VERSION) {
1001 printk("GDT-EISA: Illegal protocol version\n");
1002 return 0;
1003 }
1004 ha->bmic = eisa_adr;
1005 ha->brd_phys = (ulong32)eisa_adr >> 12;
1006
1007 outl(0,eisa_adr+MAILBOXREG);
1008 outl(0,eisa_adr+MAILBOXREG+4);
1009 outl(0,eisa_adr+MAILBOXREG+8);
1010 outl(0,eisa_adr+MAILBOXREG+12);
1011
1012 /* detect IRQ */
1013 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
1014 ha->oem_id = OEM_ID_ICP;
1015 ha->type = GDT_EISA;
1016 ha->stype = id;
1017 outl(1,eisa_adr+MAILBOXREG+8);
1018 outb(0xfe,eisa_adr+LDOORREG);
1019 retries = INIT_RETRIES;
1020 gdth_delay(20);
1021 while (inb(eisa_adr+EDOORREG) != 0xfe) {
1022 if (--retries == 0) {
1023 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
1024 return 0;
1025 }
1026 gdth_delay(1);
1027 }
1028 ha->irq = inb(eisa_adr+MAILBOXREG);
1029 outb(0xff,eisa_adr+EDOORREG);
1030 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
1031 /* check the result */
1032 if (ha->irq == 0) {
1033 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
1034 for (i = 0, irq_found = FALSE;
1035 i < MAXHA && irq[i] != 0xff; ++i) {
1036 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
1037 irq_found = TRUE;
1038 break;
1039 }
1040 }
1041 if (irq_found) {
1042 ha->irq = irq[i];
1043 irq[i] = 0;
1044 printk("GDT-EISA: Can not detect controller IRQ,\n");
1045 printk("Use IRQ setting from command line (IRQ = %d)\n",
1046 ha->irq);
1047 } else {
1048 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
1049 printk("the controller BIOS or use command line parameters\n");
1050 return 0;
1051 }
1052 }
1053 } else {
1054 eisacf = inb(eisa_adr+EISAREG) & 7;
1055 if (eisacf > 4) /* level triggered */
1056 eisacf -= 4;
1057 ha->irq = gdth_irq_tab[eisacf];
1058 ha->oem_id = OEM_ID_ICP;
1059 ha->type = GDT_EISA;
1060 ha->stype = id;
1061 }
1062
1063 ha->dma64_support = 0;
1064 return 1;
1065 }
1066
1067
1068 static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
1069 {
1070 register gdt2_dpram_str __iomem *dp2_ptr;
1071 int i;
1072 unchar irq_drq,prot_ver;
1073 ulong32 retries;
1074
1075 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
1076
1077 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
1078 if (ha->brd == NULL) {
1079 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
1080 return 0;
1081 }
1082 dp2_ptr = ha->brd;
1083 gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
1084 /* reset interface area */
1085 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
1086 if (gdth_readl(&dp2_ptr->u) != 0) {
1087 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
1088 iounmap(ha->brd);
1089 return 0;
1090 }
1091
1092 /* disable board interrupts, read DRQ and IRQ */
1093 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1094 gdth_writeb(0x00, &dp2_ptr->io.irqen);
1095 gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
1096 gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
1097
1098 irq_drq = gdth_readb(&dp2_ptr->io.rq);
1099 for (i=0; i<3; ++i) {
1100 if ((irq_drq & 1)==0)
1101 break;
1102 irq_drq >>= 1;
1103 }
1104 ha->drq = gdth_drq_tab[i];
1105
1106 irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
1107 for (i=1; i<5; ++i) {
1108 if ((irq_drq & 1)==0)
1109 break;
1110 irq_drq >>= 1;
1111 }
1112 ha->irq = gdth_irq_tab[i];
1113
1114 /* deinitialize services */
1115 gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
1116 gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
1117 gdth_writeb(0, &dp2_ptr->io.event);
1118 retries = INIT_RETRIES;
1119 gdth_delay(20);
1120 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1121 if (--retries == 0) {
1122 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
1123 iounmap(ha->brd);
1124 return 0;
1125 }
1126 gdth_delay(1);
1127 }
1128 prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
1129 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1130 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1131 if (prot_ver != PROTOCOL_VERSION) {
1132 printk("GDT-ISA: Illegal protocol version\n");
1133 iounmap(ha->brd);
1134 return 0;
1135 }
1136
1137 ha->oem_id = OEM_ID_ICP;
1138 ha->type = GDT_ISA;
1139 ha->ic_all_size = sizeof(dp2_ptr->u);
1140 ha->stype= GDT2_ID;
1141 ha->brd_phys = bios_adr >> 4;
1142
1143 /* special request to controller BIOS */
1144 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
1145 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
1146 gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
1147 gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
1148 gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
1149 gdth_writeb(0, &dp2_ptr->io.event);
1150 retries = INIT_RETRIES;
1151 gdth_delay(20);
1152 while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1153 if (--retries == 0) {
1154 printk("GDT-ISA: Initialization error\n");
1155 iounmap(ha->brd);
1156 return 0;
1157 }
1158 gdth_delay(1);
1159 }
1160 gdth_writeb(0, &dp2_ptr->u.ic.Status);
1161 gdth_writeb(0xff, &dp2_ptr->io.irqdel);
1162
1163 ha->dma64_support = 0;
1164 return 1;
1165 }
1166
1167
1168 static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
1169 {
1170 register gdt6_dpram_str __iomem *dp6_ptr;
1171 register gdt6c_dpram_str __iomem *dp6c_ptr;
1172 register gdt6m_dpram_str __iomem *dp6m_ptr;
1173 ulong32 retries;
1174 unchar prot_ver;
1175 ushort command;
1176 int i, found = FALSE;
1177
1178 TRACE(("gdth_init_pci()\n"));
1179
1180 if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
1181 ha->oem_id = OEM_ID_INTEL;
1182 else
1183 ha->oem_id = OEM_ID_ICP;
1184 ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
1185 ha->stype = (ulong32)pcistr->device_id;
1186 ha->subdevice_id = pcistr->subdevice_id;
1187 ha->irq = pcistr->irq;
1188 ha->pdev = pcistr->pdev;
1189
1190 if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1191 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1192 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
1193 if (ha->brd == NULL) {
1194 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1195 return 0;
1196 }
1197 /* check and reset interface area */
1198 dp6_ptr = ha->brd;
1199 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1200 if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1201 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1202 pcistr->dpmem);
1203 found = FALSE;
1204 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1205 iounmap(ha->brd);
1206 ha->brd = ioremap(i, sizeof(ushort));
1207 if (ha->brd == NULL) {
1208 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1209 return 0;
1210 }
1211 if (gdth_readw(ha->brd) != 0xffff) {
1212 TRACE2(("init_pci_old() address 0x%x busy\n", i));
1213 continue;
1214 }
1215 iounmap(ha->brd);
1216 pci_write_config_dword(pcistr->pdev,
1217 PCI_BASE_ADDRESS_0, i);
1218 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
1219 if (ha->brd == NULL) {
1220 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1221 return 0;
1222 }
1223 dp6_ptr = ha->brd;
1224 gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
1225 if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1226 printk("GDT-PCI: Use free address at 0x%x\n", i);
1227 found = TRUE;
1228 break;
1229 }
1230 }
1231 if (!found) {
1232 printk("GDT-PCI: No free address found!\n");
1233 iounmap(ha->brd);
1234 return 0;
1235 }
1236 }
1237 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
1238 if (gdth_readl(&dp6_ptr->u) != 0) {
1239 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1240 iounmap(ha->brd);
1241 return 0;
1242 }
1243
1244 /* disable board interrupts, deinit services */
1245 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1246 gdth_writeb(0x00, &dp6_ptr->io.irqen);
1247 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
1248 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
1249
1250 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
1251 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
1252 gdth_writeb(0, &dp6_ptr->io.event);
1253 retries = INIT_RETRIES;
1254 gdth_delay(20);
1255 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1256 if (--retries == 0) {
1257 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1258 iounmap(ha->brd);
1259 return 0;
1260 }
1261 gdth_delay(1);
1262 }
1263 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
1264 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1265 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1266 if (prot_ver != PROTOCOL_VERSION) {
1267 printk("GDT-PCI: Illegal protocol version\n");
1268 iounmap(ha->brd);
1269 return 0;
1270 }
1271
1272 ha->type = GDT_PCI;
1273 ha->ic_all_size = sizeof(dp6_ptr->u);
1274
1275 /* special command to controller BIOS */
1276 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
1277 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
1278 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
1279 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
1280 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
1281 gdth_writeb(0, &dp6_ptr->io.event);
1282 retries = INIT_RETRIES;
1283 gdth_delay(20);
1284 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1285 if (--retries == 0) {
1286 printk("GDT-PCI: Initialization error\n");
1287 iounmap(ha->brd);
1288 return 0;
1289 }
1290 gdth_delay(1);
1291 }
1292 gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
1293 gdth_writeb(0xff, &dp6_ptr->io.irqdel);
1294
1295 ha->dma64_support = 0;
1296
1297 } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1298 ha->plx = (gdt6c_plx_regs *)pcistr->io;
1299 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
1300 pcistr->dpmem,ha->irq));
1301 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1302 if (ha->brd == NULL) {
1303 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1304 iounmap(ha->brd);
1305 return 0;
1306 }
1307 /* check and reset interface area */
1308 dp6c_ptr = ha->brd;
1309 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1310 if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1311 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1312 pcistr->dpmem);
1313 found = FALSE;
1314 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1315 iounmap(ha->brd);
1316 ha->brd = ioremap(i, sizeof(ushort));
1317 if (ha->brd == NULL) {
1318 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1319 return 0;
1320 }
1321 if (gdth_readw(ha->brd) != 0xffff) {
1322 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1323 continue;
1324 }
1325 iounmap(ha->brd);
1326 pci_write_config_dword(pcistr->pdev,
1327 PCI_BASE_ADDRESS_2, i);
1328 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1329 if (ha->brd == NULL) {
1330 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1331 return 0;
1332 }
1333 dp6c_ptr = ha->brd;
1334 gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
1335 if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1336 printk("GDT-PCI: Use free address at 0x%x\n", i);
1337 found = TRUE;
1338 break;
1339 }
1340 }
1341 if (!found) {
1342 printk("GDT-PCI: No free address found!\n");
1343 iounmap(ha->brd);
1344 return 0;
1345 }
1346 }
1347 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
1348 if (gdth_readl(&dp6c_ptr->u) != 0) {
1349 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1350 iounmap(ha->brd);
1351 return 0;
1352 }
1353
1354 /* disable board interrupts, deinit services */
1355 outb(0x00,PTR2USHORT(&ha->plx->control1));
1356 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1357
1358 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1359 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1360
1361 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1362 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1363
1364 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1365
1366 retries = INIT_RETRIES;
1367 gdth_delay(20);
1368 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1369 if (--retries == 0) {
1370 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1371 iounmap(ha->brd);
1372 return 0;
1373 }
1374 gdth_delay(1);
1375 }
1376 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
1377 gdth_writeb(0, &dp6c_ptr->u.ic.Status);
1378 if (prot_ver != PROTOCOL_VERSION) {
1379 printk("GDT-PCI: Illegal protocol version\n");
1380 iounmap(ha->brd);
1381 return 0;
1382 }
1383
1384 ha->type = GDT_PCINEW;
1385 ha->ic_all_size = sizeof(dp6c_ptr->u);
1386
1387 /* special command to controller BIOS */
1388 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1389 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1390 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1391 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1392 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1393
1394 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1395
1396 retries = INIT_RETRIES;
1397 gdth_delay(20);
1398 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1399 if (--retries == 0) {
1400 printk("GDT-PCI: Initialization error\n");
1401 iounmap(ha->brd);
1402 return 0;
1403 }
1404 gdth_delay(1);
1405 }
1406 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
1407
1408 ha->dma64_support = 0;
1409
1410 } else { /* MPR */
1411 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1412 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1413 if (ha->brd == NULL) {
1414 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1415 return 0;
1416 }
1417
1418 /* manipulate config. space to enable DPMEM, start RP controller */
1419 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1420 command |= 6;
1421 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1422 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1423 pci_resource_start(pcistr->pdev, 8) = 0UL;
1424 i = 0xFEFF0001UL;
1425 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1426 gdth_delay(1);
1427 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1428 pci_resource_start(pcistr->pdev, 8));
1429
1430 dp6m_ptr = ha->brd;
1431
1432 /* Ensure that it is safe to access the non HW portions of DPMEM.
1433 * Aditional check needed for Xscale based RAID controllers */
1434 while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1435 gdth_delay(1);
1436
1437 /* check and reset interface area */
1438 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1439 if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1440 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1441 pcistr->dpmem);
1442 found = FALSE;
1443 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1444 iounmap(ha->brd);
1445 ha->brd = ioremap(i, sizeof(ushort));
1446 if (ha->brd == NULL) {
1447 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1448 return 0;
1449 }
1450 if (gdth_readw(ha->brd) != 0xffff) {
1451 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1452 continue;
1453 }
1454 iounmap(ha->brd);
1455 pci_write_config_dword(pcistr->pdev,
1456 PCI_BASE_ADDRESS_0, i);
1457 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1458 if (ha->brd == NULL) {
1459 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1460 return 0;
1461 }
1462 dp6m_ptr = ha->brd;
1463 gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
1464 if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1465 printk("GDT-PCI: Use free address at 0x%x\n", i);
1466 found = TRUE;
1467 break;
1468 }
1469 }
1470 if (!found) {
1471 printk("GDT-PCI: No free address found!\n");
1472 iounmap(ha->brd);
1473 return 0;
1474 }
1475 }
1476 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1477
1478 /* disable board interrupts, deinit services */
1479 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1480 &dp6m_ptr->i960r.edoor_en_reg);
1481 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1482 gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1483 gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1484
1485 gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1486 gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1487 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1488 retries = INIT_RETRIES;
1489 gdth_delay(20);
1490 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1491 if (--retries == 0) {
1492 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1493 iounmap(ha->brd);
1494 return 0;
1495 }
1496 gdth_delay(1);
1497 }
1498 prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
1499 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1500 if (prot_ver != PROTOCOL_VERSION) {
1501 printk("GDT-PCI: Illegal protocol version\n");
1502 iounmap(ha->brd);
1503 return 0;
1504 }
1505
1506 ha->type = GDT_PCIMPR;
1507 ha->ic_all_size = sizeof(dp6m_ptr->u);
1508
1509 /* special command to controller BIOS */
1510 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1511 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1512 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1513 gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1514 gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1515 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1516 retries = INIT_RETRIES;
1517 gdth_delay(20);
1518 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1519 if (--retries == 0) {
1520 printk("GDT-PCI: Initialization error\n");
1521 iounmap(ha->brd);
1522 return 0;
1523 }
1524 gdth_delay(1);
1525 }
1526 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1527
1528 /* read FW version to detect 64-bit DMA support */
1529 gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1530 gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1531 retries = INIT_RETRIES;
1532 gdth_delay(20);
1533 while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1534 if (--retries == 0) {
1535 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1536 iounmap(ha->brd);
1537 return 0;
1538 }
1539 gdth_delay(1);
1540 }
1541 prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1542 gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
1543 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1544 ha->dma64_support = 0;
1545 else
1546 ha->dma64_support = 1;
1547 }
1548
1549 return 1;
1550 }
1551
1552
1553 /* controller protocol functions */
1554
1555 static void __init gdth_enable_int(int hanum)
1556 {
1557 gdth_ha_str *ha;
1558 ulong flags;
1559 gdt2_dpram_str __iomem *dp2_ptr;
1560 gdt6_dpram_str __iomem *dp6_ptr;
1561 gdt6m_dpram_str __iomem *dp6m_ptr;
1562
1563 TRACE(("gdth_enable_int() hanum %d\n",hanum));
1564 ha = HADATA(gdth_ctr_tab[hanum]);
1565 spin_lock_irqsave(&ha->smp_lock, flags);
1566
1567 if (ha->type == GDT_EISA) {
1568 outb(0xff, ha->bmic + EDOORREG);
1569 outb(0xff, ha->bmic + EDENABREG);
1570 outb(0x01, ha->bmic + EINTENABREG);
1571 } else if (ha->type == GDT_ISA) {
1572 dp2_ptr = ha->brd;
1573 gdth_writeb(1, &dp2_ptr->io.irqdel);
1574 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1575 gdth_writeb(1, &dp2_ptr->io.irqen);
1576 } else if (ha->type == GDT_PCI) {
1577 dp6_ptr = ha->brd;
1578 gdth_writeb(1, &dp6_ptr->io.irqdel);
1579 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1580 gdth_writeb(1, &dp6_ptr->io.irqen);
1581 } else if (ha->type == GDT_PCINEW) {
1582 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1583 outb(0x03, PTR2USHORT(&ha->plx->control1));
1584 } else if (ha->type == GDT_PCIMPR) {
1585 dp6m_ptr = ha->brd;
1586 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1587 gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1588 &dp6m_ptr->i960r.edoor_en_reg);
1589 }
1590 spin_unlock_irqrestore(&ha->smp_lock, flags);
1591 }
1592
1593
1594 static int gdth_get_status(unchar *pIStatus,int irq)
1595 {
1596 register gdth_ha_str *ha;
1597 int i;
1598
1599 TRACE(("gdth_get_status() irq %d ctr_count %d\n",
1600 irq,gdth_ctr_count));
1601
1602 *pIStatus = 0;
1603 for (i=0; i<gdth_ctr_count; ++i) {
1604 ha = HADATA(gdth_ctr_tab[i]);
1605 if (ha->irq != (unchar)irq) /* check IRQ */
1606 continue;
1607 if (ha->type == GDT_EISA)
1608 *pIStatus = inb((ushort)ha->bmic + EDOORREG);
1609 else if (ha->type == GDT_ISA)
1610 *pIStatus =
1611 gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1612 else if (ha->type == GDT_PCI)
1613 *pIStatus =
1614 gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1615 else if (ha->type == GDT_PCINEW)
1616 *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1617 else if (ha->type == GDT_PCIMPR)
1618 *pIStatus =
1619 gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
1620
1621 if (*pIStatus)
1622 return i; /* board found */
1623 }
1624 return -1;
1625 }
1626
1627
1628 static int gdth_test_busy(int hanum)
1629 {
1630 register gdth_ha_str *ha;
1631 register int gdtsema0 = 0;
1632
1633 TRACE(("gdth_test_busy() hanum %d\n",hanum));
1634
1635 ha = HADATA(gdth_ctr_tab[hanum]);
1636 if (ha->type == GDT_EISA)
1637 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1638 else if (ha->type == GDT_ISA)
1639 gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1640 else if (ha->type == GDT_PCI)
1641 gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1642 else if (ha->type == GDT_PCINEW)
1643 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1644 else if (ha->type == GDT_PCIMPR)
1645 gdtsema0 =
1646 (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1647
1648 return (gdtsema0 & 1);
1649 }
1650
1651
1652 static int gdth_get_cmd_index(int hanum)
1653 {
1654 register gdth_ha_str *ha;
1655 int i;
1656
1657 TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
1658
1659 ha = HADATA(gdth_ctr_tab[hanum]);
1660 for (i=0; i<GDTH_MAXCMDS; ++i) {
1661 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1662 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1663 ha->cmd_tab[i].service = ha->pccb->Service;
1664 ha->pccb->CommandIndex = (ulong32)i+2;
1665 return (i+2);
1666 }
1667 }
1668 return 0;
1669 }
1670
1671
1672 static void gdth_set_sema0(int hanum)
1673 {
1674 register gdth_ha_str *ha;
1675
1676 TRACE(("gdth_set_sema0() hanum %d\n",hanum));
1677
1678 ha = HADATA(gdth_ctr_tab[hanum]);
1679 if (ha->type == GDT_EISA) {
1680 outb(1, ha->bmic + SEMA0REG);
1681 } else if (ha->type == GDT_ISA) {
1682 gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1683 } else if (ha->type == GDT_PCI) {
1684 gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1685 } else if (ha->type == GDT_PCINEW) {
1686 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1687 } else if (ha->type == GDT_PCIMPR) {
1688 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1689 }
1690 }
1691
1692
1693 static void gdth_copy_command(int hanum)
1694 {
1695 register gdth_ha_str *ha;
1696 register gdth_cmd_str *cmd_ptr;
1697 register gdt6m_dpram_str __iomem *dp6m_ptr;
1698 register gdt6c_dpram_str __iomem *dp6c_ptr;
1699 gdt6_dpram_str __iomem *dp6_ptr;
1700 gdt2_dpram_str __iomem *dp2_ptr;
1701 ushort cp_count,dp_offset,cmd_no;
1702
1703 TRACE(("gdth_copy_command() hanum %d\n",hanum));
1704
1705 ha = HADATA(gdth_ctr_tab[hanum]);
1706 cp_count = ha->cmd_len;
1707 dp_offset= ha->cmd_offs_dpmem;
1708 cmd_no = ha->cmd_cnt;
1709 cmd_ptr = ha->pccb;
1710
1711 ++ha->cmd_cnt;
1712 if (ha->type == GDT_EISA)
1713 return; /* no DPMEM, no copy */
1714
1715 /* set cpcount dword aligned */
1716 if (cp_count & 3)
1717 cp_count += (4 - (cp_count & 3));
1718
1719 ha->cmd_offs_dpmem += cp_count;
1720
1721 /* set offset and service, copy command to DPMEM */
1722 if (ha->type == GDT_ISA) {
1723 dp2_ptr = ha->brd;
1724 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1725 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
1726 gdth_writew((ushort)cmd_ptr->Service,
1727 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1728 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1729 } else if (ha->type == GDT_PCI) {
1730 dp6_ptr = ha->brd;
1731 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1732 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
1733 gdth_writew((ushort)cmd_ptr->Service,
1734 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1735 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1736 } else if (ha->type == GDT_PCINEW) {
1737 dp6c_ptr = ha->brd;
1738 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1739 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
1740 gdth_writew((ushort)cmd_ptr->Service,
1741 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1742 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1743 } else if (ha->type == GDT_PCIMPR) {
1744 dp6m_ptr = ha->brd;
1745 gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
1746 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
1747 gdth_writew((ushort)cmd_ptr->Service,
1748 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1749 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1750 }
1751 }
1752
1753
1754 static void gdth_release_event(int hanum)
1755 {
1756 register gdth_ha_str *ha;
1757
1758 TRACE(("gdth_release_event() hanum %d\n",hanum));
1759 ha = HADATA(gdth_ctr_tab[hanum]);
1760
1761 #ifdef GDTH_STATISTICS
1762 {
1763 ulong32 i,j;
1764 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1765 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1766 ++i;
1767 }
1768 if (max_index < i) {
1769 max_index = i;
1770 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1771 }
1772 }
1773 #endif
1774
1775 if (ha->pccb->OpCode == GDT_INIT)
1776 ha->pccb->Service |= 0x80;
1777
1778 if (ha->type == GDT_EISA) {
1779 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1780 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1781 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1782 } else if (ha->type == GDT_ISA) {
1783 gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1784 } else if (ha->type == GDT_PCI) {
1785 gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1786 } else if (ha->type == GDT_PCINEW) {
1787 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1788 } else if (ha->type == GDT_PCIMPR) {
1789 gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1790 }
1791 }
1792
1793
1794 static int gdth_wait(int hanum,int index,ulong32 time)
1795 {
1796 gdth_ha_str *ha;
1797 int answer_found = FALSE;
1798
1799 TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
1800
1801 ha = HADATA(gdth_ctr_tab[hanum]);
1802 if (index == 0)
1803 return 1; /* no wait required */
1804
1805 gdth_from_wait = TRUE;
1806 do {
1807 gdth_interrupt((int)ha->irq,ha);
1808 if (wait_hanum==hanum && wait_index==index) {
1809 answer_found = TRUE;
1810 break;
1811 }
1812 gdth_delay(1);
1813 } while (--time);
1814 gdth_from_wait = FALSE;
1815
1816 while (gdth_test_busy(hanum))
1817 gdth_delay(0);
1818
1819 return (answer_found);
1820 }
1821
1822
1823 static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
1824 ulong64 p2,ulong64 p3)
1825 {
1826 register gdth_ha_str *ha;
1827 register gdth_cmd_str *cmd_ptr;
1828 int retries,index;
1829
1830 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1831
1832 ha = HADATA(gdth_ctr_tab[hanum]);
1833 cmd_ptr = ha->pccb;
1834 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1835
1836 /* make command */
1837 for (retries = INIT_RETRIES;;) {
1838 cmd_ptr->Service = service;
1839 cmd_ptr->RequestBuffer = INTERNAL_CMND;
1840 if (!(index=gdth_get_cmd_index(hanum))) {
1841 TRACE(("GDT: No free command index found\n"));
1842 return 0;
1843 }
1844 gdth_set_sema0(hanum);
1845 cmd_ptr->OpCode = opcode;
1846 cmd_ptr->BoardNode = LOCALBOARD;
1847 if (service == CACHESERVICE) {
1848 if (opcode == GDT_IOCTL) {
1849 cmd_ptr->u.ioctl.subfunc = p1;
1850 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1851 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1852 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1853 } else {
1854 if (ha->cache_feat & GDT_64BIT) {
1855 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1856 cmd_ptr->u.cache64.BlockNo = p2;
1857 } else {
1858 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1859 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1860 }
1861 }
1862 } else if (service == SCSIRAWSERVICE) {
1863 if (ha->raw_feat & GDT_64BIT) {
1864 cmd_ptr->u.raw64.direction = p1;
1865 cmd_ptr->u.raw64.bus = (unchar)p2;
1866 cmd_ptr->u.raw64.target = (unchar)p3;
1867 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1868 } else {
1869 cmd_ptr->u.raw.direction = p1;
1870 cmd_ptr->u.raw.bus = (unchar)p2;
1871 cmd_ptr->u.raw.target = (unchar)p3;
1872 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1873 }
1874 } else if (service == SCREENSERVICE) {
1875 if (opcode == GDT_REALTIME) {
1876 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1877 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1878 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1879 }
1880 }
1881 ha->cmd_len = sizeof(gdth_cmd_str);
1882 ha->cmd_offs_dpmem = 0;
1883 ha->cmd_cnt = 0;
1884 gdth_copy_command(hanum);
1885 gdth_release_event(hanum);
1886 gdth_delay(20);
1887 if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
1888 printk("GDT: Initialization error (timeout service %d)\n",service);
1889 return 0;
1890 }
1891 if (ha->status != S_BSY || --retries == 0)
1892 break;
1893 gdth_delay(1);
1894 }
1895
1896 return (ha->status != S_OK ? 0:1);
1897 }
1898
1899
1900 /* search for devices */
1901
1902 static int __init gdth_search_drives(int hanum)
1903 {
1904 register gdth_ha_str *ha;
1905 ushort cdev_cnt, i;
1906 int ok;
1907 ulong32 bus_no, drv_cnt, drv_no, j;
1908 gdth_getch_str *chn;
1909 gdth_drlist_str *drl;
1910 gdth_iochan_str *ioc;
1911 gdth_raw_iochan_str *iocr;
1912 gdth_arcdl_str *alst;
1913 gdth_alist_str *alst2;
1914 gdth_oem_str_ioctl *oemstr;
1915 #ifdef INT_COAL
1916 gdth_perf_modes *pmod;
1917 #endif
1918
1919 #ifdef GDTH_RTC
1920 unchar rtc[12];
1921 ulong flags;
1922 #endif
1923
1924 TRACE(("gdth_search_drives() hanum %d\n",hanum));
1925 ha = HADATA(gdth_ctr_tab[hanum]);
1926 ok = 0;
1927
1928 /* initialize controller services, at first: screen service */
1929 ha->screen_feat = 0;
1930 if (!force_dma32) {
1931 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
1932 if (ok)
1933 ha->screen_feat = GDT_64BIT;
1934 }
1935 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1936 ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
1937 if (!ok) {
1938 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
1939 hanum, ha->status);
1940 return 0;
1941 }
1942 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1943
1944 #ifdef GDTH_RTC
1945 /* read realtime clock info, send to controller */
1946 /* 1. wait for the falling edge of update flag */
1947 spin_lock_irqsave(&rtc_lock, flags);
1948 for (j = 0; j < 1000000; ++j)
1949 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1950 break;
1951 for (j = 0; j < 1000000; ++j)
1952 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1953 break;
1954 /* 2. read info */
1955 do {
1956 for (j = 0; j < 12; ++j)
1957 rtc[j] = CMOS_READ(j);
1958 } while (rtc[0] != CMOS_READ(0));
1959 spin_lock_irqrestore(&rtc_lock, flags);
1960 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1961 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1962 /* 3. send to controller firmware */
1963 gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
1964 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1965 #endif
1966
1967 /* unfreeze all IOs */
1968 gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
1969
1970 /* initialize cache service */
1971 ha->cache_feat = 0;
1972 if (!force_dma32) {
1973 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
1974 if (ok)
1975 ha->cache_feat = GDT_64BIT;
1976 }
1977 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
1978 ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
1979 if (!ok) {
1980 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
1981 hanum, ha->status);
1982 return 0;
1983 }
1984 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1985 cdev_cnt = (ushort)ha->info;
1986 ha->fw_vers = ha->service;
1987
1988 #ifdef INT_COAL
1989 if (ha->type == GDT_PCIMPR) {
1990 /* set perf. modes */
1991 pmod = (gdth_perf_modes *)ha->pscratch;
1992 pmod->version = 1;
1993 pmod->st_mode = 1; /* enable one status buffer */
1994 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1995 pmod->st_buff_indx1 = COALINDEX;
1996 pmod->st_buff_addr2 = 0;
1997 pmod->st_buff_u_addr2 = 0;
1998 pmod->st_buff_indx2 = 0;
1999 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
2000 pmod->cmd_mode = 0; // disable all cmd buffers
2001 pmod->cmd_buff_addr1 = 0;
2002 pmod->cmd_buff_u_addr1 = 0;
2003 pmod->cmd_buff_indx1 = 0;
2004 pmod->cmd_buff_addr2 = 0;
2005 pmod->cmd_buff_u_addr2 = 0;
2006 pmod->cmd_buff_indx2 = 0;
2007 pmod->cmd_buff_size = 0;
2008 pmod->reserved1 = 0;
2009 pmod->reserved2 = 0;
2010 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
2011 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
2012 printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
2013 }
2014 }
2015 #endif
2016
2017 /* detect number of buses - try new IOCTL */
2018 iocr = (gdth_raw_iochan_str *)ha->pscratch;
2019 iocr->hdr.version = 0xffffffff;
2020 iocr->hdr.list_entries = MAXBUS;
2021 iocr->hdr.first_chan = 0;
2022 iocr->hdr.last_chan = MAXBUS-1;
2023 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
2024 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
2025 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
2026 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
2027 ha->bus_cnt = iocr->hdr.chan_count;
2028 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2029 if (iocr->list[bus_no].proc_id < MAXID)
2030 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
2031 else
2032 ha->bus_id[bus_no] = 0xff;
2033 }
2034 } else {
2035 /* old method */
2036 chn = (gdth_getch_str *)ha->pscratch;
2037 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
2038 chn->channel_no = bus_no;
2039 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2040 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2041 IO_CHANNEL | INVALID_CHANNEL,
2042 sizeof(gdth_getch_str))) {
2043 if (bus_no == 0) {
2044 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
2045 hanum, ha->status);
2046 return 0;
2047 }
2048 break;
2049 }
2050 if (chn->siop_id < MAXID)
2051 ha->bus_id[bus_no] = chn->siop_id;
2052 else
2053 ha->bus_id[bus_no] = 0xff;
2054 }
2055 ha->bus_cnt = (unchar)bus_no;
2056 }
2057 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
2058
2059 /* read cache configuration */
2060 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
2061 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
2062 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
2063 hanum, ha->status);
2064 return 0;
2065 }
2066 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
2067 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
2068 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
2069 ha->cpar.write_back,ha->cpar.block_size));
2070
2071 /* read board info and features */
2072 ha->more_proc = FALSE;
2073 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
2074 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
2075 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
2076 sizeof(gdth_binfo_str));
2077 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
2078 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
2079 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
2080 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
2081 ha->more_proc = TRUE;
2082 }
2083 } else {
2084 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
2085 strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
2086 }
2087 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
2088
2089 /* read more informations */
2090 if (ha->more_proc) {
2091 /* physical drives, channel addresses */
2092 ioc = (gdth_iochan_str *)ha->pscratch;
2093 ioc->hdr.version = 0xffffffff;
2094 ioc->hdr.list_entries = MAXBUS;
2095 ioc->hdr.first_chan = 0;
2096 ioc->hdr.last_chan = MAXBUS-1;
2097 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
2098 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
2099 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
2100 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2101 ha->raw[bus_no].address = ioc->list[bus_no].address;
2102 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
2103 }
2104 } else {
2105 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2106 ha->raw[bus_no].address = IO_CHANNEL;
2107 ha->raw[bus_no].local_no = bus_no;
2108 }
2109 }
2110 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
2111 chn = (gdth_getch_str *)ha->pscratch;
2112 chn->channel_no = ha->raw[bus_no].local_no;
2113 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2114 SCSI_CHAN_CNT | L_CTRL_PATTERN,
2115 ha->raw[bus_no].address | INVALID_CHANNEL,
2116 sizeof(gdth_getch_str))) {
2117 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
2118 TRACE2(("Channel %d: %d phys. drives\n",
2119 bus_no,chn->drive_cnt));
2120 }
2121 if (ha->raw[bus_no].pdev_cnt > 0) {
2122 drl = (gdth_drlist_str *)ha->pscratch;
2123 drl->sc_no = ha->raw[bus_no].local_no;
2124 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
2125 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2126 SCSI_DR_LIST | L_CTRL_PATTERN,
2127 ha->raw[bus_no].address | INVALID_CHANNEL,
2128 sizeof(gdth_drlist_str))) {
2129 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
2130 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
2131 } else {
2132 ha->raw[bus_no].pdev_cnt = 0;
2133 }
2134 }
2135 }
2136
2137 /* logical drives */
2138 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
2139 INVALID_CHANNEL,sizeof(ulong32))) {
2140 drv_cnt = *(ulong32 *)ha->pscratch;
2141 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
2142 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
2143 for (j = 0; j < drv_cnt; ++j) {
2144 drv_no = ((ulong32 *)ha->pscratch)[j];
2145 if (drv_no < MAX_LDRIVES) {
2146 ha->hdr[drv_no].is_logdrv = TRUE;
2147 TRACE2(("Drive %d is log. drive\n",drv_no));
2148 }
2149 }
2150 }
2151 alst = (gdth_arcdl_str *)ha->pscratch;
2152 alst->entries_avail = MAX_LDRIVES;
2153 alst->first_entry = 0;
2154 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
2155 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2156 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
2157 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
2158 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
2159 for (j = 0; j < alst->entries_init; ++j) {
2160 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
2161 ha->hdr[j].is_master = alst->list[j].is_master;
2162 ha->hdr[j].is_parity = alst->list[j].is_parity;
2163 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
2164 ha->hdr[j].master_no = alst->list[j].cd_handle;
2165 }
2166 } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2167 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
2168 0, 35 * sizeof(gdth_alist_str))) {
2169 for (j = 0; j < 35; ++j) {
2170 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
2171 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
2172 ha->hdr[j].is_master = alst2->is_master;
2173 ha->hdr[j].is_parity = alst2->is_parity;
2174 ha->hdr[j].is_hotfix = alst2->is_hotfix;
2175 ha->hdr[j].master_no = alst2->cd_handle;
2176 }
2177 }
2178 }
2179 }
2180
2181 /* initialize raw service */
2182 ha->raw_feat = 0;
2183 if (!force_dma32) {
2184 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
2185 if (ok)
2186 ha->raw_feat = GDT_64BIT;
2187 }
2188 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
2189 ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
2190 if (!ok) {
2191 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
2192 hanum, ha->status);
2193 return 0;
2194 }
2195 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
2196
2197 /* set/get features raw service (scatter/gather) */
2198 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
2199 0,0)) {
2200 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
2201 if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
2202 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
2203 ha->info));
2204 ha->raw_feat |= (ushort)ha->info;
2205 }
2206 }
2207
2208 /* set/get features cache service (equal to raw service) */
2209 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
2210 SCATTER_GATHER,0)) {
2211 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
2212 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
2213 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
2214 ha->info));
2215 ha->cache_feat |= (ushort)ha->info;
2216 }
2217 }
2218
2219 /* reserve drives for raw service */
2220 if (reserve_mode != 0) {
2221 gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
2222 reserve_mode == 1 ? 1 : 3, 0, 0);
2223 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
2224 ha->status));
2225 }
2226 for (i = 0; i < MAX_RES_ARGS; i += 4) {
2227 if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
2228 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
2229 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
2230 reserve_list[i], reserve_list[i+1],
2231 reserve_list[i+2], reserve_list[i+3]));
2232 if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
2233 reserve_list[i+1], reserve_list[i+2] |
2234 (reserve_list[i+3] << 8))) {
2235 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
2236 hanum, ha->status);
2237 }
2238 }
2239 }
2240
2241 /* Determine OEM string using IOCTL */
2242 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
2243 oemstr->params.ctl_version = 0x01;
2244 oemstr->params.buffer_size = sizeof(oemstr->text);
2245 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
2246 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
2247 sizeof(gdth_oem_str_ioctl))) {
2248 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
2249 printk("GDT-HA %d: Vendor: %s Name: %s\n",
2250 hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
2251 /* Save the Host Drive inquiry data */
2252 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2253 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
2254 sizeof(ha->oem_name));
2255 #else
2256 strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
2257 ha->oem_name[7] = '\0';
2258 #endif
2259 } else {
2260 /* Old method, based on PCI ID */
2261 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
2262 printk("GDT-HA %d: Name: %s\n",
2263 hanum,ha->binfo.type_string);
2264 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2265 if (ha->oem_id == OEM_ID_INTEL)
2266 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
2267 else
2268 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
2269 #else
2270 if (ha->oem_id == OEM_ID_INTEL)
2271 strcpy(ha->oem_name,"Intel ");
2272 else
2273 strcpy(ha->oem_name,"ICP ");
2274 #endif
2275 }
2276
2277 /* scanning for host drives */
2278 for (i = 0; i < cdev_cnt; ++i)
2279 gdth_analyse_hdrive(hanum,i);
2280
2281 TRACE(("gdth_search_drives() OK\n"));
2282 return 1;
2283 }
2284
2285 static int gdth_analyse_hdrive(int hanum,ushort hdrive)
2286 {
2287 register gdth_ha_str *ha;
2288 ulong32 drv_cyls;
2289 int drv_hds, drv_secs;
2290
2291 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
2292 if (hdrive >= MAX_HDRIVES)
2293 return 0;
2294 ha = HADATA(gdth_ctr_tab[hanum]);
2295
2296 if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
2297 return 0;
2298 ha->hdr[hdrive].present = TRUE;
2299 ha->hdr[hdrive].size = ha->info;
2300
2301 /* evaluate mapping (sectors per head, heads per cylinder) */
2302 ha->hdr[hdrive].size &= ~SECS32;
2303 if (ha->info2 == 0) {
2304 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
2305 } else {
2306 drv_hds = ha->info2 & 0xff;
2307 drv_secs = (ha->info2 >> 8) & 0xff;
2308 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
2309 }
2310 ha->hdr[hdrive].heads = (unchar)drv_hds;
2311 ha->hdr[hdrive].secs = (unchar)drv_secs;
2312 /* round size */
2313 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
2314
2315 if (ha->cache_feat & GDT_64BIT) {
2316 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
2317 && ha->info2 != 0) {
2318 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
2319 }
2320 }
2321 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
2322 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
2323
2324 /* get informations about device */
2325 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
2326 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
2327 hdrive,ha->info));
2328 ha->hdr[hdrive].devtype = (ushort)ha->info;
2329 }
2330
2331 /* cluster info */
2332 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
2333 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
2334 hdrive,ha->info));
2335 if (!shared_access)
2336 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
2337 }
2338
2339 /* R/W attributes */
2340 if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
2341 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
2342 hdrive,ha->info));
2343 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
2344 }
2345
2346 return 1;
2347 }
2348
2349
2350 /* command queueing/sending functions */
2351
2352 static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
2353 {
2354 register gdth_ha_str *ha;
2355 register Scsi_Cmnd *pscp;
2356 register Scsi_Cmnd *nscp;
2357 ulong flags;
2358 unchar b, t;
2359
2360 TRACE(("gdth_putq() priority %d\n",priority));
2361 ha = HADATA(gdth_ctr_tab[hanum]);
2362 spin_lock_irqsave(&ha->smp_lock, flags);
2363
2364 if (scp->done != gdth_scsi_done) {
2365 scp->SCp.this_residual = (int)priority;
2366 b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
2367 t = scp->device->id;
2368 if (priority >= DEFAULT_PRI) {
2369 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2370 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2371 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
2372 scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
2373 }
2374 }
2375 }
2376
2377 if (ha->req_first==NULL) {
2378 ha->req_first = scp; /* queue was empty */
2379 scp->SCp.ptr = NULL;
2380 } else { /* queue not empty */
2381 pscp = ha->req_first;
2382 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2383 /* priority: 0-highest,..,0xff-lowest */
2384 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2385 pscp = nscp;
2386 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2387 }
2388 pscp->SCp.ptr = (char *)scp;
2389 scp->SCp.ptr = (char *)nscp;
2390 }
2391 spin_unlock_irqrestore(&ha->smp_lock, flags);
2392
2393 #ifdef GDTH_STATISTICS
2394 flags = 0;
2395 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2396 ++flags;
2397 if (max_rq < flags) {
2398 max_rq = flags;
2399 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2400 }
2401 #endif
2402 }
2403
2404 static void gdth_next(int hanum)
2405 {
2406 register gdth_ha_str *ha;
2407 register Scsi_Cmnd *pscp;
2408 register Scsi_Cmnd *nscp;
2409 unchar b, t, l, firsttime;
2410 unchar this_cmd, next_cmd;
2411 ulong flags = 0;
2412 int cmd_index;
2413
2414 TRACE(("gdth_next() hanum %d\n",hanum));
2415 ha = HADATA(gdth_ctr_tab[hanum]);
2416 if (!gdth_polling)
2417 spin_lock_irqsave(&ha->smp_lock, flags);
2418
2419 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2420 this_cmd = firsttime = TRUE;
2421 next_cmd = gdth_polling ? FALSE:TRUE;
2422 cmd_index = 0;
2423
2424 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2425 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2426 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2427 if (nscp->done != gdth_scsi_done) {
2428 b = virt_ctr ?
2429 NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
2430 t = nscp->device->id;
2431 l = nscp->device->lun;
2432 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2433 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2434 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2435 continue;
2436 }
2437 } else
2438 b = t = l = 0;
2439
2440 if (firsttime) {
2441 if (gdth_test_busy(hanum)) { /* controller busy ? */
2442 TRACE(("gdth_next() controller %d busy !\n",hanum));
2443 if (!gdth_polling) {
2444 spin_unlock_irqrestore(&ha->smp_lock, flags);
2445 return;
2446 }
2447 while (gdth_test_busy(hanum))
2448 gdth_delay(1);
2449 }
2450 firsttime = FALSE;
2451 }
2452
2453 if (nscp->done != gdth_scsi_done) {
2454 if (nscp->SCp.phase == -1) {
2455 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2456 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2457 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2458 b, t, l));
2459 /* TEST_UNIT_READY -> set scan mode */
2460 if ((ha->scan_mode & 0x0f) == 0) {
2461 if (b == 0 && t == 0 && l == 0) {
2462 ha->scan_mode |= 1;
2463 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2464 }
2465 } else if ((ha->scan_mode & 0x0f) == 1) {
2466 if (b == 0 && ((t == 0 && l == 1) ||
2467 (t == 1 && l == 0))) {
2468 nscp->SCp.sent_command = GDT_SCAN_START;
2469 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2470 | SCSIRAWSERVICE;
2471 ha->scan_mode = 0x12;
2472 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2473 ha->scan_mode));
2474 } else {
2475 ha->scan_mode &= 0x10;
2476 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2477 }
2478 } else if (ha->scan_mode == 0x12) {
2479 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2480 nscp->SCp.phase = SCSIRAWSERVICE;
2481 nscp->SCp.sent_command = GDT_SCAN_END;
2482 ha->scan_mode &= 0x10;
2483 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2484 ha->scan_mode));
2485 }
2486 }
2487 }
2488 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2489 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2490 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2491 /* always GDT_CLUST_INFO! */
2492 nscp->SCp.sent_command = GDT_CLUST_INFO;
2493 }
2494 }
2495 }
2496
2497 if (nscp->SCp.sent_command != -1) {
2498 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
2499 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2500 this_cmd = FALSE;
2501 next_cmd = FALSE;
2502 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
2503 if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2504 this_cmd = FALSE;
2505 next_cmd = FALSE;
2506 } else {
2507 memset((char*)nscp->sense_buffer,0,16);
2508 nscp->sense_buffer[0] = 0x70;
2509 nscp->sense_buffer[2] = NOT_READY;
2510 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2511 if (!nscp->SCp.have_data_in)
2512 nscp->SCp.have_data_in++;
2513 else
2514 nscp->scsi_done(nscp);
2515 }
2516 } else if (nscp->done == gdth_scsi_done) {
2517 if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
2518 this_cmd = FALSE;
2519 next_cmd = FALSE;
2520 } else if (b != ha->virt_bus) {
2521 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
2522 !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
2523 this_cmd = FALSE;
2524 else
2525 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2526 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2527 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2528 nscp->cmnd[0], b, t, l));
2529 nscp->result = DID_BAD_TARGET << 16;
2530 if (!nscp->SCp.have_data_in)
2531 nscp->SCp.have_data_in++;
2532 else
2533 nscp->scsi_done(nscp);
2534 } else {
2535 switch (nscp->cmnd[0]) {
2536 case TEST_UNIT_READY:
2537 case INQUIRY:
2538 case REQUEST_SENSE:
2539 case READ_CAPACITY:
2540 case VERIFY:
2541 case START_STOP:
2542 case MODE_SENSE:
2543 case SERVICE_ACTION_IN:
2544 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2545 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2546 nscp->cmnd[4],nscp->cmnd[5]));
2547 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2548 /* return UNIT_ATTENTION */
2549 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2550 nscp->cmnd[0], t));
2551 ha->hdr[t].media_changed = FALSE;
2552 memset((char*)nscp->sense_buffer,0,16);
2553 nscp->sense_buffer[0] = 0x70;
2554 nscp->sense_buffer[2] = UNIT_ATTENTION;
2555 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2556 if (!nscp->SCp.have_data_in)
2557 nscp->SCp.have_data_in++;
2558 else
2559 nscp->scsi_done(nscp);
2560 } else if (gdth_internal_cache_cmd(hanum,nscp))
2561 nscp->scsi_done(nscp);
2562 break;
2563
2564 case ALLOW_MEDIUM_REMOVAL:
2565 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2566 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2567 nscp->cmnd[4],nscp->cmnd[5]));
2568 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2569 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2570 nscp->result = DID_OK << 16;
2571 nscp->sense_buffer[0] = 0;
2572 if (!nscp->SCp.have_data_in)
2573 nscp->SCp.have_data_in++;
2574 else
2575 nscp->scsi_done(nscp);
2576 } else {
2577 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2578 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2579 nscp->cmnd[4],nscp->cmnd[3]));
2580 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2581 this_cmd = FALSE;
2582 }
2583 break;
2584
2585 case RESERVE:
2586 case RELEASE:
2587 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2588 "RESERVE" : "RELEASE"));
2589 if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2590 this_cmd = FALSE;
2591 break;
2592
2593 case READ_6:
2594 case WRITE_6:
2595 case READ_10:
2596 case WRITE_10:
2597 case READ_16:
2598 case WRITE_16:
2599 if (ha->hdr[t].media_changed) {
2600 /* return UNIT_ATTENTION */
2601 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2602 nscp->cmnd[0], t));
2603 ha->hdr[t].media_changed = FALSE;
2604 memset((char*)nscp->sense_buffer,0,16);
2605 nscp->sense_buffer[0] = 0x70;
2606 nscp->sense_buffer[2] = UNIT_ATTENTION;
2607 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2608 if (!nscp->SCp.have_data_in)
2609 nscp->SCp.have_data_in++;
2610 else
2611 nscp->scsi_done(nscp);
2612 } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
2613 this_cmd = FALSE;
2614 break;
2615
2616 default:
2617 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2618 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2619 nscp->cmnd[4],nscp->cmnd[5]));
2620 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
2621 hanum, nscp->cmnd[0]);
2622 nscp->result = DID_ABORT << 16;
2623 if (!nscp->SCp.have_data_in)
2624 nscp->SCp.have_data_in++;
2625 else
2626 nscp->scsi_done(nscp);
2627 break;
2628 }
2629 }
2630
2631 if (!this_cmd)
2632 break;
2633 if (nscp == ha->req_first)
2634 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2635 else
2636 pscp->SCp.ptr = nscp->SCp.ptr;
2637 if (!next_cmd)
2638 break;
2639 }
2640
2641 if (ha->cmd_cnt > 0) {
2642 gdth_release_event(hanum);
2643 }
2644
2645 if (!gdth_polling)
2646 spin_unlock_irqrestore(&ha->smp_lock, flags);
2647
2648 if (gdth_polling && ha->cmd_cnt > 0) {
2649 if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
2650 printk("GDT-HA %d: Command %d timed out !\n",
2651 hanum,cmd_index);
2652 }
2653 }
2654
2655 static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
2656 char *buffer,ushort count)
2657 {
2658 ushort cpcount,i;
2659 ushort cpsum,cpnow;
2660 struct scatterlist *sl;
2661 gdth_ha_str *ha;
2662 char *address;
2663
2664 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
2665 ha = HADATA(gdth_ctr_tab[hanum]);
2666
2667 if (scp->use_sg) {
2668 sl = (struct scatterlist *)scp->request_buffer;
2669 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
2670 unsigned long flags;
2671 cpnow = (ushort)sl->length;
2672 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2673 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2674 if (cpsum+cpnow > cpcount)
2675 cpnow = cpcount - cpsum;
2676 cpsum += cpnow;
2677 if (!sl->page) {
2678 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
2679 hanum);
2680 return;
2681 }
2682 local_irq_save(flags);
2683 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2684 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2685 memcpy(address,buffer,cpnow);
2686 flush_dcache_page(sl->page);
2687 kunmap_atomic(address, KM_BIO_SRC_IRQ);
2688 #else
2689 address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
2690 memcpy(address,buffer,cpnow);
2691 flush_dcache_page(sl->page);
2692 kunmap_atomic(address, KM_BH_IRQ);
2693 #endif
2694 local_irq_restore(flags);
2695 if (cpsum == cpcount)
2696 break;
2697 buffer += cpnow;
2698 }
2699 } else {
2700 TRACE(("copy_internal() count %d\n",cpcount));
2701 memcpy((char*)scp->request_buffer,buffer,cpcount);
2702 }
2703 }
2704
2705 static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
2706 {
2707 register gdth_ha_str *ha;
2708 unchar t;
2709 gdth_inq_data inq;
2710 gdth_rdcap_data rdc;
2711 gdth_sense_data sd;
2712 gdth_modep_data mpd;
2713
2714 ha = HADATA(gdth_ctr_tab[hanum]);
2715 t = scp->device->id;
2716 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2717 scp->cmnd[0],t));
2718
2719 scp->result = DID_OK << 16;
2720 scp->sense_buffer[0] = 0;
2721
2722 switch (scp->cmnd[0]) {
2723 case TEST_UNIT_READY:
2724 case VERIFY:
2725 case START_STOP:
2726 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2727 break;
2728
2729 case INQUIRY:
2730 TRACE2(("Inquiry hdrive %d devtype %d\n",
2731 t,ha->hdr[t].devtype));
2732 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2733 /* you can here set all disks to removable, if you want to do
2734 a flush using the ALLOW_MEDIUM_REMOVAL command */
2735 inq.modif_rmb = 0x00;
2736 if ((ha->hdr[t].devtype & 1) ||
2737 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2738 inq.modif_rmb = 0x80;
2739 inq.version = 2;
2740 inq.resp_aenc = 2;
2741 inq.add_length= 32;
2742 strcpy(inq.vendor,ha->oem_name);
2743 sprintf(inq.product,"Host Drive #%02d",t);
2744 strcpy(inq.revision," ");
2745 gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
2746 break;
2747
2748 case REQUEST_SENSE:
2749 TRACE2(("Request sense hdrive %d\n",t));
2750 sd.errorcode = 0x70;
2751 sd.segno = 0x00;
2752 sd.key = NO_SENSE;
2753 sd.info = 0;
2754 sd.add_length= 0;
2755 gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
2756 break;
2757
2758 case MODE_SENSE:
2759 TRACE2(("Mode sense hdrive %d\n",t));
2760 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2761 mpd.hd.data_length = sizeof(gdth_modep_data);
2762 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2763 mpd.hd.bd_length = sizeof(mpd.bd);
2764 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2765 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2766 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
2767 gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
2768 break;
2769
2770 case READ_CAPACITY:
2771 TRACE2(("Read capacity hdrive %d\n",t));
2772 if (ha->hdr[t].size > (ulong64)0xffffffff)
2773 rdc.last_block_no = 0xffffffff;
2774 else
2775 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2776 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
2777 gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
2778 break;
2779
2780 case SERVICE_ACTION_IN:
2781 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2782 (ha->cache_feat & GDT_64BIT)) {
2783 gdth_rdcap16_data rdc16;
2784
2785 TRACE2(("Read capacity (16) hdrive %d\n",t));
2786 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2787 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
2788 gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
2789 } else {
2790 scp->result = DID_ABORT << 16;
2791 }
2792 break;
2793
2794 default:
2795 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2796 break;
2797 }
2798
2799 if (!scp->SCp.have_data_in)
2800 scp->SCp.have_data_in++;
2801 else
2802 return 1;
2803
2804 return 0;
2805 }
2806
2807 static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
2808 {
2809 register gdth_ha_str *ha;
2810 register gdth_cmd_str *cmdp;
2811 struct scatterlist *sl;
2812 ulong32 cnt, blockcnt;
2813 ulong64 no, blockno;
2814 dma_addr_t phys_addr;
2815 int i, cmd_index, read_write, sgcnt, mode64;
2816 struct page *page;
2817 ulong offset;
2818
2819 ha = HADATA(gdth_ctr_tab[hanum]);
2820 cmdp = ha->pccb;
2821 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2822 scp->cmnd[0],scp->cmd_len,hdrive));
2823
2824 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2825 return 0;
2826
2827 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2828 /* test for READ_16, WRITE_16 if !mode64 ? ---
2829 not required, should not occur due to error return on
2830 READ_CAPACITY_16 */
2831
2832 cmdp->Service = CACHESERVICE;
2833 cmdp->RequestBuffer = scp;
2834 /* search free command index */
2835 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
2836 TRACE(("GDT: No free command index found\n"));
2837 return 0;
2838 }
2839 /* if it's the first command, set command semaphore */
2840 if (ha->cmd_cnt == 0)
2841 gdth_set_sema0(hanum);
2842
2843 /* fill command */
2844 read_write = 0;
2845 if (scp->SCp.sent_command != -1)
2846 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2847 else if (scp->cmnd[0] == RESERVE)
2848 cmdp->OpCode = GDT_RESERVE_DRV;
2849 else if (scp->cmnd[0] == RELEASE)
2850 cmdp->OpCode = GDT_RELEASE_DRV;
2851 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2852 if (scp->cmnd[4] & 1) /* prevent ? */
2853 cmdp->OpCode = GDT_MOUNT;
2854 else if (scp->cmnd[3] & 1) /* removable drive ? */
2855 cmdp->OpCode = GDT_UNMOUNT;
2856 else
2857 cmdp->OpCode = GDT_FLUSH;
2858 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2859 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2860 ) {
2861 read_write = 1;
2862 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2863 (ha->cache_feat & GDT_WR_THROUGH)))
2864 cmdp->OpCode = GDT_WRITE_THR;
2865 else
2866 cmdp->OpCode = GDT_WRITE;
2867 } else {
2868 read_write = 2;
2869 cmdp->OpCode = GDT_READ;
2870 }
2871
2872 cmdp->BoardNode = LOCALBOARD;
2873 if (mode64) {
2874 cmdp->u.cache64.DeviceNo = hdrive;
2875 cmdp->u.cache64.BlockNo = 1;
2876 cmdp->u.cache64.sg_canz = 0;
2877 } else {
2878 cmdp->u.cache.DeviceNo = hdrive;
2879 cmdp->u.cache.BlockNo = 1;
2880 cmdp->u.cache.sg_canz = 0;
2881 }
2882
2883 if (read_write) {
2884 if (scp->cmd_len == 16) {
2885 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2886 blockno = be64_to_cpu(no);
2887 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2888 blockcnt = be32_to_cpu(cnt);
2889 } else if (scp->cmd_len == 10) {
2890 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2891 blockno = be32_to_cpu(no);
2892 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2893 blockcnt = be16_to_cpu(cnt);
2894 } else {
2895 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2896 blockno = be32_to_cpu(no) & 0x001fffffUL;
2897 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2898 }
2899 if (mode64) {
2900 cmdp->u.cache64.BlockNo = blockno;
2901 cmdp->u.cache64.BlockCnt = blockcnt;
2902 } else {
2903 cmdp->u.cache.BlockNo = (ulong32)blockno;
2904 cmdp->u.cache.BlockCnt = blockcnt;
2905 }
2906
2907 if (scp->use_sg) {
2908 sl = (struct scatterlist *)scp->request_buffer;
2909 sgcnt = scp->use_sg;
2910 scp->SCp.Status = GDTH_MAP_SG;
2911 scp->SCp.Message = (read_write == 1 ?
2912 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2913 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2914 if (mode64) {
2915 cmdp->u.cache64.DestAddr= (ulong64)-1;
2916 cmdp->u.cache64.sg_canz = sgcnt;
2917 for (i=0; i<sgcnt; ++i,++sl) {
2918 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2919 #ifdef GDTH_DMA_STATISTICS
2920 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2921 ha->dma64_cnt++;
2922 else
2923 ha->dma32_cnt++;
2924 #endif
2925 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2926 }
2927 } else {
2928 cmdp->u.cache.DestAddr= 0xffffffff;
2929 cmdp->u.cache.sg_canz = sgcnt;
2930 for (i=0; i<sgcnt; ++i,++sl) {
2931 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2932 #ifdef GDTH_DMA_STATISTICS
2933 ha->dma32_cnt++;
2934 #endif
2935 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2936 }
2937 }
2938
2939 #ifdef GDTH_STATISTICS
2940 if (max_sg < (ulong32)sgcnt) {
2941 max_sg = (ulong32)sgcnt;
2942 TRACE3(("GDT: max_sg = %d\n",max_sg));
2943 }
2944 #endif
2945
2946 } else if (scp->request_bufflen) {
2947 scp->SCp.Status = GDTH_MAP_SINGLE;
2948 scp->SCp.Message = (read_write == 1 ?
2949 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2950 page = virt_to_page(scp->request_buffer);
2951 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2952 phys_addr = pci_map_page(ha->pdev,page,offset,
2953 scp->request_bufflen,scp->SCp.Message);
2954 scp->SCp.dma_handle = phys_addr;
2955 if (mode64) {
2956 if (ha->cache_feat & SCATTER_GATHER) {
2957 cmdp->u.cache64.DestAddr = (ulong64)-1;
2958 cmdp->u.cache64.sg_canz = 1;
2959 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2960 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2961 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2962 } else {
2963 cmdp->u.cache64.DestAddr = phys_addr;
2964 cmdp->u.cache64.sg_canz= 0;
2965 }
2966 } else {
2967 if (ha->cache_feat & SCATTER_GATHER) {
2968 cmdp->u.cache.DestAddr = 0xffffffff;
2969 cmdp->u.cache.sg_canz = 1;
2970 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2971 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2972 cmdp->u.cache.sg_lst[1].sg_len = 0;
2973 } else {
2974 cmdp->u.cache.DestAddr = phys_addr;
2975 cmdp->u.cache.sg_canz= 0;
2976 }
2977 }
2978 }
2979 }
2980 /* evaluate command size, check space */
2981 if (mode64) {
2982 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2983 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2984 cmdp->u.cache64.sg_lst[0].sg_ptr,
2985 cmdp->u.cache64.sg_lst[0].sg_len));
2986 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2987 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2988 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2989 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2990 } else {
2991 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2992 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2993 cmdp->u.cache.sg_lst[0].sg_ptr,
2994 cmdp->u.cache.sg_lst[0].sg_len));
2995 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2996 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2997 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2998 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2999 }
3000 if (ha->cmd_len & 3)
3001 ha->cmd_len += (4 - (ha->cmd_len & 3));
3002
3003 if (ha->cmd_cnt > 0) {
3004 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3005 ha->ic_all_size) {
3006 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
3007 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3008 return 0;
3009 }
3010 }
3011
3012 /* copy command */
3013 gdth_copy_command(hanum);
3014 return cmd_index;
3015 }
3016
3017 static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
3018 {
3019 register gdth_ha_str *ha;
3020 register gdth_cmd_str *cmdp;
3021 struct scatterlist *sl;
3022 ushort i;
3023 dma_addr_t phys_addr, sense_paddr;
3024 int cmd_index, sgcnt, mode64;
3025 unchar t,l;
3026 struct page *page;
3027 ulong offset;
3028
3029 ha = HADATA(gdth_ctr_tab[hanum]);
3030 t = scp->device->id;
3031 l = scp->device->lun;
3032 cmdp = ha->pccb;
3033 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
3034 scp->cmnd[0],b,t,l));
3035
3036 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3037 return 0;
3038
3039 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
3040
3041 cmdp->Service = SCSIRAWSERVICE;
3042 cmdp->RequestBuffer = scp;
3043 /* search free command index */
3044 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3045 TRACE(("GDT: No free command index found\n"));
3046 return 0;
3047 }
3048 /* if it's the first command, set command semaphore */
3049 if (ha->cmd_cnt == 0)
3050 gdth_set_sema0(hanum);
3051
3052 /* fill command */
3053 if (scp->SCp.sent_command != -1) {
3054 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
3055 cmdp->BoardNode = LOCALBOARD;
3056 if (mode64) {
3057 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
3058 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3059 cmdp->OpCode, cmdp->u.raw64.direction));
3060 /* evaluate command size */
3061 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
3062 } else {
3063 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
3064 TRACE2(("special raw cmd 0x%x param 0x%x\n",
3065 cmdp->OpCode, cmdp->u.raw.direction));
3066 /* evaluate command size */
3067 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
3068 }
3069
3070 } else {
3071 page = virt_to_page(scp->sense_buffer);
3072 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
3073 sense_paddr = pci_map_page(ha->pdev,page,offset,
3074 16,PCI_DMA_FROMDEVICE);
3075 *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
3076 /* high part, if 64bit */
3077 *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
3078 cmdp->OpCode = GDT_WRITE; /* always */
3079 cmdp->BoardNode = LOCALBOARD;
3080 if (mode64) {
3081 cmdp->u.raw64.reserved = 0;
3082 cmdp->u.raw64.mdisc_time = 0;
3083 cmdp->u.raw64.mcon_time = 0;
3084 cmdp->u.raw64.clen = scp->cmd_len;
3085 cmdp->u.raw64.target = t;
3086 cmdp->u.raw64.lun = l;
3087 cmdp->u.raw64.bus = b;
3088 cmdp->u.raw64.priority = 0;
3089 cmdp->u.raw64.sdlen = scp->request_bufflen;
3090 cmdp->u.raw64.sense_len = 16;
3091 cmdp->u.raw64.sense_data = sense_paddr;
3092 cmdp->u.raw64.direction =
3093 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3094 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
3095 } else {
3096 cmdp->u.raw.reserved = 0;
3097 cmdp->u.raw.mdisc_time = 0;
3098 cmdp->u.raw.mcon_time = 0;
3099 cmdp->u.raw.clen = scp->cmd_len;
3100 cmdp->u.raw.target = t;
3101 cmdp->u.raw.lun = l;
3102 cmdp->u.raw.bus = b;
3103 cmdp->u.raw.priority = 0;
3104 cmdp->u.raw.link_p = 0;
3105 cmdp->u.raw.sdlen = scp->request_bufflen;
3106 cmdp->u.raw.sense_len = 16;
3107 cmdp->u.raw.sense_data = sense_paddr;
3108 cmdp->u.raw.direction =
3109 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
3110 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
3111 }
3112
3113 if (scp->use_sg) {
3114 sl = (struct scatterlist *)scp->request_buffer;
3115 sgcnt = scp->use_sg;
3116 scp->SCp.Status = GDTH_MAP_SG;
3117 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3118 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
3119 if (mode64) {
3120 cmdp->u.raw64.sdata = (ulong64)-1;
3121 cmdp->u.raw64.sg_ranz = sgcnt;
3122 for (i=0; i<sgcnt; ++i,++sl) {
3123 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
3124 #ifdef GDTH_DMA_STATISTICS
3125 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
3126 ha->dma64_cnt++;
3127 else
3128 ha->dma32_cnt++;
3129 #endif
3130 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
3131 }
3132 } else {
3133 cmdp->u.raw.sdata = 0xffffffff;
3134 cmdp->u.raw.sg_ranz = sgcnt;
3135 for (i=0; i<sgcnt; ++i,++sl) {
3136 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
3137 #ifdef GDTH_DMA_STATISTICS
3138 ha->dma32_cnt++;
3139 #endif
3140 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
3141 }
3142 }
3143
3144 #ifdef GDTH_STATISTICS
3145 if (max_sg < sgcnt) {
3146 max_sg = sgcnt;
3147 TRACE3(("GDT: max_sg = %d\n",sgcnt));
3148 }
3149 #endif
3150
3151 } else if (scp->request_bufflen) {
3152 scp->SCp.Status = GDTH_MAP_SINGLE;
3153 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
3154 page = virt_to_page(scp->request_buffer);
3155 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
3156 phys_addr = pci_map_page(ha->pdev,page,offset,
3157 scp->request_bufflen,scp->SCp.Message);
3158 scp->SCp.dma_handle = phys_addr;
3159
3160 if (mode64) {
3161 if (ha->raw_feat & SCATTER_GATHER) {
3162 cmdp->u.raw64.sdata = (ulong64)-1;
3163 cmdp->u.raw64.sg_ranz= 1;
3164 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
3165 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
3166 cmdp->u.raw64.sg_lst[1].sg_len = 0;
3167 } else {
3168 cmdp->u.raw64.sdata = phys_addr;
3169 cmdp->u.raw64.sg_ranz= 0;
3170 }
3171 } else {
3172 if (ha->raw_feat & SCATTER_GATHER) {
3173 cmdp->u.raw.sdata = 0xffffffff;
3174 cmdp->u.raw.sg_ranz= 1;
3175 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
3176 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
3177 cmdp->u.raw.sg_lst[1].sg_len = 0;
3178 } else {
3179 cmdp->u.raw.sdata = phys_addr;
3180 cmdp->u.raw.sg_ranz= 0;
3181 }
3182 }
3183 }
3184 if (mode64) {
3185 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3186 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
3187 cmdp->u.raw64.sg_lst[0].sg_ptr,
3188 cmdp->u.raw64.sg_lst[0].sg_len));
3189 /* evaluate command size */
3190 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
3191 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
3192 } else {
3193 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
3194 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
3195 cmdp->u.raw.sg_lst[0].sg_ptr,
3196 cmdp->u.raw.sg_lst[0].sg_len));
3197 /* evaluate command size */
3198 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
3199 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
3200 }
3201 }
3202 /* check space */
3203 if (ha->cmd_len & 3)
3204 ha->cmd_len += (4 - (ha->cmd_len & 3));
3205
3206 if (ha->cmd_cnt > 0) {
3207 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3208 ha->ic_all_size) {
3209 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
3210 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3211 return 0;
3212 }
3213 }
3214
3215 /* copy command */
3216 gdth_copy_command(hanum);
3217 return cmd_index;
3218 }
3219
3220 static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
3221 {
3222 register gdth_ha_str *ha;
3223 register gdth_cmd_str *cmdp;
3224 int cmd_index;
3225
3226 ha = HADATA(gdth_ctr_tab[hanum]);
3227 cmdp= ha->pccb;
3228 TRACE2(("gdth_special_cmd(): "));
3229
3230 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
3231 return 0;
3232
3233 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
3234 cmdp->RequestBuffer = scp;
3235
3236 /* search free command index */
3237 if (!(cmd_index=gdth_get_cmd_index(hanum))) {
3238 TRACE(("GDT: No free command index found\n"));
3239 return 0;
3240 }
3241
3242 /* if it's the first command, set command semaphore */
3243 if (ha->cmd_cnt == 0)
3244 gdth_set_sema0(hanum);
3245
3246 /* evaluate command size, check space */
3247 if (cmdp->OpCode == GDT_IOCTL) {
3248 TRACE2(("IOCTL\n"));
3249 ha->cmd_len =
3250 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
3251 } else if (cmdp->Service == CACHESERVICE) {
3252 TRACE2(("cache command %d\n",cmdp->OpCode));
3253 if (ha->cache_feat & GDT_64BIT)
3254 ha->cmd_len =
3255 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
3256 else
3257 ha->cmd_len =
3258 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
3259 } else if (cmdp->Service == SCSIRAWSERVICE) {
3260 TRACE2(("raw command %d\n",cmdp->OpCode));
3261 if (ha->raw_feat & GDT_64BIT)
3262 ha->cmd_len =
3263 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
3264 else
3265 ha->cmd_len =
3266 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
3267 }
3268
3269 if (ha->cmd_len & 3)
3270 ha->cmd_len += (4 - (ha->cmd_len & 3));
3271
3272 if (ha->cmd_cnt > 0) {
3273 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
3274 ha->ic_all_size) {
3275 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
3276 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
3277 return 0;
3278 }
3279 }
3280
3281 /* copy command */
3282 gdth_copy_command(hanum);
3283 return cmd_index;
3284 }
3285
3286
3287 /* Controller event handling functions */
3288 static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
3289 ushort idx, gdth_evt_data *evt)
3290 {
3291 gdth_evt_str *e;
3292 struct timeval tv;
3293
3294 /* no GDTH_LOCK_HA() ! */
3295 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
3296 if (source == 0) /* no source -> no event */
3297 return NULL;
3298
3299 if (ebuffer[elastidx].event_source == source &&
3300 ebuffer[elastidx].event_idx == idx &&
3301 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
3302 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
3303 (char *)&evt->eu, evt->size)) ||
3304 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
3305 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
3306 (char *)&evt->event_string)))) {
3307 e = &ebuffer[elastidx];
3308 do_gettimeofday(&tv);
3309 e->last_stamp = tv.tv_sec;
3310 ++e->same_count;
3311 } else {
3312 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
3313 ++elastidx;
3314 if (elastidx == MAX_EVENTS)
3315 elastidx = 0;
3316 if (elastidx == eoldidx) { /* reached mark ? */
3317 ++eoldidx;
3318 if (eoldidx == MAX_EVENTS)
3319 eoldidx = 0;
3320 }
3321 }
3322 e = &ebuffer[elastidx];
3323 e->event_source = source;
3324 e->event_idx = idx;
3325 do_gettimeofday(&tv);
3326 e->first_stamp = e->last_stamp = tv.tv_sec;
3327 e->same_count = 1;
3328 e->event_data = *evt;
3329 e->application = 0;
3330 }
3331 return e;
3332 }
3333
3334 static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
3335 {
3336 gdth_evt_str *e;
3337 int eindex;
3338 ulong flags;
3339
3340 TRACE2(("gdth_read_event() handle %d\n", handle));
3341 spin_lock_irqsave(&ha->smp_lock, flags);
3342 if (handle == -1)
3343 eindex = eoldidx;
3344 else
3345 eindex = handle;
3346 estr->event_source = 0;
3347
3348 if (eindex >= MAX_EVENTS) {
3349 spin_unlock_irqrestore(&ha->smp_lock, flags);
3350 return eindex;
3351 }
3352 e = &ebuffer[eindex];
3353 if (e->event_source != 0) {
3354 if (eindex != elastidx) {
3355 if (++eindex == MAX_EVENTS)
3356 eindex = 0;
3357 } else {
3358 eindex = -1;
3359 }
3360 memcpy(estr, e, sizeof(gdth_evt_str));
3361 }
3362 spin_unlock_irqrestore(&ha->smp_lock, flags);
3363 return eindex;
3364 }
3365
3366 static void gdth_readapp_event(gdth_ha_str *ha,
3367 unchar application, gdth_evt_str *estr)
3368 {
3369 gdth_evt_str *e;
3370 int eindex;
3371 ulong flags;
3372 unchar found = FALSE;
3373
3374 TRACE2(("gdth_readapp_event() app. %d\n", application));
3375 spin_lock_irqsave(&ha->smp_lock, flags);
3376 eindex = eoldidx;
3377 for (;;) {
3378 e = &ebuffer[eindex];
3379 if (e->event_source == 0)
3380 break;
3381 if ((e->application & application) == 0) {
3382 e->application |= application;
3383 found = TRUE;
3384 break;
3385 }
3386 if (eindex == elastidx)
3387 break;
3388 if (++eindex == MAX_EVENTS)
3389 eindex = 0;
3390 }
3391 if (found)
3392 memcpy(estr, e, sizeof(gdth_evt_str));
3393 else
3394 estr->event_source = 0;
3395 spin_unlock_irqrestore(&ha->smp_lock, flags);
3396 }
3397
3398 static void gdth_clear_events(void)
3399 {
3400 TRACE(("gdth_clear_events()"));
3401
3402 eoldidx = elastidx = 0;
3403 ebuffer[0].event_source = 0;
3404 }
3405
3406
3407 /* SCSI interface functions */
3408
3409 static irqreturn_t gdth_interrupt(int irq,void *dev_id)
3410 {
3411 gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
3412 register gdth_ha_str *ha;
3413 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3414 gdt6_dpram_str __iomem *dp6_ptr;
3415 gdt2_dpram_str __iomem *dp2_ptr;
3416 Scsi_Cmnd *scp;
3417 int hanum, rval, i;
3418 unchar IStatus;
3419 ushort Service;
3420 ulong flags = 0;
3421 #ifdef INT_COAL
3422 int coalesced = FALSE;
3423 int next = FALSE;
3424 gdth_coal_status *pcs = NULL;
3425 int act_int_coal = 0;
3426 #endif
3427
3428 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3429
3430 /* if polling and not from gdth_wait() -> return */
3431 if (gdth_polling) {
3432 if (!gdth_from_wait) {
3433 return IRQ_HANDLED;
3434 }
3435 }
3436
3437 if (!gdth_polling)
3438 spin_lock_irqsave(&ha2->smp_lock, flags);
3439 wait_index = 0;
3440
3441 /* search controller */
3442 if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
3443 /* spurious interrupt */
3444 if (!gdth_polling)
3445 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3446 return IRQ_HANDLED;
3447 }
3448 ha = HADATA(gdth_ctr_tab[hanum]);
3449
3450 #ifdef GDTH_STATISTICS
3451 ++act_ints;
3452 #endif
3453
3454 #ifdef INT_COAL
3455 /* See if the fw is returning coalesced status */
3456 if (IStatus == COALINDEX) {
3457 /* Coalesced status. Setup the initial status
3458 buffer pointer and flags */
3459 pcs = ha->coal_stat;
3460 coalesced = TRUE;
3461 next = TRUE;
3462 }
3463
3464 do {
3465 if (coalesced) {
3466 /* For coalesced requests all status
3467 information is found in the status buffer */
3468 IStatus = (unchar)(pcs->status & 0xff);
3469 }
3470 #endif
3471
3472 if (ha->type == GDT_EISA) {
3473 if (IStatus & 0x80) { /* error flag */
3474 IStatus &= ~0x80;
3475 ha->status = inw(ha->bmic + MAILBOXREG+8);
3476 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3477 } else /* no error */
3478 ha->status = S_OK;
3479 ha->info = inl(ha->bmic + MAILBOXREG+12);
3480 ha->service = inw(ha->bmic + MAILBOXREG+10);
3481 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3482
3483 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3484 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3485 } else if (ha->type == GDT_ISA) {
3486 dp2_ptr = ha->brd;
3487 if (IStatus & 0x80) { /* error flag */
3488 IStatus &= ~0x80;
3489 ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
3490 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3491 } else /* no error */
3492 ha->status = S_OK;
3493 ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
3494 ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
3495 ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
3496
3497 gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3498 gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3499 gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
3500 } else if (ha->type == GDT_PCI) {
3501 dp6_ptr = ha->brd;
3502 if (IStatus & 0x80) { /* error flag */
3503 IStatus &= ~0x80;
3504 ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
3505 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3506 } else /* no error */
3507 ha->status = S_OK;
3508 ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
3509 ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
3510 ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
3511
3512 gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3513 gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3514 gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
3515 } else if (ha->type == GDT_PCINEW) {
3516 if (IStatus & 0x80) { /* error flag */
3517 IStatus &= ~0x80;
3518 ha->status = inw(PTR2USHORT(&ha->plx->status));
3519 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3520 } else
3521 ha->status = S_OK;
3522 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3523 ha->service = inw(PTR2USHORT(&ha->plx->service));
3524 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3525
3526 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3527 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3528 } else if (ha->type == GDT_PCIMPR) {
3529 dp6m_ptr = ha->brd;
3530 if (IStatus & 0x80) { /* error flag */
3531 IStatus &= ~0x80;
3532 #ifdef INT_COAL
3533 if (coalesced)
3534 ha->status = pcs->ext_status && 0xffff;
3535 else
3536 #endif
3537 ha->status = gdth_readw(&dp6m_ptr->i960r.status);
3538 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3539 } else /* no error */
3540 ha->status = S_OK;
3541 #ifdef INT_COAL
3542 /* get information */
3543 if (coalesced) {
3544 ha->info = pcs->info0;
3545 ha->info2 = pcs->info1;
3546 ha->service = (pcs->ext_status >> 16) && 0xffff;
3547 } else
3548 #endif
3549 {
3550 ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
3551 ha->service = gdth_readw(&dp6m_ptr->i960r.service);
3552 ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
3553 }
3554 /* event string */
3555 if (IStatus == ASYNCINDEX) {
3556 if (ha->service != SCREENSERVICE &&
3557 (ha->fw_vers & 0xff) >= 0x1a) {
3558 ha->dvr.severity = gdth_readb
3559 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3560 for (i = 0; i < 256; ++i) {
3561 ha->dvr.event_string[i] = gdth_readb
3562 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3563 if (ha->dvr.event_string[i] == 0)
3564 break;
3565 }
3566 }
3567 }
3568 #ifdef INT_COAL
3569 /* Make sure that non coalesced interrupts get cleared
3570 before being handled by gdth_async_event/gdth_sync_event */
3571 if (!coalesced)
3572 #endif
3573 {
3574 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3575 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3576 }
3577 } else {
3578 TRACE2(("gdth_interrupt() unknown controller type\n"));
3579 if (!gdth_polling)
3580 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3581 return IRQ_HANDLED;
3582 }
3583
3584 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3585 IStatus,ha->status,ha->info));
3586
3587 if (gdth_from_wait) {
3588 wait_hanum = hanum;
3589 wait_index = (int)IStatus;
3590 }
3591
3592 if (IStatus == ASYNCINDEX) {
3593 TRACE2(("gdth_interrupt() async. event\n"));
3594 gdth_async_event(hanum);
3595 if (!gdth_polling)
3596 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3597 gdth_next(hanum);
3598 return IRQ_HANDLED;
3599 }
3600
3601 if (IStatus == SPEZINDEX) {
3602 TRACE2(("Service unknown or not initialized !\n"));
3603 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3604 ha->dvr.eu.driver.ionode = hanum;
3605 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3606 if (!gdth_polling)
3607 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3608 return IRQ_HANDLED;
3609 }
3610 scp = ha->cmd_tab[IStatus-2].cmnd;
3611 Service = ha->cmd_tab[IStatus-2].service;
3612 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3613 if (scp == UNUSED_CMND) {
3614 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3615 ha->dvr.size = sizeof(ha->dvr.eu.driver);
3616 ha->dvr.eu.driver.ionode = hanum;
3617 ha->dvr.eu.driver.index = IStatus;
3618 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3619 if (!gdth_polling)
3620 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3621 return IRQ_HANDLED;
3622 }
3623 if (scp == INTERNAL_CMND) {
3624 TRACE(("gdth_interrupt() answer to internal command\n"));
3625 if (!gdth_polling)
3626 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3627 return IRQ_HANDLED;
3628 }
3629
3630 TRACE(("gdth_interrupt() sync. status\n"));
3631 rval = gdth_sync_event(hanum,Service,IStatus,scp);
3632 if (!gdth_polling)
3633 spin_unlock_irqrestore(&ha2->smp_lock, flags);
3634 if (rval == 2) {
3635 gdth_putq(hanum,scp,scp->SCp.this_residual);
3636 } else if (rval == 1) {
3637 scp->scsi_done(scp);
3638 }
3639
3640 #ifdef INT_COAL
3641 if (coalesced) {
3642 /* go to the next status in the status buffer */
3643 ++pcs;
3644 #ifdef GDTH_STATISTICS
3645 ++act_int_coal;
3646 if (act_int_coal > max_int_coal) {
3647 max_int_coal = act_int_coal;
3648 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3649 }
3650 #endif
3651 /* see if there is another status */
3652 if (pcs->status == 0)
3653 /* Stop the coalesce loop */
3654 next = FALSE;
3655 }
3656 } while (next);
3657
3658 /* coalescing only for new GDT_PCIMPR controllers available */
3659 if (ha->type == GDT_PCIMPR && coalesced) {
3660 gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3661 gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
3662 }
3663 #endif
3664
3665 gdth_next(hanum);
3666 return IRQ_HANDLED;
3667 }
3668
3669 static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
3670 {
3671 register gdth_ha_str *ha;
3672 gdth_msg_str *msg;
3673 gdth_cmd_str *cmdp;
3674 unchar b, t;
3675
3676 ha = HADATA(gdth_ctr_tab[hanum]);
3677 cmdp = ha->pccb;
3678 TRACE(("gdth_sync_event() serv %d status %d\n",
3679 service,ha->status));
3680
3681 if (service == SCREENSERVICE) {
3682 msg = ha->pmsg;
3683 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3684 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3685 if (msg->msg_len > MSGLEN+1)
3686 msg->msg_len = MSGLEN+1;
3687 if (msg->msg_len)
3688 if (!(msg->msg_answer && msg->msg_ext)) {
3689 msg->msg_text[msg->msg_len] = '\0';
3690 printk("%s",msg->msg_text);
3691 }
3692
3693 if (msg->msg_ext && !msg->msg_answer) {
3694 while (gdth_test_busy(hanum))
3695 gdth_delay(0);
3696 cmdp->Service = SCREENSERVICE;
3697 cmdp->RequestBuffer = SCREEN_CMND;
3698 gdth_get_cmd_index(hanum);
3699 gdth_set_sema0(hanum);
3700 cmdp->OpCode = GDT_READ;
3701 cmdp->BoardNode = LOCALBOARD;
3702 cmdp->u.screen.reserved = 0;
3703 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3704 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3705 ha->cmd_offs_dpmem = 0;
3706 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3707 + sizeof(ulong64);
3708 ha->cmd_cnt = 0;
3709 gdth_copy_command(hanum);
3710 gdth_release_event(hanum);
3711 return 0;
3712 }
3713
3714 if (msg->msg_answer && msg->msg_alen) {
3715 /* default answers (getchar() not possible) */
3716 if (msg->msg_alen == 1) {
3717 msg->msg_alen = 0;
3718 msg->msg_len = 1;
3719 msg->msg_text[0] = 0;
3720 } else {
3721 msg->msg_alen -= 2;
3722 msg->msg_len = 2;
3723 msg->msg_text[0] = 1;
3724 msg->msg_text[1] = 0;
3725 }
3726 msg->msg_ext = 0;
3727 msg->msg_answer = 0;
3728 while (gdth_test_busy(hanum))
3729 gdth_delay(0);
3730 cmdp->Service = SCREENSERVICE;
3731 cmdp->RequestBuffer = SCREEN_CMND;
3732 gdth_get_cmd_index(hanum);
3733 gdth_set_sema0(hanum);
3734 cmdp->OpCode = GDT_WRITE;
3735 cmdp->BoardNode = LOCALBOARD;
3736 cmdp->u.screen.reserved = 0;
3737 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3738 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3739 ha->cmd_offs_dpmem = 0;
3740 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3741 + sizeof(ulong64);
3742 ha->cmd_cnt = 0;
3743 gdth_copy_command(hanum);
3744 gdth_release_event(hanum);
3745 return 0;
3746 }
3747 printk("\n");
3748
3749 } else {
3750 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
3751 t = scp->device->id;
3752 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3753 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3754 }
3755 /* cache or raw service */
3756 if (ha->status == S_BSY) {
3757 TRACE2(("Controller busy -> retry !\n"));
3758 if (scp->SCp.sent_command == GDT_MOUNT)
3759 scp->SCp.sent_command = GDT_CLUST_INFO;
3760 /* retry */
3761 return 2;
3762 }
3763 if (scp->SCp.Status == GDTH_MAP_SG)
3764 pci_unmap_sg(ha->pdev,scp->request_buffer,
3765 scp->use_sg,scp->SCp.Message);
3766 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3767 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3768 scp->request_bufflen,scp->SCp.Message);
3769 if (scp->SCp.buffer) {
3770 dma_addr_t addr;
3771 addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
3772 if (scp->host_scribble)
3773 addr += (dma_addr_t)
3774 ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
3775 pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
3776 }
3777
3778 if (ha->status == S_OK) {
3779 scp->SCp.Status = S_OK;
3780 scp->SCp.Message = ha->info;
3781 if (scp->SCp.sent_command != -1) {
3782 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3783 scp->SCp.sent_command));
3784 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3785 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3786 ha->hdr[t].cluster_type = (unchar)ha->info;
3787 if (!(ha->hdr[t].cluster_type &
3788 CLUSTER_MOUNTED)) {
3789 /* NOT MOUNTED -> MOUNT */
3790 scp->SCp.sent_command = GDT_MOUNT;
3791 if (ha->hdr[t].cluster_type &
3792 CLUSTER_RESERVED) {
3793 /* cluster drive RESERVED (on the other node) */
3794 scp->SCp.phase = -2; /* reservation conflict */
3795 }
3796 } else {
3797 scp->SCp.sent_command = -1;
3798 }
3799 } else {
3800 if (scp->SCp.sent_command == GDT_MOUNT) {
3801 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3802 ha->hdr[t].media_changed = TRUE;
3803 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3804 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3805 ha->hdr[t].media_changed = TRUE;
3806 }
3807 scp->SCp.sent_command = -1;
3808 }
3809 /* retry */
3810 scp->SCp.this_residual = HIGH_PRI;
3811 return 2;
3812 } else {
3813 /* RESERVE/RELEASE ? */
3814 if (scp->cmnd[0] == RESERVE) {
3815 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3816 } else if (scp->cmnd[0] == RELEASE) {
3817 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3818 }
3819 scp->result = DID_OK << 16;
3820 scp->sense_buffer[0] = 0;
3821 }
3822 } else {
3823 scp->SCp.Status = ha->status;
3824 scp->SCp.Message = ha->info;
3825
3826 if (scp->SCp.sent_command != -1) {
3827 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3828 scp->SCp.sent_command, ha->status));
3829 if (scp->SCp.sent_command == GDT_SCAN_START ||
3830 scp->SCp.sent_command == GDT_SCAN_END) {
3831 scp->SCp.sent_command = -1;
3832 /* retry */
3833 scp->SCp.this_residual = HIGH_PRI;
3834 return 2;
3835 }
3836 memset((char*)scp->sense_buffer,0,16);
3837 scp->sense_buffer[0] = 0x70;
3838 scp->sense_buffer[2] = NOT_READY;
3839 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3840 } else if (service == CACHESERVICE) {
3841 if (ha->status == S_CACHE_UNKNOWN &&
3842 (ha->hdr[t].cluster_type &
3843 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3844 /* bus reset -> force GDT_CLUST_INFO */
3845 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3846 }
3847 memset((char*)scp->sense_buffer,0,16);
3848 if (ha->status == (ushort)S_CACHE_RESERV) {
3849 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3850 } else {
3851 scp->sense_buffer[0] = 0x70;
3852 scp->sense_buffer[2] = NOT_READY;
3853 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3854 }
3855 if (scp->done != gdth_scsi_done) {
3856 ha->dvr.size = sizeof(ha->dvr.eu.sync);
3857 ha->dvr.eu.sync.ionode = hanum;
3858 ha->dvr.eu.sync.service = service;
3859 ha->dvr.eu.sync.status = ha->status;
3860 ha->dvr.eu.sync.info = ha->info;
3861 ha->dvr.eu.sync.hostdrive = t;
3862 if (ha->status >= 0x8000)
3863 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3864 else
3865 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3866 }
3867 } else {
3868 /* sense buffer filled from controller firmware (DMA) */
3869 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3870 scp->result = DID_BAD_TARGET << 16;
3871 } else {
3872 scp->result = (DID_OK << 16) | ha->info;
3873 }
3874 }
3875 }
3876 if (!scp->SCp.have_data_in)
3877 scp->SCp.have_data_in++;
3878 else
3879 return 1;
3880 }
3881
3882 return 0;
3883 }
3884
3885 static char *async_cache_tab[] = {
3886 /* 0*/ "\011\000\002\002\002\004\002\006\004"
3887 "GDT HA %u, service %u, async. status %u/%lu unknown",
3888 /* 1*/ "\011\000\002\002\002\004\002\006\004"
3889 "GDT HA %u, service %u, async. status %u/%lu unknown",
3890 /* 2*/ "\005\000\002\006\004"
3891 "GDT HA %u, Host Drive %lu not ready",
3892 /* 3*/ "\005\000\002\006\004"
3893 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3894 /* 4*/ "\005\000\002\006\004"
3895 "GDT HA %u, mirror update on Host Drive %lu failed",
3896 /* 5*/ "\005\000\002\006\004"
3897 "GDT HA %u, Mirror Drive %lu failed",
3898 /* 6*/ "\005\000\002\006\004"
3899 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3900 /* 7*/ "\005\000\002\006\004"
3901 "GDT HA %u, Host Drive %lu write protected",
3902 /* 8*/ "\005\000\002\006\004"
3903 "GDT HA %u, media changed in Host Drive %lu",
3904 /* 9*/ "\005\000\002\006\004"
3905 "GDT HA %u, Host Drive %lu is offline",
3906 /*10*/ "\005\000\002\006\004"
3907 "GDT HA %u, media change of Mirror Drive %lu",
3908 /*11*/ "\005\000\002\006\004"
3909 "GDT HA %u, Mirror Drive %lu is write protected",
3910 /*12*/ "\005\000\002\006\004"
3911 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3912 /*13*/ "\007\000\002\006\002\010\002"
3913 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3914 /*14*/ "\005\000\002\006\002"
3915 "GDT HA %u, Array Drive %u: FAIL state entered",
3916 /*15*/ "\005\000\002\006\002"
3917 "GDT HA %u, Array Drive %u: error",
3918 /*16*/ "\007\000\002\006\002\010\002"
3919 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3920 /*17*/ "\005\000\002\006\002"
3921 "GDT HA %u, Array Drive %u: parity build failed",
3922 /*18*/ "\005\000\002\006\002"
3923 "GDT HA %u, Array Drive %u: drive rebuild failed",
3924 /*19*/ "\005\000\002\010\002"
3925 "GDT HA %u, Test of Hot Fix %u failed",
3926 /*20*/ "\005\000\002\006\002"
3927 "GDT HA %u, Array Drive %u: drive build finished successfully",
3928 /*21*/ "\005\000\002\006\002"
3929 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3930 /*22*/ "\007\000\002\006\002\010\002"
3931 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3932 /*23*/ "\005\000\002\006\002"
3933 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3934 /*24*/ "\005\000\002\010\002"
3935 "GDT HA %u, mirror update on Cache Drive %u completed",
3936 /*25*/ "\005\000\002\010\002"
3937 "GDT HA %u, mirror update on Cache Drive %lu failed",
3938 /*26*/ "\005\000\002\006\002"
3939 "GDT HA %u, Array Drive %u: drive rebuild started",
3940 /*27*/ "\005\000\002\012\001"
3941 "GDT HA %u, Fault bus %u: SHELF OK detected",
3942 /*28*/ "\005\000\002\012\001"
3943 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3944 /*29*/ "\007\000\002\012\001\013\001"
3945 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3946 /*30*/ "\007\000\002\012\001\013\001"
3947 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3948 /*31*/ "\007\000\002\012\001\013\001"
3949 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3950 /*32*/ "\007\000\002\012\001\013\001"
3951 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3952 /*33*/ "\007\000\002\012\001\013\001"
3953 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3954 /*34*/ "\011\000\002\012\001\013\001\006\004"
3955 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3956 /*35*/ "\007\000\002\012\001\013\001"
3957 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3958 /*36*/ "\007\000\002\012\001\013\001"
3959 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3960 /*37*/ "\007\000\002\012\001\006\004"
3961 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3962 /*38*/ "\007\000\002\012\001\013\001"
3963 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3964 /*39*/ "\007\000\002\012\001\013\001"
3965 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3966 /*40*/ "\007\000\002\012\001\013\001"
3967 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3968 /*41*/ "\007\000\002\012\001\013\001"
3969 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3970 /*42*/ "\005\000\002\006\002"
3971 "GDT HA %u, Array Drive %u: drive build started",
3972 /*43*/ "\003\000\002"
3973 "GDT HA %u, DRAM parity error detected",
3974 /*44*/ "\005\000\002\006\002"
3975 "GDT HA %u, Mirror Drive %u: update started",
3976 /*45*/ "\007\000\002\006\002\010\002"
3977 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3978 /*46*/ "\005\000\002\006\002"
3979 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3980 /*47*/ "\005\000\002\006\002"
3981 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3982 /*48*/ "\005\000\002\006\002"
3983 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3984 /*49*/ "\005\000\002\006\002"
3985 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3986 /*50*/ "\007\000\002\012\001\013\001"
3987 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3988 /*51*/ "\005\000\002\006\002"
3989 "GDT HA %u, Array Drive %u: expand started",
3990 /*52*/ "\005\000\002\006\002"
3991 "GDT HA %u, Array Drive %u: expand finished successfully",
3992 /*53*/ "\005\000\002\006\002"
3993 "GDT HA %u, Array Drive %u: expand failed",
3994 /*54*/ "\003\000\002"
3995 "GDT HA %u, CPU temperature critical",
3996 /*55*/ "\003\000\002"
3997 "GDT HA %u, CPU temperature OK",
3998 /*56*/ "\005\000\002\006\004"
3999 "GDT HA %u, Host drive %lu created",
4000 /*57*/ "\005\000\002\006\002"
4001 "GDT HA %u, Array Drive %u: expand restarted",
4002 /*58*/ "\005\000\002\006\002"
4003 "GDT HA %u, Array Drive %u: expand stopped",
4004 /*59*/ "\005\000\002\010\002"
4005 "GDT HA %u, Mirror Drive %u: drive build quited",
4006 /*60*/ "\005\000\002\006\002"
4007 "GDT HA %u, Array Drive %u: parity build quited",
4008 /*61*/ "\005\000\002\006\002"
4009 "GDT HA %u, Array Drive %u: drive rebuild quited",
4010 /*62*/ "\005\000\002\006\002"
4011 "GDT HA %u, Array Drive %u: parity verify started",
4012 /*63*/ "\005\000\002\006\002"
4013 "GDT HA %u, Array Drive %u: parity verify done",
4014 /*64*/ "\005\000\002\006\002"
4015 "GDT HA %u, Array Drive %u: parity verify failed",
4016 /*65*/ "\005\000\002\006\002"
4017 "GDT HA %u, Array Drive %u: parity error detected",
4018 /*66*/ "\005\000\002\006\002"
4019 "GDT HA %u, Array Drive %u: parity verify quited",
4020 /*67*/ "\005\000\002\006\002"
4021 "GDT HA %u, Host Drive %u reserved",
4022 /*68*/ "\005\000\002\006\002"
4023 "GDT HA %u, Host Drive %u mounted and released",
4024 /*69*/ "\005\000\002\006\002"
4025 "GDT HA %u, Host Drive %u released",
4026 /*70*/ "\003\000\002"
4027 "GDT HA %u, DRAM error detected and corrected with ECC",
4028 /*71*/ "\003\000\002"
4029 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
4030 /*72*/ "\011\000\002\012\001\013\001\014\001"
4031 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
4032 /*73*/ "\005\000\002\006\002"
4033 "GDT HA %u, Host drive %u resetted locally",
4034 /*74*/ "\005\000\002\006\002"
4035 "GDT HA %u, Host drive %u resetted remotely",
4036 /*75*/ "\003\000\002"
4037 "GDT HA %u, async. status 75 unknown",
4038 };
4039
4040
4041 static int gdth_async_event(int hanum)
4042 {
4043 gdth_ha_str *ha;
4044 gdth_cmd_str *cmdp;
4045 int cmd_index;
4046
4047 ha = HADATA(gdth_ctr_tab[hanum]);
4048 cmdp= ha->pccb;
4049 TRACE2(("gdth_async_event() ha %d serv %d\n",
4050 hanum,ha->service));
4051
4052 if (ha->service == SCREENSERVICE) {
4053 if (ha->status == MSG_REQUEST) {
4054 while (gdth_test_busy(hanum))
4055 gdth_delay(0);
4056 cmdp->Service = SCREENSERVICE;
4057 cmdp->RequestBuffer = SCREEN_CMND;
4058 cmd_index = gdth_get_cmd_index(hanum);
4059 gdth_set_sema0(hanum);
4060 cmdp->OpCode = GDT_READ;
4061 cmdp->BoardNode = LOCALBOARD;
4062 cmdp->u.screen.reserved = 0;
4063 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
4064 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
4065 ha->cmd_offs_dpmem = 0;
4066 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
4067 + sizeof(ulong64);
4068 ha->cmd_cnt = 0;
4069 gdth_copy_command(hanum);
4070 if (ha->type == GDT_EISA)
4071 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
4072 else if (ha->type == GDT_ISA)
4073 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
4074 else
4075 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
4076 (ushort)((ha->brd_phys>>3)&0x1f));
4077 gdth_release_event(hanum);
4078 }
4079
4080 } else {
4081 if (ha->type == GDT_PCIMPR &&
4082 (ha->fw_vers & 0xff) >= 0x1a) {
4083 ha->dvr.size = 0;
4084 ha->dvr.eu.async.ionode = hanum;
4085 ha->dvr.eu.async.status = ha->status;
4086 /* severity and event_string already set! */
4087 } else {
4088 ha->dvr.size = sizeof(ha->dvr.eu.async);
4089 ha->dvr.eu.async.ionode = hanum;
4090 ha->dvr.eu.async.service = ha->service;
4091 ha->dvr.eu.async.status = ha->status;
4092 ha->dvr.eu.async.info = ha->info;
4093 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
4094 }
4095 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
4096 gdth_log_event( &ha->dvr, NULL );
4097
4098 /* new host drive from expand? */
4099 if (ha->service == CACHESERVICE && ha->status == 56) {
4100 TRACE2(("gdth_async_event(): new host drive %d created\n",
4101 (ushort)ha->info));
4102 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
4103 }
4104 }
4105 return 1;
4106 }
4107
4108 static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
4109 {
4110 gdth_stackframe stack;
4111 char *f = NULL;
4112 int i,j;
4113
4114 TRACE2(("gdth_log_event()\n"));
4115 if (dvr->size == 0) {
4116 if (buffer == NULL) {
4117 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
4118 } else {
4119 sprintf(buffer,"Adapter %d: %s\n",
4120 dvr->eu.async.ionode,dvr->event_string);
4121 }
4122 } else if (dvr->eu.async.service == CACHESERVICE &&
4123 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
4124 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
4125 dvr->eu.async.status));
4126
4127 f = async_cache_tab[dvr->eu.async.status];
4128
4129 /* i: parameter to push, j: stack element to fill */
4130 for (j=0,i=1; i < f[0]; i+=2) {
4131 switch (f[i+1]) {
4132 case 4:
4133 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
4134 break;
4135 case 2:
4136 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
4137 break;
4138 case 1:
4139 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
4140 break;
4141 default:
4142 break;
4143 }
4144 }
4145
4146 if (buffer == NULL) {
4147 printk(&f[(int)f[0]],stack);
4148 printk("\n");
4149 } else {
4150 sprintf(buffer,&f[(int)f[0]],stack);
4151 }
4152
4153 } else {
4154 if (buffer == NULL) {
4155 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
4156 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4157 } else {
4158 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
4159 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
4160 }
4161 }
4162 }
4163
4164 #ifdef GDTH_STATISTICS
4165 static void gdth_timeout(ulong data)
4166 {
4167 ulong32 i;
4168 Scsi_Cmnd *nscp;
4169 gdth_ha_str *ha;
4170 ulong flags;
4171 int hanum = 0;
4172
4173 ha = HADATA(gdth_ctr_tab[hanum]);
4174 spin_lock_irqsave(&ha->smp_lock, flags);
4175
4176 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
4177 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
4178 ++act_stats;
4179
4180 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
4181 ++act_rq;
4182
4183 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
4184 act_ints, act_ios, act_stats, act_rq));
4185 act_ints = act_ios = 0;
4186
4187 gdth_timer.expires = jiffies + 30 * HZ;
4188 add_timer(&gdth_timer);
4189 spin_unlock_irqrestore(&ha->smp_lock, flags);
4190 }
4191 #endif
4192
4193 static void __init internal_setup(char *str,int *ints)
4194 {
4195 int i, argc;
4196 char *cur_str, *argv;
4197
4198 TRACE2(("internal_setup() str %s ints[0] %d\n",
4199 str ? str:"NULL", ints ? ints[0]:0));
4200
4201 /* read irq[] from ints[] */
4202 if (ints) {
4203 argc = ints[0];
4204 if (argc > 0) {
4205 if (argc > MAXHA)
4206 argc = MAXHA;
4207 for (i = 0; i < argc; ++i)
4208 irq[i] = ints[i+1];
4209 }
4210 }
4211
4212 /* analyse string */
4213 argv = str;
4214 while (argv && (cur_str = strchr(argv, ':'))) {
4215 int val = 0, c = *++cur_str;
4216
4217 if (c == 'n' || c == 'N')
4218 val = 0;
4219 else if (c == 'y' || c == 'Y')
4220 val = 1;
4221 else
4222 val = (int)simple_strtoul(cur_str, NULL, 0);
4223
4224 if (!strncmp(argv, "disable:", 8))
4225 disable = val;
4226 else if (!strncmp(argv, "reserve_mode:", 13))
4227 reserve_mode = val;
4228 else if (!strncmp(argv, "reverse_scan:", 13))
4229 reverse_scan = val;
4230 else if (!strncmp(argv, "hdr_channel:", 12))
4231 hdr_channel = val;
4232 else if (!strncmp(argv, "max_ids:", 8))
4233 max_ids = val;
4234 else if (!strncmp(argv, "rescan:", 7))
4235 rescan = val;
4236 else if (!strncmp(argv, "virt_ctr:", 9))
4237 virt_ctr = val;
4238 else if (!strncmp(argv, "shared_access:", 14))
4239 shared_access = val;
4240 else if (!strncmp(argv, "probe_eisa_isa:", 15))
4241 probe_eisa_isa = val;
4242 else if (!strncmp(argv, "reserve_list:", 13)) {
4243 reserve_list[0] = val;
4244 for (i = 1; i < MAX_RES_ARGS; i++) {
4245 cur_str = strchr(cur_str, ',');
4246 if (!cur_str)
4247 break;
4248 if (!isdigit((int)*++cur_str)) {
4249 --cur_str;
4250 break;
4251 }
4252 reserve_list[i] =
4253 (int)simple_strtoul(cur_str, NULL, 0);
4254 }
4255 if (!cur_str)
4256 break;
4257 argv = ++cur_str;
4258 continue;
4259 }
4260
4261 if ((argv = strchr(argv, ',')))
4262 ++argv;
4263 }
4264 }
4265
4266 int __init option_setup(char *str)
4267 {
4268 int ints[MAXHA];
4269 char *cur = str;
4270 int i = 1;
4271
4272 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
4273
4274 while (cur && isdigit(*cur) && i <= MAXHA) {
4275 ints[i++] = simple_strtoul(cur, NULL, 0);
4276 if ((cur = strchr(cur, ',')) != NULL) cur++;
4277 }
4278
4279 ints[0] = i - 1;
4280 internal_setup(cur, ints);
4281 return 1;
4282 }
4283
4284 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4285 static int __init gdth_detect(struct scsi_host_template *shtp)
4286 #else
4287 static int __init gdth_detect(Scsi_Host_Template *shtp)
4288 #endif
4289 {
4290 struct Scsi_Host *shp;
4291 gdth_pci_str pcistr[MAXHA];
4292 gdth_ha_str *ha;
4293 ulong32 isa_bios;
4294 ushort eisa_slot;
4295 int i,hanum,cnt,ctr,err;
4296 unchar b;
4297
4298
4299 #ifdef DEBUG_GDTH
4300 printk("GDT: This driver contains debugging information !! Trace level = %d\n",
4301 DebugState);
4302 printk(" Destination of debugging information: ");
4303 #ifdef __SERIAL__
4304 #ifdef __COM2__
4305 printk("Serial port COM2\n");
4306 #else
4307 printk("Serial port COM1\n");
4308 #endif
4309 #else
4310 printk("Console\n");
4311 #endif
4312 gdth_delay(3000);
4313 #endif
4314
4315 TRACE(("gdth_detect()\n"));
4316
4317 if (disable) {
4318 printk("GDT-HA: Controller driver disabled from command line !\n");
4319 return 0;
4320 }
4321
4322 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
4323 /* initializations */
4324 gdth_polling = TRUE; b = 0;
4325 gdth_clear_events();
4326
4327 /* As default we do not probe for EISA or ISA controllers */
4328 if (probe_eisa_isa) {
4329 /* scanning for controllers, at first: ISA controller */
4330 for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
4331 dma_addr_t scratch_dma_handle;
4332 scratch_dma_handle = 0;
4333
4334 if (gdth_ctr_count >= MAXHA)
4335 break;
4336 if (gdth_search_isa(isa_bios)) { /* controller found */
4337 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4338 if (shp == NULL)
4339 continue;
4340
4341 ha = HADATA(shp);
4342 if (!gdth_init_isa(isa_bios,ha)) {
4343 scsi_unregister(shp);
4344 continue;
4345 }
4346 #ifdef __ia64__
4347 break;
4348 #else
4349 /* controller found and initialized */
4350 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4351 isa_bios,ha->irq,ha->drq);
4352
4353 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
4354 printk("GDT-ISA: Unable to allocate IRQ\n");
4355 scsi_unregister(shp);
4356 continue;
4357 }
4358 if (request_dma(ha->drq,"gdth")) {
4359 printk("GDT-ISA: Unable to allocate DMA channel\n");
4360 free_irq(ha->irq,ha);
4361 scsi_unregister(shp);
4362 continue;
4363 }
4364 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4365 enable_dma(ha->drq);
4366 shp->unchecked_isa_dma = 1;
4367 shp->irq = ha->irq;
4368 shp->dma_channel = ha->drq;
4369 hanum = gdth_ctr_count;
4370 gdth_ctr_tab[gdth_ctr_count++] = shp;
4371 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4372
4373 NUMDATA(shp)->hanum = (ushort)hanum;
4374 NUMDATA(shp)->busnum= 0;
4375
4376 ha->pccb = CMDDATA(shp);
4377 ha->ccb_phys = 0L;
4378 ha->pdev = NULL;
4379 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4380 &scratch_dma_handle);
4381 ha->scratch_phys = scratch_dma_handle;
4382 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4383 &scratch_dma_handle);
4384 ha->msg_phys = scratch_dma_handle;
4385 #ifdef INT_COAL
4386 ha->coal_stat = (gdth_coal_status *)
4387 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4388 MAXOFFSETS, &scratch_dma_handle);
4389 ha->coal_stat_phys = scratch_dma_handle;
4390 #endif
4391
4392 ha->scratch_busy = FALSE;
4393 ha->req_first = NULL;
4394 ha->tid_cnt = MAX_HDRIVES;
4395 if (max_ids > 0 && max_ids < ha->tid_cnt)
4396 ha->tid_cnt = max_ids;
4397 for (i=0; i<GDTH_MAXCMDS; ++i)
4398 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4399 ha->scan_mode = rescan ? 0x10 : 0;
4400
4401 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4402 !gdth_search_drives(hanum)) {
4403 printk("GDT-ISA: Error during device scan\n");
4404 --gdth_ctr_count;
4405 --gdth_ctr_vcount;
4406
4407 #ifdef INT_COAL
4408 if (ha->coal_stat)
4409 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4410 MAXOFFSETS, ha->coal_stat,
4411 ha->coal_stat_phys);
4412 #endif
4413 if (ha->pscratch)
4414 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4415 ha->pscratch, ha->scratch_phys);
4416 if (ha->pmsg)
4417 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4418 ha->pmsg, ha->msg_phys);
4419
4420 free_irq(ha->irq,ha);
4421 scsi_unregister(shp);
4422 continue;
4423 }
4424 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4425 hdr_channel = ha->bus_cnt;
4426 ha->virt_bus = hdr_channel;
4427
4428 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4429 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4430 shp->highmem_io = 0;
4431 #endif
4432 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4433 shp->max_cmd_len = 16;
4434
4435 shp->max_id = ha->tid_cnt;
4436 shp->max_lun = MAXLUN;
4437 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4438 if (virt_ctr) {
4439 virt_ctr = 1;
4440 /* register addit. SCSI channels as virtual controllers */
4441 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4442 shp = scsi_register(shtp,sizeof(gdth_num_str));
4443 shp->unchecked_isa_dma = 1;
4444 shp->irq = ha->irq;
4445 shp->dma_channel = ha->drq;
4446 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4447 NUMDATA(shp)->hanum = (ushort)hanum;
4448 NUMDATA(shp)->busnum = b;
4449 }
4450 }
4451
4452 spin_lock_init(&ha->smp_lock);
4453 gdth_enable_int(hanum);
4454 #endif /* !__ia64__ */
4455 }
4456 }
4457
4458 /* scanning for EISA controllers */
4459 for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
4460 dma_addr_t scratch_dma_handle;
4461 scratch_dma_handle = 0;
4462
4463 if (gdth_ctr_count >= MAXHA)
4464 break;
4465 if (gdth_search_eisa(eisa_slot)) { /* controller found */
4466 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4467 if (shp == NULL)
4468 continue;
4469
4470 ha = HADATA(shp);
4471 if (!gdth_init_eisa(eisa_slot,ha)) {
4472 scsi_unregister(shp);
4473 continue;
4474 }
4475 /* controller found and initialized */
4476 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4477 eisa_slot>>12,ha->irq);
4478
4479 if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
4480 printk("GDT-EISA: Unable to allocate IRQ\n");
4481 scsi_unregister(shp);
4482 continue;
4483 }
4484 shp->unchecked_isa_dma = 0;
4485 shp->irq = ha->irq;
4486 shp->dma_channel = 0xff;
4487 hanum = gdth_ctr_count;
4488 gdth_ctr_tab[gdth_ctr_count++] = shp;
4489 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4490
4491 NUMDATA(shp)->hanum = (ushort)hanum;
4492 NUMDATA(shp)->busnum= 0;
4493 TRACE2(("EISA detect Bus 0: hanum %d\n",
4494 NUMDATA(shp)->hanum));
4495
4496 ha->pccb = CMDDATA(shp);
4497 ha->ccb_phys = 0L;
4498
4499 ha->pdev = NULL;
4500 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4501 &scratch_dma_handle);
4502 ha->scratch_phys = scratch_dma_handle;
4503 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4504 &scratch_dma_handle);
4505 ha->msg_phys = scratch_dma_handle;
4506 #ifdef INT_COAL
4507 ha->coal_stat = (gdth_coal_status *)
4508 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4509 MAXOFFSETS, &scratch_dma_handle);
4510 ha->coal_stat_phys = scratch_dma_handle;
4511 #endif
4512 ha->ccb_phys =
4513 pci_map_single(ha->pdev,ha->pccb,
4514 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4515 ha->scratch_busy = FALSE;
4516 ha->req_first = NULL;
4517 ha->tid_cnt = MAX_HDRIVES;
4518 if (max_ids > 0 && max_ids < ha->tid_cnt)
4519 ha->tid_cnt = max_ids;
4520 for (i=0; i<GDTH_MAXCMDS; ++i)
4521 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4522 ha->scan_mode = rescan ? 0x10 : 0;
4523
4524 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4525 !gdth_search_drives(hanum)) {
4526 printk("GDT-EISA: Error during device scan\n");
4527 --gdth_ctr_count;
4528 --gdth_ctr_vcount;
4529 #ifdef INT_COAL
4530 if (ha->coal_stat)
4531 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4532 MAXOFFSETS, ha->coal_stat,
4533 ha->coal_stat_phys);
4534 #endif
4535 if (ha->pscratch)
4536 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4537 ha->pscratch, ha->scratch_phys);
4538 if (ha->pmsg)
4539 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4540 ha->pmsg, ha->msg_phys);
4541 if (ha->ccb_phys)
4542 pci_unmap_single(ha->pdev,ha->ccb_phys,
4543 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4544 free_irq(ha->irq,ha);
4545 scsi_unregister(shp);
4546 continue;
4547 }
4548 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4549 hdr_channel = ha->bus_cnt;
4550 ha->virt_bus = hdr_channel;
4551
4552 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
4553 LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4554 shp->highmem_io = 0;
4555 #endif
4556 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4557 shp->max_cmd_len = 16;
4558
4559 shp->max_id = ha->tid_cnt;
4560 shp->max_lun = MAXLUN;
4561 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4562 if (virt_ctr) {
4563 virt_ctr = 1;
4564 /* register addit. SCSI channels as virtual controllers */
4565 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4566 shp = scsi_register(shtp,sizeof(gdth_num_str));
4567 shp->unchecked_isa_dma = 0;
4568 shp->irq = ha->irq;
4569 shp->dma_channel = 0xff;
4570 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4571 NUMDATA(shp)->hanum = (ushort)hanum;
4572 NUMDATA(shp)->busnum = b;
4573 }
4574 }
4575
4576 spin_lock_init(&ha->smp_lock);
4577 gdth_enable_int(hanum);
4578 }
4579 }
4580 }
4581
4582 /* scanning for PCI controllers */
4583 cnt = gdth_search_pci(pcistr);
4584 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
4585 gdth_sort_pci(pcistr,cnt);
4586 for (ctr = 0; ctr < cnt; ++ctr) {
4587 dma_addr_t scratch_dma_handle;
4588 scratch_dma_handle = 0;
4589
4590 if (gdth_ctr_count >= MAXHA)
4591 break;
4592 shp = scsi_register(shtp,sizeof(gdth_ext_str));
4593 if (shp == NULL)
4594 continue;
4595
4596 ha = HADATA(shp);
4597 if (!gdth_init_pci(&pcistr[ctr],ha)) {
4598 scsi_unregister(shp);
4599 continue;
4600 }
4601 /* controller found and initialized */
4602 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
4603 pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
4604
4605 if (request_irq(ha->irq, gdth_interrupt,
4606 IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
4607 {
4608 printk("GDT-PCI: Unable to allocate IRQ\n");
4609 scsi_unregister(shp);
4610 continue;
4611 }
4612 shp->unchecked_isa_dma = 0;
4613 shp->irq = ha->irq;
4614 shp->dma_channel = 0xff;
4615 hanum = gdth_ctr_count;
4616 gdth_ctr_tab[gdth_ctr_count++] = shp;
4617 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4618
4619 NUMDATA(shp)->hanum = (ushort)hanum;
4620 NUMDATA(shp)->busnum= 0;
4621
4622 ha->pccb = CMDDATA(shp);
4623 ha->ccb_phys = 0L;
4624
4625 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4626 &scratch_dma_handle);
4627 ha->scratch_phys = scratch_dma_handle;
4628 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4629 &scratch_dma_handle);
4630 ha->msg_phys = scratch_dma_handle;
4631 #ifdef INT_COAL
4632 ha->coal_stat = (gdth_coal_status *)
4633 pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
4634 MAXOFFSETS, &scratch_dma_handle);
4635 ha->coal_stat_phys = scratch_dma_handle;
4636 #endif
4637 ha->scratch_busy = FALSE;
4638 ha->req_first = NULL;
4639 ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
4640 if (max_ids > 0 && max_ids < ha->tid_cnt)
4641 ha->tid_cnt = max_ids;
4642 for (i=0; i<GDTH_MAXCMDS; ++i)
4643 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4644 ha->scan_mode = rescan ? 0x10 : 0;
4645
4646 err = FALSE;
4647 if (ha->pscratch == NULL || ha->pmsg == NULL ||
4648 !gdth_search_drives(hanum)) {
4649 err = TRUE;
4650 } else {
4651 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4652 hdr_channel = ha->bus_cnt;
4653 ha->virt_bus = hdr_channel;
4654
4655
4656 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
4657 scsi_set_pci_device(shp, pcistr[ctr].pdev);
4658 #endif
4659 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
4660 /* 64-bit DMA only supported from FW >= x.43 */
4661 (!ha->dma64_support)) {
4662 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4663 printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
4664 err = TRUE;
4665 }
4666 } else {
4667 shp->max_cmd_len = 16;
4668 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
4669 printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
4670 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
4671 printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
4672 err = TRUE;
4673 }
4674 }
4675 }
4676
4677 if (err) {
4678 printk("GDT-PCI %d: Error during device scan\n", hanum);
4679 --gdth_ctr_count;
4680 --gdth_ctr_vcount;
4681 #ifdef INT_COAL
4682 if (ha->coal_stat)
4683 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4684 MAXOFFSETS, ha->coal_stat,
4685 ha->coal_stat_phys);
4686 #endif
4687 if (ha->pscratch)
4688 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4689 ha->pscratch, ha->scratch_phys);
4690 if (ha->pmsg)
4691 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4692 ha->pmsg, ha->msg_phys);
4693 free_irq(ha->irq,ha);
4694 scsi_unregister(shp);
4695 continue;
4696 }
4697
4698 shp->max_id = ha->tid_cnt;
4699 shp->max_lun = MAXLUN;
4700 shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
4701 if (virt_ctr) {
4702 virt_ctr = 1;
4703 /* register addit. SCSI channels as virtual controllers */
4704 for (b = 1; b < ha->bus_cnt + 1; ++b) {
4705 shp = scsi_register(shtp,sizeof(gdth_num_str));
4706 shp->unchecked_isa_dma = 0;
4707 shp->irq = ha->irq;
4708 shp->dma_channel = 0xff;
4709 gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
4710 NUMDATA(shp)->hanum = (ushort)hanum;
4711 NUMDATA(shp)->busnum = b;
4712 }
4713 }
4714
4715 spin_lock_init(&ha->smp_lock);
4716 gdth_enable_int(hanum);
4717 }
4718
4719 TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
4720 if (gdth_ctr_count > 0) {
4721 #ifdef GDTH_STATISTICS
4722 TRACE2(("gdth_detect(): Initializing timer !\n"));
4723 init_timer(&gdth_timer);
4724 gdth_timer.expires = jiffies + HZ;
4725 gdth_timer.data = 0L;
4726 gdth_timer.function = gdth_timeout;
4727 add_timer(&gdth_timer);
4728 #endif
4729 major = register_chrdev(0,"gdth",&gdth_fops);
4730 notifier_disabled = 0;
4731 register_reboot_notifier(&gdth_notifier);
4732 }
4733 gdth_polling = FALSE;
4734 return gdth_ctr_vcount;
4735 }
4736
4737 static int gdth_release(struct Scsi_Host *shp)
4738 {
4739 int hanum;
4740 gdth_ha_str *ha;
4741
4742 TRACE2(("gdth_release()\n"));
4743 if (NUMDATA(shp)->busnum == 0) {
4744 hanum = NUMDATA(shp)->hanum;
4745 ha = HADATA(gdth_ctr_tab[hanum]);
4746 if (ha->sdev) {
4747 scsi_free_host_dev(ha->sdev);
4748 ha->sdev = NULL;
4749 }
4750 gdth_flush(hanum);
4751
4752 if (shp->irq) {
4753 free_irq(shp->irq,ha);
4754 }
4755 #ifndef __ia64__
4756 if (shp->dma_channel != 0xff) {
4757 free_dma(shp->dma_channel);
4758 }
4759 #endif
4760 #ifdef INT_COAL
4761 if (ha->coal_stat)
4762 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
4763 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
4764 #endif
4765 if (ha->pscratch)
4766 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4767 ha->pscratch, ha->scratch_phys);
4768 if (ha->pmsg)
4769 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4770 ha->pmsg, ha->msg_phys);
4771 if (ha->ccb_phys)
4772 pci_unmap_single(ha->pdev,ha->ccb_phys,
4773 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
4774 gdth_ctr_released++;
4775 TRACE2(("gdth_release(): HA %d of %d\n",
4776 gdth_ctr_released, gdth_ctr_count));
4777
4778 if (gdth_ctr_released == gdth_ctr_count) {
4779 #ifdef GDTH_STATISTICS
4780 del_timer(&gdth_timer);
4781 #endif
4782 unregister_chrdev(major,"gdth");
4783 unregister_reboot_notifier(&gdth_notifier);
4784 }
4785 }
4786
4787 scsi_unregister(shp);
4788 return 0;
4789 }
4790
4791
4792 static const char *gdth_ctr_name(int hanum)
4793 {
4794 gdth_ha_str *ha;
4795
4796 TRACE2(("gdth_ctr_name()\n"));
4797
4798 ha = HADATA(gdth_ctr_tab[hanum]);
4799
4800 if (ha->type == GDT_EISA) {
4801 switch (ha->stype) {
4802 case GDT3_ID:
4803 return("GDT3000/3020");
4804 case GDT3A_ID:
4805 return("GDT3000A/3020A/3050A");
4806 case GDT3B_ID:
4807 return("GDT3000B/3010A");
4808 }
4809 } else if (ha->type == GDT_ISA) {
4810 return("GDT2000/2020");
4811 } else if (ha->type == GDT_PCI) {
4812 switch (ha->stype) {
4813 case PCI_DEVICE_ID_VORTEX_GDT60x0:
4814 return("GDT6000/6020/6050");
4815 case PCI_DEVICE_ID_VORTEX_GDT6000B:
4816 return("GDT6000B/6010");
4817 }
4818 }
4819 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
4820
4821 return("");
4822 }
4823
4824 static const char *gdth_info(struct Scsi_Host *shp)
4825 {
4826 int hanum;
4827 gdth_ha_str *ha;
4828
4829 TRACE2(("gdth_info()\n"));
4830 hanum = NUMDATA(shp)->hanum;
4831 ha = HADATA(gdth_ctr_tab[hanum]);
4832
4833 return ((const char *)ha->binfo.type_string);
4834 }
4835
4836 static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
4837 {
4838 int i, hanum;
4839 gdth_ha_str *ha;
4840 ulong flags;
4841 Scsi_Cmnd *cmnd;
4842 unchar b;
4843
4844 TRACE2(("gdth_eh_bus_reset()\n"));
4845
4846 hanum = NUMDATA(scp->device->host)->hanum;
4847 b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
4848 ha = HADATA(gdth_ctr_tab[hanum]);
4849
4850 /* clear command tab */
4851 spin_lock_irqsave(&ha->smp_lock, flags);
4852 for (i = 0; i < GDTH_MAXCMDS; ++i) {
4853 cmnd = ha->cmd_tab[i].cmnd;
4854 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
4855 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4856 }
4857 spin_unlock_irqrestore(&ha->smp_lock, flags);
4858
4859 if (b == ha->virt_bus) {
4860 /* host drives */
4861 for (i = 0; i < MAX_HDRIVES; ++i) {
4862 if (ha->hdr[i].present) {
4863 spin_lock_irqsave(&ha->smp_lock, flags);
4864 gdth_polling = TRUE;
4865 while (gdth_test_busy(hanum))
4866 gdth_delay(0);
4867 if (gdth_internal_cmd(hanum, CACHESERVICE,
4868 GDT_CLUST_RESET, i, 0, 0))
4869 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
4870 gdth_polling = FALSE;
4871 spin_unlock_irqrestore(&ha->smp_lock, flags);
4872 }
4873 }
4874 } else {
4875 /* raw devices */
4876 spin_lock_irqsave(&ha->smp_lock, flags);
4877 for (i = 0; i < MAXID; ++i)
4878 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
4879 gdth_polling = TRUE;
4880 while (gdth_test_busy(hanum))
4881 gdth_delay(0);
4882 gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
4883 BUS_L2P(ha,b), 0, 0);
4884 gdth_polling = FALSE;
4885 spin_unlock_irqrestore(&ha->smp_lock, flags);
4886 }
4887 return SUCCESS;
4888 }
4889
4890 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4891 static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
4892 #else
4893 static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
4894 #endif
4895 {
4896 unchar b, t;
4897 int hanum;
4898 gdth_ha_str *ha;
4899 struct scsi_device *sd;
4900 unsigned capacity;
4901
4902 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
4903 sd = sdev;
4904 capacity = cap;
4905 #else
4906 sd = disk->device;
4907 capacity = disk->capacity;
4908 #endif
4909 hanum = NUMDATA(sd->host)->hanum;
4910 b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
4911 t = sd->id;
4912 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
4913 ha = HADATA(gdth_ctr_tab[hanum]);
4914
4915 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4916 /* raw device or host drive without mapping information */
4917 TRACE2(("Evaluate mapping\n"));
4918 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4919 } else {
4920 ip[0] = ha->hdr[t].heads;
4921 ip[1] = ha->hdr[t].secs;
4922 ip[2] = capacity / ip[0] / ip[1];
4923 }
4924
4925 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4926 ip[0],ip[1],ip[2]));
4927 return 0;
4928 }
4929
4930
4931 static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
4932 {
4933 int hanum;
4934 int priority;
4935
4936 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
4937
4938 scp->scsi_done = (void *)done;
4939 scp->SCp.have_data_in = 1;
4940 scp->SCp.phase = -1;
4941 scp->SCp.sent_command = -1;
4942 scp->SCp.Status = GDTH_MAP_NONE;
4943 scp->SCp.buffer = (struct scatterlist *)NULL;
4944
4945 hanum = NUMDATA(scp->device->host)->hanum;
4946 #ifdef GDTH_STATISTICS
4947 ++act_ios;
4948 #endif
4949
4950 priority = DEFAULT_PRI;
4951 if (scp->done == gdth_scsi_done)
4952 priority = scp->SCp.this_residual;
4953 else
4954 gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
4955
4956 gdth_putq( hanum, scp, priority );
4957 gdth_next( hanum );
4958 return 0;
4959 }
4960
4961
4962 static int gdth_open(struct inode *inode, struct file *filep)
4963 {
4964 gdth_ha_str *ha;
4965 int i;
4966
4967 for (i = 0; i < gdth_ctr_count; i++) {
4968 ha = HADATA(gdth_ctr_tab[i]);
4969 if (!ha->sdev)
4970 ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
4971 }
4972
4973 TRACE(("gdth_open()\n"));
4974 return 0;
4975 }
4976
4977 static int gdth_close(struct inode *inode, struct file *filep)
4978 {
4979 TRACE(("gdth_close()\n"));
4980 return 0;
4981 }
4982
4983 static int ioc_event(void __user *arg)
4984 {
4985 gdth_ioctl_event evt;
4986 gdth_ha_str *ha;
4987 ulong flags;
4988
4989 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
4990 evt.ionode >= gdth_ctr_count)
4991 return -EFAULT;
4992 ha = HADATA(gdth_ctr_tab[evt.ionode]);
4993
4994 if (evt.erase == 0xff) {
4995 if (evt.event.event_source == ES_TEST)
4996 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4997 else if (evt.event.event_source == ES_DRIVER)
4998 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4999 else if (evt.event.event_source == ES_SYNC)
5000 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
5001 else
5002 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
5003 spin_lock_irqsave(&ha->smp_lock, flags);
5004 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
5005 &evt.event.event_data);
5006 spin_unlock_irqrestore(&ha->smp_lock, flags);
5007 } else if (evt.erase == 0xfe) {
5008 gdth_clear_events();
5009 } else if (evt.erase == 0) {
5010 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
5011 } else {
5012 gdth_readapp_event(ha, evt.erase, &evt.event);
5013 }
5014 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
5015 return -EFAULT;
5016 return 0;
5017 }
5018
5019 static int ioc_lockdrv(void __user *arg)
5020 {
5021 gdth_ioctl_lockdrv ldrv;
5022 unchar i, j;
5023 ulong flags;
5024 gdth_ha_str *ha;
5025
5026 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
5027 ldrv.ionode >= gdth_ctr_count)
5028 return -EFAULT;
5029 ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
5030
5031 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
5032 j = ldrv.drives[i];
5033 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
5034 continue;
5035 if (ldrv.lock) {
5036 spin_lock_irqsave(&ha->smp_lock, flags);
5037 ha->hdr[j].lock = 1;
5038 spin_unlock_irqrestore(&ha->smp_lock, flags);
5039 gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
5040 gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
5041 } else {
5042 spin_lock_irqsave(&ha->smp_lock, flags);
5043 ha->hdr[j].lock = 0;
5044 spin_unlock_irqrestore(&ha->smp_lock, flags);
5045 gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
5046 gdth_next(ldrv.ionode);
5047 }
5048 }
5049 return 0;
5050 }
5051
5052 static int ioc_resetdrv(void __user *arg, char *cmnd)
5053 {
5054 gdth_ioctl_reset res;
5055 gdth_cmd_str cmd;
5056 int hanum;
5057 gdth_ha_str *ha;
5058 int rval;
5059
5060 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
5061 res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
5062 return -EFAULT;
5063 hanum = res.ionode;
5064 ha = HADATA(gdth_ctr_tab[hanum]);
5065
5066 if (!ha->hdr[res.number].present)
5067 return 0;
5068 memset(&cmd, 0, sizeof(gdth_cmd_str));
5069 cmd.Service = CACHESERVICE;
5070 cmd.OpCode = GDT_CLUST_RESET;
5071 if (ha->cache_feat & GDT_64BIT)
5072 cmd.u.cache64.DeviceNo = res.number;
5073 else
5074 cmd.u.cache.DeviceNo = res.number;
5075
5076 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
5077 if (rval < 0)
5078 return rval;
5079 res.status = rval;
5080
5081 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
5082 return -EFAULT;
5083 return 0;
5084 }
5085
5086 static int ioc_general(void __user *arg, char *cmnd)
5087 {
5088 gdth_ioctl_general gen;
5089 char *buf = NULL;
5090 ulong64 paddr;
5091 int hanum;
5092 gdth_ha_str *ha;
5093 int rval;
5094
5095 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
5096 gen.ionode >= gdth_ctr_count)
5097 return -EFAULT;
5098 hanum = gen.ionode;
5099 ha = HADATA(gdth_ctr_tab[hanum]);
5100 if (gen.data_len + gen.sense_len != 0) {
5101 if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
5102 FALSE, &paddr)))
5103 return -EFAULT;
5104 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
5105 gen.data_len + gen.sense_len)) {
5106 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5107 return -EFAULT;
5108 }
5109
5110 if (gen.command.OpCode == GDT_IOCTL) {
5111 gen.command.u.ioctl.p_param = paddr;
5112 } else if (gen.command.Service == CACHESERVICE) {
5113 if (ha->cache_feat & GDT_64BIT) {
5114 /* copy elements from 32-bit IOCTL structure */
5115 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
5116 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
5117 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
5118 /* addresses */
5119 if (ha->cache_feat & SCATTER_GATHER) {
5120 gen.command.u.cache64.DestAddr = (ulong64)-1;
5121 gen.command.u.cache64.sg_canz = 1;
5122 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
5123 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
5124 gen.command.u.cache64.sg_lst[1].sg_len = 0;
5125 } else {
5126 gen.command.u.cache64.DestAddr = paddr;
5127 gen.command.u.cache64.sg_canz = 0;
5128 }
5129 } else {
5130 if (ha->cache_feat & SCATTER_GATHER) {
5131 gen.command.u.cache.DestAddr = 0xffffffff;
5132 gen.command.u.cache.sg_canz = 1;
5133 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
5134 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
5135 gen.command.u.cache.sg_lst[1].sg_len = 0;
5136 } else {
5137 gen.command.u.cache.DestAddr = paddr;
5138 gen.command.u.cache.sg_canz = 0;
5139 }
5140 }
5141 } else if (gen.command.Service == SCSIRAWSERVICE) {
5142 if (ha->raw_feat & GDT_64BIT) {
5143 /* copy elements from 32-bit IOCTL structure */
5144 char cmd[16];
5145 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
5146 gen.command.u.raw64.bus = gen.command.u.raw.bus;
5147 gen.command.u.raw64.lun = gen.command.u.raw.lun;
5148 gen.command.u.raw64.target = gen.command.u.raw.target;
5149 memcpy(cmd, gen.command.u.raw.cmd, 16);
5150 memcpy(gen.command.u.raw64.cmd, cmd, 16);
5151 gen.command.u.raw64.clen = gen.command.u.raw.clen;
5152 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
5153 gen.command.u.raw64.direction = gen.command.u.raw.direction;
5154 /* addresses */
5155 if (ha->raw_feat & SCATTER_GATHER) {
5156 gen.command.u.raw64.sdata = (ulong64)-1;
5157 gen.command.u.raw64.sg_ranz = 1;
5158 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
5159 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
5160 gen.command.u.raw64.sg_lst[1].sg_len = 0;
5161 } else {
5162 gen.command.u.raw64.sdata = paddr;
5163 gen.command.u.raw64.sg_ranz = 0;
5164 }
5165 gen.command.u.raw64.sense_data = paddr + gen.data_len;
5166 } else {
5167 if (ha->raw_feat & SCATTER_GATHER) {
5168 gen.command.u.raw.sdata = 0xffffffff;
5169 gen.command.u.raw.sg_ranz = 1;
5170 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
5171 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
5172 gen.command.u.raw.sg_lst[1].sg_len = 0;
5173 } else {
5174 gen.command.u.raw.sdata = paddr;
5175 gen.command.u.raw.sg_ranz = 0;
5176 }
5177 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
5178 }
5179 } else {
5180 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5181 return -EFAULT;
5182 }
5183 }
5184
5185 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
5186 if (rval < 0)
5187 return rval;
5188 gen.status = rval;
5189
5190 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
5191 gen.data_len + gen.sense_len)) {
5192 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5193 return -EFAULT;
5194 }
5195 if (copy_to_user(arg, &gen,
5196 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
5197 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5198 return -EFAULT;
5199 }
5200 gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
5201 return 0;
5202 }
5203
5204 static int ioc_hdrlist(void __user *arg, char *cmnd)
5205 {
5206 gdth_ioctl_rescan *rsc;
5207 gdth_cmd_str *cmd;
5208 gdth_ha_str *ha;
5209 unchar i;
5210 int hanum, rc = -ENOMEM;
5211 u32 cluster_type = 0;
5212
5213 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5214 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5215 if (!rsc || !cmd)
5216 goto free_fail;
5217
5218 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5219 rsc->ionode >= gdth_ctr_count) {
5220 rc = -EFAULT;
5221 goto free_fail;
5222 }
5223 hanum = rsc->ionode;
5224 ha = HADATA(gdth_ctr_tab[hanum]);
5225 memset(cmd, 0, sizeof(gdth_cmd_str));
5226
5227 for (i = 0; i < MAX_HDRIVES; ++i) {
5228 if (!ha->hdr[i].present) {
5229 rsc->hdr_list[i].bus = 0xff;
5230 continue;
5231 }
5232 rsc->hdr_list[i].bus = ha->virt_bus;
5233 rsc->hdr_list[i].target = i;
5234 rsc->hdr_list[i].lun = 0;
5235 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5236 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
5237 cmd->Service = CACHESERVICE;
5238 cmd->OpCode = GDT_CLUST_INFO;
5239 if (ha->cache_feat & GDT_64BIT)
5240 cmd->u.cache64.DeviceNo = i;
5241 else
5242 cmd->u.cache.DeviceNo = i;
5243 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
5244 rsc->hdr_list[i].cluster_type = cluster_type;
5245 }
5246 }
5247
5248 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5249 rc = -EFAULT;
5250 else
5251 rc = 0;
5252
5253 free_fail:
5254 kfree(rsc);
5255 kfree(cmd);
5256 return rc;
5257 }
5258
5259 static int ioc_rescan(void __user *arg, char *cmnd)
5260 {
5261 gdth_ioctl_rescan *rsc;
5262 gdth_cmd_str *cmd;
5263 ushort i, status, hdr_cnt;
5264 ulong32 info;
5265 int hanum, cyls, hds, secs;
5266 int rc = -ENOMEM;
5267 ulong flags;
5268 gdth_ha_str *ha;
5269
5270 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
5271 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
5272 if (!cmd || !rsc)
5273 goto free_fail;
5274
5275 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
5276 rsc->ionode >= gdth_ctr_count) {
5277 rc = -EFAULT;
5278 goto free_fail;
5279 }
5280 hanum = rsc->ionode;
5281 ha = HADATA(gdth_ctr_tab[hanum]);
5282 memset(cmd, 0, sizeof(gdth_cmd_str));
5283
5284 if (rsc->flag == 0) {
5285 /* old method: re-init. cache service */
5286 cmd->Service = CACHESERVICE;
5287 if (ha->cache_feat & GDT_64BIT) {
5288 cmd->OpCode = GDT_X_INIT_HOST;
5289 cmd->u.cache64.DeviceNo = LINUX_OS;
5290 } else {
5291 cmd->OpCode = GDT_INIT;
5292 cmd->u.cache.DeviceNo = LINUX_OS;
5293 }
5294
5295 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5296 i = 0;
5297 hdr_cnt = (status == S_OK ? (ushort)info : 0);
5298 } else {
5299 i = rsc->hdr_no;
5300 hdr_cnt = i + 1;
5301 }
5302
5303 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
5304 cmd->Service = CACHESERVICE;
5305 cmd->OpCode = GDT_INFO;
5306 if (ha->cache_feat & GDT_64BIT)
5307 cmd->u.cache64.DeviceNo = i;
5308 else
5309 cmd->u.cache.DeviceNo = i;
5310
5311 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5312
5313 spin_lock_irqsave(&ha->smp_lock, flags);
5314 rsc->hdr_list[i].bus = ha->virt_bus;
5315 rsc->hdr_list[i].target = i;
5316 rsc->hdr_list[i].lun = 0;
5317 if (status != S_OK) {
5318 ha->hdr[i].present = FALSE;
5319 } else {
5320 ha->hdr[i].present = TRUE;
5321 ha->hdr[i].size = info;
5322 /* evaluate mapping */
5323 ha->hdr[i].size &= ~SECS32;
5324 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
5325 ha->hdr[i].heads = hds;
5326 ha->hdr[i].secs = secs;
5327 /* round size */
5328 ha->hdr[i].size = cyls * hds * secs;
5329 }
5330 spin_unlock_irqrestore(&ha->smp_lock, flags);
5331 if (status != S_OK)
5332 continue;
5333
5334 /* extended info, if GDT_64BIT, for drives > 2 TB */
5335 /* but we need ha->info2, not yet stored in scp->SCp */
5336
5337 /* devtype, cluster info, R/W attribs */
5338 cmd->Service = CACHESERVICE;
5339 cmd->OpCode = GDT_DEVTYPE;
5340 if (ha->cache_feat & GDT_64BIT)
5341 cmd->u.cache64.DeviceNo = i;
5342 else
5343 cmd->u.cache.DeviceNo = i;
5344
5345 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5346
5347 spin_lock_irqsave(&ha->smp_lock, flags);
5348 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
5349 spin_unlock_irqrestore(&ha->smp_lock, flags);
5350
5351 cmd->Service = CACHESERVICE;
5352 cmd->OpCode = GDT_CLUST_INFO;
5353 if (ha->cache_feat & GDT_64BIT)
5354 cmd->u.cache64.DeviceNo = i;
5355 else
5356 cmd->u.cache.DeviceNo = i;
5357
5358 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5359
5360 spin_lock_irqsave(&ha->smp_lock, flags);
5361 ha->hdr[i].cluster_type =
5362 ((status == S_OK && !shared_access) ? (ushort)info : 0);
5363 spin_unlock_irqrestore(&ha->smp_lock, flags);
5364 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
5365
5366 cmd->Service = CACHESERVICE;
5367 cmd->OpCode = GDT_RW_ATTRIBS;
5368 if (ha->cache_feat & GDT_64BIT)
5369 cmd->u.cache64.DeviceNo = i;
5370 else
5371 cmd->u.cache.DeviceNo = i;
5372
5373 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
5374
5375 spin_lock_irqsave(&ha->smp_lock, flags);
5376 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
5377 spin_unlock_irqrestore(&ha->smp_lock, flags);
5378 }
5379
5380 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
5381 rc = -EFAULT;
5382 else
5383 rc = 0;
5384
5385 free_fail:
5386 kfree(rsc);
5387 kfree(cmd);
5388 return rc;
5389 }
5390
5391 static int gdth_ioctl(struct inode *inode, struct file *filep,
5392 unsigned int cmd, unsigned long arg)
5393 {
5394 gdth_ha_str *ha;
5395 Scsi_Cmnd *scp;
5396 ulong flags;
5397 char cmnd[MAX_COMMAND_SIZE];
5398 void __user *argp = (void __user *)arg;
5399
5400 memset(cmnd, 0xff, 12);
5401
5402 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
5403
5404 switch (cmd) {
5405 case GDTIOCTL_CTRCNT:
5406 {
5407 int cnt = gdth_ctr_count;
5408 if (put_user(cnt, (int __user *)argp))
5409 return -EFAULT;
5410 break;
5411 }
5412
5413 case GDTIOCTL_DRVERS:
5414 {
5415 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
5416 if (put_user(ver, (int __user *)argp))
5417 return -EFAULT;
5418 break;
5419 }
5420
5421 case GDTIOCTL_OSVERS:
5422 {
5423 gdth_ioctl_osvers osv;
5424
5425 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
5426 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
5427 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
5428 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
5429 return -EFAULT;
5430 break;
5431 }
5432
5433 case GDTIOCTL_CTRTYPE:
5434 {
5435 gdth_ioctl_ctrtype ctrt;
5436
5437 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
5438 ctrt.ionode >= gdth_ctr_count)
5439 return -EFAULT;
5440 ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
5441 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
5442 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
5443 } else {
5444 if (ha->type != GDT_PCIMPR) {
5445 ctrt.type = (unchar)((ha->stype<<4) + 6);
5446 } else {
5447 ctrt.type =
5448 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
5449 if (ha->stype >= 0x300)
5450 ctrt.ext_type = 0x6000 | ha->subdevice_id;
5451 else
5452 ctrt.ext_type = 0x6000 | ha->stype;
5453 }
5454 ctrt.device_id = ha->stype;
5455 ctrt.sub_device_id = ha->subdevice_id;
5456 }
5457 ctrt.info = ha->brd_phys;
5458 ctrt.oem_id = ha->oem_id;
5459 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
5460 return -EFAULT;
5461 break;
5462 }
5463
5464 case GDTIOCTL_GENERAL:
5465 return ioc_general(argp, cmnd);
5466
5467 case GDTIOCTL_EVENT:
5468 return ioc_event(argp);
5469
5470 case GDTIOCTL_LOCKDRV:
5471 return ioc_lockdrv(argp);
5472
5473 case GDTIOCTL_LOCKCHN:
5474 {
5475 gdth_ioctl_lockchn lchn;
5476 unchar i, j;
5477
5478 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
5479 lchn.ionode >= gdth_ctr_count)
5480 return -EFAULT;
5481 ha = HADATA(gdth_ctr_tab[lchn.ionode]);
5482
5483 i = lchn.channel;
5484 if (i < ha->bus_cnt) {
5485 if (lchn.lock) {
5486 spin_lock_irqsave(&ha->smp_lock, flags);
5487 ha->raw[i].lock = 1;
5488 spin_unlock_irqrestore(&ha->smp_lock, flags);
5489 for (j = 0; j < ha->tid_cnt; ++j) {
5490 gdth_wait_completion(lchn.ionode, i, j);
5491 gdth_stop_timeout(lchn.ionode, i, j);
5492 }
5493 } else {
5494 spin_lock_irqsave(&ha->smp_lock, flags);
5495 ha->raw[i].lock = 0;
5496 spin_unlock_irqrestore(&ha->smp_lock, flags);
5497 for (j = 0; j < ha->tid_cnt; ++j) {
5498 gdth_start_timeout(lchn.ionode, i, j);
5499 gdth_next(lchn.ionode);
5500 }
5501 }
5502 }
5503 break;
5504 }
5505
5506 case GDTIOCTL_RESCAN:
5507 return ioc_rescan(argp, cmnd);
5508
5509 case GDTIOCTL_HDRLIST:
5510 return ioc_hdrlist(argp, cmnd);
5511
5512 case GDTIOCTL_RESET_BUS:
5513 {
5514 gdth_ioctl_reset res;
5515 int hanum, rval;
5516
5517 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
5518 res.ionode >= gdth_ctr_count)
5519 return -EFAULT;
5520 hanum = res.ionode;
5521 ha = HADATA(gdth_ctr_tab[hanum]);
5522
5523 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5524 scp = kmalloc(sizeof(*scp), GFP_KERNEL);
5525 if (!scp)
5526 return -ENOMEM;
5527 memset(scp, 0, sizeof(*scp));
5528 scp->device = ha->sdev;
5529 scp->cmd_len = 12;
5530 scp->use_sg = 0;
5531 scp->device->channel = virt_ctr ? 0 : res.number;
5532 rval = gdth_eh_bus_reset(scp);
5533 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5534 kfree(scp);
5535 #else
5536 scp = scsi_allocate_device(ha->sdev, 1, FALSE);
5537 if (!scp)
5538 return -ENOMEM;
5539 scp->cmd_len = 12;
5540 scp->use_sg = 0;
5541 scp->channel = virt_ctr ? 0 : res.number;
5542 rval = gdth_eh_bus_reset(scp);
5543 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
5544 scsi_release_command(scp);
5545 #endif
5546 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
5547 return -EFAULT;
5548 break;
5549 }
5550
5551 case GDTIOCTL_RESET_DRV:
5552 return ioc_resetdrv(argp, cmnd);
5553
5554 default:
5555 break;
5556 }
5557 return 0;
5558 }
5559
5560
5561 /* flush routine */
5562 static void gdth_flush(int hanum)
5563 {
5564 int i;
5565 gdth_ha_str *ha;
5566 gdth_cmd_str gdtcmd;
5567 char cmnd[MAX_COMMAND_SIZE];
5568 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5569
5570 TRACE2(("gdth_flush() hanum %d\n",hanum));
5571 ha = HADATA(gdth_ctr_tab[hanum]);
5572
5573 for (i = 0; i < MAX_HDRIVES; ++i) {
5574 if (ha->hdr[i].present) {
5575 gdtcmd.BoardNode = LOCALBOARD;
5576 gdtcmd.Service = CACHESERVICE;
5577 gdtcmd.OpCode = GDT_FLUSH;
5578 if (ha->cache_feat & GDT_64BIT) {
5579 gdtcmd.u.cache64.DeviceNo = i;
5580 gdtcmd.u.cache64.BlockNo = 1;
5581 gdtcmd.u.cache64.sg_canz = 0;
5582 } else {
5583 gdtcmd.u.cache.DeviceNo = i;
5584 gdtcmd.u.cache.BlockNo = 1;
5585 gdtcmd.u.cache.sg_canz = 0;
5586 }
5587 TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
5588
5589 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
5590 }
5591 }
5592 }
5593
5594 /* shutdown routine */
5595 static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
5596 {
5597 int hanum;
5598 #ifndef __alpha__
5599 gdth_cmd_str gdtcmd;
5600 char cmnd[MAX_COMMAND_SIZE];
5601 #endif
5602
5603 if (notifier_disabled)
5604 return NOTIFY_OK;
5605
5606 TRACE2(("gdth_halt() event %d\n",(int)event));
5607 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
5608 return NOTIFY_DONE;
5609
5610 notifier_disabled = 1;
5611 printk("GDT-HA: Flushing all host drives .. ");
5612 for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
5613 gdth_flush(hanum);
5614
5615 #ifndef __alpha__
5616 /* controller reset */
5617 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
5618 gdtcmd.BoardNode = LOCALBOARD;
5619 gdtcmd.Service = CACHESERVICE;
5620 gdtcmd.OpCode = GDT_RESET;
5621 TRACE2(("gdth_halt(): reset controller %d\n", hanum));
5622 gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
5623 #endif
5624 }
5625 printk("Done.\n");
5626
5627 #ifdef GDTH_STATISTICS
5628 del_timer(&gdth_timer);
5629 #endif
5630 return NOTIFY_OK;
5631 }
5632
5633 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5634 /* configure lun */
5635 static int gdth_slave_configure(struct scsi_device *sdev)
5636 {
5637 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
5638 sdev->skip_ms_page_3f = 1;
5639 sdev->skip_ms_page_8 = 1;
5640 return 0;
5641 }
5642 #endif
5643
5644 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5645 static struct scsi_host_template driver_template = {
5646 #else
5647 static Scsi_Host_Template driver_template = {
5648 #endif
5649 .proc_name = "gdth",
5650 .proc_info = gdth_proc_info,
5651 .name = "GDT SCSI Disk Array Controller",
5652 .detect = gdth_detect,
5653 .release = gdth_release,
5654 .info = gdth_info,
5655 .queuecommand = gdth_queuecommand,
5656 .eh_bus_reset_handler = gdth_eh_bus_reset,
5657 .bios_param = gdth_bios_param,
5658 .can_queue = GDTH_MAXCMDS,
5659 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
5660 .slave_configure = gdth_slave_configure,
5661 #endif
5662 .this_id = -1,
5663 .sg_tablesize = GDTH_MAXSG,
5664 .cmd_per_lun = GDTH_MAXC_P_L,
5665 .unchecked_isa_dma = 1,
5666 .use_clustering = ENABLE_CLUSTERING,
5667 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
5668 .use_new_eh_code = 1,
5669 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
5670 .highmem_io = 1,
5671 #endif
5672 #endif
5673 };
5674
5675 #include "scsi_module.c"
5676 #ifndef MODULE
5677 __setup("gdth=", option_setup);
5678 #endif
kernel source for telekom puls (alcatel/mediatek)