2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/pci.h>
45 #include <linux/init.h>
46 #include <linux/blkdev.h>
47 #include <linux/delay.h>
48 #include <linux/device.h>
49 #include <scsi/scsi_host.h>
50 #include <linux/libata.h>
52 #define DRV_NAME "ata_piix"
53 #define DRV_VERSION "1.04"
56 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
57 ICH5_PMR
= 0x90, /* port mapping register */
58 ICH5_PCS
= 0x92, /* port control and status */
59 PIIX_SCC
= 0x0A, /* sub-class code register */
61 PIIX_FLAG_AHCI
= (1 << 28), /* AHCI possible */
62 PIIX_FLAG_CHECKINTR
= (1 << 29), /* make sure PCI INTx enabled */
63 PIIX_FLAG_COMBINED
= (1 << 30), /* combined mode possible */
65 /* combined mode. if set, PATA is channel 0.
66 * if clear, PATA is channel 1.
68 PIIX_COMB_PATA_P0
= (1 << 1),
69 PIIX_COMB
= (1 << 2), /* combined mode enabled? */
71 PIIX_PORT_ENABLED
= (1 << 0),
72 PIIX_PORT_PRESENT
= (1 << 4),
74 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
75 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
86 static int piix_init_one (struct pci_dev
*pdev
,
87 const struct pci_device_id
*ent
);
89 static void piix_pata_phy_reset(struct ata_port
*ap
);
90 static void piix_sata_phy_reset(struct ata_port
*ap
);
91 static void piix_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
);
92 static void piix_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
);
94 static unsigned int in_module_init
= 1;
96 static const struct pci_device_id piix_pci_tbl
[] = {
97 #ifdef ATA_ENABLE_PATA
98 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix4_pata
},
99 { 0x8086, 0x24db, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_pata
},
100 { 0x8086, 0x25a2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_pata
},
103 /* NOTE: The following PCI ids must be kept in sync with the
104 * list in drivers/pci/quirks.c.
107 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
108 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
109 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
110 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
111 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
112 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
113 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
114 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
115 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
116 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
118 { } /* terminate list */
121 static struct pci_driver piix_pci_driver
= {
123 .id_table
= piix_pci_tbl
,
124 .probe
= piix_init_one
,
125 .remove
= ata_pci_remove_one
,
128 static struct scsi_host_template piix_sht
= {
129 .module
= THIS_MODULE
,
131 .ioctl
= ata_scsi_ioctl
,
132 .queuecommand
= ata_scsi_queuecmd
,
133 .eh_strategy_handler
= ata_scsi_error
,
134 .can_queue
= ATA_DEF_QUEUE
,
135 .this_id
= ATA_SHT_THIS_ID
,
136 .sg_tablesize
= LIBATA_MAX_PRD
,
137 .max_sectors
= ATA_MAX_SECTORS
,
138 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
139 .emulated
= ATA_SHT_EMULATED
,
140 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
141 .proc_name
= DRV_NAME
,
142 .dma_boundary
= ATA_DMA_BOUNDARY
,
143 .slave_configure
= ata_scsi_slave_config
,
144 .bios_param
= ata_std_bios_param
,
148 static const struct ata_port_operations piix_pata_ops
= {
149 .port_disable
= ata_port_disable
,
150 .set_piomode
= piix_set_piomode
,
151 .set_dmamode
= piix_set_dmamode
,
153 .tf_load
= ata_tf_load
,
154 .tf_read
= ata_tf_read
,
155 .check_status
= ata_check_status
,
156 .exec_command
= ata_exec_command
,
157 .dev_select
= ata_std_dev_select
,
159 .phy_reset
= piix_pata_phy_reset
,
161 .bmdma_setup
= ata_bmdma_setup
,
162 .bmdma_start
= ata_bmdma_start
,
163 .bmdma_stop
= ata_bmdma_stop
,
164 .bmdma_status
= ata_bmdma_status
,
165 .qc_prep
= ata_qc_prep
,
166 .qc_issue
= ata_qc_issue_prot
,
168 .eng_timeout
= ata_eng_timeout
,
170 .irq_handler
= ata_interrupt
,
171 .irq_clear
= ata_bmdma_irq_clear
,
173 .port_start
= ata_port_start
,
174 .port_stop
= ata_port_stop
,
175 .host_stop
= ata_host_stop
,
178 static const struct ata_port_operations piix_sata_ops
= {
179 .port_disable
= ata_port_disable
,
181 .tf_load
= ata_tf_load
,
182 .tf_read
= ata_tf_read
,
183 .check_status
= ata_check_status
,
184 .exec_command
= ata_exec_command
,
185 .dev_select
= ata_std_dev_select
,
187 .phy_reset
= piix_sata_phy_reset
,
189 .bmdma_setup
= ata_bmdma_setup
,
190 .bmdma_start
= ata_bmdma_start
,
191 .bmdma_stop
= ata_bmdma_stop
,
192 .bmdma_status
= ata_bmdma_status
,
193 .qc_prep
= ata_qc_prep
,
194 .qc_issue
= ata_qc_issue_prot
,
196 .eng_timeout
= ata_eng_timeout
,
198 .irq_handler
= ata_interrupt
,
199 .irq_clear
= ata_bmdma_irq_clear
,
201 .port_start
= ata_port_start
,
202 .port_stop
= ata_port_stop
,
203 .host_stop
= ata_host_stop
,
206 static struct ata_port_info piix_port_info
[] = {
210 .host_flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
|
212 .pio_mask
= 0x1f, /* pio0-4 */
214 .mwdma_mask
= 0x06, /* mwdma1-2 */
216 .mwdma_mask
= 0x00, /* mwdma broken */
218 .udma_mask
= 0x3f, /* udma0-5 */
219 .port_ops
= &piix_pata_ops
,
225 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SRST
|
226 PIIX_FLAG_COMBINED
| PIIX_FLAG_CHECKINTR
,
227 .pio_mask
= 0x1f, /* pio0-4 */
228 .mwdma_mask
= 0x07, /* mwdma0-2 */
229 .udma_mask
= 0x7f, /* udma0-6 */
230 .port_ops
= &piix_sata_ops
,
236 .host_flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
237 .pio_mask
= 0x1f, /* pio0-4 */
239 .mwdma_mask
= 0x06, /* mwdma1-2 */
241 .mwdma_mask
= 0x00, /* mwdma broken */
243 .udma_mask
= ATA_UDMA_MASK_40C
,
244 .port_ops
= &piix_pata_ops
,
250 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SRST
|
251 PIIX_FLAG_COMBINED
| PIIX_FLAG_CHECKINTR
|
253 .pio_mask
= 0x1f, /* pio0-4 */
254 .mwdma_mask
= 0x07, /* mwdma0-2 */
255 .udma_mask
= 0x7f, /* udma0-6 */
256 .port_ops
= &piix_sata_ops
,
262 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SRST
|
263 PIIX_FLAG_COMBINED
| PIIX_FLAG_CHECKINTR
|
264 ATA_FLAG_SLAVE_POSS
| PIIX_FLAG_AHCI
,
265 .pio_mask
= 0x1f, /* pio0-4 */
266 .mwdma_mask
= 0x07, /* mwdma0-2 */
267 .udma_mask
= 0x7f, /* udma0-6 */
268 .port_ops
= &piix_sata_ops
,
272 static struct pci_bits piix_enable_bits
[] = {
273 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
274 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
277 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
278 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
279 MODULE_LICENSE("GPL");
280 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
281 MODULE_VERSION(DRV_VERSION
);
284 * piix_pata_cbl_detect - Probe host controller cable detect info
285 * @ap: Port for which cable detect info is desired
287 * Read 80c cable indicator from ATA PCI device's PCI config
288 * register. This register is normally set by firmware (BIOS).
291 * None (inherited from caller).
293 static void piix_pata_cbl_detect(struct ata_port
*ap
)
295 struct pci_dev
*pdev
= to_pci_dev(ap
->host_set
->dev
);
298 /* no 80c support in host controller? */
299 if ((ap
->udma_mask
& ~ATA_UDMA_MASK_40C
) == 0)
302 /* check BIOS cable detect results */
303 mask
= ap
->hard_port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
304 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
305 if ((tmp
& mask
) == 0)
308 ap
->cbl
= ATA_CBL_PATA80
;
312 ap
->cbl
= ATA_CBL_PATA40
;
313 ap
->udma_mask
&= ATA_UDMA_MASK_40C
;
317 * piix_pata_phy_reset - Probe specified port on PATA host controller
323 * None (inherited from caller).
326 static void piix_pata_phy_reset(struct ata_port
*ap
)
328 struct pci_dev
*pdev
= to_pci_dev(ap
->host_set
->dev
);
330 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->hard_port_no
])) {
331 ata_port_disable(ap
);
332 printk(KERN_INFO
"ata%u: port disabled. ignoring.\n", ap
->id
);
336 piix_pata_cbl_detect(ap
);
344 * piix_sata_probe - Probe PCI device for present SATA devices
345 * @ap: Port associated with the PCI device we wish to probe
347 * Reads SATA PCI device's PCI config register Port Configuration
348 * and Status (PCS) to determine port and device availability.
351 * None (inherited from caller).
354 * Non-zero if port is enabled, it may or may not have a device
355 * attached in that case (PRESENT bit would only be set if BIOS probe
356 * was done). Zero is returned if port is disabled.
358 static int piix_sata_probe (struct ata_port
*ap
)
360 struct pci_dev
*pdev
= to_pci_dev(ap
->host_set
->dev
);
361 int combined
= (ap
->flags
& ATA_FLAG_SLAVE_POSS
);
362 int orig_mask
, mask
, i
;
365 mask
= (PIIX_PORT_PRESENT
<< ap
->hard_port_no
) |
366 (PIIX_PORT_ENABLED
<< ap
->hard_port_no
);
368 pci_read_config_byte(pdev
, ICH5_PCS
, &pcs
);
369 orig_mask
= (int) pcs
& 0xff;
371 /* TODO: this is vaguely wrong for ICH6 combined mode,
372 * where only two of the four SATA ports are mapped
373 * onto a single ATA channel. It is also vaguely inaccurate
374 * for ICH5, which has only two ports. However, this is ok,
375 * as further device presence detection code will handle
376 * any false positives produced here.
379 for (i
= 0; i
< 4; i
++) {
380 mask
= (PIIX_PORT_ENABLED
<< i
);
382 if ((orig_mask
& mask
) == mask
)
383 if (combined
|| (i
== ap
->hard_port_no
))
391 * piix_sata_phy_reset - Probe specified port on SATA host controller
397 * None (inherited from caller).
400 static void piix_sata_phy_reset(struct ata_port
*ap
)
402 if (!piix_sata_probe(ap
)) {
403 ata_port_disable(ap
);
404 printk(KERN_INFO
"ata%u: SATA port has no device.\n", ap
->id
);
408 ap
->cbl
= ATA_CBL_SATA
;
416 * piix_set_piomode - Initialize host controller PATA PIO timings
417 * @ap: Port whose timings we are configuring
420 * Set PIO mode for device, in host controller PCI config space.
423 * None (inherited from caller).
426 static void piix_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
428 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
429 struct pci_dev
*dev
= to_pci_dev(ap
->host_set
->dev
);
430 unsigned int is_slave
= (adev
->devno
!= 0);
431 unsigned int master_port
= ap
->hard_port_no
? 0x42 : 0x40;
432 unsigned int slave_port
= 0x44;
436 static const /* ISP RTC */
437 u8 timings
[][2] = { { 0, 0 },
443 pci_read_config_word(dev
, master_port
, &master_data
);
445 master_data
|= 0x4000;
446 /* enable PPE, IE and TIME */
447 master_data
|= 0x0070;
448 pci_read_config_byte(dev
, slave_port
, &slave_data
);
449 slave_data
&= (ap
->hard_port_no
? 0x0f : 0xf0);
451 (timings
[pio
][0] << 2) |
452 (timings
[pio
][1] << (ap
->hard_port_no
? 4 : 0));
454 master_data
&= 0xccf8;
455 /* enable PPE, IE and TIME */
456 master_data
|= 0x0007;
458 (timings
[pio
][0] << 12) |
459 (timings
[pio
][1] << 8);
461 pci_write_config_word(dev
, master_port
, master_data
);
463 pci_write_config_byte(dev
, slave_port
, slave_data
);
467 * piix_set_dmamode - Initialize host controller PATA PIO timings
468 * @ap: Port whose timings we are configuring
470 * @udma: udma mode, 0 - 6
472 * Set UDMA mode for device, in host controller PCI config space.
475 * None (inherited from caller).
478 static void piix_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
480 unsigned int udma
= adev
->dma_mode
; /* FIXME: MWDMA too */
481 struct pci_dev
*dev
= to_pci_dev(ap
->host_set
->dev
);
482 u8 maslave
= ap
->hard_port_no
? 0x42 : 0x40;
484 unsigned int drive_dn
= (ap
->hard_port_no
? 2 : 0) + adev
->devno
;
485 int a_speed
= 3 << (drive_dn
* 4);
486 int u_flag
= 1 << drive_dn
;
487 int v_flag
= 0x01 << drive_dn
;
488 int w_flag
= 0x10 << drive_dn
;
492 u8 reg48
, reg54
, reg55
;
494 pci_read_config_word(dev
, maslave
, ®4042
);
495 DPRINTK("reg4042 = 0x%04x\n", reg4042
);
496 sitre
= (reg4042
& 0x4000) ? 1 : 0;
497 pci_read_config_byte(dev
, 0x48, ®48
);
498 pci_read_config_word(dev
, 0x4a, ®4a
);
499 pci_read_config_byte(dev
, 0x54, ®54
);
500 pci_read_config_byte(dev
, 0x55, ®55
);
504 case XFER_UDMA_2
: u_speed
= 2 << (drive_dn
* 4); break;
508 case XFER_UDMA_1
: u_speed
= 1 << (drive_dn
* 4); break;
509 case XFER_UDMA_0
: u_speed
= 0 << (drive_dn
* 4); break;
511 case XFER_MW_DMA_1
: break;
517 if (speed
>= XFER_UDMA_0
) {
518 if (!(reg48
& u_flag
))
519 pci_write_config_byte(dev
, 0x48, reg48
| u_flag
);
520 if (speed
== XFER_UDMA_5
) {
521 pci_write_config_byte(dev
, 0x55, (u8
) reg55
|w_flag
);
523 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
525 if ((reg4a
& a_speed
) != u_speed
)
526 pci_write_config_word(dev
, 0x4a, (reg4a
& ~a_speed
) | u_speed
);
527 if (speed
> XFER_UDMA_2
) {
528 if (!(reg54
& v_flag
))
529 pci_write_config_byte(dev
, 0x54, reg54
| v_flag
);
531 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
534 pci_write_config_byte(dev
, 0x48, reg48
& ~u_flag
);
536 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
538 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
540 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
544 #define AHCI_PCI_BAR 5
545 #define AHCI_GLOBAL_CTL 0x04
546 #define AHCI_ENABLE (1 << 31)
547 static int piix_disable_ahci(struct pci_dev
*pdev
)
553 /* BUG: pci_enable_device has not yet been called. This
554 * works because this device is usually set up by BIOS.
557 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
558 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
561 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
565 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
566 if (tmp
& AHCI_ENABLE
) {
568 writel(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
570 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
571 if (tmp
& AHCI_ENABLE
)
575 pci_iounmap(pdev
, mmio
);
580 * piix_init_one - Register PIIX ATA PCI device with kernel services
581 * @pdev: PCI device to register
582 * @ent: Entry in piix_pci_tbl matching with @pdev
584 * Called from kernel PCI layer. We probe for combined mode (sigh),
585 * and then hand over control to libata, for it to do the rest.
588 * Inherited from PCI layer (may sleep).
591 * Zero on success, or -ERRNO value.
594 static int piix_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
596 static int printed_version
;
597 struct ata_port_info
*port_info
[2];
598 unsigned int combined
= 0;
599 unsigned int pata_chan
= 0, sata_chan
= 0;
601 if (!printed_version
++)
602 dev_printk(KERN_DEBUG
, &pdev
->dev
,
603 "version " DRV_VERSION
"\n");
605 /* no hotplugging support (FIXME) */
609 port_info
[0] = &piix_port_info
[ent
->driver_data
];
610 port_info
[1] = &piix_port_info
[ent
->driver_data
];
612 if (port_info
[0]->host_flags
& PIIX_FLAG_AHCI
) {
614 pci_read_config_byte(pdev
, PIIX_SCC
, &tmp
);
615 if (tmp
== PIIX_AHCI_DEVICE
) {
616 int rc
= piix_disable_ahci(pdev
);
622 if (port_info
[0]->host_flags
& PIIX_FLAG_COMBINED
) {
624 pci_read_config_byte(pdev
, ICH5_PMR
, &tmp
);
626 if (tmp
& PIIX_COMB
) {
628 if (tmp
& PIIX_COMB_PATA_P0
)
635 /* On ICH5, some BIOSen disable the interrupt using the
636 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
637 * On ICH6, this bit has the same effect, but only when
638 * MSI is disabled (and it is disabled, as we don't use
639 * message-signalled interrupts currently).
641 if (port_info
[0]->host_flags
& PIIX_FLAG_CHECKINTR
)
645 port_info
[sata_chan
] = &piix_port_info
[ent
->driver_data
];
646 port_info
[sata_chan
]->host_flags
|= ATA_FLAG_SLAVE_POSS
;
647 port_info
[pata_chan
] = &piix_port_info
[ich5_pata
];
649 dev_printk(KERN_WARNING
, &pdev
->dev
,
650 "combined mode detected (p=%u, s=%u)\n",
651 pata_chan
, sata_chan
);
654 return ata_pci_init_one(pdev
, port_info
, 2);
657 static int __init
piix_init(void)
661 DPRINTK("pci_module_init\n");
662 rc
= pci_module_init(&piix_pci_driver
);
672 static void __exit
piix_exit(void)
674 pci_unregister_driver(&piix_pci_driver
);
677 module_init(piix_init
);
678 module_exit(piix_exit
);