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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / ata_piix.c
1 /*
2
3 ata_piix.c - Intel PATA/SATA controllers
4
5 Maintained by: Jeff Garzik <jgarzik@pobox.com>
6 Please ALWAYS copy linux-ide@vger.kernel.org
7 on emails.
8
9
10 Copyright 2003-2004 Red Hat Inc
11 Copyright 2003-2004 Jeff Garzik
12
13
14 Copyright header from piix.c:
15
16 Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
17 Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
18 Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
19
20 May be copied or modified under the terms of the GNU General Public License
21
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include "scsi.h"
31 #include <scsi/scsi_host.h>
32 #include <linux/libata.h>
33
34 #define DRV_NAME "ata_piix"
35 #define DRV_VERSION "1.03"
36
37 enum {
38 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
39 ICH5_PMR = 0x90, /* port mapping register */
40 ICH5_PCS = 0x92, /* port control and status */
41
42 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
43 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
44 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
45
46 /* combined mode. if set, PATA is channel 0.
47 * if clear, PATA is channel 1.
48 */
49 PIIX_COMB_PATA_P0 = (1 << 1),
50 PIIX_COMB = (1 << 2), /* combined mode enabled? */
51
52 PIIX_PORT_PRESENT = (1 << 0),
53 PIIX_PORT_ENABLED = (1 << 4),
54
55 PIIX_80C_PRI = (1 << 5) | (1 << 4),
56 PIIX_80C_SEC = (1 << 7) | (1 << 6),
57
58 ich5_pata = 0,
59 ich5_sata = 1,
60 piix4_pata = 2,
61 ich6_sata = 3,
62 ich6_sata_rm = 4,
63 ich7_sata = 5,
64 esb2_sata = 6,
65 };
66
67 static int piix_init_one (struct pci_dev *pdev,
68 const struct pci_device_id *ent);
69
70 static void piix_pata_phy_reset(struct ata_port *ap);
71 static void piix_sata_phy_reset(struct ata_port *ap);
72 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
73 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
74
75 static unsigned int in_module_init = 1;
76
77 static struct pci_device_id piix_pci_tbl[] = {
78 #ifdef ATA_ENABLE_PATA
79 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
80 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
81 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
82 #endif
83
84 /* NOTE: The following PCI ids must be kept in sync with the
85 * list in drivers/pci/quirks.c.
86 */
87
88 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
89 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
90 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
91 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
92 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
93 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
94 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
95 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
96 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
97 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
98
99 { } /* terminate list */
100 };
101
102 static struct pci_driver piix_pci_driver = {
103 .name = DRV_NAME,
104 .id_table = piix_pci_tbl,
105 .probe = piix_init_one,
106 .remove = ata_pci_remove_one,
107 };
108
109 static Scsi_Host_Template piix_sht = {
110 .module = THIS_MODULE,
111 .name = DRV_NAME,
112 .ioctl = ata_scsi_ioctl,
113 .queuecommand = ata_scsi_queuecmd,
114 .eh_strategy_handler = ata_scsi_error,
115 .can_queue = ATA_DEF_QUEUE,
116 .this_id = ATA_SHT_THIS_ID,
117 .sg_tablesize = LIBATA_MAX_PRD,
118 .max_sectors = ATA_MAX_SECTORS,
119 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
120 .emulated = ATA_SHT_EMULATED,
121 .use_clustering = ATA_SHT_USE_CLUSTERING,
122 .proc_name = DRV_NAME,
123 .dma_boundary = ATA_DMA_BOUNDARY,
124 .slave_configure = ata_scsi_slave_config,
125 .bios_param = ata_std_bios_param,
126 .ordered_flush = 1,
127 };
128
129 static struct ata_port_operations piix_pata_ops = {
130 .port_disable = ata_port_disable,
131 .set_piomode = piix_set_piomode,
132 .set_dmamode = piix_set_dmamode,
133
134 .tf_load = ata_tf_load,
135 .tf_read = ata_tf_read,
136 .check_status = ata_check_status,
137 .exec_command = ata_exec_command,
138 .dev_select = ata_std_dev_select,
139
140 .phy_reset = piix_pata_phy_reset,
141
142 .bmdma_setup = ata_bmdma_setup,
143 .bmdma_start = ata_bmdma_start,
144 .bmdma_stop = ata_bmdma_stop,
145 .bmdma_status = ata_bmdma_status,
146 .qc_prep = ata_qc_prep,
147 .qc_issue = ata_qc_issue_prot,
148
149 .eng_timeout = ata_eng_timeout,
150
151 .irq_handler = ata_interrupt,
152 .irq_clear = ata_bmdma_irq_clear,
153
154 .port_start = ata_port_start,
155 .port_stop = ata_port_stop,
156 };
157
158 static struct ata_port_operations piix_sata_ops = {
159 .port_disable = ata_port_disable,
160
161 .tf_load = ata_tf_load,
162 .tf_read = ata_tf_read,
163 .check_status = ata_check_status,
164 .exec_command = ata_exec_command,
165 .dev_select = ata_std_dev_select,
166
167 .phy_reset = piix_sata_phy_reset,
168
169 .bmdma_setup = ata_bmdma_setup,
170 .bmdma_start = ata_bmdma_start,
171 .bmdma_stop = ata_bmdma_stop,
172 .bmdma_status = ata_bmdma_status,
173 .qc_prep = ata_qc_prep,
174 .qc_issue = ata_qc_issue_prot,
175
176 .eng_timeout = ata_eng_timeout,
177
178 .irq_handler = ata_interrupt,
179 .irq_clear = ata_bmdma_irq_clear,
180
181 .port_start = ata_port_start,
182 .port_stop = ata_port_stop,
183 };
184
185 static struct ata_port_info piix_port_info[] = {
186 /* ich5_pata */
187 {
188 .sht = &piix_sht,
189 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
190 PIIX_FLAG_CHECKINTR,
191 .pio_mask = 0x1f, /* pio0-4 */
192 #if 0
193 .mwdma_mask = 0x06, /* mwdma1-2 */
194 #else
195 .mwdma_mask = 0x00, /* mwdma broken */
196 #endif
197 .udma_mask = 0x3f, /* udma0-5 */
198 .port_ops = &piix_pata_ops,
199 },
200
201 /* ich5_sata */
202 {
203 .sht = &piix_sht,
204 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
205 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
206 .pio_mask = 0x1f, /* pio0-4 */
207 .mwdma_mask = 0x07, /* mwdma0-2 */
208 .udma_mask = 0x7f, /* udma0-6 */
209 .port_ops = &piix_sata_ops,
210 },
211
212 /* piix4_pata */
213 {
214 .sht = &piix_sht,
215 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
216 .pio_mask = 0x1f, /* pio0-4 */
217 #if 0
218 .mwdma_mask = 0x06, /* mwdma1-2 */
219 #else
220 .mwdma_mask = 0x00, /* mwdma broken */
221 #endif
222 .udma_mask = ATA_UDMA_MASK_40C,
223 .port_ops = &piix_pata_ops,
224 },
225
226 /* ich6_sata */
227 {
228 .sht = &piix_sht,
229 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
230 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
231 ATA_FLAG_SLAVE_POSS,
232 .pio_mask = 0x1f, /* pio0-4 */
233 .mwdma_mask = 0x07, /* mwdma0-2 */
234 .udma_mask = 0x7f, /* udma0-6 */
235 .port_ops = &piix_sata_ops,
236 },
237
238 /* ich6_sata_rm */
239 {
240 .sht = &piix_sht,
241 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
242 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
243 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
244 .pio_mask = 0x1f, /* pio0-4 */
245 .mwdma_mask = 0x07, /* mwdma0-2 */
246 .udma_mask = 0x7f, /* udma0-6 */
247 .port_ops = &piix_sata_ops,
248 },
249
250 /* ich7_sata */
251 {
252 .sht = &piix_sht,
253 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
254 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
255 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
256 .pio_mask = 0x1f, /* pio0-4 */
257 .mwdma_mask = 0x07, /* mwdma0-2 */
258 .udma_mask = 0x7f, /* udma0-6 */
259 .port_ops = &piix_sata_ops,
260 },
261
262 /* esb2_sata */
263 {
264 .sht = &piix_sht,
265 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
266 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
267 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
268 .pio_mask = 0x1f, /* pio0-4 */
269 .mwdma_mask = 0x07, /* mwdma0-2 */
270 .udma_mask = 0x7f, /* udma0-6 */
271 .port_ops = &piix_sata_ops,
272 },
273 };
274
275 static struct pci_bits piix_enable_bits[] = {
276 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
277 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
278 };
279
280 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
281 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
282 MODULE_LICENSE("GPL");
283 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
284 MODULE_VERSION(DRV_VERSION);
285
286 /**
287 * piix_pata_cbl_detect - Probe host controller cable detect info
288 * @ap: Port for which cable detect info is desired
289 *
290 * Read 80c cable indicator from ATA PCI device's PCI config
291 * register. This register is normally set by firmware (BIOS).
292 *
293 * LOCKING:
294 * None (inherited from caller).
295 */
296 static void piix_pata_cbl_detect(struct ata_port *ap)
297 {
298 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
299 u8 tmp, mask;
300
301 /* no 80c support in host controller? */
302 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
303 goto cbl40;
304
305 /* check BIOS cable detect results */
306 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
307 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
308 if ((tmp & mask) == 0)
309 goto cbl40;
310
311 ap->cbl = ATA_CBL_PATA80;
312 return;
313
314 cbl40:
315 ap->cbl = ATA_CBL_PATA40;
316 ap->udma_mask &= ATA_UDMA_MASK_40C;
317 }
318
319 /**
320 * piix_pata_phy_reset - Probe specified port on PATA host controller
321 * @ap: Port to probe
322 *
323 * Probe PATA phy.
324 *
325 * LOCKING:
326 * None (inherited from caller).
327 */
328
329 static void piix_pata_phy_reset(struct ata_port *ap)
330 {
331 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
332
333 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
334 ata_port_disable(ap);
335 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
336 return;
337 }
338
339 piix_pata_cbl_detect(ap);
340
341 ata_port_probe(ap);
342
343 ata_bus_reset(ap);
344 }
345
346 /**
347 * piix_sata_probe - Probe PCI device for present SATA devices
348 * @ap: Port associated with the PCI device we wish to probe
349 *
350 * Reads SATA PCI device's PCI config register Port Configuration
351 * and Status (PCS) to determine port and device availability.
352 *
353 * LOCKING:
354 * None (inherited from caller).
355 *
356 * RETURNS:
357 * Non-zero if device detected, zero otherwise.
358 */
359 static int piix_sata_probe (struct ata_port *ap)
360 {
361 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
362 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
363 int orig_mask, mask, i;
364 u8 pcs;
365
366 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
367 (PIIX_PORT_ENABLED << ap->hard_port_no);
368
369 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
370 orig_mask = (int) pcs & 0xff;
371
372 /* TODO: this is vaguely wrong for ICH6 combined mode,
373 * where only two of the four SATA ports are mapped
374 * onto a single ATA channel. It is also vaguely inaccurate
375 * for ICH5, which has only two ports. However, this is ok,
376 * as further device presence detection code will handle
377 * any false positives produced here.
378 */
379
380 for (i = 0; i < 4; i++) {
381 mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
382
383 if ((orig_mask & mask) == mask)
384 if (combined || (i == ap->hard_port_no))
385 return 1;
386 }
387
388 return 0;
389 }
390
391 /**
392 * piix_sata_phy_reset - Probe specified port on SATA host controller
393 * @ap: Port to probe
394 *
395 * Probe SATA phy.
396 *
397 * LOCKING:
398 * None (inherited from caller).
399 */
400
401 static void piix_sata_phy_reset(struct ata_port *ap)
402 {
403 if (!piix_sata_probe(ap)) {
404 ata_port_disable(ap);
405 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
406 return;
407 }
408
409 ap->cbl = ATA_CBL_SATA;
410
411 ata_port_probe(ap);
412
413 ata_bus_reset(ap);
414 }
415
416 /**
417 * piix_set_piomode - Initialize host controller PATA PIO timings
418 * @ap: Port whose timings we are configuring
419 * @adev: um
420 * @pio: PIO mode, 0 - 4
421 *
422 * Set PIO mode for device, in host controller PCI config space.
423 *
424 * LOCKING:
425 * None (inherited from caller).
426 */
427
428 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
429 {
430 unsigned int pio = adev->pio_mode - XFER_PIO_0;
431 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
432 unsigned int is_slave = (adev->devno != 0);
433 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
434 unsigned int slave_port = 0x44;
435 u16 master_data;
436 u8 slave_data;
437
438 static const /* ISP RTC */
439 u8 timings[][2] = { { 0, 0 },
440 { 0, 0 },
441 { 1, 0 },
442 { 2, 1 },
443 { 2, 3 }, };
444
445 pci_read_config_word(dev, master_port, &master_data);
446 if (is_slave) {
447 master_data |= 0x4000;
448 /* enable PPE, IE and TIME */
449 master_data |= 0x0070;
450 pci_read_config_byte(dev, slave_port, &slave_data);
451 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
452 slave_data |=
453 (timings[pio][0] << 2) |
454 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
455 } else {
456 master_data &= 0xccf8;
457 /* enable PPE, IE and TIME */
458 master_data |= 0x0007;
459 master_data |=
460 (timings[pio][0] << 12) |
461 (timings[pio][1] << 8);
462 }
463 pci_write_config_word(dev, master_port, master_data);
464 if (is_slave)
465 pci_write_config_byte(dev, slave_port, slave_data);
466 }
467
468 /**
469 * piix_set_dmamode - Initialize host controller PATA PIO timings
470 * @ap: Port whose timings we are configuring
471 * @adev: um
472 * @udma: udma mode, 0 - 6
473 *
474 * Set UDMA mode for device, in host controller PCI config space.
475 *
476 * LOCKING:
477 * None (inherited from caller).
478 */
479
480 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
481 {
482 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
483 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
484 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
485 u8 speed = udma;
486 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
487 int a_speed = 3 << (drive_dn * 4);
488 int u_flag = 1 << drive_dn;
489 int v_flag = 0x01 << drive_dn;
490 int w_flag = 0x10 << drive_dn;
491 int u_speed = 0;
492 int sitre;
493 u16 reg4042, reg4a;
494 u8 reg48, reg54, reg55;
495
496 pci_read_config_word(dev, maslave, &reg4042);
497 DPRINTK("reg4042 = 0x%04x\n", reg4042);
498 sitre = (reg4042 & 0x4000) ? 1 : 0;
499 pci_read_config_byte(dev, 0x48, &reg48);
500 pci_read_config_word(dev, 0x4a, &reg4a);
501 pci_read_config_byte(dev, 0x54, &reg54);
502 pci_read_config_byte(dev, 0x55, &reg55);
503
504 switch(speed) {
505 case XFER_UDMA_4:
506 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
507 case XFER_UDMA_6:
508 case XFER_UDMA_5:
509 case XFER_UDMA_3:
510 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
511 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
512 case XFER_MW_DMA_2:
513 case XFER_MW_DMA_1: break;
514 default:
515 BUG();
516 return;
517 }
518
519 if (speed >= XFER_UDMA_0) {
520 if (!(reg48 & u_flag))
521 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
522 if (speed == XFER_UDMA_5) {
523 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
524 } else {
525 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
526 }
527 if ((reg4a & a_speed) != u_speed)
528 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
529 if (speed > XFER_UDMA_2) {
530 if (!(reg54 & v_flag))
531 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
532 } else
533 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
534 } else {
535 if (reg48 & u_flag)
536 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
537 if (reg4a & a_speed)
538 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
539 if (reg54 & v_flag)
540 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
541 if (reg55 & w_flag)
542 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
543 }
544 }
545
546 /* move to PCI layer, integrate w/ MSI stuff */
547 static void pci_enable_intx(struct pci_dev *pdev)
548 {
549 u16 pci_command;
550
551 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
552 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
553 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
554 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
555 }
556 }
557
558 #define AHCI_PCI_BAR 5
559 #define AHCI_GLOBAL_CTL 0x04
560 #define AHCI_ENABLE (1 << 31)
561 static int piix_disable_ahci(struct pci_dev *pdev)
562 {
563 void *mmio;
564 unsigned long addr;
565 u32 tmp;
566 int rc = 0;
567
568 /* BUG: pci_enable_device has not yet been called. This
569 * works because this device is usually set up by BIOS.
570 */
571
572 addr = pci_resource_start(pdev, AHCI_PCI_BAR);
573 if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
574 return 0;
575
576 mmio = ioremap(addr, 64);
577 if (!mmio)
578 return -ENOMEM;
579
580 tmp = readl(mmio + AHCI_GLOBAL_CTL);
581 if (tmp & AHCI_ENABLE) {
582 tmp &= ~AHCI_ENABLE;
583 writel(tmp, mmio + AHCI_GLOBAL_CTL);
584
585 tmp = readl(mmio + AHCI_GLOBAL_CTL);
586 if (tmp & AHCI_ENABLE)
587 rc = -EIO;
588 }
589
590 iounmap(mmio);
591 return rc;
592 }
593
594 /**
595 * piix_init_one - Register PIIX ATA PCI device with kernel services
596 * @pdev: PCI device to register
597 * @ent: Entry in piix_pci_tbl matching with @pdev
598 *
599 * Called from kernel PCI layer. We probe for combined mode (sigh),
600 * and then hand over control to libata, for it to do the rest.
601 *
602 * LOCKING:
603 * Inherited from PCI layer (may sleep).
604 *
605 * RETURNS:
606 * Zero on success, or -ERRNO value.
607 */
608
609 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
610 {
611 static int printed_version;
612 struct ata_port_info *port_info[2];
613 unsigned int combined = 0, n_ports = 1;
614 unsigned int pata_chan = 0, sata_chan = 0;
615
616 if (!printed_version++)
617 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
618
619 /* no hotplugging support (FIXME) */
620 if (!in_module_init)
621 return -ENODEV;
622
623 port_info[0] = &piix_port_info[ent->driver_data];
624 port_info[1] = NULL;
625
626 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
627 int rc = piix_disable_ahci(pdev);
628 if (rc)
629 return rc;
630 }
631
632 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
633 u8 tmp;
634 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
635
636 if (tmp & PIIX_COMB) {
637 combined = 1;
638 if (tmp & PIIX_COMB_PATA_P0)
639 sata_chan = 1;
640 else
641 pata_chan = 1;
642 }
643 }
644
645 /* On ICH5, some BIOSen disable the interrupt using the
646 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
647 * On ICH6, this bit has the same effect, but only when
648 * MSI is disabled (and it is disabled, as we don't use
649 * message-signalled interrupts currently).
650 */
651 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
652 pci_enable_intx(pdev);
653
654 if (combined) {
655 port_info[sata_chan] = &piix_port_info[ent->driver_data];
656 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
657 port_info[pata_chan] = &piix_port_info[ich5_pata];
658 n_ports++;
659
660 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
661 }
662
663 return ata_pci_init_one(pdev, port_info, n_ports);
664 }
665
666 static int __init piix_init(void)
667 {
668 int rc;
669
670 DPRINTK("pci_module_init\n");
671 rc = pci_module_init(&piix_pci_driver);
672 if (rc)
673 return rc;
674
675 in_module_init = 0;
676
677 DPRINTK("done\n");
678 return 0;
679 }
680
681 static void __exit piix_exit(void)
682 {
683 pci_unregister_driver(&piix_pci_driver);
684 }
685
686 module_init(piix_init);
687 module_exit(piix_exit);
688
kernel source for telekom puls (alcatel/mediatek)