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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / aic7xxx / aic7xxx_pci.c
1 /*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#79 $
43 */
44
45 #ifdef __linux__
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aic7xxx_93cx6.h"
49 #else
50 #include <dev/aic7xxx/aic7xxx_osm.h>
51 #include <dev/aic7xxx/aic7xxx_inline.h>
52 #include <dev/aic7xxx/aic7xxx_93cx6.h>
53 #endif
54
55 #include "aic7xxx_pci.h"
56
57 static __inline uint64_t
58 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
59 {
60 uint64_t id;
61
62 id = subvendor
63 | (subdevice << 16)
64 | ((uint64_t)vendor << 32)
65 | ((uint64_t)device << 48);
66
67 return (id);
68 }
69
70 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
71 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
72
73 #define DEVID_9005_TYPE(id) ((id) & 0xF)
74 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
75 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
76 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
77 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
78
79 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
80 #define DEVID_9005_MAXRATE_U160 0x0
81 #define DEVID_9005_MAXRATE_ULTRA2 0x1
82 #define DEVID_9005_MAXRATE_ULTRA 0x2
83 #define DEVID_9005_MAXRATE_FAST 0x3
84
85 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
86
87 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
88 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
89
90 #define SUBID_9005_TYPE(id) ((id) & 0xF)
91 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
92 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
93 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
94 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
95
96 #define SUBID_9005_TYPE_KNOWN(id) \
97 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
98 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
99 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
100 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
101
102 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
103 #define SUBID_9005_MAXRATE_ULTRA2 0x0
104 #define SUBID_9005_MAXRATE_ULTRA 0x1
105 #define SUBID_9005_MAXRATE_U160 0x2
106 #define SUBID_9005_MAXRATE_RESERVED 0x3
107
108 #define SUBID_9005_SEEPTYPE(id) \
109 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
110 ? ((id) & 0xC0) >> 6 \
111 : ((id) & 0x300) >> 8)
112 #define SUBID_9005_SEEPTYPE_NONE 0x0
113 #define SUBID_9005_SEEPTYPE_1K 0x1
114 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
115 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
116 #define SUBID_9005_AUTOTERM(id) \
117 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
118 ? (((id) & 0x400) >> 10) == 0 \
119 : (((id) & 0x40) >> 6) == 0)
120
121 #define SUBID_9005_NUMCHAN(id) \
122 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
123 ? ((id) & 0x300) >> 8 \
124 : ((id) & 0xC00) >> 10)
125
126 #define SUBID_9005_LEGACYCONN(id) \
127 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
128 ? 0 \
129 : ((id) & 0x80) >> 7)
130
131 #define SUBID_9005_MFUNCENB(id) \
132 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
133 ? ((id) & 0x800) >> 11 \
134 : ((id) & 0x1000) >> 12)
135 /*
136 * Informational only. Should use chip register to be
137 * certain, but may be use in identification strings.
138 */
139 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
140 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
141 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
142
143 static ahc_device_setup_t ahc_aic785X_setup;
144 static ahc_device_setup_t ahc_aic7860_setup;
145 static ahc_device_setup_t ahc_apa1480_setup;
146 static ahc_device_setup_t ahc_aic7870_setup;
147 static ahc_device_setup_t ahc_aha394X_setup;
148 static ahc_device_setup_t ahc_aha494X_setup;
149 static ahc_device_setup_t ahc_aha398X_setup;
150 static ahc_device_setup_t ahc_aic7880_setup;
151 static ahc_device_setup_t ahc_aha2940Pro_setup;
152 static ahc_device_setup_t ahc_aha394XU_setup;
153 static ahc_device_setup_t ahc_aha398XU_setup;
154 static ahc_device_setup_t ahc_aic7890_setup;
155 static ahc_device_setup_t ahc_aic7892_setup;
156 static ahc_device_setup_t ahc_aic7895_setup;
157 static ahc_device_setup_t ahc_aic7896_setup;
158 static ahc_device_setup_t ahc_aic7899_setup;
159 static ahc_device_setup_t ahc_aha29160C_setup;
160 static ahc_device_setup_t ahc_raid_setup;
161 static ahc_device_setup_t ahc_aha394XX_setup;
162 static ahc_device_setup_t ahc_aha494XX_setup;
163 static ahc_device_setup_t ahc_aha398XX_setup;
164
165 struct ahc_pci_identity ahc_pci_ident_table [] =
166 {
167 /* aic7850 based controllers */
168 {
169 ID_AHA_2902_04_10_15_20C_30C,
170 ID_ALL_MASK,
171 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
172 ahc_aic785X_setup
173 },
174 /* aic7860 based controllers */
175 {
176 ID_AHA_2930CU,
177 ID_ALL_MASK,
178 "Adaptec 2930CU SCSI adapter",
179 ahc_aic7860_setup
180 },
181 {
182 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
183 ID_DEV_VENDOR_MASK,
184 "Adaptec 1480A Ultra SCSI adapter",
185 ahc_apa1480_setup
186 },
187 {
188 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
189 ID_DEV_VENDOR_MASK,
190 "Adaptec 2940A Ultra SCSI adapter",
191 ahc_aic7860_setup
192 },
193 {
194 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
195 ID_DEV_VENDOR_MASK,
196 "Adaptec 2940A/CN Ultra SCSI adapter",
197 ahc_aic7860_setup
198 },
199 {
200 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
201 ID_DEV_VENDOR_MASK,
202 "Adaptec 2930C Ultra SCSI adapter (VAR)",
203 ahc_aic7860_setup
204 },
205 /* aic7870 based controllers */
206 {
207 ID_AHA_2940,
208 ID_ALL_MASK,
209 "Adaptec 2940 SCSI adapter",
210 ahc_aic7870_setup
211 },
212 {
213 ID_AHA_3940,
214 ID_ALL_MASK,
215 "Adaptec 3940 SCSI adapter",
216 ahc_aha394X_setup
217 },
218 {
219 ID_AHA_398X,
220 ID_ALL_MASK,
221 "Adaptec 398X SCSI RAID adapter",
222 ahc_aha398X_setup
223 },
224 {
225 ID_AHA_2944,
226 ID_ALL_MASK,
227 "Adaptec 2944 SCSI adapter",
228 ahc_aic7870_setup
229 },
230 {
231 ID_AHA_3944,
232 ID_ALL_MASK,
233 "Adaptec 3944 SCSI adapter",
234 ahc_aha394X_setup
235 },
236 {
237 ID_AHA_4944,
238 ID_ALL_MASK,
239 "Adaptec 4944 SCSI adapter",
240 ahc_aha494X_setup
241 },
242 /* aic7880 based controllers */
243 {
244 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
245 ID_DEV_VENDOR_MASK,
246 "Adaptec 2940 Ultra SCSI adapter",
247 ahc_aic7880_setup
248 },
249 {
250 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
251 ID_DEV_VENDOR_MASK,
252 "Adaptec 3940 Ultra SCSI adapter",
253 ahc_aha394XU_setup
254 },
255 {
256 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
257 ID_DEV_VENDOR_MASK,
258 "Adaptec 2944 Ultra SCSI adapter",
259 ahc_aic7880_setup
260 },
261 {
262 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
263 ID_DEV_VENDOR_MASK,
264 "Adaptec 3944 Ultra SCSI adapter",
265 ahc_aha394XU_setup
266 },
267 {
268 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
269 ID_DEV_VENDOR_MASK,
270 "Adaptec 398X Ultra SCSI RAID adapter",
271 ahc_aha398XU_setup
272 },
273 {
274 /*
275 * XXX Don't know the slot numbers
276 * so we can't identify channels
277 */
278 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
279 ID_DEV_VENDOR_MASK,
280 "Adaptec 4944 Ultra SCSI adapter",
281 ahc_aic7880_setup
282 },
283 {
284 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
285 ID_DEV_VENDOR_MASK,
286 "Adaptec 2930 Ultra SCSI adapter",
287 ahc_aic7880_setup
288 },
289 {
290 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
291 ID_DEV_VENDOR_MASK,
292 "Adaptec 2940 Pro Ultra SCSI adapter",
293 ahc_aha2940Pro_setup
294 },
295 {
296 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
297 ID_DEV_VENDOR_MASK,
298 "Adaptec 2940/CN Ultra SCSI adapter",
299 ahc_aic7880_setup
300 },
301 /* Ignore all SISL (AAC on MB) based controllers. */
302 {
303 ID_9005_SISL_ID,
304 ID_9005_SISL_MASK,
305 NULL,
306 NULL
307 },
308 /* aic7890 based controllers */
309 {
310 ID_AHA_2930U2,
311 ID_ALL_MASK,
312 "Adaptec 2930 Ultra2 SCSI adapter",
313 ahc_aic7890_setup
314 },
315 {
316 ID_AHA_2940U2B,
317 ID_ALL_MASK,
318 "Adaptec 2940B Ultra2 SCSI adapter",
319 ahc_aic7890_setup
320 },
321 {
322 ID_AHA_2940U2_OEM,
323 ID_ALL_MASK,
324 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
325 ahc_aic7890_setup
326 },
327 {
328 ID_AHA_2940U2,
329 ID_ALL_MASK,
330 "Adaptec 2940 Ultra2 SCSI adapter",
331 ahc_aic7890_setup
332 },
333 {
334 ID_AHA_2950U2B,
335 ID_ALL_MASK,
336 "Adaptec 2950 Ultra2 SCSI adapter",
337 ahc_aic7890_setup
338 },
339 {
340 ID_AIC7890_ARO,
341 ID_ALL_MASK,
342 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
343 ahc_aic7890_setup
344 },
345 {
346 ID_AAA_131U2,
347 ID_ALL_MASK,
348 "Adaptec AAA-131 Ultra2 RAID adapter",
349 ahc_aic7890_setup
350 },
351 /* aic7892 based controllers */
352 {
353 ID_AHA_29160,
354 ID_ALL_MASK,
355 "Adaptec 29160 Ultra160 SCSI adapter",
356 ahc_aic7892_setup
357 },
358 {
359 ID_AHA_29160_CPQ,
360 ID_ALL_MASK,
361 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
362 ahc_aic7892_setup
363 },
364 {
365 ID_AHA_29160N,
366 ID_ALL_MASK,
367 "Adaptec 29160N Ultra160 SCSI adapter",
368 ahc_aic7892_setup
369 },
370 {
371 ID_AHA_29160C,
372 ID_ALL_MASK,
373 "Adaptec 29160C Ultra160 SCSI adapter",
374 ahc_aha29160C_setup
375 },
376 {
377 ID_AHA_29160B,
378 ID_ALL_MASK,
379 "Adaptec 29160B Ultra160 SCSI adapter",
380 ahc_aic7892_setup
381 },
382 {
383 ID_AHA_19160B,
384 ID_ALL_MASK,
385 "Adaptec 19160B Ultra160 SCSI adapter",
386 ahc_aic7892_setup
387 },
388 {
389 ID_AIC7892_ARO,
390 ID_ALL_MASK,
391 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
392 ahc_aic7892_setup
393 },
394 {
395 ID_AHA_2915_30LP,
396 ID_ALL_MASK,
397 "Adaptec 2915/30LP Ultra160 SCSI adapter",
398 ahc_aic7892_setup
399 },
400 /* aic7895 based controllers */
401 {
402 ID_AHA_2940U_DUAL,
403 ID_ALL_MASK,
404 "Adaptec 2940/DUAL Ultra SCSI adapter",
405 ahc_aic7895_setup
406 },
407 {
408 ID_AHA_3940AU,
409 ID_ALL_MASK,
410 "Adaptec 3940A Ultra SCSI adapter",
411 ahc_aic7895_setup
412 },
413 {
414 ID_AHA_3944AU,
415 ID_ALL_MASK,
416 "Adaptec 3944A Ultra SCSI adapter",
417 ahc_aic7895_setup
418 },
419 {
420 ID_AIC7895_ARO,
421 ID_AIC7895_ARO_MASK,
422 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
423 ahc_aic7895_setup
424 },
425 /* aic7896/97 based controllers */
426 {
427 ID_AHA_3950U2B_0,
428 ID_ALL_MASK,
429 "Adaptec 3950B Ultra2 SCSI adapter",
430 ahc_aic7896_setup
431 },
432 {
433 ID_AHA_3950U2B_1,
434 ID_ALL_MASK,
435 "Adaptec 3950B Ultra2 SCSI adapter",
436 ahc_aic7896_setup
437 },
438 {
439 ID_AHA_3950U2D_0,
440 ID_ALL_MASK,
441 "Adaptec 3950D Ultra2 SCSI adapter",
442 ahc_aic7896_setup
443 },
444 {
445 ID_AHA_3950U2D_1,
446 ID_ALL_MASK,
447 "Adaptec 3950D Ultra2 SCSI adapter",
448 ahc_aic7896_setup
449 },
450 {
451 ID_AIC7896_ARO,
452 ID_ALL_MASK,
453 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
454 ahc_aic7896_setup
455 },
456 /* aic7899 based controllers */
457 {
458 ID_AHA_3960D,
459 ID_ALL_MASK,
460 "Adaptec 3960D Ultra160 SCSI adapter",
461 ahc_aic7899_setup
462 },
463 {
464 ID_AHA_3960D_CPQ,
465 ID_ALL_MASK,
466 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
467 ahc_aic7899_setup
468 },
469 {
470 ID_AIC7899_ARO,
471 ID_ALL_MASK,
472 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
473 ahc_aic7899_setup
474 },
475 /* Generic chip probes for devices we don't know 'exactly' */
476 {
477 ID_AIC7850 & ID_DEV_VENDOR_MASK,
478 ID_DEV_VENDOR_MASK,
479 "Adaptec aic7850 SCSI adapter",
480 ahc_aic785X_setup
481 },
482 {
483 ID_AIC7855 & ID_DEV_VENDOR_MASK,
484 ID_DEV_VENDOR_MASK,
485 "Adaptec aic7855 SCSI adapter",
486 ahc_aic785X_setup
487 },
488 {
489 ID_AIC7859 & ID_DEV_VENDOR_MASK,
490 ID_DEV_VENDOR_MASK,
491 "Adaptec aic7859 SCSI adapter",
492 ahc_aic7860_setup
493 },
494 {
495 ID_AIC7860 & ID_DEV_VENDOR_MASK,
496 ID_DEV_VENDOR_MASK,
497 "Adaptec aic7860 Ultra SCSI adapter",
498 ahc_aic7860_setup
499 },
500 {
501 ID_AIC7870 & ID_DEV_VENDOR_MASK,
502 ID_DEV_VENDOR_MASK,
503 "Adaptec aic7870 SCSI adapter",
504 ahc_aic7870_setup
505 },
506 {
507 ID_AIC7880 & ID_DEV_VENDOR_MASK,
508 ID_DEV_VENDOR_MASK,
509 "Adaptec aic7880 Ultra SCSI adapter",
510 ahc_aic7880_setup
511 },
512 {
513 ID_AIC7890 & ID_9005_GENERIC_MASK,
514 ID_9005_GENERIC_MASK,
515 "Adaptec aic7890/91 Ultra2 SCSI adapter",
516 ahc_aic7890_setup
517 },
518 {
519 ID_AIC7892 & ID_9005_GENERIC_MASK,
520 ID_9005_GENERIC_MASK,
521 "Adaptec aic7892 Ultra160 SCSI adapter",
522 ahc_aic7892_setup
523 },
524 {
525 ID_AIC7895 & ID_DEV_VENDOR_MASK,
526 ID_DEV_VENDOR_MASK,
527 "Adaptec aic7895 Ultra SCSI adapter",
528 ahc_aic7895_setup
529 },
530 {
531 ID_AIC7896 & ID_9005_GENERIC_MASK,
532 ID_9005_GENERIC_MASK,
533 "Adaptec aic7896/97 Ultra2 SCSI adapter",
534 ahc_aic7896_setup
535 },
536 {
537 ID_AIC7899 & ID_9005_GENERIC_MASK,
538 ID_9005_GENERIC_MASK,
539 "Adaptec aic7899 Ultra160 SCSI adapter",
540 ahc_aic7899_setup
541 },
542 {
543 ID_AIC7810 & ID_DEV_VENDOR_MASK,
544 ID_DEV_VENDOR_MASK,
545 "Adaptec aic7810 RAID memory controller",
546 ahc_raid_setup
547 },
548 {
549 ID_AIC7815 & ID_DEV_VENDOR_MASK,
550 ID_DEV_VENDOR_MASK,
551 "Adaptec aic7815 RAID memory controller",
552 ahc_raid_setup
553 }
554 };
555
556 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
557
558 #define AHC_394X_SLOT_CHANNEL_A 4
559 #define AHC_394X_SLOT_CHANNEL_B 5
560
561 #define AHC_398X_SLOT_CHANNEL_A 4
562 #define AHC_398X_SLOT_CHANNEL_B 8
563 #define AHC_398X_SLOT_CHANNEL_C 12
564
565 #define AHC_494X_SLOT_CHANNEL_A 4
566 #define AHC_494X_SLOT_CHANNEL_B 5
567 #define AHC_494X_SLOT_CHANNEL_C 6
568 #define AHC_494X_SLOT_CHANNEL_D 7
569
570 #define DEVCONFIG 0x40
571 #define PCIERRGENDIS 0x80000000ul
572 #define SCBSIZE32 0x00010000ul /* aic789X only */
573 #define REXTVALID 0x00001000ul /* ultra cards only */
574 #define MPORTMODE 0x00000400ul /* aic7870+ only */
575 #define RAMPSM 0x00000200ul /* aic7870+ only */
576 #define VOLSENSE 0x00000100ul
577 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
578 #define SCBRAMSEL 0x00000080ul
579 #define MRDCEN 0x00000040ul
580 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
581 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
582 #define BERREN 0x00000008ul
583 #define DACEN 0x00000004ul
584 #define STPWLEVEL 0x00000002ul
585 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
586
587 #define CSIZE_LATTIME 0x0c
588 #define CACHESIZE 0x0000003ful /* only 5 bits */
589 #define LATTIME 0x0000ff00ul
590
591 /* PCI STATUS definitions */
592 #define DPE 0x80
593 #define SSE 0x40
594 #define RMA 0x20
595 #define RTA 0x10
596 #define STA 0x08
597 #define DPR 0x01
598
599 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
600 uint16_t subvendor, uint16_t subdevice);
601 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
602 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
603 int pcheck, int fast, int large);
604 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
605 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
606 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
607 struct seeprom_config *sc);
608 static void configure_termination(struct ahc_softc *ahc,
609 struct seeprom_descriptor *sd,
610 u_int adapter_control,
611 u_int *sxfrctl1);
612
613 static void ahc_new_term_detect(struct ahc_softc *ahc,
614 int *enableSEC_low,
615 int *enableSEC_high,
616 int *enablePRI_low,
617 int *enablePRI_high,
618 int *eeprom_present);
619 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
620 int *internal68_present,
621 int *externalcable_present,
622 int *eeprom_present);
623 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
624 int *externalcable_present,
625 int *eeprom_present);
626 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
627 static uint8_t read_brdctl(struct ahc_softc *ahc);
628 static void ahc_pci_intr(struct ahc_softc *ahc);
629 static int ahc_pci_chip_init(struct ahc_softc *ahc);
630 static int ahc_pci_suspend(struct ahc_softc *ahc);
631 static int ahc_pci_resume(struct ahc_softc *ahc);
632
633 static int
634 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
635 uint16_t subdevice, uint16_t subvendor)
636 {
637 int result;
638
639 /* Default to invalid. */
640 result = 0;
641 if (vendor == 0x9005
642 && subvendor == 0x9005
643 && subdevice != device
644 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
645
646 switch (SUBID_9005_TYPE(subdevice)) {
647 case SUBID_9005_TYPE_MB:
648 break;
649 case SUBID_9005_TYPE_CARD:
650 case SUBID_9005_TYPE_LCCARD:
651 /*
652 * Currently only trust Adaptec cards to
653 * get the sub device info correct.
654 */
655 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
656 result = 1;
657 break;
658 case SUBID_9005_TYPE_RAID:
659 break;
660 default:
661 break;
662 }
663 }
664 return (result);
665 }
666
667 struct ahc_pci_identity *
668 ahc_find_pci_device(ahc_dev_softc_t pci)
669 {
670 uint64_t full_id;
671 uint16_t device;
672 uint16_t vendor;
673 uint16_t subdevice;
674 uint16_t subvendor;
675 struct ahc_pci_identity *entry;
676 u_int i;
677
678 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
679 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
680 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
681 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
682 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
683
684 /*
685 * If the second function is not hooked up, ignore it.
686 * Unfortunately, not all MB vendors implement the
687 * subdevice ID as per the Adaptec spec, so do our best
688 * to sanity check it prior to accepting the subdevice
689 * ID as valid.
690 */
691 if (ahc_get_pci_function(pci) > 0
692 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
693 && SUBID_9005_MFUNCENB(subdevice) == 0)
694 return (NULL);
695
696 for (i = 0; i < ahc_num_pci_devs; i++) {
697 entry = &ahc_pci_ident_table[i];
698 if (entry->full_id == (full_id & entry->id_mask)) {
699 /* Honor exclusion entries. */
700 if (entry->name == NULL)
701 return (NULL);
702 return (entry);
703 }
704 }
705 return (NULL);
706 }
707
708 int
709 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
710 {
711 u_int command;
712 u_int our_id;
713 u_int sxfrctl1;
714 u_int scsiseq;
715 u_int dscommand0;
716 uint32_t devconfig;
717 int error;
718 uint8_t sblkctl;
719
720 our_id = 0;
721 error = entry->setup(ahc);
722 if (error != 0)
723 return (error);
724 ahc->chip |= AHC_PCI;
725 ahc->description = entry->name;
726
727 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
728
729 error = ahc_pci_map_registers(ahc);
730 if (error != 0)
731 return (error);
732
733 /*
734 * Before we continue probing the card, ensure that
735 * its interrupts are *disabled*. We don't want
736 * a misstep to hang the machine in an interrupt
737 * storm.
738 */
739 ahc_intr_enable(ahc, FALSE);
740
741 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
742
743 /*
744 * If we need to support high memory, enable dual
745 * address cycles. This bit must be set to enable
746 * high address bit generation even if we are on a
747 * 64bit bus (PCI64BIT set in devconfig).
748 */
749 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
750
751 if (bootverbose)
752 printf("%s: Enabling 39Bit Addressing\n",
753 ahc_name(ahc));
754 devconfig |= DACEN;
755 }
756
757 /* Ensure that pci error generation, a test feature, is disabled. */
758 devconfig |= PCIERRGENDIS;
759
760 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
761
762 /* Ensure busmastering is enabled */
763 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
764 command |= PCIM_CMD_BUSMASTEREN;
765
766 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
767
768 /* On all PCI adapters, we allow SCB paging */
769 ahc->flags |= AHC_PAGESCBS;
770
771 error = ahc_softc_init(ahc);
772 if (error != 0)
773 return (error);
774
775 /*
776 * Disable PCI parity error checking. Users typically
777 * do this to work around broken PCI chipsets that get
778 * the parity timing wrong and thus generate lots of spurious
779 * errors. The chip only allows us to disable *all* parity
780 * error reporting when doing this, so CIO bus, scb ram, and
781 * scratch ram parity errors will be ignored too.
782 */
783 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
784 ahc->seqctl |= FAILDIS;
785
786 ahc->bus_intr = ahc_pci_intr;
787 ahc->bus_chip_init = ahc_pci_chip_init;
788 ahc->bus_suspend = ahc_pci_suspend;
789 ahc->bus_resume = ahc_pci_resume;
790
791 /* Remeber how the card was setup in case there is no SEEPROM */
792 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
793 ahc_pause(ahc);
794 if ((ahc->features & AHC_ULTRA2) != 0)
795 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
796 else
797 our_id = ahc_inb(ahc, SCSIID) & OID;
798 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
799 scsiseq = ahc_inb(ahc, SCSISEQ);
800 } else {
801 sxfrctl1 = STPWEN;
802 our_id = 7;
803 scsiseq = 0;
804 }
805
806 error = ahc_reset(ahc, /*reinit*/FALSE);
807 if (error != 0)
808 return (ENXIO);
809
810 if ((ahc->features & AHC_DT) != 0) {
811 u_int sfunct;
812
813 /* Perform ALT-Mode Setup */
814 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
815 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
816 ahc_outb(ahc, OPTIONMODE,
817 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
818 ahc_outb(ahc, SFUNCT, sfunct);
819
820 /* Normal mode setup */
821 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
822 |TARGCRCENDEN);
823 }
824
825 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
826 dscommand0 |= MPARCKEN|CACHETHEN;
827 if ((ahc->features & AHC_ULTRA2) != 0) {
828
829 /*
830 * DPARCKEN doesn't work correctly on
831 * some MBs so don't use it.
832 */
833 dscommand0 &= ~DPARCKEN;
834 }
835
836 /*
837 * Handle chips that must have cache line
838 * streaming (dis/en)abled.
839 */
840 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
841 dscommand0 |= CACHETHEN;
842
843 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
844 dscommand0 &= ~CACHETHEN;
845
846 ahc_outb(ahc, DSCOMMAND0, dscommand0);
847
848 ahc->pci_cachesize =
849 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
850 /*bytes*/1) & CACHESIZE;
851 ahc->pci_cachesize *= 4;
852
853 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
854 && ahc->pci_cachesize == 4) {
855
856 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
857 0, /*bytes*/1);
858 ahc->pci_cachesize = 0;
859 }
860
861 /*
862 * We cannot perform ULTRA speeds without the presense
863 * of the external precision resistor.
864 */
865 if ((ahc->features & AHC_ULTRA) != 0) {
866 uint32_t devconfig;
867
868 devconfig = ahc_pci_read_config(ahc->dev_softc,
869 DEVCONFIG, /*bytes*/4);
870 if ((devconfig & REXTVALID) == 0)
871 ahc->features &= ~AHC_ULTRA;
872 }
873
874 /* See if we have a SEEPROM and perform auto-term */
875 check_extport(ahc, &sxfrctl1);
876
877 /*
878 * Take the LED out of diagnostic mode
879 */
880 sblkctl = ahc_inb(ahc, SBLKCTL);
881 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
882
883 if ((ahc->features & AHC_ULTRA2) != 0) {
884 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
885 } else {
886 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
887 }
888
889 if (ahc->flags & AHC_USEDEFAULTS) {
890 /*
891 * PCI Adapter default setup
892 * Should only be used if the adapter does not have
893 * a SEEPROM.
894 */
895 /* See if someone else set us up already */
896 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
897 && scsiseq != 0) {
898 printf("%s: Using left over BIOS settings\n",
899 ahc_name(ahc));
900 ahc->flags &= ~AHC_USEDEFAULTS;
901 ahc->flags |= AHC_BIOS_ENABLED;
902 } else {
903 /*
904 * Assume only one connector and always turn
905 * on termination.
906 */
907 our_id = 0x07;
908 sxfrctl1 = STPWEN;
909 }
910 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
911
912 ahc->our_id = our_id;
913 }
914
915 /*
916 * Take a look to see if we have external SRAM.
917 * We currently do not attempt to use SRAM that is
918 * shared among multiple controllers.
919 */
920 ahc_probe_ext_scbram(ahc);
921
922 /*
923 * Record our termination setting for the
924 * generic initialization routine.
925 */
926 if ((sxfrctl1 & STPWEN) != 0)
927 ahc->flags |= AHC_TERM_ENB_A;
928
929 /*
930 * Save chip register configuration data for chip resets
931 * that occur during runtime and resume events.
932 */
933 ahc->bus_softc.pci_softc.devconfig =
934 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
935 ahc->bus_softc.pci_softc.command =
936 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
937 ahc->bus_softc.pci_softc.csize_lattime =
938 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
939 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
940 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
941 if ((ahc->features & AHC_DT) != 0) {
942 u_int sfunct;
943
944 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
945 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
946 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
947 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
948 ahc_outb(ahc, SFUNCT, sfunct);
949 ahc->bus_softc.pci_softc.crccontrol1 =
950 ahc_inb(ahc, CRCCONTROL1);
951 }
952 if ((ahc->features & AHC_MULTI_FUNC) != 0)
953 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
954
955 if ((ahc->features & AHC_ULTRA2) != 0)
956 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
957
958 /* Core initialization */
959 error = ahc_init(ahc);
960 if (error != 0)
961 return (error);
962
963 /*
964 * Allow interrupts now that we are completely setup.
965 */
966 error = ahc_pci_map_int(ahc);
967 if (error != 0)
968 return (error);
969
970 ahc->init_level++;
971 return (0);
972 }
973
974 /*
975 * Test for the presense of external sram in an
976 * "unshared" configuration.
977 */
978 static int
979 ahc_ext_scbram_present(struct ahc_softc *ahc)
980 {
981 u_int chip;
982 int ramps;
983 int single_user;
984 uint32_t devconfig;
985
986 chip = ahc->chip & AHC_CHIPID_MASK;
987 devconfig = ahc_pci_read_config(ahc->dev_softc,
988 DEVCONFIG, /*bytes*/4);
989 single_user = (devconfig & MPORTMODE) != 0;
990
991 if ((ahc->features & AHC_ULTRA2) != 0)
992 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
993 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
994 /*
995 * External SCBRAM arbitration is flakey
996 * on these chips. Unfortunately this means
997 * we don't use the extra SCB ram space on the
998 * 3940AUW.
999 */
1000 ramps = 0;
1001 else if (chip >= AHC_AIC7870)
1002 ramps = (devconfig & RAMPSM) != 0;
1003 else
1004 ramps = 0;
1005
1006 if (ramps && single_user)
1007 return (1);
1008 return (0);
1009 }
1010
1011 /*
1012 * Enable external scbram.
1013 */
1014 static void
1015 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1016 int fast, int large)
1017 {
1018 uint32_t devconfig;
1019
1020 if (ahc->features & AHC_MULTI_FUNC) {
1021 /*
1022 * Set the SCB Base addr (highest address bit)
1023 * depending on which channel we are.
1024 */
1025 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1026 }
1027
1028 ahc->flags &= ~AHC_LSCBS_ENABLED;
1029 if (large)
1030 ahc->flags |= AHC_LSCBS_ENABLED;
1031 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1032 if ((ahc->features & AHC_ULTRA2) != 0) {
1033 u_int dscommand0;
1034
1035 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1036 if (enable)
1037 dscommand0 &= ~INTSCBRAMSEL;
1038 else
1039 dscommand0 |= INTSCBRAMSEL;
1040 if (large)
1041 dscommand0 &= ~USCBSIZE32;
1042 else
1043 dscommand0 |= USCBSIZE32;
1044 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1045 } else {
1046 if (fast)
1047 devconfig &= ~EXTSCBTIME;
1048 else
1049 devconfig |= EXTSCBTIME;
1050 if (enable)
1051 devconfig &= ~SCBRAMSEL;
1052 else
1053 devconfig |= SCBRAMSEL;
1054 if (large)
1055 devconfig &= ~SCBSIZE32;
1056 else
1057 devconfig |= SCBSIZE32;
1058 }
1059 if (pcheck)
1060 devconfig |= EXTSCBPEN;
1061 else
1062 devconfig &= ~EXTSCBPEN;
1063
1064 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1065 }
1066
1067 /*
1068 * Take a look to see if we have external SRAM.
1069 * We currently do not attempt to use SRAM that is
1070 * shared among multiple controllers.
1071 */
1072 static void
1073 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1074 {
1075 int num_scbs;
1076 int test_num_scbs;
1077 int enable;
1078 int pcheck;
1079 int fast;
1080 int large;
1081
1082 enable = FALSE;
1083 pcheck = FALSE;
1084 fast = FALSE;
1085 large = FALSE;
1086 num_scbs = 0;
1087
1088 if (ahc_ext_scbram_present(ahc) == 0)
1089 goto done;
1090
1091 /*
1092 * Probe for the best parameters to use.
1093 */
1094 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1095 num_scbs = ahc_probe_scbs(ahc);
1096 if (num_scbs == 0) {
1097 /* The SRAM wasn't really present. */
1098 goto done;
1099 }
1100 enable = TRUE;
1101
1102 /*
1103 * Clear any outstanding parity error
1104 * and ensure that parity error reporting
1105 * is enabled.
1106 */
1107 ahc_outb(ahc, SEQCTL, 0);
1108 ahc_outb(ahc, CLRINT, CLRPARERR);
1109 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1110
1111 /* Now see if we can do parity */
1112 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1113 num_scbs = ahc_probe_scbs(ahc);
1114 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1115 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1116 pcheck = TRUE;
1117
1118 /* Clear any resulting parity error */
1119 ahc_outb(ahc, CLRINT, CLRPARERR);
1120 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1121
1122 /* Now see if we can do fast timing */
1123 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1124 test_num_scbs = ahc_probe_scbs(ahc);
1125 if (test_num_scbs == num_scbs
1126 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1127 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1128 fast = TRUE;
1129
1130 /*
1131 * See if we can use large SCBs and still maintain
1132 * the same overall count of SCBs.
1133 */
1134 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1135 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1136 test_num_scbs = ahc_probe_scbs(ahc);
1137 if (test_num_scbs >= num_scbs) {
1138 large = TRUE;
1139 num_scbs = test_num_scbs;
1140 if (num_scbs >= 64) {
1141 /*
1142 * We have enough space to move the
1143 * "busy targets table" into SCB space
1144 * and make it qualify all the way to the
1145 * lun level.
1146 */
1147 ahc->flags |= AHC_SCB_BTT;
1148 }
1149 }
1150 }
1151 done:
1152 /*
1153 * Disable parity error reporting until we
1154 * can load instruction ram.
1155 */
1156 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1157 /* Clear any latched parity error */
1158 ahc_outb(ahc, CLRINT, CLRPARERR);
1159 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1160 if (bootverbose && enable) {
1161 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1162 ahc_name(ahc), fast ? "fast" : "slow",
1163 pcheck ? ", parity checking enabled" : "",
1164 large ? 64 : 32);
1165 }
1166 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1167 }
1168
1169 /*
1170 * Perform some simple tests that should catch situations where
1171 * our registers are invalidly mapped.
1172 */
1173 int
1174 ahc_pci_test_register_access(struct ahc_softc *ahc)
1175 {
1176 int error;
1177 u_int status1;
1178 uint32_t cmd;
1179 uint8_t hcntrl;
1180
1181 error = EIO;
1182
1183 /*
1184 * Enable PCI error interrupt status, but suppress NMIs
1185 * generated by SERR raised due to target aborts.
1186 */
1187 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1188 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1189 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1190
1191 /*
1192 * First a simple test to see if any
1193 * registers can be read. Reading
1194 * HCNTRL has no side effects and has
1195 * at least one bit that is guaranteed to
1196 * be zero so it is a good register to
1197 * use for this test.
1198 */
1199 hcntrl = ahc_inb(ahc, HCNTRL);
1200
1201 if (hcntrl == 0xFF)
1202 goto fail;
1203
1204 if ((hcntrl & CHIPRST) != 0) {
1205 /*
1206 * The chip has not been initialized since
1207 * PCI/EISA/VLB bus reset. Don't trust
1208 * "left over BIOS data".
1209 */
1210 ahc->flags |= AHC_NO_BIOS_INIT;
1211 }
1212
1213 /*
1214 * Next create a situation where write combining
1215 * or read prefetching could be initiated by the
1216 * CPU or host bridge. Our device does not support
1217 * either, so look for data corruption and/or flagged
1218 * PCI errors. First pause without causing another
1219 * chip reset.
1220 */
1221 hcntrl &= ~CHIPRST;
1222 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1223 while (ahc_is_paused(ahc) == 0)
1224 ;
1225
1226 /* Clear any PCI errors that occurred before our driver attached. */
1227 status1 = ahc_pci_read_config(ahc->dev_softc,
1228 PCIR_STATUS + 1, /*bytes*/1);
1229 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1230 status1, /*bytes*/1);
1231 ahc_outb(ahc, CLRINT, CLRPARERR);
1232
1233 ahc_outb(ahc, SEQCTL, PERRORDIS);
1234 ahc_outb(ahc, SCBPTR, 0);
1235 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1236 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1237 goto fail;
1238
1239 status1 = ahc_pci_read_config(ahc->dev_softc,
1240 PCIR_STATUS + 1, /*bytes*/1);
1241 if ((status1 & STA) != 0)
1242 goto fail;
1243
1244 error = 0;
1245
1246 fail:
1247 /* Silently clear any latched errors. */
1248 status1 = ahc_pci_read_config(ahc->dev_softc,
1249 PCIR_STATUS + 1, /*bytes*/1);
1250 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1251 status1, /*bytes*/1);
1252 ahc_outb(ahc, CLRINT, CLRPARERR);
1253 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1254 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1255 return (error);
1256 }
1257
1258 /*
1259 * Check the external port logic for a serial eeprom
1260 * and termination/cable detection contrls.
1261 */
1262 static void
1263 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1264 {
1265 struct seeprom_descriptor sd;
1266 struct seeprom_config *sc;
1267 int have_seeprom;
1268 int have_autoterm;
1269
1270 sd.sd_ahc = ahc;
1271 sd.sd_control_offset = SEECTL;
1272 sd.sd_status_offset = SEECTL;
1273 sd.sd_dataout_offset = SEECTL;
1274 sc = ahc->seep_config;
1275
1276 /*
1277 * For some multi-channel devices, the c46 is simply too
1278 * small to work. For the other controller types, we can
1279 * get our information from either SEEPROM type. Set the
1280 * type to start our probe with accordingly.
1281 */
1282 if (ahc->flags & AHC_LARGE_SEEPROM)
1283 sd.sd_chip = C56_66;
1284 else
1285 sd.sd_chip = C46;
1286
1287 sd.sd_MS = SEEMS;
1288 sd.sd_RDY = SEERDY;
1289 sd.sd_CS = SEECS;
1290 sd.sd_CK = SEECK;
1291 sd.sd_DO = SEEDO;
1292 sd.sd_DI = SEEDI;
1293
1294 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1295 if (have_seeprom) {
1296
1297 if (bootverbose)
1298 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1299
1300 for (;;) {
1301 u_int start_addr;
1302
1303 start_addr = 32 * (ahc->channel - 'A');
1304
1305 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1306 start_addr,
1307 sizeof(*sc)/2);
1308
1309 if (have_seeprom)
1310 have_seeprom = ahc_verify_cksum(sc);
1311
1312 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1313 if (bootverbose) {
1314 if (have_seeprom == 0)
1315 printf ("checksum error\n");
1316 else
1317 printf ("done.\n");
1318 }
1319 break;
1320 }
1321 sd.sd_chip = C56_66;
1322 }
1323 ahc_release_seeprom(&sd);
1324
1325 /* Remember the SEEPROM type for later */
1326 if (sd.sd_chip == C56_66)
1327 ahc->flags |= AHC_LARGE_SEEPROM;
1328 }
1329
1330 if (!have_seeprom) {
1331 /*
1332 * Pull scratch ram settings and treat them as
1333 * if they are the contents of an seeprom if
1334 * the 'ADPT' signature is found in SCB2.
1335 * We manually compose the data as 16bit values
1336 * to avoid endian issues.
1337 */
1338 ahc_outb(ahc, SCBPTR, 2);
1339 if (ahc_inb(ahc, SCB_BASE) == 'A'
1340 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1341 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1342 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1343 uint16_t *sc_data;
1344 int i;
1345
1346 sc_data = (uint16_t *)sc;
1347 for (i = 0; i < 32; i++, sc_data++) {
1348 int j;
1349
1350 j = i * 2;
1351 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1352 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1353 }
1354 have_seeprom = ahc_verify_cksum(sc);
1355 if (have_seeprom)
1356 ahc->flags |= AHC_SCB_CONFIG_USED;
1357 }
1358 /*
1359 * Clear any SCB parity errors in case this data and
1360 * its associated parity was not initialized by the BIOS
1361 */
1362 ahc_outb(ahc, CLRINT, CLRPARERR);
1363 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1364 }
1365
1366 if (!have_seeprom) {
1367 if (bootverbose)
1368 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1369 ahc->flags |= AHC_USEDEFAULTS;
1370 free(ahc->seep_config, M_DEVBUF);
1371 ahc->seep_config = NULL;
1372 sc = NULL;
1373 } else {
1374 ahc_parse_pci_eeprom(ahc, sc);
1375 }
1376
1377 /*
1378 * Cards that have the external logic necessary to talk to
1379 * a SEEPROM, are almost certain to have the remaining logic
1380 * necessary for auto-termination control. This assumption
1381 * hasn't failed yet...
1382 */
1383 have_autoterm = have_seeprom;
1384
1385 /*
1386 * Some low-cost chips have SEEPROM and auto-term control built
1387 * in, instead of using a GAL. They can tell us directly
1388 * if the termination logic is enabled.
1389 */
1390 if ((ahc->features & AHC_SPIOCAP) != 0) {
1391 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1392 have_autoterm = FALSE;
1393 }
1394
1395 if (have_autoterm) {
1396 ahc->flags |= AHC_HAS_TERM_LOGIC;
1397 ahc_acquire_seeprom(ahc, &sd);
1398 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1399 ahc_release_seeprom(&sd);
1400 } else if (have_seeprom) {
1401 *sxfrctl1 &= ~STPWEN;
1402 if ((sc->adapter_control & CFSTERM) != 0)
1403 *sxfrctl1 |= STPWEN;
1404 if (bootverbose)
1405 printf("%s: Low byte termination %sabled\n",
1406 ahc_name(ahc),
1407 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1408 }
1409 }
1410
1411 static void
1412 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1413 {
1414 /*
1415 * Put the data we've collected down into SRAM
1416 * where ahc_init will find it.
1417 */
1418 int i;
1419 int max_targ = sc->max_targets & CFMAXTARG;
1420 u_int scsi_conf;
1421 uint16_t discenable;
1422 uint16_t ultraenb;
1423
1424 discenable = 0;
1425 ultraenb = 0;
1426 if ((sc->adapter_control & CFULTRAEN) != 0) {
1427 /*
1428 * Determine if this adapter has a "newstyle"
1429 * SEEPROM format.
1430 */
1431 for (i = 0; i < max_targ; i++) {
1432 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1433 ahc->flags |= AHC_NEWEEPROM_FMT;
1434 break;
1435 }
1436 }
1437 }
1438
1439 for (i = 0; i < max_targ; i++) {
1440 u_int scsirate;
1441 uint16_t target_mask;
1442
1443 target_mask = 0x01 << i;
1444 if (sc->device_flags[i] & CFDISC)
1445 discenable |= target_mask;
1446 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1447 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1448 ultraenb |= target_mask;
1449 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1450 ultraenb |= target_mask;
1451 }
1452 if ((sc->device_flags[i] & CFXFER) == 0x04
1453 && (ultraenb & target_mask) != 0) {
1454 /* Treat 10MHz as a non-ultra speed */
1455 sc->device_flags[i] &= ~CFXFER;
1456 ultraenb &= ~target_mask;
1457 }
1458 if ((ahc->features & AHC_ULTRA2) != 0) {
1459 u_int offset;
1460
1461 if (sc->device_flags[i] & CFSYNCH)
1462 offset = MAX_OFFSET_ULTRA2;
1463 else
1464 offset = 0;
1465 ahc_outb(ahc, TARG_OFFSET + i, offset);
1466
1467 /*
1468 * The ultra enable bits contain the
1469 * high bit of the ultra2 sync rate
1470 * field.
1471 */
1472 scsirate = (sc->device_flags[i] & CFXFER)
1473 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1474 if (sc->device_flags[i] & CFWIDEB)
1475 scsirate |= WIDEXFER;
1476 } else {
1477 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1478 if (sc->device_flags[i] & CFSYNCH)
1479 scsirate |= SOFS;
1480 if (sc->device_flags[i] & CFWIDEB)
1481 scsirate |= WIDEXFER;
1482 }
1483 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1484 }
1485 ahc->our_id = sc->brtime_id & CFSCSIID;
1486
1487 scsi_conf = (ahc->our_id & 0x7);
1488 if (sc->adapter_control & CFSPARITY)
1489 scsi_conf |= ENSPCHK;
1490 if (sc->adapter_control & CFRESETB)
1491 scsi_conf |= RESET_SCSI;
1492
1493 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1494
1495 if (sc->bios_control & CFEXTEND)
1496 ahc->flags |= AHC_EXTENDED_TRANS_A;
1497
1498 if (sc->bios_control & CFBIOSEN)
1499 ahc->flags |= AHC_BIOS_ENABLED;
1500 if (ahc->features & AHC_ULTRA
1501 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1502 /* Should we enable Ultra mode? */
1503 if (!(sc->adapter_control & CFULTRAEN))
1504 /* Treat us as a non-ultra card */
1505 ultraenb = 0;
1506 }
1507
1508 if (sc->signature == CFSIGNATURE
1509 || sc->signature == CFSIGNATURE2) {
1510 uint32_t devconfig;
1511
1512 /* Honor the STPWLEVEL settings */
1513 devconfig = ahc_pci_read_config(ahc->dev_softc,
1514 DEVCONFIG, /*bytes*/4);
1515 devconfig &= ~STPWLEVEL;
1516 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1517 devconfig |= STPWLEVEL;
1518 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1519 devconfig, /*bytes*/4);
1520 }
1521 /* Set SCSICONF info */
1522 ahc_outb(ahc, SCSICONF, scsi_conf);
1523 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1524 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1525 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1526 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1527 }
1528
1529 static void
1530 configure_termination(struct ahc_softc *ahc,
1531 struct seeprom_descriptor *sd,
1532 u_int adapter_control,
1533 u_int *sxfrctl1)
1534 {
1535 uint8_t brddat;
1536
1537 brddat = 0;
1538
1539 /*
1540 * Update the settings in sxfrctl1 to match the
1541 * termination settings
1542 */
1543 *sxfrctl1 = 0;
1544
1545 /*
1546 * SEECS must be on for the GALS to latch
1547 * the data properly. Be sure to leave MS
1548 * on or we will release the seeprom.
1549 */
1550 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1551 if ((adapter_control & CFAUTOTERM) != 0
1552 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1553 int internal50_present;
1554 int internal68_present;
1555 int externalcable_present;
1556 int eeprom_present;
1557 int enableSEC_low;
1558 int enableSEC_high;
1559 int enablePRI_low;
1560 int enablePRI_high;
1561 int sum;
1562
1563 enableSEC_low = 0;
1564 enableSEC_high = 0;
1565 enablePRI_low = 0;
1566 enablePRI_high = 0;
1567 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1568 ahc_new_term_detect(ahc, &enableSEC_low,
1569 &enableSEC_high,
1570 &enablePRI_low,
1571 &enablePRI_high,
1572 &eeprom_present);
1573 if ((adapter_control & CFSEAUTOTERM) == 0) {
1574 if (bootverbose)
1575 printf("%s: Manual SE Termination\n",
1576 ahc_name(ahc));
1577 enableSEC_low = (adapter_control & CFSELOWTERM);
1578 enableSEC_high =
1579 (adapter_control & CFSEHIGHTERM);
1580 }
1581 if ((adapter_control & CFAUTOTERM) == 0) {
1582 if (bootverbose)
1583 printf("%s: Manual LVD Termination\n",
1584 ahc_name(ahc));
1585 enablePRI_low = (adapter_control & CFSTERM);
1586 enablePRI_high = (adapter_control & CFWSTERM);
1587 }
1588 /* Make the table calculations below happy */
1589 internal50_present = 0;
1590 internal68_present = 1;
1591 externalcable_present = 1;
1592 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1593 aic785X_cable_detect(ahc, &internal50_present,
1594 &externalcable_present,
1595 &eeprom_present);
1596 /* Can never support a wide connector. */
1597 internal68_present = 0;
1598 } else {
1599 aic787X_cable_detect(ahc, &internal50_present,
1600 &internal68_present,
1601 &externalcable_present,
1602 &eeprom_present);
1603 }
1604
1605 if ((ahc->features & AHC_WIDE) == 0)
1606 internal68_present = 0;
1607
1608 if (bootverbose
1609 && (ahc->features & AHC_ULTRA2) == 0) {
1610 printf("%s: internal 50 cable %s present",
1611 ahc_name(ahc),
1612 internal50_present ? "is":"not");
1613
1614 if ((ahc->features & AHC_WIDE) != 0)
1615 printf(", internal 68 cable %s present",
1616 internal68_present ? "is":"not");
1617 printf("\n%s: external cable %s present\n",
1618 ahc_name(ahc),
1619 externalcable_present ? "is":"not");
1620 }
1621 if (bootverbose)
1622 printf("%s: BIOS eeprom %s present\n",
1623 ahc_name(ahc), eeprom_present ? "is" : "not");
1624
1625 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1626 /*
1627 * The 50 pin connector is a separate bus,
1628 * so force it to always be terminated.
1629 * In the future, perform current sensing
1630 * to determine if we are in the middle of
1631 * a properly terminated bus.
1632 */
1633 internal50_present = 0;
1634 }
1635
1636 /*
1637 * Now set the termination based on what
1638 * we found.
1639 * Flash Enable = BRDDAT7
1640 * Secondary High Term Enable = BRDDAT6
1641 * Secondary Low Term Enable = BRDDAT5 (7890)
1642 * Primary High Term Enable = BRDDAT4 (7890)
1643 */
1644 if ((ahc->features & AHC_ULTRA2) == 0
1645 && (internal50_present != 0)
1646 && (internal68_present != 0)
1647 && (externalcable_present != 0)) {
1648 printf("%s: Illegal cable configuration!!. "
1649 "Only two connectors on the "
1650 "adapter may be used at a "
1651 "time!\n", ahc_name(ahc));
1652
1653 /*
1654 * Pretend there are no cables in the hope
1655 * that having all of the termination on
1656 * gives us a more stable bus.
1657 */
1658 internal50_present = 0;
1659 internal68_present = 0;
1660 externalcable_present = 0;
1661 }
1662
1663 if ((ahc->features & AHC_WIDE) != 0
1664 && ((externalcable_present == 0)
1665 || (internal68_present == 0)
1666 || (enableSEC_high != 0))) {
1667 brddat |= BRDDAT6;
1668 if (bootverbose) {
1669 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1670 printf("%s: 68 pin termination "
1671 "Enabled\n", ahc_name(ahc));
1672 else
1673 printf("%s: %sHigh byte termination "
1674 "Enabled\n", ahc_name(ahc),
1675 enableSEC_high ? "Secondary "
1676 : "");
1677 }
1678 }
1679
1680 sum = internal50_present + internal68_present
1681 + externalcable_present;
1682 if (sum < 2 || (enableSEC_low != 0)) {
1683 if ((ahc->features & AHC_ULTRA2) != 0)
1684 brddat |= BRDDAT5;
1685 else
1686 *sxfrctl1 |= STPWEN;
1687 if (bootverbose) {
1688 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1689 printf("%s: 50 pin termination "
1690 "Enabled\n", ahc_name(ahc));
1691 else
1692 printf("%s: %sLow byte termination "
1693 "Enabled\n", ahc_name(ahc),
1694 enableSEC_low ? "Secondary "
1695 : "");
1696 }
1697 }
1698
1699 if (enablePRI_low != 0) {
1700 *sxfrctl1 |= STPWEN;
1701 if (bootverbose)
1702 printf("%s: Primary Low Byte termination "
1703 "Enabled\n", ahc_name(ahc));
1704 }
1705
1706 /*
1707 * Setup STPWEN before setting up the rest of
1708 * the termination per the tech note on the U160 cards.
1709 */
1710 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1711
1712 if (enablePRI_high != 0) {
1713 brddat |= BRDDAT4;
1714 if (bootverbose)
1715 printf("%s: Primary High Byte "
1716 "termination Enabled\n",
1717 ahc_name(ahc));
1718 }
1719
1720 write_brdctl(ahc, brddat);
1721
1722 } else {
1723 if ((adapter_control & CFSTERM) != 0) {
1724 *sxfrctl1 |= STPWEN;
1725
1726 if (bootverbose)
1727 printf("%s: %sLow byte termination Enabled\n",
1728 ahc_name(ahc),
1729 (ahc->features & AHC_ULTRA2) ? "Primary "
1730 : "");
1731 }
1732
1733 if ((adapter_control & CFWSTERM) != 0
1734 && (ahc->features & AHC_WIDE) != 0) {
1735 brddat |= BRDDAT6;
1736 if (bootverbose)
1737 printf("%s: %sHigh byte termination Enabled\n",
1738 ahc_name(ahc),
1739 (ahc->features & AHC_ULTRA2)
1740 ? "Secondary " : "");
1741 }
1742
1743 /*
1744 * Setup STPWEN before setting up the rest of
1745 * the termination per the tech note on the U160 cards.
1746 */
1747 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1748
1749 if ((ahc->features & AHC_WIDE) != 0)
1750 write_brdctl(ahc, brddat);
1751 }
1752 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1753 }
1754
1755 static void
1756 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1757 int *enableSEC_high, int *enablePRI_low,
1758 int *enablePRI_high, int *eeprom_present)
1759 {
1760 uint8_t brdctl;
1761
1762 /*
1763 * BRDDAT7 = Eeprom
1764 * BRDDAT6 = Enable Secondary High Byte termination
1765 * BRDDAT5 = Enable Secondary Low Byte termination
1766 * BRDDAT4 = Enable Primary high byte termination
1767 * BRDDAT3 = Enable Primary low byte termination
1768 */
1769 brdctl = read_brdctl(ahc);
1770 *eeprom_present = brdctl & BRDDAT7;
1771 *enableSEC_high = (brdctl & BRDDAT6);
1772 *enableSEC_low = (brdctl & BRDDAT5);
1773 *enablePRI_high = (brdctl & BRDDAT4);
1774 *enablePRI_low = (brdctl & BRDDAT3);
1775 }
1776
1777 static void
1778 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1779 int *internal68_present, int *externalcable_present,
1780 int *eeprom_present)
1781 {
1782 uint8_t brdctl;
1783
1784 /*
1785 * First read the status of our cables.
1786 * Set the rom bank to 0 since the
1787 * bank setting serves as a multiplexor
1788 * for the cable detection logic.
1789 * BRDDAT5 controls the bank switch.
1790 */
1791 write_brdctl(ahc, 0);
1792
1793 /*
1794 * Now read the state of the internal
1795 * connectors. BRDDAT6 is INT50 and
1796 * BRDDAT7 is INT68.
1797 */
1798 brdctl = read_brdctl(ahc);
1799 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1800 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1801
1802 /*
1803 * Set the rom bank to 1 and determine
1804 * the other signals.
1805 */
1806 write_brdctl(ahc, BRDDAT5);
1807
1808 /*
1809 * Now read the state of the external
1810 * connectors. BRDDAT6 is EXT68 and
1811 * BRDDAT7 is EPROMPS.
1812 */
1813 brdctl = read_brdctl(ahc);
1814 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1815 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1816 }
1817
1818 static void
1819 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1820 int *externalcable_present, int *eeprom_present)
1821 {
1822 uint8_t brdctl;
1823 uint8_t spiocap;
1824
1825 spiocap = ahc_inb(ahc, SPIOCAP);
1826 spiocap &= ~SOFTCMDEN;
1827 spiocap |= EXT_BRDCTL;
1828 ahc_outb(ahc, SPIOCAP, spiocap);
1829 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1830 ahc_flush_device_writes(ahc);
1831 ahc_delay(500);
1832 ahc_outb(ahc, BRDCTL, 0);
1833 ahc_flush_device_writes(ahc);
1834 ahc_delay(500);
1835 brdctl = ahc_inb(ahc, BRDCTL);
1836 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1837 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1838 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1839 }
1840
1841 int
1842 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1843 {
1844 int wait;
1845
1846 if ((ahc->features & AHC_SPIOCAP) != 0
1847 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1848 return (0);
1849
1850 /*
1851 * Request access of the memory port. When access is
1852 * granted, SEERDY will go high. We use a 1 second
1853 * timeout which should be near 1 second more than
1854 * is needed. Reason: after the chip reset, there
1855 * should be no contention.
1856 */
1857 SEEPROM_OUTB(sd, sd->sd_MS);
1858 wait = 1000; /* 1 second timeout in msec */
1859 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1860 ahc_delay(1000); /* delay 1 msec */
1861 }
1862 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1863 SEEPROM_OUTB(sd, 0);
1864 return (0);
1865 }
1866 return(1);
1867 }
1868
1869 void
1870 ahc_release_seeprom(struct seeprom_descriptor *sd)
1871 {
1872 /* Release access to the memory port and the serial EEPROM. */
1873 SEEPROM_OUTB(sd, 0);
1874 }
1875
1876 static void
1877 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1878 {
1879 uint8_t brdctl;
1880
1881 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1882 brdctl = BRDSTB;
1883 if (ahc->channel == 'B')
1884 brdctl |= BRDCS;
1885 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1886 brdctl = 0;
1887 } else {
1888 brdctl = BRDSTB|BRDCS;
1889 }
1890 ahc_outb(ahc, BRDCTL, brdctl);
1891 ahc_flush_device_writes(ahc);
1892 brdctl |= value;
1893 ahc_outb(ahc, BRDCTL, brdctl);
1894 ahc_flush_device_writes(ahc);
1895 if ((ahc->features & AHC_ULTRA2) != 0)
1896 brdctl |= BRDSTB_ULTRA2;
1897 else
1898 brdctl &= ~BRDSTB;
1899 ahc_outb(ahc, BRDCTL, brdctl);
1900 ahc_flush_device_writes(ahc);
1901 if ((ahc->features & AHC_ULTRA2) != 0)
1902 brdctl = 0;
1903 else
1904 brdctl &= ~BRDCS;
1905 ahc_outb(ahc, BRDCTL, brdctl);
1906 }
1907
1908 static uint8_t
1909 read_brdctl(struct ahc_softc *ahc)
1910 {
1911 uint8_t brdctl;
1912 uint8_t value;
1913
1914 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1915 brdctl = BRDRW;
1916 if (ahc->channel == 'B')
1917 brdctl |= BRDCS;
1918 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1919 brdctl = BRDRW_ULTRA2;
1920 } else {
1921 brdctl = BRDRW|BRDCS;
1922 }
1923 ahc_outb(ahc, BRDCTL, brdctl);
1924 ahc_flush_device_writes(ahc);
1925 value = ahc_inb(ahc, BRDCTL);
1926 ahc_outb(ahc, BRDCTL, 0);
1927 return (value);
1928 }
1929
1930 static void
1931 ahc_pci_intr(struct ahc_softc *ahc)
1932 {
1933 u_int error;
1934 u_int status1;
1935
1936 error = ahc_inb(ahc, ERROR);
1937 if ((error & PCIERRSTAT) == 0)
1938 return;
1939
1940 status1 = ahc_pci_read_config(ahc->dev_softc,
1941 PCIR_STATUS + 1, /*bytes*/1);
1942
1943 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1944 ahc_name(ahc),
1945 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1946
1947 if (status1 & DPE) {
1948 ahc->pci_target_perr_count++;
1949 printf("%s: Data Parity Error Detected during address "
1950 "or write data phase\n", ahc_name(ahc));
1951 }
1952 if (status1 & SSE) {
1953 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
1954 }
1955 if (status1 & RMA) {
1956 printf("%s: Received a Master Abort\n", ahc_name(ahc));
1957 }
1958 if (status1 & RTA) {
1959 printf("%s: Received a Target Abort\n", ahc_name(ahc));
1960 }
1961 if (status1 & STA) {
1962 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
1963 }
1964 if (status1 & DPR) {
1965 printf("%s: Data Parity Error has been reported via PERR#\n",
1966 ahc_name(ahc));
1967 }
1968
1969 /* Clear latched errors. */
1970 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1971 status1, /*bytes*/1);
1972
1973 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1974 printf("%s: Latched PCIERR interrupt with "
1975 "no status bits set\n", ahc_name(ahc));
1976 } else {
1977 ahc_outb(ahc, CLRINT, CLRPARERR);
1978 }
1979
1980 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
1981 printf(
1982 "%s: WARNING WARNING WARNING WARNING\n"
1983 "%s: Too many PCI parity errors observed as a target.\n"
1984 "%s: Some device on this bus is generating bad parity.\n"
1985 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
1986 "%s: PCI parity error checking has been disabled.\n"
1987 "%s: WARNING WARNING WARNING WARNING\n",
1988 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
1989 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
1990 ahc->seqctl |= FAILDIS;
1991 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1992 }
1993 ahc_unpause(ahc);
1994 }
1995
1996 static int
1997 ahc_pci_chip_init(struct ahc_softc *ahc)
1998 {
1999 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2000 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2001 if ((ahc->features & AHC_DT) != 0) {
2002 u_int sfunct;
2003
2004 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2005 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2006 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2007 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2008 ahc_outb(ahc, SFUNCT, sfunct);
2009 ahc_outb(ahc, CRCCONTROL1,
2010 ahc->bus_softc.pci_softc.crccontrol1);
2011 }
2012 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2013 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2014
2015 if ((ahc->features & AHC_ULTRA2) != 0)
2016 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2017
2018 return (ahc_chip_init(ahc));
2019 }
2020
2021 static int
2022 ahc_pci_suspend(struct ahc_softc *ahc)
2023 {
2024 return (ahc_suspend(ahc));
2025 }
2026
2027 static int
2028 ahc_pci_resume(struct ahc_softc *ahc)
2029 {
2030
2031 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0);
2032
2033 /*
2034 * We assume that the OS has restored our register
2035 * mappings, etc. Just update the config space registers
2036 * that the OS doesn't know about and rely on our chip
2037 * reset handler to handle the rest.
2038 */
2039 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2040 ahc->bus_softc.pci_softc.devconfig);
2041 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2042 ahc->bus_softc.pci_softc.command);
2043 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2044 ahc->bus_softc.pci_softc.csize_lattime);
2045 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2046 struct seeprom_descriptor sd;
2047 u_int sxfrctl1;
2048
2049 sd.sd_ahc = ahc;
2050 sd.sd_control_offset = SEECTL;
2051 sd.sd_status_offset = SEECTL;
2052 sd.sd_dataout_offset = SEECTL;
2053
2054 ahc_acquire_seeprom(ahc, &sd);
2055 configure_termination(ahc, &sd,
2056 ahc->seep_config->adapter_control,
2057 &sxfrctl1);
2058 ahc_release_seeprom(&sd);
2059 }
2060 return (ahc_resume(ahc));
2061 }
2062
2063 static int
2064 ahc_aic785X_setup(struct ahc_softc *ahc)
2065 {
2066 ahc_dev_softc_t pci;
2067 uint8_t rev;
2068
2069 pci = ahc->dev_softc;
2070 ahc->channel = 'A';
2071 ahc->chip = AHC_AIC7850;
2072 ahc->features = AHC_AIC7850_FE;
2073 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2074 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2075 if (rev >= 1)
2076 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2077 ahc->instruction_ram_size = 512;
2078 return (0);
2079 }
2080
2081 static int
2082 ahc_aic7860_setup(struct ahc_softc *ahc)
2083 {
2084 ahc_dev_softc_t pci;
2085 uint8_t rev;
2086
2087 pci = ahc->dev_softc;
2088 ahc->channel = 'A';
2089 ahc->chip = AHC_AIC7860;
2090 ahc->features = AHC_AIC7860_FE;
2091 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2092 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2093 if (rev >= 1)
2094 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2095 ahc->instruction_ram_size = 512;
2096 return (0);
2097 }
2098
2099 static int
2100 ahc_apa1480_setup(struct ahc_softc *ahc)
2101 {
2102 int error;
2103
2104 error = ahc_aic7860_setup(ahc);
2105 if (error != 0)
2106 return (error);
2107 ahc->features |= AHC_REMOVABLE;
2108 return (0);
2109 }
2110
2111 static int
2112 ahc_aic7870_setup(struct ahc_softc *ahc)
2113 {
2114
2115 ahc->channel = 'A';
2116 ahc->chip = AHC_AIC7870;
2117 ahc->features = AHC_AIC7870_FE;
2118 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2119 ahc->instruction_ram_size = 512;
2120 return (0);
2121 }
2122
2123 static int
2124 ahc_aha394X_setup(struct ahc_softc *ahc)
2125 {
2126 int error;
2127
2128 error = ahc_aic7870_setup(ahc);
2129 if (error == 0)
2130 error = ahc_aha394XX_setup(ahc);
2131 return (error);
2132 }
2133
2134 static int
2135 ahc_aha398X_setup(struct ahc_softc *ahc)
2136 {
2137 int error;
2138
2139 error = ahc_aic7870_setup(ahc);
2140 if (error == 0)
2141 error = ahc_aha398XX_setup(ahc);
2142 return (error);
2143 }
2144
2145 static int
2146 ahc_aha494X_setup(struct ahc_softc *ahc)
2147 {
2148 int error;
2149
2150 error = ahc_aic7870_setup(ahc);
2151 if (error == 0)
2152 error = ahc_aha494XX_setup(ahc);
2153 return (error);
2154 }
2155
2156 static int
2157 ahc_aic7880_setup(struct ahc_softc *ahc)
2158 {
2159 ahc_dev_softc_t pci;
2160 uint8_t rev;
2161
2162 pci = ahc->dev_softc;
2163 ahc->channel = 'A';
2164 ahc->chip = AHC_AIC7880;
2165 ahc->features = AHC_AIC7880_FE;
2166 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2167 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2168 if (rev >= 1) {
2169 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2170 } else {
2171 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2172 }
2173 ahc->instruction_ram_size = 512;
2174 return (0);
2175 }
2176
2177 static int
2178 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2179 {
2180
2181 ahc->flags |= AHC_INT50_SPEEDFLEX;
2182 return (ahc_aic7880_setup(ahc));
2183 }
2184
2185 static int
2186 ahc_aha394XU_setup(struct ahc_softc *ahc)
2187 {
2188 int error;
2189
2190 error = ahc_aic7880_setup(ahc);
2191 if (error == 0)
2192 error = ahc_aha394XX_setup(ahc);
2193 return (error);
2194 }
2195
2196 static int
2197 ahc_aha398XU_setup(struct ahc_softc *ahc)
2198 {
2199 int error;
2200
2201 error = ahc_aic7880_setup(ahc);
2202 if (error == 0)
2203 error = ahc_aha398XX_setup(ahc);
2204 return (error);
2205 }
2206
2207 static int
2208 ahc_aic7890_setup(struct ahc_softc *ahc)
2209 {
2210 ahc_dev_softc_t pci;
2211 uint8_t rev;
2212
2213 pci = ahc->dev_softc;
2214 ahc->channel = 'A';
2215 ahc->chip = AHC_AIC7890;
2216 ahc->features = AHC_AIC7890_FE;
2217 ahc->flags |= AHC_NEWEEPROM_FMT;
2218 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2219 if (rev == 0)
2220 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2221 ahc->instruction_ram_size = 768;
2222 return (0);
2223 }
2224
2225 static int
2226 ahc_aic7892_setup(struct ahc_softc *ahc)
2227 {
2228
2229 ahc->channel = 'A';
2230 ahc->chip = AHC_AIC7892;
2231 ahc->features = AHC_AIC7892_FE;
2232 ahc->flags |= AHC_NEWEEPROM_FMT;
2233 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2234 ahc->instruction_ram_size = 1024;
2235 return (0);
2236 }
2237
2238 static int
2239 ahc_aic7895_setup(struct ahc_softc *ahc)
2240 {
2241 ahc_dev_softc_t pci;
2242 uint8_t rev;
2243
2244 pci = ahc->dev_softc;
2245 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2246 /*
2247 * The 'C' revision of the aic7895 has a few additional features.
2248 */
2249 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2250 if (rev >= 4) {
2251 ahc->chip = AHC_AIC7895C;
2252 ahc->features = AHC_AIC7895C_FE;
2253 } else {
2254 u_int command;
2255
2256 ahc->chip = AHC_AIC7895;
2257 ahc->features = AHC_AIC7895_FE;
2258
2259 /*
2260 * The BIOS disables the use of MWI transactions
2261 * since it does not have the MWI bug work around
2262 * we have. Disabling MWI reduces performance, so
2263 * turn it on again.
2264 */
2265 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2266 command |= PCIM_CMD_MWRICEN;
2267 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2268 ahc->bugs |= AHC_PCI_MWI_BUG;
2269 }
2270 /*
2271 * XXX Does CACHETHEN really not work??? What about PCI retry?
2272 * on C level chips. Need to test, but for now, play it safe.
2273 */
2274 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2275 | AHC_CACHETHEN_BUG;
2276
2277 #if 0
2278 uint32_t devconfig;
2279
2280 /*
2281 * Cachesize must also be zero due to stray DAC
2282 * problem when sitting behind some bridges.
2283 */
2284 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2285 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2286 devconfig |= MRDCEN;
2287 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2288 #endif
2289 ahc->flags |= AHC_NEWEEPROM_FMT;
2290 ahc->instruction_ram_size = 512;
2291 return (0);
2292 }
2293
2294 static int
2295 ahc_aic7896_setup(struct ahc_softc *ahc)
2296 {
2297 ahc_dev_softc_t pci;
2298
2299 pci = ahc->dev_softc;
2300 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2301 ahc->chip = AHC_AIC7896;
2302 ahc->features = AHC_AIC7896_FE;
2303 ahc->flags |= AHC_NEWEEPROM_FMT;
2304 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2305 ahc->instruction_ram_size = 768;
2306 return (0);
2307 }
2308
2309 static int
2310 ahc_aic7899_setup(struct ahc_softc *ahc)
2311 {
2312 ahc_dev_softc_t pci;
2313
2314 pci = ahc->dev_softc;
2315 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2316 ahc->chip = AHC_AIC7899;
2317 ahc->features = AHC_AIC7899_FE;
2318 ahc->flags |= AHC_NEWEEPROM_FMT;
2319 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2320 ahc->instruction_ram_size = 1024;
2321 return (0);
2322 }
2323
2324 static int
2325 ahc_aha29160C_setup(struct ahc_softc *ahc)
2326 {
2327 int error;
2328
2329 error = ahc_aic7899_setup(ahc);
2330 if (error != 0)
2331 return (error);
2332 ahc->features |= AHC_REMOVABLE;
2333 return (0);
2334 }
2335
2336 static int
2337 ahc_raid_setup(struct ahc_softc *ahc)
2338 {
2339 printf("RAID functionality unsupported\n");
2340 return (ENXIO);
2341 }
2342
2343 static int
2344 ahc_aha394XX_setup(struct ahc_softc *ahc)
2345 {
2346 ahc_dev_softc_t pci;
2347
2348 pci = ahc->dev_softc;
2349 switch (ahc_get_pci_slot(pci)) {
2350 case AHC_394X_SLOT_CHANNEL_A:
2351 ahc->channel = 'A';
2352 break;
2353 case AHC_394X_SLOT_CHANNEL_B:
2354 ahc->channel = 'B';
2355 break;
2356 default:
2357 printf("adapter at unexpected slot %d\n"
2358 "unable to map to a channel\n",
2359 ahc_get_pci_slot(pci));
2360 ahc->channel = 'A';
2361 }
2362 return (0);
2363 }
2364
2365 static int
2366 ahc_aha398XX_setup(struct ahc_softc *ahc)
2367 {
2368 ahc_dev_softc_t pci;
2369
2370 pci = ahc->dev_softc;
2371 switch (ahc_get_pci_slot(pci)) {
2372 case AHC_398X_SLOT_CHANNEL_A:
2373 ahc->channel = 'A';
2374 break;
2375 case AHC_398X_SLOT_CHANNEL_B:
2376 ahc->channel = 'B';
2377 break;
2378 case AHC_398X_SLOT_CHANNEL_C:
2379 ahc->channel = 'C';
2380 break;
2381 default:
2382 printf("adapter at unexpected slot %d\n"
2383 "unable to map to a channel\n",
2384 ahc_get_pci_slot(pci));
2385 ahc->channel = 'A';
2386 break;
2387 }
2388 ahc->flags |= AHC_LARGE_SEEPROM;
2389 return (0);
2390 }
2391
2392 static int
2393 ahc_aha494XX_setup(struct ahc_softc *ahc)
2394 {
2395 ahc_dev_softc_t pci;
2396
2397 pci = ahc->dev_softc;
2398 switch (ahc_get_pci_slot(pci)) {
2399 case AHC_494X_SLOT_CHANNEL_A:
2400 ahc->channel = 'A';
2401 break;
2402 case AHC_494X_SLOT_CHANNEL_B:
2403 ahc->channel = 'B';
2404 break;
2405 case AHC_494X_SLOT_CHANNEL_C:
2406 ahc->channel = 'C';
2407 break;
2408 case AHC_494X_SLOT_CHANNEL_D:
2409 ahc->channel = 'D';
2410 break;
2411 default:
2412 printf("adapter at unexpected slot %d\n"
2413 "unable to map to a channel\n",
2414 ahc_get_pci_slot(pci));
2415 ahc->channel = 'A';
2416 }
2417 ahc->flags |= AHC_LARGE_SEEPROM;
2418 return (0);
2419 }
kernel source for telekom puls (alcatel/mediatek)