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Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / sbus / char / cpwatchdog.c
1 /* cpwatchdog.c - driver implementation for hardware watchdog
2 * timers found on Sun Microsystems CP1400 and CP1500 boards.
3 *
4 * This device supports both the generic Linux watchdog
5 * interface and Solaris-compatible ioctls as best it is
6 * able.
7 *
8 * NOTE: CP1400 systems appear to have a defective intr_mask
9 * register on the PLD, preventing the disabling of
10 * timer interrupts. We use a timer to periodically
11 * reset 'stopped' watchdogs on affected platforms.
12 *
13 * TODO: DevFS support (/dev/watchdogs/0 ... /dev/watchdogs/2)
14 *
15 * Copyright (c) 2000 Eric Brower (ebrower@usa.net)
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/fs.h>
21 #include <linux/errno.h>
22 #include <linux/major.h>
23 #include <linux/init.h>
24 #include <linux/miscdevice.h>
25 #include <linux/sched.h>
26 #include <linux/interrupt.h>
27 #include <linux/ioport.h>
28 #include <linux/timer.h>
29 #include <asm/irq.h>
30 #include <asm/ebus.h>
31 #include <asm/oplib.h>
32 #include <asm/uaccess.h>
33
34 #include <asm/watchdog.h>
35
36 #define WD_OBPNAME "watchdog"
37 #define WD_BADMODEL "SUNW,501-5336"
38 #define WD_BTIMEOUT (jiffies + (HZ * 1000))
39 #define WD_BLIMIT 0xFFFF
40
41 #define WD0_DEVNAME "watchdog0"
42 #define WD1_DEVNAME "watchdog1"
43 #define WD2_DEVNAME "watchdog2"
44
45 #define WD0_MINOR 212
46 #define WD1_MINOR 213
47 #define WD2_MINOR 214
48
49
50 /* Internal driver definitions
51 */
52 #define WD0_ID 0 /* Watchdog0 */
53 #define WD1_ID 1 /* Watchdog1 */
54 #define WD2_ID 2 /* Watchdog2 */
55 #define WD_NUMDEVS 3 /* Device contains 3 timers */
56
57 #define WD_INTR_OFF 0 /* Interrupt disable value */
58 #define WD_INTR_ON 1 /* Interrupt enable value */
59
60 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
61 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
62 #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */
63
64 /* Register value definitions
65 */
66 #define WD0_INTR_MASK 0x01 /* Watchdog device interrupt masks */
67 #define WD1_INTR_MASK 0x02
68 #define WD2_INTR_MASK 0x04
69
70 #define WD_S_RUNNING 0x01 /* Watchdog device status running */
71 #define WD_S_EXPIRED 0x02 /* Watchdog device status expired */
72
73 /* Sun uses Altera PLD EPF8820ATC144-4
74 * providing three hardware watchdogs:
75 *
76 * 1) RIC - sends an interrupt when triggered
77 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
78 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
79 *
80 *** Timer register block definition (struct wd_timer_regblk)
81 *
82 * dcntr and limit registers (halfword access):
83 * -------------------
84 * | 15 | ...| 1 | 0 |
85 * -------------------
86 * |- counter val -|
87 * -------------------
88 * dcntr - Current 16-bit downcounter value.
89 * When downcounter reaches '0' watchdog expires.
90 * Reading this register resets downcounter with 'limit' value.
91 * limit - 16-bit countdown value in 1/10th second increments.
92 * Writing this register begins countdown with input value.
93 * Reading from this register does not affect counter.
94 * NOTES: After watchdog reset, dcntr and limit contain '1'
95 *
96 * status register (byte access):
97 * ---------------------------
98 * | 7 | ... | 2 | 1 | 0 |
99 * --------------+------------
100 * |- UNUSED -| EXP | RUN |
101 * ---------------------------
102 * status- Bit 0 - Watchdog is running
103 * Bit 1 - Watchdog has expired
104 *
105 *** PLD register block definition (struct wd_pld_regblk)
106 *
107 * intr_mask register (byte access):
108 * ---------------------------------
109 * | 7 | ... | 3 | 2 | 1 | 0 |
110 * +-------------+------------------
111 * |- UNUSED -| WD3 | WD2 | WD1 |
112 * ---------------------------------
113 * WD3 - 1 == Interrupt disabled for watchdog 3
114 * WD2 - 1 == Interrupt disabled for watchdog 2
115 * WD1 - 1 == Interrupt disabled for watchdog 1
116 *
117 * pld_status register (byte access):
118 * UNKNOWN, MAGICAL MYSTERY REGISTER
119 *
120 */
121 #define WD_TIMER_REGSZ 16
122 #define WD0_OFF 0
123 #define WD1_OFF (WD_TIMER_REGSZ * 1)
124 #define WD2_OFF (WD_TIMER_REGSZ * 2)
125 #define PLD_OFF (WD_TIMER_REGSZ * 3)
126
127 #define WD_DCNTR 0x00
128 #define WD_LIMIT 0x04
129 #define WD_STATUS 0x08
130
131 #define PLD_IMASK (PLD_OFF + 0x00)
132 #define PLD_STATUS (PLD_OFF + 0x04)
133
134 /* Individual timer structure
135 */
136 struct wd_timer {
137 __u16 timeout;
138 __u8 intr_mask;
139 unsigned char runstatus;
140 void __iomem *regs;
141 };
142
143 /* Device structure
144 */
145 struct wd_device {
146 int irq;
147 spinlock_t lock;
148 unsigned char isbaddoggie; /* defective PLD */
149 unsigned char opt_enable;
150 unsigned char opt_reboot;
151 unsigned short opt_timeout;
152 unsigned char initialized;
153 struct wd_timer watchdog[WD_NUMDEVS];
154 void __iomem *regs;
155 };
156
157 static struct wd_device wd_dev = {
158 0, SPIN_LOCK_UNLOCKED, 0, 0, 0, 0,
159 };
160
161 static struct timer_list wd_timer;
162
163 static int wd0_timeout = 0;
164 static int wd1_timeout = 0;
165 static int wd2_timeout = 0;
166
167 #ifdef MODULE
168 module_param (wd0_timeout, int, 0);
169 MODULE_PARM_DESC(wd0_timeout, "Default watchdog0 timeout in 1/10secs");
170 module_param (wd1_timeout, int, 0);
171 MODULE_PARM_DESC(wd1_timeout, "Default watchdog1 timeout in 1/10secs");
172 module_param (wd2_timeout, int, 0);
173 MODULE_PARM_DESC(wd2_timeout, "Default watchdog2 timeout in 1/10secs");
174
175 MODULE_AUTHOR
176 ("Eric Brower <ebrower@usa.net>");
177 MODULE_DESCRIPTION
178 ("Hardware watchdog driver for Sun Microsystems CP1400/1500");
179 MODULE_LICENSE("GPL");
180 MODULE_SUPPORTED_DEVICE
181 ("watchdog");
182 #endif /* ifdef MODULE */
183
184 /* Forward declarations of internal methods
185 */
186 #ifdef WD_DEBUG
187 static void wd_dumpregs(void);
188 #endif
189 static irqreturn_t wd_interrupt(int irq, void *dev_id, struct pt_regs *regs);
190 static void wd_toggleintr(struct wd_timer* pTimer, int enable);
191 static void wd_pingtimer(struct wd_timer* pTimer);
192 static void wd_starttimer(struct wd_timer* pTimer);
193 static void wd_resetbrokentimer(struct wd_timer* pTimer);
194 static void wd_stoptimer(struct wd_timer* pTimer);
195 static void wd_brokentimer(unsigned long data);
196 static int wd_getstatus(struct wd_timer* pTimer);
197
198 /* PLD expects words to be written in LSB format,
199 * so we must flip all words prior to writing them to regs
200 */
201 static inline unsigned short flip_word(unsigned short word)
202 {
203 return ((word & 0xff) << 8) | ((word >> 8) & 0xff);
204 }
205
206 #define wd_writew(val, addr) (writew(flip_word(val), addr))
207 #define wd_readw(addr) (flip_word(readw(addr)))
208 #define wd_writeb(val, addr) (writeb(val, addr))
209 #define wd_readb(addr) (readb(addr))
210
211
212 /* CP1400s seem to have broken PLD implementations--
213 * the interrupt_mask register cannot be written, so
214 * no timer interrupts can be masked within the PLD.
215 */
216 static inline int wd_isbroken(void)
217 {
218 /* we could test this by read/write/read/restore
219 * on the interrupt mask register only if OBP
220 * 'watchdog-enable?' == FALSE, but it seems
221 * ubiquitous on CP1400s
222 */
223 char val[32];
224 prom_getproperty(prom_root_node, "model", val, sizeof(val));
225 return((!strcmp(val, WD_BADMODEL)) ? 1 : 0);
226 }
227
228 /* Retrieve watchdog-enable? option from OBP
229 * Returns 0 if false, 1 if true
230 */
231 static inline int wd_opt_enable(void)
232 {
233 int opt_node;
234
235 opt_node = prom_getchild(prom_root_node);
236 opt_node = prom_searchsiblings(opt_node, "options");
237 return((-1 == prom_getint(opt_node, "watchdog-enable?")) ? 0 : 1);
238 }
239
240 /* Retrieve watchdog-reboot? option from OBP
241 * Returns 0 if false, 1 if true
242 */
243 static inline int wd_opt_reboot(void)
244 {
245 int opt_node;
246
247 opt_node = prom_getchild(prom_root_node);
248 opt_node = prom_searchsiblings(opt_node, "options");
249 return((-1 == prom_getint(opt_node, "watchdog-reboot?")) ? 0 : 1);
250 }
251
252 /* Retrieve watchdog-timeout option from OBP
253 * Returns OBP value, or 0 if not located
254 */
255 static inline int wd_opt_timeout(void)
256 {
257 int opt_node;
258 char value[32];
259 char *p = value;
260
261 opt_node = prom_getchild(prom_root_node);
262 opt_node = prom_searchsiblings(opt_node, "options");
263 opt_node = prom_getproperty(opt_node,
264 "watchdog-timeout",
265 value,
266 sizeof(value));
267 if(-1 != opt_node) {
268 /* atoi implementation */
269 for(opt_node = 0; /* nop */; p++) {
270 if(*p >= '0' && *p <= '9') {
271 opt_node = (10*opt_node)+(*p-'0');
272 }
273 else {
274 break;
275 }
276 }
277 }
278 return((-1 == opt_node) ? (0) : (opt_node));
279 }
280
281 static int wd_open(struct inode *inode, struct file *f)
282 {
283 switch(iminor(inode))
284 {
285 case WD0_MINOR:
286 f->private_data = &wd_dev.watchdog[WD0_ID];
287 break;
288 case WD1_MINOR:
289 f->private_data = &wd_dev.watchdog[WD1_ID];
290 break;
291 case WD2_MINOR:
292 f->private_data = &wd_dev.watchdog[WD2_ID];
293 break;
294 default:
295 return(-ENODEV);
296 }
297
298 /* Register IRQ on first open of device */
299 if(0 == wd_dev.initialized)
300 {
301 if (request_irq(wd_dev.irq,
302 &wd_interrupt,
303 SA_SHIRQ,
304 WD_OBPNAME,
305 (void *)wd_dev.regs)) {
306 printk("%s: Cannot register IRQ %s\n",
307 WD_OBPNAME, __irq_itoa(wd_dev.irq));
308 return(-EBUSY);
309 }
310 wd_dev.initialized = 1;
311 }
312
313 return(nonseekable_open(inode, f));
314 }
315
316 static int wd_release(struct inode *inode, struct file *file)
317 {
318 return 0;
319 }
320
321 static int wd_ioctl(struct inode *inode, struct file *file,
322 unsigned int cmd, unsigned long arg)
323 {
324 int setopt = 0;
325 struct wd_timer* pTimer = (struct wd_timer*)file->private_data;
326 void __user *argp = (void __user *)arg;
327 struct watchdog_info info = {
328 0,
329 0,
330 "Altera EPF8820ATC144-4"
331 };
332
333 if(NULL == pTimer) {
334 return(-EINVAL);
335 }
336
337 switch(cmd)
338 {
339 /* Generic Linux IOCTLs */
340 case WDIOC_GETSUPPORT:
341 if(copy_to_user(argp, &info, sizeof(struct watchdog_info))) {
342 return(-EFAULT);
343 }
344 break;
345 case WDIOC_GETSTATUS:
346 case WDIOC_GETBOOTSTATUS:
347 if (put_user(0, (int __user *)argp))
348 return -EFAULT;
349 break;
350 case WDIOC_KEEPALIVE:
351 wd_pingtimer(pTimer);
352 break;
353 case WDIOC_SETOPTIONS:
354 if(copy_from_user(&setopt, argp, sizeof(unsigned int))) {
355 return -EFAULT;
356 }
357 if(setopt & WDIOS_DISABLECARD) {
358 if(wd_dev.opt_enable) {
359 printk(
360 "%s: cannot disable watchdog in ENABLED mode\n",
361 WD_OBPNAME);
362 return(-EINVAL);
363 }
364 wd_stoptimer(pTimer);
365 }
366 else if(setopt & WDIOS_ENABLECARD) {
367 wd_starttimer(pTimer);
368 }
369 else {
370 return(-EINVAL);
371 }
372 break;
373 /* Solaris-compatible IOCTLs */
374 case WIOCGSTAT:
375 setopt = wd_getstatus(pTimer);
376 if(copy_to_user(argp, &setopt, sizeof(unsigned int))) {
377 return(-EFAULT);
378 }
379 break;
380 case WIOCSTART:
381 wd_starttimer(pTimer);
382 break;
383 case WIOCSTOP:
384 if(wd_dev.opt_enable) {
385 printk("%s: cannot disable watchdog in ENABLED mode\n",
386 WD_OBPNAME);
387 return(-EINVAL);
388 }
389 wd_stoptimer(pTimer);
390 break;
391 default:
392 return(-EINVAL);
393 }
394 return(0);
395 }
396
397 static ssize_t wd_write(struct file *file,
398 const char __user *buf,
399 size_t count,
400 loff_t *ppos)
401 {
402 struct wd_timer* pTimer = (struct wd_timer*)file->private_data;
403
404 if(NULL == pTimer) {
405 return(-EINVAL);
406 }
407
408 if (count) {
409 wd_pingtimer(pTimer);
410 return 1;
411 }
412 return 0;
413 }
414
415 static ssize_t wd_read(struct file * file, char __user *buffer,
416 size_t count, loff_t *ppos)
417 {
418 #ifdef WD_DEBUG
419 wd_dumpregs();
420 return(0);
421 #else
422 return(-EINVAL);
423 #endif /* ifdef WD_DEBUG */
424 }
425
426 static irqreturn_t wd_interrupt(int irq, void *dev_id, struct pt_regs *regs)
427 {
428 /* Only WD0 will interrupt-- others are NMI and we won't
429 * see them here....
430 */
431 spin_lock_irq(&wd_dev.lock);
432 if((unsigned long)wd_dev.regs == (unsigned long)dev_id)
433 {
434 wd_stoptimer(&wd_dev.watchdog[WD0_ID]);
435 wd_dev.watchdog[WD0_ID].runstatus |= WD_STAT_SVCD;
436 }
437 spin_unlock_irq(&wd_dev.lock);
438 return IRQ_HANDLED;
439 }
440
441 static struct file_operations wd_fops = {
442 .owner = THIS_MODULE,
443 .ioctl = wd_ioctl,
444 .open = wd_open,
445 .write = wd_write,
446 .read = wd_read,
447 .release = wd_release,
448 };
449
450 static struct miscdevice wd0_miscdev = { WD0_MINOR, WD0_DEVNAME, &wd_fops };
451 static struct miscdevice wd1_miscdev = { WD1_MINOR, WD1_DEVNAME, &wd_fops };
452 static struct miscdevice wd2_miscdev = { WD2_MINOR, WD2_DEVNAME, &wd_fops };
453
454 #ifdef WD_DEBUG
455 static void wd_dumpregs(void)
456 {
457 /* Reading from downcounters initiates watchdog countdown--
458 * Example is included below for illustration purposes.
459 */
460 int i;
461 printk("%s: dumping register values\n", WD_OBPNAME);
462 for(i = WD0_ID; i < WD_NUMDEVS; ++i) {
463 /* printk("\t%s%i: dcntr at 0x%lx: 0x%x\n",
464 * WD_OBPNAME,
465 * i,
466 * (unsigned long)(&wd_dev.watchdog[i].regs->dcntr),
467 * readw(&wd_dev.watchdog[i].regs->dcntr));
468 */
469 printk("\t%s%i: limit at 0x%lx: 0x%x\n",
470 WD_OBPNAME,
471 i,
472 (unsigned long)(&wd_dev.watchdog[i].regs->limit),
473 readw(&wd_dev.watchdog[i].regs->limit));
474 printk("\t%s%i: status at 0x%lx: 0x%x\n",
475 WD_OBPNAME,
476 i,
477 (unsigned long)(&wd_dev.watchdog[i].regs->status),
478 readb(&wd_dev.watchdog[i].regs->status));
479 printk("\t%s%i: driver status: 0x%x\n",
480 WD_OBPNAME,
481 i,
482 wd_getstatus(&wd_dev.watchdog[i]));
483 }
484 printk("\tintr_mask at %p: 0x%x\n",
485 wd_dev.regs + PLD_IMASK,
486 readb(wd_dev.regs + PLD_IMASK));
487 printk("\tpld_status at %p: 0x%x\n",
488 wd_dev.regs + PLD_STATUS,
489 readb(wd_dev.regs + PLD_STATUS));
490 }
491 #endif
492
493 /* Enable or disable watchdog interrupts
494 * Because of the CP1400 defect this should only be
495 * called during initialzation or by wd_[start|stop]timer()
496 *
497 * pTimer - pointer to timer device, or NULL to indicate all timers
498 * enable - non-zero to enable interrupts, zero to disable
499 */
500 static void wd_toggleintr(struct wd_timer* pTimer, int enable)
501 {
502 unsigned char curregs = wd_readb(wd_dev.regs + PLD_IMASK);
503 unsigned char setregs =
504 (NULL == pTimer) ?
505 (WD0_INTR_MASK | WD1_INTR_MASK | WD2_INTR_MASK) :
506 (pTimer->intr_mask);
507
508 (WD_INTR_ON == enable) ?
509 (curregs &= ~setregs):
510 (curregs |= setregs);
511
512 wd_writeb(curregs, wd_dev.regs + PLD_IMASK);
513 return;
514 }
515
516 /* Reset countdown timer with 'limit' value and continue countdown.
517 * This will not start a stopped timer.
518 *
519 * pTimer - pointer to timer device
520 */
521 static void wd_pingtimer(struct wd_timer* pTimer)
522 {
523 if (wd_readb(pTimer->regs + WD_STATUS) & WD_S_RUNNING) {
524 wd_readw(pTimer->regs + WD_DCNTR);
525 }
526 }
527
528 /* Stop a running watchdog timer-- the timer actually keeps
529 * running, but the interrupt is masked so that no action is
530 * taken upon expiration.
531 *
532 * pTimer - pointer to timer device
533 */
534 static void wd_stoptimer(struct wd_timer* pTimer)
535 {
536 if(wd_readb(pTimer->regs + WD_STATUS) & WD_S_RUNNING) {
537 wd_toggleintr(pTimer, WD_INTR_OFF);
538
539 if(wd_dev.isbaddoggie) {
540 pTimer->runstatus |= WD_STAT_BSTOP;
541 wd_brokentimer((unsigned long)&wd_dev);
542 }
543 }
544 }
545
546 /* Start a watchdog timer with the specified limit value
547 * If the watchdog is running, it will be restarted with
548 * the provided limit value.
549 *
550 * This function will enable interrupts on the specified
551 * watchdog.
552 *
553 * pTimer - pointer to timer device
554 * limit - limit (countdown) value in 1/10th seconds
555 */
556 static void wd_starttimer(struct wd_timer* pTimer)
557 {
558 if(wd_dev.isbaddoggie) {
559 pTimer->runstatus &= ~WD_STAT_BSTOP;
560 }
561 pTimer->runstatus &= ~WD_STAT_SVCD;
562
563 wd_writew(pTimer->timeout, pTimer->regs + WD_LIMIT);
564 wd_toggleintr(pTimer, WD_INTR_ON);
565 }
566
567 /* Restarts timer with maximum limit value and
568 * does not unset 'brokenstop' value.
569 */
570 static void wd_resetbrokentimer(struct wd_timer* pTimer)
571 {
572 wd_toggleintr(pTimer, WD_INTR_ON);
573 wd_writew(WD_BLIMIT, pTimer->regs + WD_LIMIT);
574 }
575
576 /* Timer device initialization helper.
577 * Returns 0 on success, other on failure
578 */
579 static int wd_inittimer(int whichdog)
580 {
581 struct miscdevice *whichmisc;
582 void __iomem *whichregs;
583 char whichident[8];
584 int whichmask;
585 __u16 whichlimit;
586
587 switch(whichdog)
588 {
589 case WD0_ID:
590 whichmisc = &wd0_miscdev;
591 strcpy(whichident, "RIC");
592 whichregs = wd_dev.regs + WD0_OFF;
593 whichmask = WD0_INTR_MASK;
594 whichlimit= (0 == wd0_timeout) ?
595 (wd_dev.opt_timeout):
596 (wd0_timeout);
597 break;
598 case WD1_ID:
599 whichmisc = &wd1_miscdev;
600 strcpy(whichident, "XIR");
601 whichregs = wd_dev.regs + WD1_OFF;
602 whichmask = WD1_INTR_MASK;
603 whichlimit= (0 == wd1_timeout) ?
604 (wd_dev.opt_timeout):
605 (wd1_timeout);
606 break;
607 case WD2_ID:
608 whichmisc = &wd2_miscdev;
609 strcpy(whichident, "POR");
610 whichregs = wd_dev.regs + WD2_OFF;
611 whichmask = WD2_INTR_MASK;
612 whichlimit= (0 == wd2_timeout) ?
613 (wd_dev.opt_timeout):
614 (wd2_timeout);
615 break;
616 default:
617 printk("%s: %s: invalid watchdog id: %i\n",
618 WD_OBPNAME, __FUNCTION__, whichdog);
619 return(1);
620 }
621 if(0 != misc_register(whichmisc))
622 {
623 return(1);
624 }
625 wd_dev.watchdog[whichdog].regs = whichregs;
626 wd_dev.watchdog[whichdog].timeout = whichlimit;
627 wd_dev.watchdog[whichdog].intr_mask = whichmask;
628 wd_dev.watchdog[whichdog].runstatus &= ~WD_STAT_BSTOP;
629 wd_dev.watchdog[whichdog].runstatus |= WD_STAT_INIT;
630
631 printk("%s%i: %s hardware watchdog [%01i.%i sec] %s\n",
632 WD_OBPNAME,
633 whichdog,
634 whichident,
635 wd_dev.watchdog[whichdog].timeout / 10,
636 wd_dev.watchdog[whichdog].timeout % 10,
637 (0 != wd_dev.opt_enable) ? "in ENABLED mode" : "");
638 return(0);
639 }
640
641 /* Timer method called to reset stopped watchdogs--
642 * because of the PLD bug on CP1400, we cannot mask
643 * interrupts within the PLD so me must continually
644 * reset the timers ad infinitum.
645 */
646 static void wd_brokentimer(unsigned long data)
647 {
648 struct wd_device* pDev = (struct wd_device*)data;
649 int id, tripped = 0;
650
651 /* kill a running timer instance, in case we
652 * were called directly instead of by kernel timer
653 */
654 if(timer_pending(&wd_timer)) {
655 del_timer(&wd_timer);
656 }
657
658 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
659 if(pDev->watchdog[id].runstatus & WD_STAT_BSTOP) {
660 ++tripped;
661 wd_resetbrokentimer(&pDev->watchdog[id]);
662 }
663 }
664
665 if(tripped) {
666 /* there is at least one timer brokenstopped-- reschedule */
667 init_timer(&wd_timer);
668 wd_timer.expires = WD_BTIMEOUT;
669 add_timer(&wd_timer);
670 }
671 }
672
673 static int wd_getstatus(struct wd_timer* pTimer)
674 {
675 unsigned char stat = wd_readb(pTimer->regs + WD_STATUS);
676 unsigned char intr = wd_readb(wd_dev.regs + PLD_IMASK);
677 unsigned char ret = WD_STOPPED;
678
679 /* determine STOPPED */
680 if(0 == stat ) {
681 return(ret);
682 }
683 /* determine EXPIRED vs FREERUN vs RUNNING */
684 else if(WD_S_EXPIRED & stat) {
685 ret = WD_EXPIRED;
686 }
687 else if(WD_S_RUNNING & stat) {
688 if(intr & pTimer->intr_mask) {
689 ret = WD_FREERUN;
690 }
691 else {
692 /* Fudge WD_EXPIRED status for defective CP1400--
693 * IF timer is running
694 * AND brokenstop is set
695 * AND an interrupt has been serviced
696 * we are WD_EXPIRED.
697 *
698 * IF timer is running
699 * AND brokenstop is set
700 * AND no interrupt has been serviced
701 * we are WD_FREERUN.
702 */
703 if(wd_dev.isbaddoggie && (pTimer->runstatus & WD_STAT_BSTOP)) {
704 if(pTimer->runstatus & WD_STAT_SVCD) {
705 ret = WD_EXPIRED;
706 }
707 else {
708 /* we could as well pretend we are expired */
709 ret = WD_FREERUN;
710 }
711 }
712 else {
713 ret = WD_RUNNING;
714 }
715 }
716 }
717
718 /* determine SERVICED */
719 if(pTimer->runstatus & WD_STAT_SVCD) {
720 ret |= WD_SERVICED;
721 }
722
723 return(ret);
724 }
725
726 static int __init wd_init(void)
727 {
728 int id;
729 struct linux_ebus *ebus = NULL;
730 struct linux_ebus_device *edev = NULL;
731
732 for_each_ebus(ebus) {
733 for_each_ebusdev(edev, ebus) {
734 if (!strcmp(edev->prom_name, WD_OBPNAME))
735 goto ebus_done;
736 }
737 }
738
739 ebus_done:
740 if(!edev) {
741 printk("%s: unable to locate device\n", WD_OBPNAME);
742 return -ENODEV;
743 }
744
745 wd_dev.regs =
746 ioremap(edev->resource[0].start, 4 * WD_TIMER_REGSZ); /* ? */
747
748 if(NULL == wd_dev.regs) {
749 printk("%s: unable to map registers\n", WD_OBPNAME);
750 return(-ENODEV);
751 }
752
753 /* initialize device structure from OBP parameters */
754 wd_dev.irq = edev->irqs[0];
755 wd_dev.opt_enable = wd_opt_enable();
756 wd_dev.opt_reboot = wd_opt_reboot();
757 wd_dev.opt_timeout = wd_opt_timeout();
758 wd_dev.isbaddoggie = wd_isbroken();
759
760 /* disable all interrupts unless watchdog-enabled? == true */
761 if(! wd_dev.opt_enable) {
762 wd_toggleintr(NULL, WD_INTR_OFF);
763 }
764
765 /* register miscellaneous devices */
766 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
767 if(0 != wd_inittimer(id)) {
768 printk("%s%i: unable to initialize\n", WD_OBPNAME, id);
769 }
770 }
771
772 /* warn about possible defective PLD */
773 if(wd_dev.isbaddoggie) {
774 init_timer(&wd_timer);
775 wd_timer.function = wd_brokentimer;
776 wd_timer.data = (unsigned long)&wd_dev;
777 wd_timer.expires = WD_BTIMEOUT;
778
779 printk("%s: PLD defect workaround enabled for model %s\n",
780 WD_OBPNAME, WD_BADMODEL);
781 }
782 return(0);
783 }
784
785 static void __exit wd_cleanup(void)
786 {
787 int id;
788
789 /* if 'watchdog-enable?' == TRUE, timers are not stopped
790 * when module is unloaded. All brokenstopped timers will
791 * also now eventually trip.
792 */
793 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
794 if(WD_S_RUNNING == wd_readb(wd_dev.watchdog[id].regs + WD_STATUS)) {
795 if(wd_dev.opt_enable) {
796 printk(KERN_WARNING "%s%i: timer not stopped at release\n",
797 WD_OBPNAME, id);
798 }
799 else {
800 wd_stoptimer(&wd_dev.watchdog[id]);
801 if(wd_dev.watchdog[id].runstatus & WD_STAT_BSTOP) {
802 wd_resetbrokentimer(&wd_dev.watchdog[id]);
803 printk(KERN_WARNING
804 "%s%i: defect workaround disabled at release, "\
805 "timer expires in ~%01i sec\n",
806 WD_OBPNAME, id,
807 wd_readw(wd_dev.watchdog[id].regs + WD_LIMIT) / 10);
808 }
809 }
810 }
811 }
812
813 if(wd_dev.isbaddoggie && timer_pending(&wd_timer)) {
814 del_timer(&wd_timer);
815 }
816 if(0 != (wd_dev.watchdog[WD0_ID].runstatus & WD_STAT_INIT)) {
817 misc_deregister(&wd0_miscdev);
818 }
819 if(0 != (wd_dev.watchdog[WD1_ID].runstatus & WD_STAT_INIT)) {
820 misc_deregister(&wd1_miscdev);
821 }
822 if(0 != (wd_dev.watchdog[WD2_ID].runstatus & WD_STAT_INIT)) {
823 misc_deregister(&wd2_miscdev);
824 }
825 if(0 != wd_dev.initialized) {
826 free_irq(wd_dev.irq, (void *)wd_dev.regs);
827 }
828 iounmap(wd_dev.regs);
829 }
830
831 module_init(wd_init);
832 module_exit(wd_cleanup);
kernel source for telekom puls (alcatel/mediatek)