2 * R8A7796 processor support - PFC hardware block.
4 * Copyright (C) 2016 Renesas Electronics Corp.
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 * R-Car Gen3 processor support - PFC hardware block.
10 * Copyright (C) 2015 Renesas Electronics Corporation
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
17 #include <linux/kernel.h>
22 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
26 #define CPU_ALL_PORT(fn, sfx) \
27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
45 #define GPSR0_15 F_(D15, IP7_11_8)
46 #define GPSR0_14 F_(D14, IP7_7_4)
47 #define GPSR0_13 F_(D13, IP7_3_0)
48 #define GPSR0_12 F_(D12, IP6_31_28)
49 #define GPSR0_11 F_(D11, IP6_27_24)
50 #define GPSR0_10 F_(D10, IP6_23_20)
51 #define GPSR0_9 F_(D9, IP6_19_16)
52 #define GPSR0_8 F_(D8, IP6_15_12)
53 #define GPSR0_7 F_(D7, IP6_11_8)
54 #define GPSR0_6 F_(D6, IP6_7_4)
55 #define GPSR0_5 F_(D5, IP6_3_0)
56 #define GPSR0_4 F_(D4, IP5_31_28)
57 #define GPSR0_3 F_(D3, IP5_27_24)
58 #define GPSR0_2 F_(D2, IP5_23_20)
59 #define GPSR0_1 F_(D1, IP5_19_16)
60 #define GPSR0_0 F_(D0, IP5_15_12)
63 #define GPSR1_28 FM(CLKOUT)
64 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65 #define GPSR1_26 F_(WE1_N, IP5_7_4)
66 #define GPSR1_25 F_(WE0_N, IP5_3_0)
67 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68 #define GPSR1_23 F_(RD_N, IP4_27_24)
69 #define GPSR1_22 F_(BS_N, IP4_23_20)
70 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
71 #define GPSR1_20 F_(CS0_N, IP4_15_12)
72 #define GPSR1_19 F_(A19, IP4_11_8)
73 #define GPSR1_18 F_(A18, IP4_7_4)
74 #define GPSR1_17 F_(A17, IP4_3_0)
75 #define GPSR1_16 F_(A16, IP3_31_28)
76 #define GPSR1_15 F_(A15, IP3_27_24)
77 #define GPSR1_14 F_(A14, IP3_23_20)
78 #define GPSR1_13 F_(A13, IP3_19_16)
79 #define GPSR1_12 F_(A12, IP3_15_12)
80 #define GPSR1_11 F_(A11, IP3_11_8)
81 #define GPSR1_10 F_(A10, IP3_7_4)
82 #define GPSR1_9 F_(A9, IP3_3_0)
83 #define GPSR1_8 F_(A8, IP2_31_28)
84 #define GPSR1_7 F_(A7, IP2_27_24)
85 #define GPSR1_6 F_(A6, IP2_23_20)
86 #define GPSR1_5 F_(A5, IP2_19_16)
87 #define GPSR1_4 F_(A4, IP2_15_12)
88 #define GPSR1_3 F_(A3, IP2_11_8)
89 #define GPSR1_2 F_(A2, IP2_7_4)
90 #define GPSR1_1 F_(A1, IP2_3_0)
91 #define GPSR1_0 F_(A0, IP1_31_28)
94 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
101 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
102 #define GPSR2_6 F_(PWM0, IP1_19_16)
103 #define GPSR2_5 F_(IRQ5, IP1_15_12)
104 #define GPSR2_4 F_(IRQ4, IP1_11_8)
105 #define GPSR2_3 F_(IRQ3, IP1_7_4)
106 #define GPSR2_2 F_(IRQ2, IP1_3_0)
107 #define GPSR2_1 F_(IRQ1, IP0_31_28)
108 #define GPSR2_0 F_(IRQ0, IP0_27_24)
111 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
112 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
113 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
114 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
115 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
129 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
130 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
134 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
140 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
141 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
145 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
149 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152 #define GPSR5_22 FM(MSIOF0_RXD)
153 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154 #define GPSR5_20 FM(MSIOF0_TXD)
155 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157 #define GPSR5_17 FM(MSIOF0_SCK)
158 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160 #define GPSR5_14 F_(HTX0, IP13_19_16)
161 #define GPSR5_13 F_(HRX0, IP13_15_12)
162 #define GPSR5_12 F_(HSCK0, IP13_11_8)
163 #define GPSR5_11 F_(RX2_A, IP13_7_4)
164 #define GPSR5_10 F_(TX2_A, IP13_3_0)
165 #define GPSR5_9 F_(SCK2, IP12_31_28)
166 #define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
167 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
168 #define GPSR5_6 F_(TX1_A, IP12_19_16)
169 #define GPSR5_5 F_(RX1_A, IP12_15_12)
170 #define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
171 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
172 #define GPSR5_2 F_(TX0, IP12_3_0)
173 #define GPSR5_1 F_(RX0, IP11_31_28)
174 #define GPSR5_0 F_(SCK0, IP11_27_24)
177 #define GPSR6_31 F_(GP6_31, IP18_7_4)
178 #define GPSR6_30 F_(GP6_30, IP18_3_0)
179 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195 #define GPSR6_13 FM(SSI_SDATA5)
196 #define GPSR6_12 FM(SSI_WS5)
197 #define GPSR6_11 FM(SSI_SCK5)
198 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202 #define GPSR6_6 F_(SSI_WS34, IP15_15_12)
203 #define GPSR6_5 F_(SSI_SCK34, IP15_11_8)
204 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207 #define GPSR6_1 F_(SSI_WS0129, IP14_27_24)
208 #define GPSR6_0 F_(SSI_SCK0129, IP14_23_20)
211 #define GPSR7_3 FM(GP7_03)
212 #define GPSR7_2 FM(HDMI0_CEC)
213 #define GPSR7_1 FM(AVS2)
214 #define GPSR7_0 FM(AVS1)
217 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
315 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
336 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
345 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
365 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
366 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
371 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
373 #define PINMUX_GPSR \
381 GPSR1_25 GPSR5_25 GPSR6_25 \
382 GPSR1_24 GPSR5_24 GPSR6_24 \
383 GPSR1_23 GPSR5_23 GPSR6_23 \
384 GPSR1_22 GPSR5_22 GPSR6_22 \
385 GPSR1_21 GPSR5_21 GPSR6_21 \
386 GPSR1_20 GPSR5_20 GPSR6_20 \
387 GPSR1_19 GPSR5_19 GPSR6_19 \
388 GPSR1_18 GPSR5_18 GPSR6_18 \
389 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
390 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
391 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
392 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
393 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
394 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
395 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
396 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
397 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
398 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
399 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
400 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
401 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
402 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
403 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
404 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
405 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
406 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
408 #define PINMUX_IPSR \
410 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
411 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
412 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
413 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
414 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
415 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
416 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
417 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
419 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
423 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
426 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
428 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
429 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
430 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
431 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
432 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
433 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
434 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
435 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
437 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
438 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
439 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
440 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
441 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
442 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
443 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
444 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
446 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
447 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
448 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
449 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
450 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
451 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
452 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
453 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
455 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
456 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
458 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
459 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
460 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
461 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
462 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
463 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466 #define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1)
467 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
468 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
469 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
470 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
471 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
472 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
473 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
474 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
475 #define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
477 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
478 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
479 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
481 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
482 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
483 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
484 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
485 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
486 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
487 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
488 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
489 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
490 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
491 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
492 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
493 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
494 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
495 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
496 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
497 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
498 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
499 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
501 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
502 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
503 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
504 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
505 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
506 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
507 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
508 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
509 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
510 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
511 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
512 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
513 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
514 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
516 #define PINMUX_MOD_SELS \
518 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
520 MOD_SEL1_29_28_27 MOD_SEL2_29 \
521 MOD_SEL0_28_27 MOD_SEL2_28_27 \
522 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
523 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
524 MOD_SEL0_23 MOD_SEL1_23_22_21 \
525 MOD_SEL0_22 MOD_SEL2_22 \
526 MOD_SEL0_21 MOD_SEL2_21 \
527 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
528 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
529 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
531 MOD_SEL0_16 MOD_SEL1_16 \
532 MOD_SEL0_15 MOD_SEL1_15_14 \
535 MOD_SEL0_12 MOD_SEL1_12 \
536 MOD_SEL0_11 MOD_SEL1_11 \
537 MOD_SEL0_10 MOD_SEL1_10 \
538 MOD_SEL0_9_8 MOD_SEL1_9 \
541 MOD_SEL0_5 MOD_SEL1_5 \
542 MOD_SEL0_4_3 MOD_SEL1_4 \
544 MOD_SEL0_2 MOD_SEL1_2 \
546 MOD_SEL1_0 MOD_SEL2_0
549 * These pins are not able to be muxed but have other properties
550 * that can be set, such as drive-strength or pull-up/pull-down enable.
552 #define PINMUX_STATIC \
553 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
554 FM(QSPI0_IO2) FM(QSPI0_IO3) \
555 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
556 FM(QSPI1_IO2) FM(QSPI1_IO3) \
557 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
558 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
559 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
560 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
562 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
563 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
573 #define FM(x) FN_##x,
574 PINMUX_FUNCTION_BEGIN
,
584 #define FM(x) x##_MARK,
595 static const u16 pinmux_data
[] = {
596 PINMUX_DATA_GP_ALL(),
600 PINMUX_SINGLE(CLKOUT
),
601 PINMUX_SINGLE(GP7_03
),
602 PINMUX_SINGLE(HDMI0_CEC
),
603 PINMUX_SINGLE(MSIOF0_RXD
),
604 PINMUX_SINGLE(MSIOF0_SCK
),
605 PINMUX_SINGLE(MSIOF0_TXD
),
606 PINMUX_SINGLE(SSI_SCK5
),
607 PINMUX_SINGLE(SSI_SDATA5
),
608 PINMUX_SINGLE(SSI_WS5
),
611 PINMUX_IPSR_GPSR(IP0_3_0
, AVB_MDC
),
612 PINMUX_IPSR_MSEL(IP0_3_0
, MSIOF2_SS2_C
, SEL_MSIOF2_2
),
614 PINMUX_IPSR_GPSR(IP0_7_4
, AVB_MAGIC
),
615 PINMUX_IPSR_MSEL(IP0_7_4
, MSIOF2_SS1_C
, SEL_MSIOF2_2
),
616 PINMUX_IPSR_MSEL(IP0_7_4
, SCK4_A
, SEL_SCIF4_0
),
618 PINMUX_IPSR_GPSR(IP0_11_8
, AVB_PHY_INT
),
619 PINMUX_IPSR_MSEL(IP0_11_8
, MSIOF2_SYNC_C
, SEL_MSIOF2_2
),
620 PINMUX_IPSR_MSEL(IP0_11_8
, RX4_A
, SEL_SCIF4_0
),
622 PINMUX_IPSR_GPSR(IP0_15_12
, AVB_LINK
),
623 PINMUX_IPSR_MSEL(IP0_15_12
, MSIOF2_SCK_C
, SEL_MSIOF2_2
),
624 PINMUX_IPSR_MSEL(IP0_15_12
, TX4_A
, SEL_SCIF4_0
),
626 PINMUX_IPSR_MSEL(IP0_19_16
, AVB_AVTP_MATCH_A
, SEL_ETHERAVB_0
),
627 PINMUX_IPSR_MSEL(IP0_19_16
, MSIOF2_RXD_C
, SEL_MSIOF2_2
),
628 PINMUX_IPSR_MSEL(IP0_19_16
, CTS4_N_A
, SEL_SCIF4_0
),
630 PINMUX_IPSR_MSEL(IP0_23_20
, AVB_AVTP_CAPTURE_A
, SEL_ETHERAVB_0
),
631 PINMUX_IPSR_MSEL(IP0_23_20
, MSIOF2_TXD_C
, SEL_MSIOF2_2
),
632 PINMUX_IPSR_MSEL(IP0_23_20
, RTS4_N_TANS_A
, SEL_SCIF4_0
),
634 PINMUX_IPSR_GPSR(IP0_27_24
, IRQ0
),
635 PINMUX_IPSR_GPSR(IP0_27_24
, QPOLB
),
636 PINMUX_IPSR_GPSR(IP0_27_24
, DU_CDE
),
637 PINMUX_IPSR_MSEL(IP0_27_24
, VI4_DATA0_B
, SEL_VIN4_1
),
638 PINMUX_IPSR_MSEL(IP0_27_24
, CAN0_TX_B
, SEL_RCAN0_1
),
639 PINMUX_IPSR_MSEL(IP0_27_24
, CANFD0_TX_B
, SEL_CANFD0_1
),
640 PINMUX_IPSR_MSEL(IP0_27_24
, MSIOF3_SS2_E
, SEL_MSIOF3_4
),
642 PINMUX_IPSR_GPSR(IP0_31_28
, IRQ1
),
643 PINMUX_IPSR_GPSR(IP0_31_28
, QPOLA
),
644 PINMUX_IPSR_GPSR(IP0_31_28
, DU_DISP
),
645 PINMUX_IPSR_MSEL(IP0_31_28
, VI4_DATA1_B
, SEL_VIN4_1
),
646 PINMUX_IPSR_MSEL(IP0_31_28
, CAN0_RX_B
, SEL_RCAN0_1
),
647 PINMUX_IPSR_MSEL(IP0_31_28
, CANFD0_RX_B
, SEL_CANFD0_1
),
648 PINMUX_IPSR_MSEL(IP0_27_24
, MSIOF3_SS1_E
, SEL_MSIOF3_4
),
651 PINMUX_IPSR_GPSR(IP1_3_0
, IRQ2
),
652 PINMUX_IPSR_GPSR(IP1_3_0
, QCPV_QDE
),
653 PINMUX_IPSR_GPSR(IP1_3_0
, DU_EXODDF_DU_ODDF_DISP_CDE
),
654 PINMUX_IPSR_MSEL(IP1_3_0
, VI4_DATA2_B
, SEL_VIN4_1
),
655 PINMUX_IPSR_MSEL(IP1_3_0
, PWM3_B
, SEL_PWM3_1
),
656 PINMUX_IPSR_MSEL(IP1_3_0
, MSIOF3_SYNC_E
, SEL_MSIOF3_4
),
658 PINMUX_IPSR_GPSR(IP1_7_4
, IRQ3
),
659 PINMUX_IPSR_GPSR(IP1_7_4
, QSTVB_QVE
),
660 PINMUX_IPSR_GPSR(IP1_7_4
, A25
),
661 PINMUX_IPSR_GPSR(IP1_7_4
, DU_DOTCLKOUT1
),
662 PINMUX_IPSR_MSEL(IP1_7_4
, VI4_DATA3_B
, SEL_VIN4_1
),
663 PINMUX_IPSR_MSEL(IP1_7_4
, PWM4_B
, SEL_PWM4_1
),
664 PINMUX_IPSR_MSEL(IP1_7_4
, MSIOF3_SCK_E
, SEL_MSIOF3_4
),
666 PINMUX_IPSR_GPSR(IP1_11_8
, IRQ4
),
667 PINMUX_IPSR_GPSR(IP1_11_8
, QSTH_QHS
),
668 PINMUX_IPSR_GPSR(IP1_11_8
, A24
),
669 PINMUX_IPSR_GPSR(IP1_11_8
, DU_EXHSYNC_DU_HSYNC
),
670 PINMUX_IPSR_MSEL(IP1_11_8
, VI4_DATA4_B
, SEL_VIN4_1
),
671 PINMUX_IPSR_MSEL(IP1_11_8
, PWM5_B
, SEL_PWM5_1
),
672 PINMUX_IPSR_MSEL(IP1_11_8
, MSIOF3_RXD_E
, SEL_MSIOF3_4
),
674 PINMUX_IPSR_GPSR(IP1_15_12
, IRQ5
),
675 PINMUX_IPSR_GPSR(IP1_15_12
, QSTB_QHE
),
676 PINMUX_IPSR_GPSR(IP1_15_12
, A23
),
677 PINMUX_IPSR_GPSR(IP1_15_12
, DU_EXVSYNC_DU_VSYNC
),
678 PINMUX_IPSR_MSEL(IP1_15_12
, VI4_DATA5_B
, SEL_VIN4_1
),
679 PINMUX_IPSR_MSEL(IP1_15_12
, PWM6_B
, SEL_PWM6_1
),
680 PINMUX_IPSR_MSEL(IP1_15_12
, MSIOF3_TXD_E
, SEL_MSIOF3_4
),
682 PINMUX_IPSR_GPSR(IP1_19_16
, PWM0
),
683 PINMUX_IPSR_GPSR(IP1_19_16
, AVB_AVTP_PPS
),
684 PINMUX_IPSR_GPSR(IP1_19_16
, A22
),
685 PINMUX_IPSR_MSEL(IP1_19_16
, VI4_DATA6_B
, SEL_VIN4_1
),
686 PINMUX_IPSR_MSEL(IP1_19_16
, IECLK_B
, SEL_IEBUS_1
),
688 PINMUX_IPSR_MSEL(IP1_23_20
, PWM1_A
, SEL_PWM1_0
),
689 PINMUX_IPSR_GPSR(IP1_23_20
, A21
),
690 PINMUX_IPSR_MSEL(IP1_23_20
, HRX3_D
, SEL_HSCIF3_3
),
691 PINMUX_IPSR_MSEL(IP1_23_20
, VI4_DATA7_B
, SEL_VIN4_1
),
692 PINMUX_IPSR_MSEL(IP1_23_20
, IERX_B
, SEL_IEBUS_1
),
694 PINMUX_IPSR_MSEL(IP1_27_24
, PWM2_A
, SEL_PWM2_0
),
695 PINMUX_IPSR_GPSR(IP1_27_24
, A20
),
696 PINMUX_IPSR_MSEL(IP1_27_24
, HTX3_D
, SEL_HSCIF3_3
),
697 PINMUX_IPSR_MSEL(IP1_27_24
, IETX_B
, SEL_IEBUS_1
),
699 PINMUX_IPSR_GPSR(IP1_31_28
, A0
),
700 PINMUX_IPSR_GPSR(IP1_31_28
, LCDOUT16
),
701 PINMUX_IPSR_MSEL(IP1_31_28
, MSIOF3_SYNC_B
, SEL_MSIOF3_1
),
702 PINMUX_IPSR_GPSR(IP1_31_28
, VI4_DATA8
),
703 PINMUX_IPSR_GPSR(IP1_31_28
, DU_DB0
),
704 PINMUX_IPSR_MSEL(IP1_31_28
, PWM3_A
, SEL_PWM3_0
),
707 PINMUX_IPSR_GPSR(IP2_3_0
, A1
),
708 PINMUX_IPSR_GPSR(IP2_3_0
, LCDOUT17
),
709 PINMUX_IPSR_MSEL(IP2_3_0
, MSIOF3_TXD_B
, SEL_MSIOF3_1
),
710 PINMUX_IPSR_GPSR(IP2_3_0
, VI4_DATA9
),
711 PINMUX_IPSR_GPSR(IP2_3_0
, DU_DB1
),
712 PINMUX_IPSR_MSEL(IP2_3_0
, PWM4_A
, SEL_PWM4_0
),
714 PINMUX_IPSR_GPSR(IP2_7_4
, A2
),
715 PINMUX_IPSR_GPSR(IP2_7_4
, LCDOUT18
),
716 PINMUX_IPSR_MSEL(IP2_7_4
, MSIOF3_SCK_B
, SEL_MSIOF3_1
),
717 PINMUX_IPSR_GPSR(IP2_7_4
, VI4_DATA10
),
718 PINMUX_IPSR_GPSR(IP2_7_4
, DU_DB2
),
719 PINMUX_IPSR_MSEL(IP2_7_4
, PWM5_A
, SEL_PWM5_0
),
721 PINMUX_IPSR_GPSR(IP2_11_8
, A3
),
722 PINMUX_IPSR_GPSR(IP2_11_8
, LCDOUT19
),
723 PINMUX_IPSR_MSEL(IP2_11_8
, MSIOF3_RXD_B
, SEL_MSIOF3_1
),
724 PINMUX_IPSR_GPSR(IP2_11_8
, VI4_DATA11
),
725 PINMUX_IPSR_GPSR(IP2_11_8
, DU_DB3
),
726 PINMUX_IPSR_MSEL(IP2_11_8
, PWM6_A
, SEL_PWM6_0
),
728 PINMUX_IPSR_GPSR(IP2_15_12
, A4
),
729 PINMUX_IPSR_GPSR(IP2_15_12
, LCDOUT20
),
730 PINMUX_IPSR_MSEL(IP2_15_12
, MSIOF3_SS1_B
, SEL_MSIOF3_1
),
731 PINMUX_IPSR_GPSR(IP2_15_12
, VI4_DATA12
),
732 PINMUX_IPSR_GPSR(IP2_15_12
, VI5_DATA12
),
733 PINMUX_IPSR_GPSR(IP2_15_12
, DU_DB4
),
735 PINMUX_IPSR_GPSR(IP2_19_16
, A5
),
736 PINMUX_IPSR_GPSR(IP2_19_16
, LCDOUT21
),
737 PINMUX_IPSR_MSEL(IP2_19_16
, MSIOF3_SS2_B
, SEL_MSIOF3_1
),
738 PINMUX_IPSR_MSEL(IP2_19_16
, SCK4_B
, SEL_SCIF4_1
),
739 PINMUX_IPSR_GPSR(IP2_19_16
, VI4_DATA13
),
740 PINMUX_IPSR_GPSR(IP2_19_16
, VI5_DATA13
),
741 PINMUX_IPSR_GPSR(IP2_19_16
, DU_DB5
),
743 PINMUX_IPSR_GPSR(IP2_23_20
, A6
),
744 PINMUX_IPSR_GPSR(IP2_23_20
, LCDOUT22
),
745 PINMUX_IPSR_MSEL(IP2_23_20
, MSIOF2_SS1_A
, SEL_MSIOF2_0
),
746 PINMUX_IPSR_MSEL(IP2_23_20
, RX4_B
, SEL_SCIF4_1
),
747 PINMUX_IPSR_GPSR(IP2_23_20
, VI4_DATA14
),
748 PINMUX_IPSR_GPSR(IP2_23_20
, VI5_DATA14
),
749 PINMUX_IPSR_GPSR(IP2_23_20
, DU_DB6
),
751 PINMUX_IPSR_GPSR(IP2_27_24
, A7
),
752 PINMUX_IPSR_GPSR(IP2_27_24
, LCDOUT23
),
753 PINMUX_IPSR_MSEL(IP2_27_24
, MSIOF2_SS2_A
, SEL_MSIOF2_0
),
754 PINMUX_IPSR_MSEL(IP2_27_24
, TX4_B
, SEL_SCIF4_1
),
755 PINMUX_IPSR_GPSR(IP2_27_24
, VI4_DATA15
),
756 PINMUX_IPSR_GPSR(IP2_27_24
, VI5_DATA15
),
757 PINMUX_IPSR_GPSR(IP2_27_24
, DU_DB7
),
759 PINMUX_IPSR_GPSR(IP2_31_28
, A8
),
760 PINMUX_IPSR_MSEL(IP2_31_28
, RX3_B
, SEL_SCIF3_1
),
761 PINMUX_IPSR_MSEL(IP2_31_28
, MSIOF2_SYNC_A
, SEL_MSIOF2_0
),
762 PINMUX_IPSR_MSEL(IP2_31_28
, HRX4_B
, SEL_HSCIF4_1
),
763 PINMUX_IPSR_MSEL(IP2_31_28
, SDA6_A
, SEL_I2C6_0
),
764 PINMUX_IPSR_MSEL(IP2_31_28
, AVB_AVTP_MATCH_B
, SEL_ETHERAVB_1
),
765 PINMUX_IPSR_MSEL(IP2_31_28
, PWM1_B
, SEL_PWM1_1
),
768 PINMUX_IPSR_GPSR(IP3_3_0
, A9
),
769 PINMUX_IPSR_MSEL(IP3_3_0
, MSIOF2_SCK_A
, SEL_MSIOF2_0
),
770 PINMUX_IPSR_MSEL(IP3_3_0
, CTS4_N_B
, SEL_SCIF4_1
),
771 PINMUX_IPSR_GPSR(IP3_3_0
, VI5_VSYNC_N
),
773 PINMUX_IPSR_GPSR(IP3_7_4
, A10
),
774 PINMUX_IPSR_MSEL(IP3_7_4
, MSIOF2_RXD_A
, SEL_MSIOF2_0
),
775 PINMUX_IPSR_MSEL(IP3_7_4
, RTS4_N_TANS_B
, SEL_SCIF4_1
),
776 PINMUX_IPSR_GPSR(IP3_7_4
, VI5_HSYNC_N
),
778 PINMUX_IPSR_GPSR(IP3_11_8
, A11
),
779 PINMUX_IPSR_MSEL(IP3_11_8
, TX3_B
, SEL_SCIF3_1
),
780 PINMUX_IPSR_MSEL(IP3_11_8
, MSIOF2_TXD_A
, SEL_MSIOF2_0
),
781 PINMUX_IPSR_MSEL(IP3_11_8
, HTX4_B
, SEL_HSCIF4_1
),
782 PINMUX_IPSR_GPSR(IP3_11_8
, HSCK4
),
783 PINMUX_IPSR_GPSR(IP3_11_8
, VI5_FIELD
),
784 PINMUX_IPSR_MSEL(IP3_11_8
, SCL6_A
, SEL_I2C6_0
),
785 PINMUX_IPSR_MSEL(IP3_11_8
, AVB_AVTP_CAPTURE_B
, SEL_ETHERAVB_1
),
786 PINMUX_IPSR_MSEL(IP3_11_8
, PWM2_B
, SEL_PWM2_1
),
788 PINMUX_IPSR_GPSR(IP3_15_12
, A12
),
789 PINMUX_IPSR_GPSR(IP3_15_12
, LCDOUT12
),
790 PINMUX_IPSR_MSEL(IP3_15_12
, MSIOF3_SCK_C
, SEL_MSIOF3_2
),
791 PINMUX_IPSR_MSEL(IP3_15_12
, HRX4_A
, SEL_HSCIF4_0
),
792 PINMUX_IPSR_GPSR(IP3_15_12
, VI5_DATA8
),
793 PINMUX_IPSR_GPSR(IP3_15_12
, DU_DG4
),
795 PINMUX_IPSR_GPSR(IP3_19_16
, A13
),
796 PINMUX_IPSR_GPSR(IP3_19_16
, LCDOUT13
),
797 PINMUX_IPSR_MSEL(IP3_19_16
, MSIOF3_SYNC_C
, SEL_MSIOF3_2
),
798 PINMUX_IPSR_MSEL(IP3_19_16
, HTX4_A
, SEL_HSCIF4_0
),
799 PINMUX_IPSR_GPSR(IP3_19_16
, VI5_DATA9
),
800 PINMUX_IPSR_GPSR(IP3_19_16
, DU_DG5
),
802 PINMUX_IPSR_GPSR(IP3_23_20
, A14
),
803 PINMUX_IPSR_GPSR(IP3_23_20
, LCDOUT14
),
804 PINMUX_IPSR_MSEL(IP3_23_20
, MSIOF3_RXD_C
, SEL_MSIOF3_2
),
805 PINMUX_IPSR_GPSR(IP3_23_20
, HCTS4_N
),
806 PINMUX_IPSR_GPSR(IP3_23_20
, VI5_DATA10
),
807 PINMUX_IPSR_GPSR(IP3_23_20
, DU_DG6
),
809 PINMUX_IPSR_GPSR(IP3_27_24
, A15
),
810 PINMUX_IPSR_GPSR(IP3_27_24
, LCDOUT15
),
811 PINMUX_IPSR_MSEL(IP3_27_24
, MSIOF3_TXD_C
, SEL_MSIOF3_2
),
812 PINMUX_IPSR_GPSR(IP3_27_24
, HRTS4_N
),
813 PINMUX_IPSR_GPSR(IP3_27_24
, VI5_DATA11
),
814 PINMUX_IPSR_GPSR(IP3_27_24
, DU_DG7
),
816 PINMUX_IPSR_GPSR(IP3_31_28
, A16
),
817 PINMUX_IPSR_GPSR(IP3_31_28
, LCDOUT8
),
818 PINMUX_IPSR_GPSR(IP3_31_28
, VI4_FIELD
),
819 PINMUX_IPSR_GPSR(IP3_31_28
, DU_DG0
),
822 PINMUX_IPSR_GPSR(IP4_3_0
, A17
),
823 PINMUX_IPSR_GPSR(IP4_3_0
, LCDOUT9
),
824 PINMUX_IPSR_GPSR(IP4_3_0
, VI4_VSYNC_N
),
825 PINMUX_IPSR_GPSR(IP4_3_0
, DU_DG1
),
827 PINMUX_IPSR_GPSR(IP4_7_4
, A18
),
828 PINMUX_IPSR_GPSR(IP4_7_4
, LCDOUT10
),
829 PINMUX_IPSR_GPSR(IP4_7_4
, VI4_HSYNC_N
),
830 PINMUX_IPSR_GPSR(IP4_7_4
, DU_DG2
),
832 PINMUX_IPSR_GPSR(IP4_11_8
, A19
),
833 PINMUX_IPSR_GPSR(IP4_11_8
, LCDOUT11
),
834 PINMUX_IPSR_GPSR(IP4_11_8
, VI4_CLKENB
),
835 PINMUX_IPSR_GPSR(IP4_11_8
, DU_DG3
),
837 PINMUX_IPSR_GPSR(IP4_15_12
, CS0_N
),
838 PINMUX_IPSR_GPSR(IP4_15_12
, VI5_CLKENB
),
840 PINMUX_IPSR_GPSR(IP4_19_16
, CS1_N_A26
),
841 PINMUX_IPSR_GPSR(IP4_19_16
, VI5_CLK
),
842 PINMUX_IPSR_MSEL(IP4_19_16
, EX_WAIT0_B
, SEL_LBSC_1
),
844 PINMUX_IPSR_GPSR(IP4_23_20
, BS_N
),
845 PINMUX_IPSR_GPSR(IP4_23_20
, QSTVA_QVS
),
846 PINMUX_IPSR_MSEL(IP4_23_20
, MSIOF3_SCK_D
, SEL_MSIOF3_3
),
847 PINMUX_IPSR_GPSR(IP4_23_20
, SCK3
),
848 PINMUX_IPSR_GPSR(IP4_23_20
, HSCK3
),
849 PINMUX_IPSR_GPSR(IP4_23_20
, CAN1_TX
),
850 PINMUX_IPSR_GPSR(IP4_23_20
, CANFD1_TX
),
851 PINMUX_IPSR_MSEL(IP4_23_20
, IETX_A
, SEL_IEBUS_0
),
853 PINMUX_IPSR_GPSR(IP4_27_24
, RD_N
),
854 PINMUX_IPSR_MSEL(IP4_27_24
, MSIOF3_SYNC_D
, SEL_MSIOF3_3
),
855 PINMUX_IPSR_MSEL(IP4_27_24
, RX3_A
, SEL_SCIF3_0
),
856 PINMUX_IPSR_MSEL(IP4_27_24
, HRX3_A
, SEL_HSCIF3_0
),
857 PINMUX_IPSR_MSEL(IP4_27_24
, CAN0_TX_A
, SEL_RCAN0_0
),
858 PINMUX_IPSR_MSEL(IP4_27_24
, CANFD0_TX_A
, SEL_CANFD0_0
),
860 PINMUX_IPSR_GPSR(IP4_31_28
, RD_WR_N
),
861 PINMUX_IPSR_MSEL(IP4_31_28
, MSIOF3_RXD_D
, SEL_MSIOF3_3
),
862 PINMUX_IPSR_MSEL(IP4_31_28
, TX3_A
, SEL_SCIF3_0
),
863 PINMUX_IPSR_MSEL(IP4_31_28
, HTX3_A
, SEL_HSCIF3_0
),
864 PINMUX_IPSR_MSEL(IP4_31_28
, CAN0_RX_A
, SEL_RCAN0_0
),
865 PINMUX_IPSR_MSEL(IP4_31_28
, CANFD0_RX_A
, SEL_CANFD0_0
),
868 PINMUX_IPSR_GPSR(IP5_3_0
, WE0_N
),
869 PINMUX_IPSR_MSEL(IP5_3_0
, MSIOF3_TXD_D
, SEL_MSIOF3_3
),
870 PINMUX_IPSR_GPSR(IP5_3_0
, CTS3_N
),
871 PINMUX_IPSR_GPSR(IP5_3_0
, HCTS3_N
),
872 PINMUX_IPSR_MSEL(IP5_3_0
, SCL6_B
, SEL_I2C6_1
),
873 PINMUX_IPSR_GPSR(IP5_3_0
, CAN_CLK
),
874 PINMUX_IPSR_MSEL(IP5_3_0
, IECLK_A
, SEL_IEBUS_0
),
876 PINMUX_IPSR_GPSR(IP5_7_4
, WE1_N
),
877 PINMUX_IPSR_MSEL(IP5_7_4
, MSIOF3_SS1_D
, SEL_MSIOF3_3
),
878 PINMUX_IPSR_GPSR(IP5_7_4
, RTS3_N_TANS
),
879 PINMUX_IPSR_GPSR(IP5_7_4
, HRTS3_N
),
880 PINMUX_IPSR_MSEL(IP5_7_4
, SDA6_B
, SEL_I2C6_1
),
881 PINMUX_IPSR_GPSR(IP5_7_4
, CAN1_RX
),
882 PINMUX_IPSR_GPSR(IP5_7_4
, CANFD1_RX
),
883 PINMUX_IPSR_MSEL(IP5_7_4
, IERX_A
, SEL_IEBUS_0
),
885 PINMUX_IPSR_MSEL(IP5_11_8
, EX_WAIT0_A
, SEL_LBSC_0
),
886 PINMUX_IPSR_GPSR(IP5_11_8
, QCLK
),
887 PINMUX_IPSR_GPSR(IP5_11_8
, VI4_CLK
),
888 PINMUX_IPSR_GPSR(IP5_11_8
, DU_DOTCLKOUT0
),
890 PINMUX_IPSR_GPSR(IP5_15_12
, D0
),
891 PINMUX_IPSR_MSEL(IP5_15_12
, MSIOF2_SS1_B
, SEL_MSIOF2_1
),
892 PINMUX_IPSR_MSEL(IP5_15_12
, MSIOF3_SCK_A
, SEL_MSIOF3_0
),
893 PINMUX_IPSR_GPSR(IP5_15_12
, VI4_DATA16
),
894 PINMUX_IPSR_GPSR(IP5_15_12
, VI5_DATA0
),
896 PINMUX_IPSR_GPSR(IP5_19_16
, D1
),
897 PINMUX_IPSR_MSEL(IP5_19_16
, MSIOF2_SS2_B
, SEL_MSIOF2_1
),
898 PINMUX_IPSR_MSEL(IP5_19_16
, MSIOF3_SYNC_A
, SEL_MSIOF3_0
),
899 PINMUX_IPSR_GPSR(IP5_19_16
, VI4_DATA17
),
900 PINMUX_IPSR_GPSR(IP5_19_16
, VI5_DATA1
),
902 PINMUX_IPSR_GPSR(IP5_23_20
, D2
),
903 PINMUX_IPSR_MSEL(IP5_23_20
, MSIOF3_RXD_A
, SEL_MSIOF3_0
),
904 PINMUX_IPSR_GPSR(IP5_23_20
, VI4_DATA18
),
905 PINMUX_IPSR_GPSR(IP5_23_20
, VI5_DATA2
),
907 PINMUX_IPSR_GPSR(IP5_27_24
, D3
),
908 PINMUX_IPSR_MSEL(IP5_27_24
, MSIOF3_TXD_A
, SEL_MSIOF3_0
),
909 PINMUX_IPSR_GPSR(IP5_27_24
, VI4_DATA19
),
910 PINMUX_IPSR_GPSR(IP5_27_24
, VI5_DATA3
),
912 PINMUX_IPSR_GPSR(IP5_31_28
, D4
),
913 PINMUX_IPSR_MSEL(IP5_31_28
, MSIOF2_SCK_B
, SEL_MSIOF2_1
),
914 PINMUX_IPSR_GPSR(IP5_31_28
, VI4_DATA20
),
915 PINMUX_IPSR_GPSR(IP5_31_28
, VI5_DATA4
),
918 PINMUX_IPSR_GPSR(IP6_3_0
, D5
),
919 PINMUX_IPSR_MSEL(IP6_3_0
, MSIOF2_SYNC_B
, SEL_MSIOF2_1
),
920 PINMUX_IPSR_GPSR(IP6_3_0
, VI4_DATA21
),
921 PINMUX_IPSR_GPSR(IP6_3_0
, VI5_DATA5
),
923 PINMUX_IPSR_GPSR(IP6_7_4
, D6
),
924 PINMUX_IPSR_MSEL(IP6_7_4
, MSIOF2_RXD_B
, SEL_MSIOF2_1
),
925 PINMUX_IPSR_GPSR(IP6_7_4
, VI4_DATA22
),
926 PINMUX_IPSR_GPSR(IP6_7_4
, VI5_DATA6
),
928 PINMUX_IPSR_GPSR(IP6_11_8
, D7
),
929 PINMUX_IPSR_MSEL(IP6_11_8
, MSIOF2_TXD_B
, SEL_MSIOF2_1
),
930 PINMUX_IPSR_GPSR(IP6_11_8
, VI4_DATA23
),
931 PINMUX_IPSR_GPSR(IP6_11_8
, VI5_DATA7
),
933 PINMUX_IPSR_GPSR(IP6_15_12
, D8
),
934 PINMUX_IPSR_GPSR(IP6_15_12
, LCDOUT0
),
935 PINMUX_IPSR_MSEL(IP6_15_12
, MSIOF2_SCK_D
, SEL_MSIOF2_3
),
936 PINMUX_IPSR_MSEL(IP6_15_12
, SCK4_C
, SEL_SCIF4_2
),
937 PINMUX_IPSR_MSEL(IP6_15_12
, VI4_DATA0_A
, SEL_VIN4_0
),
938 PINMUX_IPSR_GPSR(IP6_15_12
, DU_DR0
),
940 PINMUX_IPSR_GPSR(IP6_19_16
, D9
),
941 PINMUX_IPSR_GPSR(IP6_19_16
, LCDOUT1
),
942 PINMUX_IPSR_MSEL(IP6_19_16
, MSIOF2_SYNC_D
, SEL_MSIOF2_3
),
943 PINMUX_IPSR_MSEL(IP6_19_16
, VI4_DATA1_A
, SEL_VIN4_0
),
944 PINMUX_IPSR_GPSR(IP6_19_16
, DU_DR1
),
946 PINMUX_IPSR_GPSR(IP6_23_20
, D10
),
947 PINMUX_IPSR_GPSR(IP6_23_20
, LCDOUT2
),
948 PINMUX_IPSR_MSEL(IP6_23_20
, MSIOF2_RXD_D
, SEL_MSIOF2_3
),
949 PINMUX_IPSR_MSEL(IP6_23_20
, HRX3_B
, SEL_HSCIF3_1
),
950 PINMUX_IPSR_MSEL(IP6_23_20
, VI4_DATA2_A
, SEL_VIN4_0
),
951 PINMUX_IPSR_MSEL(IP6_23_20
, CTS4_N_C
, SEL_SCIF4_2
),
952 PINMUX_IPSR_GPSR(IP6_23_20
, DU_DR2
),
954 PINMUX_IPSR_GPSR(IP6_27_24
, D11
),
955 PINMUX_IPSR_GPSR(IP6_27_24
, LCDOUT3
),
956 PINMUX_IPSR_MSEL(IP6_27_24
, MSIOF2_TXD_D
, SEL_MSIOF2_3
),
957 PINMUX_IPSR_MSEL(IP6_27_24
, HTX3_B
, SEL_HSCIF3_1
),
958 PINMUX_IPSR_MSEL(IP6_27_24
, VI4_DATA3_A
, SEL_VIN4_0
),
959 PINMUX_IPSR_MSEL(IP6_27_24
, RTS4_N_TANS_C
, SEL_SCIF4_2
),
960 PINMUX_IPSR_GPSR(IP6_27_24
, DU_DR3
),
962 PINMUX_IPSR_GPSR(IP6_31_28
, D12
),
963 PINMUX_IPSR_GPSR(IP6_31_28
, LCDOUT4
),
964 PINMUX_IPSR_MSEL(IP6_31_28
, MSIOF2_SS1_D
, SEL_MSIOF2_3
),
965 PINMUX_IPSR_MSEL(IP6_31_28
, RX4_C
, SEL_SCIF4_2
),
966 PINMUX_IPSR_MSEL(IP6_31_28
, VI4_DATA4_A
, SEL_VIN4_0
),
967 PINMUX_IPSR_GPSR(IP6_31_28
, DU_DR4
),
970 PINMUX_IPSR_GPSR(IP7_3_0
, D13
),
971 PINMUX_IPSR_GPSR(IP7_3_0
, LCDOUT5
),
972 PINMUX_IPSR_MSEL(IP7_3_0
, MSIOF2_SS2_D
, SEL_MSIOF2_3
),
973 PINMUX_IPSR_MSEL(IP7_3_0
, TX4_C
, SEL_SCIF4_2
),
974 PINMUX_IPSR_MSEL(IP7_3_0
, VI4_DATA5_A
, SEL_VIN4_0
),
975 PINMUX_IPSR_GPSR(IP7_3_0
, DU_DR5
),
977 PINMUX_IPSR_GPSR(IP7_7_4
, D14
),
978 PINMUX_IPSR_GPSR(IP7_7_4
, LCDOUT6
),
979 PINMUX_IPSR_MSEL(IP7_7_4
, MSIOF3_SS1_A
, SEL_MSIOF3_0
),
980 PINMUX_IPSR_MSEL(IP7_7_4
, HRX3_C
, SEL_HSCIF3_2
),
981 PINMUX_IPSR_MSEL(IP7_7_4
, VI4_DATA6_A
, SEL_VIN4_0
),
982 PINMUX_IPSR_GPSR(IP7_7_4
, DU_DR6
),
983 PINMUX_IPSR_MSEL(IP7_7_4
, SCL6_C
, SEL_I2C6_2
),
985 PINMUX_IPSR_GPSR(IP7_11_8
, D15
),
986 PINMUX_IPSR_GPSR(IP7_11_8
, LCDOUT7
),
987 PINMUX_IPSR_MSEL(IP7_11_8
, MSIOF3_SS2_A
, SEL_MSIOF3_0
),
988 PINMUX_IPSR_MSEL(IP7_11_8
, HTX3_C
, SEL_HSCIF3_2
),
989 PINMUX_IPSR_MSEL(IP7_11_8
, VI4_DATA7_A
, SEL_VIN4_0
),
990 PINMUX_IPSR_GPSR(IP7_11_8
, DU_DR7
),
991 PINMUX_IPSR_MSEL(IP7_11_8
, SDA6_C
, SEL_I2C6_2
),
993 PINMUX_IPSR_GPSR(IP7_15_12
, FSCLKST
),
995 PINMUX_IPSR_GPSR(IP7_19_16
, SD0_CLK
),
996 PINMUX_IPSR_MSEL(IP7_19_16
, MSIOF1_SCK_E
, SEL_MSIOF1_4
),
997 PINMUX_IPSR_MSEL(IP7_19_16
, STP_OPWM_0_B
, SEL_SSP1_0_1
),
999 PINMUX_IPSR_GPSR(IP7_23_20
, SD0_CMD
),
1000 PINMUX_IPSR_MSEL(IP7_23_20
, MSIOF1_SYNC_E
, SEL_MSIOF1_4
),
1001 PINMUX_IPSR_MSEL(IP7_23_20
, STP_IVCXO27_0_B
, SEL_SSP1_0_1
),
1003 PINMUX_IPSR_GPSR(IP7_27_24
, SD0_DAT0
),
1004 PINMUX_IPSR_MSEL(IP7_27_24
, MSIOF1_RXD_E
, SEL_MSIOF1_4
),
1005 PINMUX_IPSR_MSEL(IP7_27_24
, TS_SCK0_B
, SEL_TSIF0_1
),
1006 PINMUX_IPSR_MSEL(IP7_27_24
, STP_ISCLK_0_B
, SEL_SSP1_0_1
),
1008 PINMUX_IPSR_GPSR(IP7_31_28
, SD0_DAT1
),
1009 PINMUX_IPSR_MSEL(IP7_31_28
, MSIOF1_TXD_E
, SEL_MSIOF1_4
),
1010 PINMUX_IPSR_MSEL(IP7_31_28
, TS_SPSYNC0_B
, SEL_TSIF0_1
),
1011 PINMUX_IPSR_MSEL(IP7_31_28
, STP_ISSYNC_0_B
, SEL_SSP1_0_1
),
1014 PINMUX_IPSR_GPSR(IP8_3_0
, SD0_DAT2
),
1015 PINMUX_IPSR_MSEL(IP8_3_0
, MSIOF1_SS1_E
, SEL_MSIOF1_4
),
1016 PINMUX_IPSR_MSEL(IP8_3_0
, TS_SDAT0_B
, SEL_TSIF0_1
),
1017 PINMUX_IPSR_MSEL(IP8_3_0
, STP_ISD_0_B
, SEL_SSP1_0_1
),
1019 PINMUX_IPSR_GPSR(IP8_7_4
, SD0_DAT3
),
1020 PINMUX_IPSR_MSEL(IP8_7_4
, MSIOF1_SS2_E
, SEL_MSIOF1_4
),
1021 PINMUX_IPSR_MSEL(IP8_7_4
, TS_SDEN0_B
, SEL_TSIF0_1
),
1022 PINMUX_IPSR_MSEL(IP8_7_4
, STP_ISEN_0_B
, SEL_SSP1_0_1
),
1024 PINMUX_IPSR_GPSR(IP8_11_8
, SD1_CLK
),
1025 PINMUX_IPSR_MSEL(IP8_11_8
, MSIOF1_SCK_G
, SEL_MSIOF1_6
),
1026 PINMUX_IPSR_MSEL(IP8_11_8
, SIM0_CLK_A
, SEL_SIMCARD_0
),
1028 PINMUX_IPSR_GPSR(IP8_15_12
, SD1_CMD
),
1029 PINMUX_IPSR_MSEL(IP8_15_12
, MSIOF1_SYNC_G
, SEL_MSIOF1_6
),
1030 PINMUX_IPSR_MSEL(IP8_15_12
, NFCE_N_B
, SEL_NDF_1
),
1031 PINMUX_IPSR_MSEL(IP8_15_12
, SIM0_D_A
, SEL_SIMCARD_0
),
1032 PINMUX_IPSR_MSEL(IP8_15_12
, STP_IVCXO27_1_B
, SEL_SSP1_1_1
),
1034 PINMUX_IPSR_GPSR(IP8_19_16
, SD1_DAT0
),
1035 PINMUX_IPSR_GPSR(IP8_19_16
, SD2_DAT4
),
1036 PINMUX_IPSR_MSEL(IP8_19_16
, MSIOF1_RXD_G
, SEL_MSIOF1_6
),
1037 PINMUX_IPSR_MSEL(IP8_19_16
, NFWP_N_B
, SEL_NDF_1
),
1038 PINMUX_IPSR_MSEL(IP8_19_16
, TS_SCK1_B
, SEL_TSIF1_1
),
1039 PINMUX_IPSR_MSEL(IP8_19_16
, STP_ISCLK_1_B
, SEL_SSP1_1_1
),
1041 PINMUX_IPSR_GPSR(IP8_23_20
, SD1_DAT1
),
1042 PINMUX_IPSR_GPSR(IP8_23_20
, SD2_DAT5
),
1043 PINMUX_IPSR_MSEL(IP8_23_20
, MSIOF1_TXD_G
, SEL_MSIOF1_6
),
1044 PINMUX_IPSR_MSEL(IP8_23_20
, NFDATA14_B
, SEL_NDF_1
),
1045 PINMUX_IPSR_MSEL(IP8_23_20
, TS_SPSYNC1_B
, SEL_TSIF1_1
),
1046 PINMUX_IPSR_MSEL(IP8_23_20
, STP_ISSYNC_1_B
, SEL_SSP1_1_1
),
1048 PINMUX_IPSR_GPSR(IP8_27_24
, SD1_DAT2
),
1049 PINMUX_IPSR_GPSR(IP8_27_24
, SD2_DAT6
),
1050 PINMUX_IPSR_MSEL(IP8_27_24
, MSIOF1_SS1_G
, SEL_MSIOF1_6
),
1051 PINMUX_IPSR_MSEL(IP8_27_24
, NFDATA15_B
, SEL_NDF_1
),
1052 PINMUX_IPSR_MSEL(IP8_27_24
, TS_SDAT1_B
, SEL_TSIF1_1
),
1053 PINMUX_IPSR_MSEL(IP8_27_24
, STP_ISD_1_B
, SEL_SSP1_1_1
),
1055 PINMUX_IPSR_GPSR(IP8_31_28
, SD1_DAT3
),
1056 PINMUX_IPSR_GPSR(IP8_31_28
, SD2_DAT7
),
1057 PINMUX_IPSR_MSEL(IP8_31_28
, MSIOF1_SS2_G
, SEL_MSIOF1_6
),
1058 PINMUX_IPSR_MSEL(IP8_31_28
, NFRB_N_B
, SEL_NDF_1
),
1059 PINMUX_IPSR_MSEL(IP8_31_28
, TS_SDEN1_B
, SEL_TSIF1_1
),
1060 PINMUX_IPSR_MSEL(IP8_31_28
, STP_ISEN_1_B
, SEL_SSP1_1_1
),
1063 PINMUX_IPSR_GPSR(IP9_3_0
, SD2_CLK
),
1064 PINMUX_IPSR_GPSR(IP9_3_0
, NFDATA8
),
1066 PINMUX_IPSR_GPSR(IP9_7_4
, SD2_CMD
),
1067 PINMUX_IPSR_GPSR(IP9_7_4
, NFDATA9
),
1069 PINMUX_IPSR_GPSR(IP9_11_8
, SD2_DAT0
),
1070 PINMUX_IPSR_GPSR(IP9_11_8
, NFDATA10
),
1072 PINMUX_IPSR_GPSR(IP9_15_12
, SD2_DAT1
),
1073 PINMUX_IPSR_GPSR(IP9_15_12
, NFDATA11
),
1075 PINMUX_IPSR_GPSR(IP9_19_16
, SD2_DAT2
),
1076 PINMUX_IPSR_GPSR(IP9_19_16
, NFDATA12
),
1078 PINMUX_IPSR_GPSR(IP9_23_20
, SD2_DAT3
),
1079 PINMUX_IPSR_GPSR(IP9_23_20
, NFDATA13
),
1081 PINMUX_IPSR_GPSR(IP9_27_24
, SD2_DS
),
1082 PINMUX_IPSR_GPSR(IP9_27_24
, NFALE
),
1084 PINMUX_IPSR_GPSR(IP9_31_28
, SD3_CLK
),
1085 PINMUX_IPSR_GPSR(IP9_31_28
, NFWE_N
),
1088 PINMUX_IPSR_GPSR(IP10_3_0
, SD3_CMD
),
1089 PINMUX_IPSR_GPSR(IP10_3_0
, NFRE_N
),
1091 PINMUX_IPSR_GPSR(IP10_7_4
, SD3_DAT0
),
1092 PINMUX_IPSR_GPSR(IP10_7_4
, NFDATA0
),
1094 PINMUX_IPSR_GPSR(IP10_11_8
, SD3_DAT1
),
1095 PINMUX_IPSR_GPSR(IP10_11_8
, NFDATA1
),
1097 PINMUX_IPSR_GPSR(IP10_15_12
, SD3_DAT2
),
1098 PINMUX_IPSR_GPSR(IP10_15_12
, NFDATA2
),
1100 PINMUX_IPSR_GPSR(IP10_19_16
, SD3_DAT3
),
1101 PINMUX_IPSR_GPSR(IP10_19_16
, NFDATA3
),
1103 PINMUX_IPSR_GPSR(IP10_23_20
, SD3_DAT4
),
1104 PINMUX_IPSR_MSEL(IP10_23_20
, SD2_CD_A
, SEL_SDHI2_0
),
1105 PINMUX_IPSR_GPSR(IP10_23_20
, NFDATA4
),
1107 PINMUX_IPSR_GPSR(IP10_27_24
, SD3_DAT5
),
1108 PINMUX_IPSR_MSEL(IP10_27_24
, SD2_WP_A
, SEL_SDHI2_0
),
1109 PINMUX_IPSR_GPSR(IP10_27_24
, NFDATA5
),
1111 PINMUX_IPSR_GPSR(IP10_31_28
, SD3_DAT6
),
1112 PINMUX_IPSR_GPSR(IP10_31_28
, SD3_CD
),
1113 PINMUX_IPSR_GPSR(IP10_31_28
, NFDATA6
),
1116 PINMUX_IPSR_GPSR(IP11_3_0
, SD3_DAT7
),
1117 PINMUX_IPSR_GPSR(IP11_3_0
, SD3_WP
),
1118 PINMUX_IPSR_GPSR(IP11_3_0
, NFDATA7
),
1120 PINMUX_IPSR_GPSR(IP11_7_4
, SD3_DS
),
1121 PINMUX_IPSR_GPSR(IP11_7_4
, NFCLE
),
1123 PINMUX_IPSR_GPSR(IP11_11_8
, SD0_CD
),
1124 PINMUX_IPSR_MSEL(IP11_11_8
, SCL2_B
, SEL_I2C2_1
),
1125 PINMUX_IPSR_MSEL(IP11_11_8
, SIM0_RST_A
, SEL_SIMCARD_0
),
1127 PINMUX_IPSR_GPSR(IP11_15_12
, SD0_WP
),
1128 PINMUX_IPSR_MSEL(IP11_15_12
, SDA2_B
, SEL_I2C2_1
),
1130 PINMUX_IPSR_GPSR(IP11_19_16
, SD1_CD
),
1131 PINMUX_IPSR_MSEL(IP11_19_16
, SIM0_CLK_B
, SEL_SIMCARD_1
),
1133 PINMUX_IPSR_GPSR(IP11_23_20
, SD1_WP
),
1134 PINMUX_IPSR_MSEL(IP11_23_20
, SIM0_D_B
, SEL_SIMCARD_1
),
1136 PINMUX_IPSR_GPSR(IP11_27_24
, SCK0
),
1137 PINMUX_IPSR_MSEL(IP11_27_24
, HSCK1_B
, SEL_HSCIF1_1
),
1138 PINMUX_IPSR_MSEL(IP11_27_24
, MSIOF1_SS2_B
, SEL_MSIOF1_1
),
1139 PINMUX_IPSR_MSEL(IP11_27_24
, AUDIO_CLKC_B
, SEL_ADG_C_1
),
1140 PINMUX_IPSR_MSEL(IP11_27_24
, SDA2_A
, SEL_I2C2_0
),
1141 PINMUX_IPSR_MSEL(IP11_27_24
, SIM0_RST_B
, SEL_SIMCARD_1
),
1142 PINMUX_IPSR_MSEL(IP11_27_24
, STP_OPWM_0_C
, SEL_SSP1_0_2
),
1143 PINMUX_IPSR_MSEL(IP11_27_24
, RIF0_CLK_B
, SEL_DRIF0_1
),
1144 PINMUX_IPSR_GPSR(IP11_27_24
, ADICHS2
),
1145 PINMUX_IPSR_MSEL(IP11_27_24
, SCK5_B
, SEL_SCIF5_1
),
1147 PINMUX_IPSR_GPSR(IP11_31_28
, RX0
),
1148 PINMUX_IPSR_MSEL(IP11_31_28
, HRX1_B
, SEL_HSCIF1_1
),
1149 PINMUX_IPSR_MSEL(IP11_31_28
, TS_SCK0_C
, SEL_TSIF0_2
),
1150 PINMUX_IPSR_MSEL(IP11_31_28
, STP_ISCLK_0_C
, SEL_SSP1_0_2
),
1151 PINMUX_IPSR_MSEL(IP11_31_28
, RIF0_D0_B
, SEL_DRIF0_1
),
1154 PINMUX_IPSR_GPSR(IP12_3_0
, TX0
),
1155 PINMUX_IPSR_MSEL(IP12_3_0
, HTX1_B
, SEL_HSCIF1_1
),
1156 PINMUX_IPSR_MSEL(IP12_3_0
, TS_SPSYNC0_C
, SEL_TSIF0_2
),
1157 PINMUX_IPSR_MSEL(IP12_3_0
, STP_ISSYNC_0_C
, SEL_SSP1_0_2
),
1158 PINMUX_IPSR_MSEL(IP12_3_0
, RIF0_D1_B
, SEL_DRIF0_1
),
1160 PINMUX_IPSR_GPSR(IP12_7_4
, CTS0_N
),
1161 PINMUX_IPSR_MSEL(IP12_7_4
, HCTS1_N_B
, SEL_HSCIF1_1
),
1162 PINMUX_IPSR_MSEL(IP12_7_4
, MSIOF1_SYNC_B
, SEL_MSIOF1_1
),
1163 PINMUX_IPSR_MSEL(IP12_7_4
, TS_SPSYNC1_C
, SEL_TSIF1_2
),
1164 PINMUX_IPSR_MSEL(IP12_7_4
, STP_ISSYNC_1_C
, SEL_SSP1_1_2
),
1165 PINMUX_IPSR_MSEL(IP12_7_4
, RIF1_SYNC_B
, SEL_DRIF1_1
),
1166 PINMUX_IPSR_GPSR(IP12_7_4
, AUDIO_CLKOUT_C
),
1167 PINMUX_IPSR_GPSR(IP12_7_4
, ADICS_SAMP
),
1169 PINMUX_IPSR_GPSR(IP12_11_8
, RTS0_N_TANS
),
1170 PINMUX_IPSR_MSEL(IP12_11_8
, HRTS1_N_B
, SEL_HSCIF1_1
),
1171 PINMUX_IPSR_MSEL(IP12_11_8
, MSIOF1_SS1_B
, SEL_MSIOF1_1
),
1172 PINMUX_IPSR_MSEL(IP12_11_8
, AUDIO_CLKA_B
, SEL_ADG_A_1
),
1173 PINMUX_IPSR_MSEL(IP12_11_8
, SCL2_A
, SEL_I2C2_0
),
1174 PINMUX_IPSR_MSEL(IP12_11_8
, STP_IVCXO27_1_C
, SEL_SSP1_1_2
),
1175 PINMUX_IPSR_MSEL(IP12_11_8
, RIF0_SYNC_B
, SEL_DRIF0_1
),
1176 PINMUX_IPSR_MSEL(IP12_11_8
, FSO_TOE_A
, SEL_FSO_0
),
1177 PINMUX_IPSR_GPSR(IP12_11_8
, ADICHS1
),
1179 PINMUX_IPSR_MSEL(IP12_15_12
, RX1_A
, SEL_SCIF1_0
),
1180 PINMUX_IPSR_MSEL(IP12_15_12
, HRX1_A
, SEL_HSCIF1_0
),
1181 PINMUX_IPSR_MSEL(IP12_15_12
, TS_SDAT0_C
, SEL_TSIF0_2
),
1182 PINMUX_IPSR_MSEL(IP12_15_12
, STP_ISD_0_C
, SEL_SSP1_0_2
),
1183 PINMUX_IPSR_MSEL(IP12_15_12
, RIF1_CLK_C
, SEL_DRIF1_2
),
1185 PINMUX_IPSR_MSEL(IP12_19_16
, TX1_A
, SEL_SCIF1_0
),
1186 PINMUX_IPSR_MSEL(IP12_19_16
, HTX1_A
, SEL_HSCIF1_0
),
1187 PINMUX_IPSR_MSEL(IP12_19_16
, TS_SDEN0_C
, SEL_TSIF0_2
),
1188 PINMUX_IPSR_MSEL(IP12_19_16
, STP_ISEN_0_C
, SEL_SSP1_0_2
),
1189 PINMUX_IPSR_MSEL(IP12_19_16
, RIF1_D0_C
, SEL_DRIF1_2
),
1191 PINMUX_IPSR_GPSR(IP12_23_20
, CTS1_N
),
1192 PINMUX_IPSR_MSEL(IP12_23_20
, HCTS1_N_A
, SEL_HSCIF1_0
),
1193 PINMUX_IPSR_MSEL(IP12_23_20
, MSIOF1_RXD_B
, SEL_MSIOF1_1
),
1194 PINMUX_IPSR_MSEL(IP12_23_20
, TS_SDEN1_C
, SEL_TSIF1_2
),
1195 PINMUX_IPSR_MSEL(IP12_23_20
, STP_ISEN_1_C
, SEL_SSP1_1_2
),
1196 PINMUX_IPSR_MSEL(IP12_23_20
, RIF1_D0_B
, SEL_DRIF1_1
),
1197 PINMUX_IPSR_GPSR(IP12_23_20
, ADIDATA
),
1199 PINMUX_IPSR_GPSR(IP12_27_24
, RTS1_N_TANS
),
1200 PINMUX_IPSR_MSEL(IP12_27_24
, HRTS1_N_A
, SEL_HSCIF1_0
),
1201 PINMUX_IPSR_MSEL(IP12_27_24
, MSIOF1_TXD_B
, SEL_MSIOF1_1
),
1202 PINMUX_IPSR_MSEL(IP12_27_24
, TS_SDAT1_C
, SEL_TSIF1_2
),
1203 PINMUX_IPSR_MSEL(IP12_27_24
, STP_ISD_1_C
, SEL_SSP1_1_2
),
1204 PINMUX_IPSR_MSEL(IP12_27_24
, RIF1_D1_B
, SEL_DRIF1_1
),
1205 PINMUX_IPSR_GPSR(IP12_27_24
, ADICHS0
),
1207 PINMUX_IPSR_GPSR(IP12_31_28
, SCK2
),
1208 PINMUX_IPSR_MSEL(IP12_31_28
, SCIF_CLK_B
, SEL_SCIF1_1
),
1209 PINMUX_IPSR_MSEL(IP12_31_28
, MSIOF1_SCK_B
, SEL_MSIOF1_1
),
1210 PINMUX_IPSR_MSEL(IP12_31_28
, TS_SCK1_C
, SEL_TSIF1_2
),
1211 PINMUX_IPSR_MSEL(IP12_31_28
, STP_ISCLK_1_C
, SEL_SSP1_1_2
),
1212 PINMUX_IPSR_MSEL(IP12_31_28
, RIF1_CLK_B
, SEL_DRIF1_1
),
1213 PINMUX_IPSR_GPSR(IP12_31_28
, ADICLK
),
1216 PINMUX_IPSR_MSEL(IP13_3_0
, TX2_A
, SEL_SCIF2_0
),
1217 PINMUX_IPSR_MSEL(IP13_3_0
, SD2_CD_B
, SEL_SDHI2_1
),
1218 PINMUX_IPSR_MSEL(IP13_3_0
, SCL1_A
, SEL_I2C1_0
),
1219 PINMUX_IPSR_MSEL(IP13_3_0
, FMCLK_A
, SEL_FM_0
),
1220 PINMUX_IPSR_MSEL(IP13_3_0
, RIF1_D1_C
, SEL_DRIF1_2
),
1221 PINMUX_IPSR_MSEL(IP13_3_0
, FSO_CFE_0_B
, SEL_FSO_1
),
1223 PINMUX_IPSR_MSEL(IP13_7_4
, RX2_A
, SEL_SCIF2_0
),
1224 PINMUX_IPSR_MSEL(IP13_7_4
, SD2_WP_B
, SEL_SDHI2_1
),
1225 PINMUX_IPSR_MSEL(IP13_7_4
, SDA1_A
, SEL_I2C1_0
),
1226 PINMUX_IPSR_MSEL(IP13_7_4
, FMIN_A
, SEL_FM_0
),
1227 PINMUX_IPSR_MSEL(IP13_7_4
, RIF1_SYNC_C
, SEL_DRIF1_2
),
1228 PINMUX_IPSR_MSEL(IP13_7_4
, FSO_CFE_1_B
, SEL_FSO_1
),
1230 PINMUX_IPSR_GPSR(IP13_11_8
, HSCK0
),
1231 PINMUX_IPSR_MSEL(IP13_11_8
, MSIOF1_SCK_D
, SEL_MSIOF1_3
),
1232 PINMUX_IPSR_MSEL(IP13_11_8
, AUDIO_CLKB_A
, SEL_ADG_B_0
),
1233 PINMUX_IPSR_MSEL(IP13_11_8
, SSI_SDATA1_B
, SEL_SSI_1
),
1234 PINMUX_IPSR_MSEL(IP13_11_8
, TS_SCK0_D
, SEL_TSIF0_3
),
1235 PINMUX_IPSR_MSEL(IP13_11_8
, STP_ISCLK_0_D
, SEL_SSP1_0_3
),
1236 PINMUX_IPSR_MSEL(IP13_11_8
, RIF0_CLK_C
, SEL_DRIF0_2
),
1237 PINMUX_IPSR_MSEL(IP13_11_8
, RX5_B
, SEL_SCIF5_1
),
1239 PINMUX_IPSR_GPSR(IP13_15_12
, HRX0
),
1240 PINMUX_IPSR_MSEL(IP13_15_12
, MSIOF1_RXD_D
, SEL_MSIOF1_3
),
1241 PINMUX_IPSR_MSEL(IP13_15_12
, SSI_SDATA2_B
, SEL_SSI_1
),
1242 PINMUX_IPSR_MSEL(IP13_15_12
, TS_SDEN0_D
, SEL_TSIF0_3
),
1243 PINMUX_IPSR_MSEL(IP13_15_12
, STP_ISEN_0_D
, SEL_SSP1_0_3
),
1244 PINMUX_IPSR_MSEL(IP13_15_12
, RIF0_D0_C
, SEL_DRIF0_2
),
1246 PINMUX_IPSR_GPSR(IP13_19_16
, HTX0
),
1247 PINMUX_IPSR_MSEL(IP13_19_16
, MSIOF1_TXD_D
, SEL_MSIOF1_3
),
1248 PINMUX_IPSR_MSEL(IP13_19_16
, SSI_SDATA9_B
, SEL_SSI_1
),
1249 PINMUX_IPSR_MSEL(IP13_19_16
, TS_SDAT0_D
, SEL_TSIF0_3
),
1250 PINMUX_IPSR_MSEL(IP13_19_16
, STP_ISD_0_D
, SEL_SSP1_0_3
),
1251 PINMUX_IPSR_MSEL(IP13_19_16
, RIF0_D1_C
, SEL_DRIF0_2
),
1253 PINMUX_IPSR_GPSR(IP13_23_20
, HCTS0_N
),
1254 PINMUX_IPSR_MSEL(IP13_23_20
, RX2_B
, SEL_SCIF2_1
),
1255 PINMUX_IPSR_MSEL(IP13_23_20
, MSIOF1_SYNC_D
, SEL_MSIOF1_3
),
1256 PINMUX_IPSR_MSEL(IP13_23_20
, SSI_SCK9_A
, SEL_SSI_0
),
1257 PINMUX_IPSR_MSEL(IP13_23_20
, TS_SPSYNC0_D
, SEL_TSIF0_3
),
1258 PINMUX_IPSR_MSEL(IP13_23_20
, STP_ISSYNC_0_D
, SEL_SSP1_0_3
),
1259 PINMUX_IPSR_MSEL(IP13_23_20
, RIF0_SYNC_C
, SEL_DRIF0_2
),
1260 PINMUX_IPSR_GPSR(IP13_23_20
, AUDIO_CLKOUT1_A
),
1262 PINMUX_IPSR_GPSR(IP13_27_24
, HRTS0_N
),
1263 PINMUX_IPSR_MSEL(IP13_27_24
, TX2_B
, SEL_SCIF2_1
),
1264 PINMUX_IPSR_MSEL(IP13_27_24
, MSIOF1_SS1_D
, SEL_MSIOF1_3
),
1265 PINMUX_IPSR_MSEL(IP13_27_24
, SSI_WS9_A
, SEL_SSI_0
),
1266 PINMUX_IPSR_MSEL(IP13_27_24
, STP_IVCXO27_0_D
, SEL_SSP1_0_3
),
1267 PINMUX_IPSR_MSEL(IP13_27_24
, BPFCLK_A
, SEL_FM_0
),
1268 PINMUX_IPSR_GPSR(IP13_27_24
, AUDIO_CLKOUT2_A
),
1270 PINMUX_IPSR_GPSR(IP13_31_28
, MSIOF0_SYNC
),
1271 PINMUX_IPSR_GPSR(IP13_31_28
, AUDIO_CLKOUT_A
),
1272 PINMUX_IPSR_MSEL(IP13_31_28
, TX5_B
, SEL_SCIF5_1
),
1273 PINMUX_IPSR_MSEL(IP13_31_28
, BPFCLK_D
, SEL_FM_3
),
1276 PINMUX_IPSR_GPSR(IP14_3_0
, MSIOF0_SS1
),
1277 PINMUX_IPSR_MSEL(IP14_3_0
, RX5_A
, SEL_SCIF5_0
),
1278 PINMUX_IPSR_MSEL(IP14_3_0
, NFWP_N_A
, SEL_NDF_0
),
1279 PINMUX_IPSR_MSEL(IP14_3_0
, AUDIO_CLKA_C
, SEL_ADG_A_2
),
1280 PINMUX_IPSR_MSEL(IP14_3_0
, SSI_SCK2_A
, SEL_SSI_0
),
1281 PINMUX_IPSR_MSEL(IP14_3_0
, STP_IVCXO27_0_C
, SEL_SSP1_0_2
),
1282 PINMUX_IPSR_GPSR(IP14_3_0
, AUDIO_CLKOUT3_A
),
1283 PINMUX_IPSR_MSEL(IP14_3_0
, TCLK1_B
, SEL_TIMER_TMU_1
),
1285 PINMUX_IPSR_GPSR(IP14_7_4
, MSIOF0_SS2
),
1286 PINMUX_IPSR_MSEL(IP14_7_4
, TX5_A
, SEL_SCIF5_0
),
1287 PINMUX_IPSR_MSEL(IP14_7_4
, MSIOF1_SS2_D
, SEL_MSIOF1_3
),
1288 PINMUX_IPSR_MSEL(IP14_7_4
, AUDIO_CLKC_A
, SEL_ADG_C_0
),
1289 PINMUX_IPSR_MSEL(IP14_7_4
, SSI_WS2_A
, SEL_SSI_0
),
1290 PINMUX_IPSR_MSEL(IP14_7_4
, STP_OPWM_0_D
, SEL_SSP1_0_3
),
1291 PINMUX_IPSR_GPSR(IP14_7_4
, AUDIO_CLKOUT_D
),
1292 PINMUX_IPSR_MSEL(IP14_7_4
, SPEEDIN_B
, SEL_SPEED_PULSE_1
),
1294 PINMUX_IPSR_GPSR(IP14_11_8
, MLB_CLK
),
1295 PINMUX_IPSR_MSEL(IP14_11_8
, MSIOF1_SCK_F
, SEL_MSIOF1_5
),
1296 PINMUX_IPSR_MSEL(IP14_11_8
, SCL1_B
, SEL_I2C1_1
),
1298 PINMUX_IPSR_GPSR(IP14_15_12
, MLB_SIG
),
1299 PINMUX_IPSR_MSEL(IP14_15_12
, RX1_B
, SEL_SCIF1_1
),
1300 PINMUX_IPSR_MSEL(IP14_15_12
, MSIOF1_SYNC_F
, SEL_MSIOF1_5
),
1301 PINMUX_IPSR_MSEL(IP14_15_12
, SDA1_B
, SEL_I2C1_1
),
1303 PINMUX_IPSR_GPSR(IP14_19_16
, MLB_DAT
),
1304 PINMUX_IPSR_MSEL(IP14_19_16
, TX1_B
, SEL_SCIF1_1
),
1305 PINMUX_IPSR_MSEL(IP14_19_16
, MSIOF1_RXD_F
, SEL_MSIOF1_5
),
1307 PINMUX_IPSR_GPSR(IP14_23_20
, SSI_SCK0129
),
1308 PINMUX_IPSR_MSEL(IP14_23_20
, MSIOF1_TXD_F
, SEL_MSIOF1_5
),
1310 PINMUX_IPSR_GPSR(IP14_27_24
, SSI_WS0129
),
1311 PINMUX_IPSR_MSEL(IP14_27_24
, MSIOF1_SS1_F
, SEL_MSIOF1_5
),
1313 PINMUX_IPSR_GPSR(IP14_31_28
, SSI_SDATA0
),
1314 PINMUX_IPSR_MSEL(IP14_31_28
, MSIOF1_SS2_F
, SEL_MSIOF1_5
),
1317 PINMUX_IPSR_MSEL(IP15_3_0
, SSI_SDATA1_A
, SEL_SSI_0
),
1319 PINMUX_IPSR_MSEL(IP15_7_4
, SSI_SDATA2_A
, SEL_SSI_0
),
1320 PINMUX_IPSR_MSEL(IP15_7_4
, SSI_SCK1_B
, SEL_SSI_1
),
1322 PINMUX_IPSR_GPSR(IP15_11_8
, SSI_SCK34
),
1323 PINMUX_IPSR_MSEL(IP15_11_8
, MSIOF1_SS1_A
, SEL_MSIOF1_0
),
1324 PINMUX_IPSR_MSEL(IP15_11_8
, STP_OPWM_0_A
, SEL_SSP1_0_0
),
1326 PINMUX_IPSR_GPSR(IP15_15_12
, SSI_WS34
),
1327 PINMUX_IPSR_MSEL(IP15_15_12
, HCTS2_N_A
, SEL_HSCIF2_0
),
1328 PINMUX_IPSR_MSEL(IP15_15_12
, MSIOF1_SS2_A
, SEL_MSIOF1_0
),
1329 PINMUX_IPSR_MSEL(IP15_15_12
, STP_IVCXO27_0_A
, SEL_SSP1_0_0
),
1331 PINMUX_IPSR_GPSR(IP15_19_16
, SSI_SDATA3
),
1332 PINMUX_IPSR_MSEL(IP15_19_16
, HRTS2_N_A
, SEL_HSCIF2_0
),
1333 PINMUX_IPSR_MSEL(IP15_19_16
, MSIOF1_TXD_A
, SEL_MSIOF1_0
),
1334 PINMUX_IPSR_MSEL(IP15_19_16
, TS_SCK0_A
, SEL_TSIF0_0
),
1335 PINMUX_IPSR_MSEL(IP15_19_16
, STP_ISCLK_0_A
, SEL_SSP1_0_0
),
1336 PINMUX_IPSR_MSEL(IP15_19_16
, RIF0_D1_A
, SEL_DRIF0_0
),
1337 PINMUX_IPSR_MSEL(IP15_19_16
, RIF2_D0_A
, SEL_DRIF2_0
),
1339 PINMUX_IPSR_GPSR(IP15_23_20
, SSI_SCK4
),
1340 PINMUX_IPSR_MSEL(IP15_23_20
, HRX2_A
, SEL_HSCIF2_0
),
1341 PINMUX_IPSR_MSEL(IP15_23_20
, MSIOF1_SCK_A
, SEL_MSIOF1_0
),
1342 PINMUX_IPSR_MSEL(IP15_23_20
, TS_SDAT0_A
, SEL_TSIF0_0
),
1343 PINMUX_IPSR_MSEL(IP15_23_20
, STP_ISD_0_A
, SEL_SSP1_0_0
),
1344 PINMUX_IPSR_MSEL(IP15_23_20
, RIF0_CLK_A
, SEL_DRIF0_0
),
1345 PINMUX_IPSR_MSEL(IP15_23_20
, RIF2_CLK_A
, SEL_DRIF2_0
),
1347 PINMUX_IPSR_GPSR(IP15_27_24
, SSI_WS4
),
1348 PINMUX_IPSR_MSEL(IP15_27_24
, HTX2_A
, SEL_HSCIF2_0
),
1349 PINMUX_IPSR_MSEL(IP15_27_24
, MSIOF1_SYNC_A
, SEL_MSIOF1_0
),
1350 PINMUX_IPSR_MSEL(IP15_27_24
, TS_SDEN0_A
, SEL_TSIF0_0
),
1351 PINMUX_IPSR_MSEL(IP15_27_24
, STP_ISEN_0_A
, SEL_SSP1_0_0
),
1352 PINMUX_IPSR_MSEL(IP15_27_24
, RIF0_SYNC_A
, SEL_DRIF0_0
),
1353 PINMUX_IPSR_MSEL(IP15_27_24
, RIF2_SYNC_A
, SEL_DRIF2_0
),
1355 PINMUX_IPSR_GPSR(IP15_31_28
, SSI_SDATA4
),
1356 PINMUX_IPSR_MSEL(IP15_31_28
, HSCK2_A
, SEL_HSCIF2_0
),
1357 PINMUX_IPSR_MSEL(IP15_31_28
, MSIOF1_RXD_A
, SEL_MSIOF1_0
),
1358 PINMUX_IPSR_MSEL(IP15_31_28
, TS_SPSYNC0_A
, SEL_TSIF0_0
),
1359 PINMUX_IPSR_MSEL(IP15_31_28
, STP_ISSYNC_0_A
, SEL_SSP1_0_0
),
1360 PINMUX_IPSR_MSEL(IP15_31_28
, RIF0_D0_A
, SEL_DRIF0_0
),
1361 PINMUX_IPSR_MSEL(IP15_31_28
, RIF2_D1_A
, SEL_DRIF2_0
),
1364 PINMUX_IPSR_GPSR(IP16_3_0
, SSI_SCK6
),
1365 PINMUX_IPSR_MSEL(IP16_3_0
, SIM0_RST_D
, SEL_SIMCARD_3
),
1367 PINMUX_IPSR_GPSR(IP16_7_4
, SSI_WS6
),
1368 PINMUX_IPSR_MSEL(IP16_7_4
, SIM0_D_D
, SEL_SIMCARD_3
),
1370 PINMUX_IPSR_GPSR(IP16_11_8
, SSI_SDATA6
),
1371 PINMUX_IPSR_MSEL(IP16_11_8
, SIM0_CLK_D
, SEL_SIMCARD_3
),
1373 PINMUX_IPSR_GPSR(IP16_15_12
, SSI_SCK78
),
1374 PINMUX_IPSR_MSEL(IP16_15_12
, HRX2_B
, SEL_HSCIF2_1
),
1375 PINMUX_IPSR_MSEL(IP16_15_12
, MSIOF1_SCK_C
, SEL_MSIOF1_2
),
1376 PINMUX_IPSR_MSEL(IP16_15_12
, TS_SCK1_A
, SEL_TSIF1_0
),
1377 PINMUX_IPSR_MSEL(IP16_15_12
, STP_ISCLK_1_A
, SEL_SSP1_1_0
),
1378 PINMUX_IPSR_MSEL(IP16_15_12
, RIF1_CLK_A
, SEL_DRIF1_0
),
1379 PINMUX_IPSR_MSEL(IP16_15_12
, RIF3_CLK_A
, SEL_DRIF3_0
),
1381 PINMUX_IPSR_GPSR(IP16_19_16
, SSI_WS78
),
1382 PINMUX_IPSR_MSEL(IP16_19_16
, HTX2_B
, SEL_HSCIF2_1
),
1383 PINMUX_IPSR_MSEL(IP16_19_16
, MSIOF1_SYNC_C
, SEL_MSIOF1_2
),
1384 PINMUX_IPSR_MSEL(IP16_19_16
, TS_SDAT1_A
, SEL_TSIF1_0
),
1385 PINMUX_IPSR_MSEL(IP16_19_16
, STP_ISD_1_A
, SEL_SSP1_1_0
),
1386 PINMUX_IPSR_MSEL(IP16_19_16
, RIF1_SYNC_A
, SEL_DRIF1_0
),
1387 PINMUX_IPSR_MSEL(IP16_19_16
, RIF3_SYNC_A
, SEL_DRIF3_0
),
1389 PINMUX_IPSR_GPSR(IP16_23_20
, SSI_SDATA7
),
1390 PINMUX_IPSR_MSEL(IP16_23_20
, HCTS2_N_B
, SEL_HSCIF2_1
),
1391 PINMUX_IPSR_MSEL(IP16_23_20
, MSIOF1_RXD_C
, SEL_MSIOF1_2
),
1392 PINMUX_IPSR_MSEL(IP16_23_20
, TS_SDEN1_A
, SEL_TSIF1_0
),
1393 PINMUX_IPSR_MSEL(IP16_23_20
, STP_ISEN_1_A
, SEL_SSP1_1_0
),
1394 PINMUX_IPSR_MSEL(IP16_23_20
, RIF1_D0_A
, SEL_DRIF1_0
),
1395 PINMUX_IPSR_MSEL(IP16_23_20
, RIF3_D0_A
, SEL_DRIF3_0
),
1396 PINMUX_IPSR_MSEL(IP16_23_20
, TCLK2_A
, SEL_TIMER_TMU_0
),
1398 PINMUX_IPSR_GPSR(IP16_27_24
, SSI_SDATA8
),
1399 PINMUX_IPSR_MSEL(IP16_27_24
, HRTS2_N_B
, SEL_HSCIF2_1
),
1400 PINMUX_IPSR_MSEL(IP16_27_24
, MSIOF1_TXD_C
, SEL_MSIOF1_2
),
1401 PINMUX_IPSR_MSEL(IP16_27_24
, TS_SPSYNC1_A
, SEL_TSIF1_0
),
1402 PINMUX_IPSR_MSEL(IP16_27_24
, STP_ISSYNC_1_A
, SEL_SSP1_1_0
),
1403 PINMUX_IPSR_MSEL(IP16_27_24
, RIF1_D1_A
, SEL_DRIF1_0
),
1404 PINMUX_IPSR_MSEL(IP16_27_24
, RIF3_D1_A
, SEL_DRIF3_0
),
1406 PINMUX_IPSR_MSEL(IP16_31_28
, SSI_SDATA9_A
, SEL_SSI_0
),
1407 PINMUX_IPSR_MSEL(IP16_31_28
, HSCK2_B
, SEL_HSCIF2_1
),
1408 PINMUX_IPSR_MSEL(IP16_31_28
, MSIOF1_SS1_C
, SEL_MSIOF1_2
),
1409 PINMUX_IPSR_MSEL(IP16_31_28
, HSCK1_A
, SEL_HSCIF1_0
),
1410 PINMUX_IPSR_MSEL(IP16_31_28
, SSI_WS1_B
, SEL_SSI_1
),
1411 PINMUX_IPSR_GPSR(IP16_31_28
, SCK1
),
1412 PINMUX_IPSR_MSEL(IP16_31_28
, STP_IVCXO27_1_A
, SEL_SSP1_1_0
),
1413 PINMUX_IPSR_GPSR(IP16_31_28
, SCK5_A
),
1416 PINMUX_IPSR_MSEL(IP17_3_0
, AUDIO_CLKA_A
, SEL_ADG_A_0
),
1417 PINMUX_IPSR_GPSR(IP17_3_0
, CC5_OSCOUT
),
1419 PINMUX_IPSR_MSEL(IP17_7_4
, AUDIO_CLKB_B
, SEL_ADG_B_1
),
1420 PINMUX_IPSR_MSEL(IP17_7_4
, SCIF_CLK_A
, SEL_SCIF1_0
),
1421 PINMUX_IPSR_MSEL(IP17_7_4
, STP_IVCXO27_1_D
, SEL_SSP1_1_3
),
1422 PINMUX_IPSR_MSEL(IP17_7_4
, REMOCON_A
, SEL_REMOCON_0
),
1423 PINMUX_IPSR_MSEL(IP17_7_4
, TCLK1_A
, SEL_TIMER_TMU_0
),
1425 PINMUX_IPSR_GPSR(IP17_11_8
, USB0_PWEN
),
1426 PINMUX_IPSR_MSEL(IP17_11_8
, SIM0_RST_C
, SEL_SIMCARD_2
),
1427 PINMUX_IPSR_MSEL(IP17_11_8
, TS_SCK1_D
, SEL_TSIF1_3
),
1428 PINMUX_IPSR_MSEL(IP17_11_8
, STP_ISCLK_1_D
, SEL_SSP1_1_3
),
1429 PINMUX_IPSR_MSEL(IP17_11_8
, BPFCLK_B
, SEL_FM_1
),
1430 PINMUX_IPSR_MSEL(IP17_11_8
, RIF3_CLK_B
, SEL_DRIF3_1
),
1431 PINMUX_IPSR_MSEL(IP17_11_8
, HSCK2_C
, SEL_HSCIF2_2
),
1433 PINMUX_IPSR_GPSR(IP17_15_12
, USB0_OVC
),
1434 PINMUX_IPSR_MSEL(IP17_15_12
, SIM0_D_C
, SEL_SIMCARD_2
),
1435 PINMUX_IPSR_MSEL(IP17_15_12
, TS_SDAT1_D
, SEL_TSIF1_3
),
1436 PINMUX_IPSR_MSEL(IP17_15_12
, STP_ISD_1_D
, SEL_SSP1_1_3
),
1437 PINMUX_IPSR_MSEL(IP17_15_12
, RIF3_SYNC_B
, SEL_DRIF3_1
),
1438 PINMUX_IPSR_MSEL(IP17_15_12
, HRX2_C
, SEL_HSCIF2_2
),
1440 PINMUX_IPSR_GPSR(IP17_19_16
, USB1_PWEN
),
1441 PINMUX_IPSR_MSEL(IP17_19_16
, SIM0_CLK_C
, SEL_SIMCARD_2
),
1442 PINMUX_IPSR_MSEL(IP17_19_16
, SSI_SCK1_A
, SEL_SSI_0
),
1443 PINMUX_IPSR_MSEL(IP17_19_16
, TS_SCK0_E
, SEL_TSIF0_4
),
1444 PINMUX_IPSR_MSEL(IP17_19_16
, STP_ISCLK_0_E
, SEL_SSP1_0_4
),
1445 PINMUX_IPSR_MSEL(IP17_19_16
, FMCLK_B
, SEL_FM_1
),
1446 PINMUX_IPSR_MSEL(IP17_19_16
, RIF2_CLK_B
, SEL_DRIF2_1
),
1447 PINMUX_IPSR_MSEL(IP17_19_16
, SPEEDIN_A
, SEL_SPEED_PULSE_0
),
1448 PINMUX_IPSR_MSEL(IP17_19_16
, HTX2_C
, SEL_HSCIF2_2
),
1450 PINMUX_IPSR_GPSR(IP17_23_20
, USB1_OVC
),
1451 PINMUX_IPSR_MSEL(IP17_23_20
, MSIOF1_SS2_C
, SEL_MSIOF1_2
),
1452 PINMUX_IPSR_MSEL(IP17_23_20
, SSI_WS1_A
, SEL_SSI_0
),
1453 PINMUX_IPSR_MSEL(IP17_23_20
, TS_SDAT0_E
, SEL_TSIF0_4
),
1454 PINMUX_IPSR_MSEL(IP17_23_20
, STP_ISD_0_E
, SEL_SSP1_0_4
),
1455 PINMUX_IPSR_MSEL(IP17_23_20
, FMIN_B
, SEL_FM_1
),
1456 PINMUX_IPSR_MSEL(IP17_23_20
, RIF2_SYNC_B
, SEL_DRIF2_1
),
1457 PINMUX_IPSR_MSEL(IP17_23_20
, REMOCON_B
, SEL_REMOCON_1
),
1458 PINMUX_IPSR_MSEL(IP17_23_20
, HCTS2_N_C
, SEL_HSCIF2_2
),
1460 PINMUX_IPSR_GPSR(IP17_27_24
, USB30_PWEN
),
1461 PINMUX_IPSR_GPSR(IP17_27_24
, AUDIO_CLKOUT_B
),
1462 PINMUX_IPSR_MSEL(IP17_27_24
, SSI_SCK2_B
, SEL_SSI_1
),
1463 PINMUX_IPSR_MSEL(IP17_27_24
, TS_SDEN1_D
, SEL_TSIF1_3
),
1464 PINMUX_IPSR_MSEL(IP17_27_24
, STP_ISEN_1_D
, SEL_SSP1_1_2
),
1465 PINMUX_IPSR_MSEL(IP17_27_24
, STP_OPWM_0_E
, SEL_SSP1_0_4
),
1466 PINMUX_IPSR_MSEL(IP17_27_24
, RIF3_D0_B
, SEL_DRIF3_1
),
1467 PINMUX_IPSR_MSEL(IP17_27_24
, TCLK2_B
, SEL_TIMER_TMU_1
),
1468 PINMUX_IPSR_GPSR(IP17_27_24
, TPU0TO0
),
1469 PINMUX_IPSR_MSEL(IP17_27_24
, BPFCLK_C
, SEL_FM_2
),
1470 PINMUX_IPSR_MSEL(IP17_27_24
, HRTS2_N_C
, SEL_HSCIF2_2
),
1472 PINMUX_IPSR_GPSR(IP17_31_28
, USB30_OVC
),
1473 PINMUX_IPSR_GPSR(IP17_31_28
, AUDIO_CLKOUT1_B
),
1474 PINMUX_IPSR_MSEL(IP17_31_28
, SSI_WS2_B
, SEL_SSI_1
),
1475 PINMUX_IPSR_MSEL(IP17_31_28
, TS_SPSYNC1_D
, SEL_TSIF1_3
),
1476 PINMUX_IPSR_MSEL(IP17_31_28
, STP_ISSYNC_1_D
, SEL_SSP1_1_3
),
1477 PINMUX_IPSR_MSEL(IP17_31_28
, STP_IVCXO27_0_E
, SEL_SSP1_0_4
),
1478 PINMUX_IPSR_MSEL(IP17_31_28
, RIF3_D1_B
, SEL_DRIF3_1
),
1479 PINMUX_IPSR_MSEL(IP17_31_28
, FSO_TOE_B
, SEL_FSO_1
),
1480 PINMUX_IPSR_GPSR(IP17_31_28
, TPU0TO1
),
1483 PINMUX_IPSR_GPSR(IP18_3_0
, GP6_30
),
1484 PINMUX_IPSR_GPSR(IP18_3_0
, AUDIO_CLKOUT2_B
),
1485 PINMUX_IPSR_MSEL(IP18_3_0
, SSI_SCK9_B
, SEL_SSI_1
),
1486 PINMUX_IPSR_MSEL(IP18_3_0
, TS_SDEN0_E
, SEL_TSIF0_4
),
1487 PINMUX_IPSR_MSEL(IP18_3_0
, STP_ISEN_0_E
, SEL_SSP1_0_4
),
1488 PINMUX_IPSR_MSEL(IP18_3_0
, RIF2_D0_B
, SEL_DRIF2_1
),
1489 PINMUX_IPSR_GPSR(IP18_3_0
, TPU0TO2
),
1490 PINMUX_IPSR_MSEL(IP18_3_0
, FSO_CFE_0_A
, SEL_FSO_0
),
1491 PINMUX_IPSR_MSEL(IP18_3_0
, FMCLK_C
, SEL_FM_2
),
1492 PINMUX_IPSR_MSEL(IP18_3_0
, FMCLK_D
, SEL_FM_3
),
1494 PINMUX_IPSR_GPSR(IP18_7_4
, GP6_31
),
1495 PINMUX_IPSR_GPSR(IP18_7_4
, AUDIO_CLKOUT3_B
),
1496 PINMUX_IPSR_MSEL(IP18_7_4
, SSI_WS9_B
, SEL_SSI_1
),
1497 PINMUX_IPSR_MSEL(IP18_7_4
, TS_SPSYNC0_E
, SEL_TSIF0_4
),
1498 PINMUX_IPSR_MSEL(IP18_7_4
, STP_ISSYNC_0_E
, SEL_SSP1_0_4
),
1499 PINMUX_IPSR_MSEL(IP18_7_4
, RIF2_D1_B
, SEL_DRIF2_1
),
1500 PINMUX_IPSR_GPSR(IP18_7_4
, TPU0TO3
),
1501 PINMUX_IPSR_MSEL(IP18_7_4
, FSO_CFE_1_A
, SEL_FSO_0
),
1502 PINMUX_IPSR_MSEL(IP18_7_4
, FMIN_C
, SEL_FM_2
),
1503 PINMUX_IPSR_MSEL(IP18_7_4
, FMIN_D
, SEL_FM_3
),
1506 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1
),
1507 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1
),
1508 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1
),
1511 * Static pins can not be muxed between different functions but
1512 * still needs a mark entry in the pinmux list. Add each static
1513 * pin to the list without an associated function. The sh-pfc
1514 * core will do the right thing and skip trying to mux then pin
1515 * while still applying configuration to it
1517 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1523 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1524 * Physical layout rows: A - AW, cols: 1 - 39.
1526 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1527 #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1528 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1530 static const struct sh_pfc_pin pinmux_pins
[] = {
1531 PINMUX_GPIO_GP_ALL(),
1534 * Pins not associated with a GPIO port.
1536 * The pin positions are different between different r8a7796
1537 * packages, all that is needed for the pfc driver is a unique
1538 * number for each pin. To this end use the pin layout from
1539 * R-Car M3SiP to calculate a unique number for each pin.
1541 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL
, CFG_FLAGS
),
1542 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO
, CFG_FLAGS
),
1543 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK
, CFG_FLAGS
),
1544 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0
, CFG_FLAGS
),
1545 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2
, CFG_FLAGS
),
1546 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL
, CFG_FLAGS
),
1547 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2
, CFG_FLAGS
),
1548 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0
, CFG_FLAGS
),
1549 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC
, CFG_FLAGS
),
1550 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1
, CFG_FLAGS
),
1551 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3
, CFG_FLAGS
),
1552 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3
, CFG_FLAGS
),
1553 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1
, CFG_FLAGS
),
1554 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC
, CFG_FLAGS
),
1555 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT
#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF
, CFG_FLAGS
),
1557 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK
, CFG_FLAGS
),
1558 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL
, CFG_FLAGS
),
1559 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP
#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET
#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK
, CFG_FLAGS
),
1562 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL
, CFG_FLAGS
),
1563 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2
, CFG_FLAGS
),
1564 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT
#, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1
, CFG_FLAGS
),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3
, CFG_FLAGS
),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3
, CFG_FLAGS
),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0
, CFG_FLAGS
),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0
, CFG_FLAGS
),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST
, CFG_FLAGS
),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR
, SH_PFC_PIN_CFG_PULL_UP
| SH_PFC_PIN_CFG_PULL_DOWN
),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2
, CFG_FLAGS
),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1
, CFG_FLAGS
),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0
, CFG_FLAGS
),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1
, CFG_FLAGS
),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2
, CFG_FLAGS
),
1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST
#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI
, SH_PFC_PIN_CFG_PULL_UP
| SH_PFC_PIN_CFG_PULL_DOWN
),
1579 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS
, CFG_FLAGS
),
1580 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK
, SH_PFC_PIN_CFG_PULL_UP
| SH_PFC_PIN_CFG_PULL_DOWN
),
1581 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO
, SH_PFC_PIN_CFG_DRIVE_STRENGTH
),
1582 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK
, CFG_FLAGS
),
1585 /* - EtherAVB --------------------------------------------------------------- */
1586 static const unsigned int avb_link_pins
[] = {
1590 static const unsigned int avb_link_mux
[] = {
1593 static const unsigned int avb_magic_pins
[] = {
1597 static const unsigned int avb_magic_mux
[] = {
1600 static const unsigned int avb_phy_int_pins
[] = {
1604 static const unsigned int avb_phy_int_mux
[] = {
1607 static const unsigned int avb_mdc_pins
[] = {
1611 static const unsigned int avb_mdc_mux
[] = {
1614 static const unsigned int avb_avtp_pps_pins
[] = {
1618 static const unsigned int avb_avtp_pps_mux
[] = {
1621 static const unsigned int avb_avtp_match_a_pins
[] = {
1622 /* AVB_AVTP_MATCH_A */
1625 static const unsigned int avb_avtp_match_a_mux
[] = {
1626 AVB_AVTP_MATCH_A_MARK
,
1628 static const unsigned int avb_avtp_capture_a_pins
[] = {
1629 /* AVB_AVTP_CAPTURE_A */
1632 static const unsigned int avb_avtp_capture_a_mux
[] = {
1633 AVB_AVTP_CAPTURE_A_MARK
,
1635 static const unsigned int avb_avtp_match_b_pins
[] = {
1636 /* AVB_AVTP_MATCH_B */
1639 static const unsigned int avb_avtp_match_b_mux
[] = {
1640 AVB_AVTP_MATCH_B_MARK
,
1642 static const unsigned int avb_avtp_capture_b_pins
[] = {
1643 /* AVB_AVTP_CAPTURE_B */
1646 static const unsigned int avb_avtp_capture_b_mux
[] = {
1647 AVB_AVTP_CAPTURE_B_MARK
,
1650 /* - CAN ------------------------------------------------------------------ */
1651 static const unsigned int can0_data_a_pins
[] = {
1653 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1655 static const unsigned int can0_data_a_mux
[] = {
1656 CAN0_TX_A_MARK
, CAN0_RX_A_MARK
,
1658 static const unsigned int can0_data_b_pins
[] = {
1660 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1662 static const unsigned int can0_data_b_mux
[] = {
1663 CAN0_TX_B_MARK
, CAN0_RX_B_MARK
,
1665 static const unsigned int can1_data_pins
[] = {
1667 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1669 static const unsigned int can1_data_mux
[] = {
1670 CAN1_TX_MARK
, CAN1_RX_MARK
,
1673 /* - CAN Clock -------------------------------------------------------------- */
1674 static const unsigned int can_clk_pins
[] = {
1678 static const unsigned int can_clk_mux
[] = {
1682 /* - CAN FD --------------------------------------------------------------- */
1683 static const unsigned int canfd0_data_a_pins
[] = {
1685 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1687 static const unsigned int canfd0_data_a_mux
[] = {
1688 CANFD0_TX_A_MARK
, CANFD0_RX_A_MARK
,
1690 static const unsigned int canfd0_data_b_pins
[] = {
1692 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1694 static const unsigned int canfd0_data_b_mux
[] = {
1695 CANFD0_TX_B_MARK
, CANFD0_RX_B_MARK
,
1697 static const unsigned int canfd1_data_pins
[] = {
1699 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1701 static const unsigned int canfd1_data_mux
[] = {
1702 CANFD1_TX_MARK
, CANFD1_RX_MARK
,
1705 /* - DRIF0 --------------------------------------------------------------- */
1706 static const unsigned int drif0_ctrl_a_pins
[] = {
1708 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1710 static const unsigned int drif0_ctrl_a_mux
[] = {
1711 RIF0_CLK_A_MARK
, RIF0_SYNC_A_MARK
,
1713 static const unsigned int drif0_data0_a_pins
[] = {
1717 static const unsigned int drif0_data0_a_mux
[] = {
1720 static const unsigned int drif0_data1_a_pins
[] = {
1724 static const unsigned int drif0_data1_a_mux
[] = {
1727 static const unsigned int drif0_ctrl_b_pins
[] = {
1729 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1731 static const unsigned int drif0_ctrl_b_mux
[] = {
1732 RIF0_CLK_B_MARK
, RIF0_SYNC_B_MARK
,
1734 static const unsigned int drif0_data0_b_pins
[] = {
1738 static const unsigned int drif0_data0_b_mux
[] = {
1741 static const unsigned int drif0_data1_b_pins
[] = {
1745 static const unsigned int drif0_data1_b_mux
[] = {
1748 static const unsigned int drif0_ctrl_c_pins
[] = {
1750 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1752 static const unsigned int drif0_ctrl_c_mux
[] = {
1753 RIF0_CLK_C_MARK
, RIF0_SYNC_C_MARK
,
1755 static const unsigned int drif0_data0_c_pins
[] = {
1759 static const unsigned int drif0_data0_c_mux
[] = {
1762 static const unsigned int drif0_data1_c_pins
[] = {
1766 static const unsigned int drif0_data1_c_mux
[] = {
1769 /* - DRIF1 --------------------------------------------------------------- */
1770 static const unsigned int drif1_ctrl_a_pins
[] = {
1772 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1774 static const unsigned int drif1_ctrl_a_mux
[] = {
1775 RIF1_CLK_A_MARK
, RIF1_SYNC_A_MARK
,
1777 static const unsigned int drif1_data0_a_pins
[] = {
1781 static const unsigned int drif1_data0_a_mux
[] = {
1784 static const unsigned int drif1_data1_a_pins
[] = {
1788 static const unsigned int drif1_data1_a_mux
[] = {
1791 static const unsigned int drif1_ctrl_b_pins
[] = {
1793 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1795 static const unsigned int drif1_ctrl_b_mux
[] = {
1796 RIF1_CLK_B_MARK
, RIF1_SYNC_B_MARK
,
1798 static const unsigned int drif1_data0_b_pins
[] = {
1802 static const unsigned int drif1_data0_b_mux
[] = {
1805 static const unsigned int drif1_data1_b_pins
[] = {
1809 static const unsigned int drif1_data1_b_mux
[] = {
1812 static const unsigned int drif1_ctrl_c_pins
[] = {
1814 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1816 static const unsigned int drif1_ctrl_c_mux
[] = {
1817 RIF1_CLK_C_MARK
, RIF1_SYNC_C_MARK
,
1819 static const unsigned int drif1_data0_c_pins
[] = {
1823 static const unsigned int drif1_data0_c_mux
[] = {
1826 static const unsigned int drif1_data1_c_pins
[] = {
1830 static const unsigned int drif1_data1_c_mux
[] = {
1833 /* - DRIF2 --------------------------------------------------------------- */
1834 static const unsigned int drif2_ctrl_a_pins
[] = {
1836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1838 static const unsigned int drif2_ctrl_a_mux
[] = {
1839 RIF2_CLK_A_MARK
, RIF2_SYNC_A_MARK
,
1841 static const unsigned int drif2_data0_a_pins
[] = {
1845 static const unsigned int drif2_data0_a_mux
[] = {
1848 static const unsigned int drif2_data1_a_pins
[] = {
1852 static const unsigned int drif2_data1_a_mux
[] = {
1855 static const unsigned int drif2_ctrl_b_pins
[] = {
1857 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1859 static const unsigned int drif2_ctrl_b_mux
[] = {
1860 RIF2_CLK_B_MARK
, RIF2_SYNC_B_MARK
,
1862 static const unsigned int drif2_data0_b_pins
[] = {
1866 static const unsigned int drif2_data0_b_mux
[] = {
1869 static const unsigned int drif2_data1_b_pins
[] = {
1873 static const unsigned int drif2_data1_b_mux
[] = {
1876 /* - DRIF3 --------------------------------------------------------------- */
1877 static const unsigned int drif3_ctrl_a_pins
[] = {
1879 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1881 static const unsigned int drif3_ctrl_a_mux
[] = {
1882 RIF3_CLK_A_MARK
, RIF3_SYNC_A_MARK
,
1884 static const unsigned int drif3_data0_a_pins
[] = {
1888 static const unsigned int drif3_data0_a_mux
[] = {
1891 static const unsigned int drif3_data1_a_pins
[] = {
1895 static const unsigned int drif3_data1_a_mux
[] = {
1898 static const unsigned int drif3_ctrl_b_pins
[] = {
1900 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1902 static const unsigned int drif3_ctrl_b_mux
[] = {
1903 RIF3_CLK_B_MARK
, RIF3_SYNC_B_MARK
,
1905 static const unsigned int drif3_data0_b_pins
[] = {
1909 static const unsigned int drif3_data0_b_mux
[] = {
1912 static const unsigned int drif3_data1_b_pins
[] = {
1916 static const unsigned int drif3_data1_b_mux
[] = {
1920 /* - DU --------------------------------------------------------------------- */
1921 static const unsigned int du_rgb666_pins
[] = {
1922 /* R[7:2], G[7:2], B[7:2] */
1923 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1924 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1925 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1926 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1927 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1928 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1930 static const unsigned int du_rgb666_mux
[] = {
1931 DU_DR7_MARK
, DU_DR6_MARK
, DU_DR5_MARK
, DU_DR4_MARK
,
1932 DU_DR3_MARK
, DU_DR2_MARK
,
1933 DU_DG7_MARK
, DU_DG6_MARK
, DU_DG5_MARK
, DU_DG4_MARK
,
1934 DU_DG3_MARK
, DU_DG2_MARK
,
1935 DU_DB7_MARK
, DU_DB6_MARK
, DU_DB5_MARK
, DU_DB4_MARK
,
1936 DU_DB3_MARK
, DU_DB2_MARK
,
1938 static const unsigned int du_rgb888_pins
[] = {
1939 /* R[7:0], G[7:0], B[7:0] */
1940 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1941 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1942 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1943 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1944 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1945 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1946 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1947 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1948 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1950 static const unsigned int du_rgb888_mux
[] = {
1951 DU_DR7_MARK
, DU_DR6_MARK
, DU_DR5_MARK
, DU_DR4_MARK
,
1952 DU_DR3_MARK
, DU_DR2_MARK
, DU_DR1_MARK
, DU_DR0_MARK
,
1953 DU_DG7_MARK
, DU_DG6_MARK
, DU_DG5_MARK
, DU_DG4_MARK
,
1954 DU_DG3_MARK
, DU_DG2_MARK
, DU_DG1_MARK
, DU_DG0_MARK
,
1955 DU_DB7_MARK
, DU_DB6_MARK
, DU_DB5_MARK
, DU_DB4_MARK
,
1956 DU_DB3_MARK
, DU_DB2_MARK
, DU_DB1_MARK
, DU_DB0_MARK
,
1958 static const unsigned int du_clk_out_0_pins
[] = {
1962 static const unsigned int du_clk_out_0_mux
[] = {
1965 static const unsigned int du_clk_out_1_pins
[] = {
1969 static const unsigned int du_clk_out_1_mux
[] = {
1972 static const unsigned int du_sync_pins
[] = {
1973 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1974 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1976 static const unsigned int du_sync_mux
[] = {
1977 DU_EXVSYNC_DU_VSYNC_MARK
, DU_EXHSYNC_DU_HSYNC_MARK
1979 static const unsigned int du_oddf_pins
[] = {
1980 /* EXDISP/EXODDF/EXCDE */
1983 static const unsigned int du_oddf_mux
[] = {
1984 DU_EXODDF_DU_ODDF_DISP_CDE_MARK
,
1986 static const unsigned int du_cde_pins
[] = {
1990 static const unsigned int du_cde_mux
[] = {
1993 static const unsigned int du_disp_pins
[] = {
1997 static const unsigned int du_disp_mux
[] = {
2001 /* - HSCIF0 ----------------------------------------------------------------- */
2002 static const unsigned int hscif0_data_pins
[] = {
2004 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2006 static const unsigned int hscif0_data_mux
[] = {
2007 HRX0_MARK
, HTX0_MARK
,
2009 static const unsigned int hscif0_clk_pins
[] = {
2013 static const unsigned int hscif0_clk_mux
[] = {
2016 static const unsigned int hscif0_ctrl_pins
[] = {
2018 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2020 static const unsigned int hscif0_ctrl_mux
[] = {
2021 HRTS0_N_MARK
, HCTS0_N_MARK
,
2023 /* - HSCIF1 ----------------------------------------------------------------- */
2024 static const unsigned int hscif1_data_a_pins
[] = {
2026 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2028 static const unsigned int hscif1_data_a_mux
[] = {
2029 HRX1_A_MARK
, HTX1_A_MARK
,
2031 static const unsigned int hscif1_clk_a_pins
[] = {
2035 static const unsigned int hscif1_clk_a_mux
[] = {
2038 static const unsigned int hscif1_ctrl_a_pins
[] = {
2040 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2042 static const unsigned int hscif1_ctrl_a_mux
[] = {
2043 HRTS1_N_A_MARK
, HCTS1_N_A_MARK
,
2046 static const unsigned int hscif1_data_b_pins
[] = {
2048 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2050 static const unsigned int hscif1_data_b_mux
[] = {
2051 HRX1_B_MARK
, HTX1_B_MARK
,
2053 static const unsigned int hscif1_clk_b_pins
[] = {
2057 static const unsigned int hscif1_clk_b_mux
[] = {
2060 static const unsigned int hscif1_ctrl_b_pins
[] = {
2062 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2064 static const unsigned int hscif1_ctrl_b_mux
[] = {
2065 HRTS1_N_B_MARK
, HCTS1_N_B_MARK
,
2067 /* - HSCIF2 ----------------------------------------------------------------- */
2068 static const unsigned int hscif2_data_a_pins
[] = {
2070 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2072 static const unsigned int hscif2_data_a_mux
[] = {
2073 HRX2_A_MARK
, HTX2_A_MARK
,
2075 static const unsigned int hscif2_clk_a_pins
[] = {
2079 static const unsigned int hscif2_clk_a_mux
[] = {
2082 static const unsigned int hscif2_ctrl_a_pins
[] = {
2084 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2086 static const unsigned int hscif2_ctrl_a_mux
[] = {
2087 HRTS2_N_A_MARK
, HCTS2_N_A_MARK
,
2090 static const unsigned int hscif2_data_b_pins
[] = {
2092 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2094 static const unsigned int hscif2_data_b_mux
[] = {
2095 HRX2_B_MARK
, HTX2_B_MARK
,
2097 static const unsigned int hscif2_clk_b_pins
[] = {
2101 static const unsigned int hscif2_clk_b_mux
[] = {
2104 static const unsigned int hscif2_ctrl_b_pins
[] = {
2106 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2108 static const unsigned int hscif2_ctrl_b_mux
[] = {
2109 HRTS2_N_B_MARK
, HCTS2_N_B_MARK
,
2112 static const unsigned int hscif2_data_c_pins
[] = {
2114 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2116 static const unsigned int hscif2_data_c_mux
[] = {
2117 HRX2_C_MARK
, HTX2_C_MARK
,
2119 static const unsigned int hscif2_clk_c_pins
[] = {
2123 static const unsigned int hscif2_clk_c_mux
[] = {
2126 static const unsigned int hscif2_ctrl_c_pins
[] = {
2128 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2130 static const unsigned int hscif2_ctrl_c_mux
[] = {
2131 HRTS2_N_C_MARK
, HCTS2_N_C_MARK
,
2133 /* - HSCIF3 ----------------------------------------------------------------- */
2134 static const unsigned int hscif3_data_a_pins
[] = {
2136 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2138 static const unsigned int hscif3_data_a_mux
[] = {
2139 HRX3_A_MARK
, HTX3_A_MARK
,
2141 static const unsigned int hscif3_clk_pins
[] = {
2145 static const unsigned int hscif3_clk_mux
[] = {
2148 static const unsigned int hscif3_ctrl_pins
[] = {
2150 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2152 static const unsigned int hscif3_ctrl_mux
[] = {
2153 HRTS3_N_MARK
, HCTS3_N_MARK
,
2156 static const unsigned int hscif3_data_b_pins
[] = {
2158 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2160 static const unsigned int hscif3_data_b_mux
[] = {
2161 HRX3_B_MARK
, HTX3_B_MARK
,
2163 static const unsigned int hscif3_data_c_pins
[] = {
2165 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2167 static const unsigned int hscif3_data_c_mux
[] = {
2168 HRX3_C_MARK
, HTX3_C_MARK
,
2170 static const unsigned int hscif3_data_d_pins
[] = {
2172 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2174 static const unsigned int hscif3_data_d_mux
[] = {
2175 HRX3_D_MARK
, HTX3_D_MARK
,
2177 /* - HSCIF4 ----------------------------------------------------------------- */
2178 static const unsigned int hscif4_data_a_pins
[] = {
2180 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2182 static const unsigned int hscif4_data_a_mux
[] = {
2183 HRX4_A_MARK
, HTX4_A_MARK
,
2185 static const unsigned int hscif4_clk_pins
[] = {
2189 static const unsigned int hscif4_clk_mux
[] = {
2192 static const unsigned int hscif4_ctrl_pins
[] = {
2194 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2196 static const unsigned int hscif4_ctrl_mux
[] = {
2197 HRTS4_N_MARK
, HCTS4_N_MARK
,
2200 static const unsigned int hscif4_data_b_pins
[] = {
2202 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2204 static const unsigned int hscif4_data_b_mux
[] = {
2205 HRX4_B_MARK
, HTX4_B_MARK
,
2208 /* - I2C -------------------------------------------------------------------- */
2209 static const unsigned int i2c1_a_pins
[] = {
2211 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2213 static const unsigned int i2c1_a_mux
[] = {
2214 SDA1_A_MARK
, SCL1_A_MARK
,
2216 static const unsigned int i2c1_b_pins
[] = {
2218 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2220 static const unsigned int i2c1_b_mux
[] = {
2221 SDA1_B_MARK
, SCL1_B_MARK
,
2223 static const unsigned int i2c2_a_pins
[] = {
2225 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2227 static const unsigned int i2c2_a_mux
[] = {
2228 SDA2_A_MARK
, SCL2_A_MARK
,
2230 static const unsigned int i2c2_b_pins
[] = {
2232 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2234 static const unsigned int i2c2_b_mux
[] = {
2235 SDA2_B_MARK
, SCL2_B_MARK
,
2237 static const unsigned int i2c6_a_pins
[] = {
2239 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2241 static const unsigned int i2c6_a_mux
[] = {
2242 SDA6_A_MARK
, SCL6_A_MARK
,
2244 static const unsigned int i2c6_b_pins
[] = {
2246 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2248 static const unsigned int i2c6_b_mux
[] = {
2249 SDA6_B_MARK
, SCL6_B_MARK
,
2251 static const unsigned int i2c6_c_pins
[] = {
2253 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2255 static const unsigned int i2c6_c_mux
[] = {
2256 SDA6_C_MARK
, SCL6_C_MARK
,
2259 /* - MSIOF0 ----------------------------------------------------------------- */
2260 static const unsigned int msiof0_clk_pins
[] = {
2264 static const unsigned int msiof0_clk_mux
[] = {
2267 static const unsigned int msiof0_sync_pins
[] = {
2271 static const unsigned int msiof0_sync_mux
[] = {
2274 static const unsigned int msiof0_ss1_pins
[] = {
2278 static const unsigned int msiof0_ss1_mux
[] = {
2281 static const unsigned int msiof0_ss2_pins
[] = {
2285 static const unsigned int msiof0_ss2_mux
[] = {
2288 static const unsigned int msiof0_txd_pins
[] = {
2292 static const unsigned int msiof0_txd_mux
[] = {
2295 static const unsigned int msiof0_rxd_pins
[] = {
2299 static const unsigned int msiof0_rxd_mux
[] = {
2302 /* - MSIOF1 ----------------------------------------------------------------- */
2303 static const unsigned int msiof1_clk_a_pins
[] = {
2307 static const unsigned int msiof1_clk_a_mux
[] = {
2310 static const unsigned int msiof1_sync_a_pins
[] = {
2314 static const unsigned int msiof1_sync_a_mux
[] = {
2317 static const unsigned int msiof1_ss1_a_pins
[] = {
2321 static const unsigned int msiof1_ss1_a_mux
[] = {
2324 static const unsigned int msiof1_ss2_a_pins
[] = {
2328 static const unsigned int msiof1_ss2_a_mux
[] = {
2331 static const unsigned int msiof1_txd_a_pins
[] = {
2335 static const unsigned int msiof1_txd_a_mux
[] = {
2338 static const unsigned int msiof1_rxd_a_pins
[] = {
2342 static const unsigned int msiof1_rxd_a_mux
[] = {
2345 static const unsigned int msiof1_clk_b_pins
[] = {
2349 static const unsigned int msiof1_clk_b_mux
[] = {
2352 static const unsigned int msiof1_sync_b_pins
[] = {
2356 static const unsigned int msiof1_sync_b_mux
[] = {
2359 static const unsigned int msiof1_ss1_b_pins
[] = {
2363 static const unsigned int msiof1_ss1_b_mux
[] = {
2366 static const unsigned int msiof1_ss2_b_pins
[] = {
2370 static const unsigned int msiof1_ss2_b_mux
[] = {
2373 static const unsigned int msiof1_txd_b_pins
[] = {
2377 static const unsigned int msiof1_txd_b_mux
[] = {
2380 static const unsigned int msiof1_rxd_b_pins
[] = {
2384 static const unsigned int msiof1_rxd_b_mux
[] = {
2387 static const unsigned int msiof1_clk_c_pins
[] = {
2391 static const unsigned int msiof1_clk_c_mux
[] = {
2394 static const unsigned int msiof1_sync_c_pins
[] = {
2398 static const unsigned int msiof1_sync_c_mux
[] = {
2401 static const unsigned int msiof1_ss1_c_pins
[] = {
2405 static const unsigned int msiof1_ss1_c_mux
[] = {
2408 static const unsigned int msiof1_ss2_c_pins
[] = {
2412 static const unsigned int msiof1_ss2_c_mux
[] = {
2415 static const unsigned int msiof1_txd_c_pins
[] = {
2419 static const unsigned int msiof1_txd_c_mux
[] = {
2422 static const unsigned int msiof1_rxd_c_pins
[] = {
2426 static const unsigned int msiof1_rxd_c_mux
[] = {
2429 static const unsigned int msiof1_clk_d_pins
[] = {
2433 static const unsigned int msiof1_clk_d_mux
[] = {
2436 static const unsigned int msiof1_sync_d_pins
[] = {
2440 static const unsigned int msiof1_sync_d_mux
[] = {
2443 static const unsigned int msiof1_ss1_d_pins
[] = {
2447 static const unsigned int msiof1_ss1_d_mux
[] = {
2450 static const unsigned int msiof1_ss2_d_pins
[] = {
2454 static const unsigned int msiof1_ss2_d_mux
[] = {
2457 static const unsigned int msiof1_txd_d_pins
[] = {
2461 static const unsigned int msiof1_txd_d_mux
[] = {
2464 static const unsigned int msiof1_rxd_d_pins
[] = {
2468 static const unsigned int msiof1_rxd_d_mux
[] = {
2471 static const unsigned int msiof1_clk_e_pins
[] = {
2475 static const unsigned int msiof1_clk_e_mux
[] = {
2478 static const unsigned int msiof1_sync_e_pins
[] = {
2482 static const unsigned int msiof1_sync_e_mux
[] = {
2485 static const unsigned int msiof1_ss1_e_pins
[] = {
2489 static const unsigned int msiof1_ss1_e_mux
[] = {
2492 static const unsigned int msiof1_ss2_e_pins
[] = {
2496 static const unsigned int msiof1_ss2_e_mux
[] = {
2499 static const unsigned int msiof1_txd_e_pins
[] = {
2503 static const unsigned int msiof1_txd_e_mux
[] = {
2506 static const unsigned int msiof1_rxd_e_pins
[] = {
2510 static const unsigned int msiof1_rxd_e_mux
[] = {
2513 static const unsigned int msiof1_clk_f_pins
[] = {
2517 static const unsigned int msiof1_clk_f_mux
[] = {
2520 static const unsigned int msiof1_sync_f_pins
[] = {
2524 static const unsigned int msiof1_sync_f_mux
[] = {
2527 static const unsigned int msiof1_ss1_f_pins
[] = {
2531 static const unsigned int msiof1_ss1_f_mux
[] = {
2534 static const unsigned int msiof1_ss2_f_pins
[] = {
2538 static const unsigned int msiof1_ss2_f_mux
[] = {
2541 static const unsigned int msiof1_txd_f_pins
[] = {
2545 static const unsigned int msiof1_txd_f_mux
[] = {
2548 static const unsigned int msiof1_rxd_f_pins
[] = {
2552 static const unsigned int msiof1_rxd_f_mux
[] = {
2555 static const unsigned int msiof1_clk_g_pins
[] = {
2559 static const unsigned int msiof1_clk_g_mux
[] = {
2562 static const unsigned int msiof1_sync_g_pins
[] = {
2566 static const unsigned int msiof1_sync_g_mux
[] = {
2569 static const unsigned int msiof1_ss1_g_pins
[] = {
2573 static const unsigned int msiof1_ss1_g_mux
[] = {
2576 static const unsigned int msiof1_ss2_g_pins
[] = {
2580 static const unsigned int msiof1_ss2_g_mux
[] = {
2583 static const unsigned int msiof1_txd_g_pins
[] = {
2587 static const unsigned int msiof1_txd_g_mux
[] = {
2590 static const unsigned int msiof1_rxd_g_pins
[] = {
2594 static const unsigned int msiof1_rxd_g_mux
[] = {
2597 /* - MSIOF2 ----------------------------------------------------------------- */
2598 static const unsigned int msiof2_clk_a_pins
[] = {
2602 static const unsigned int msiof2_clk_a_mux
[] = {
2605 static const unsigned int msiof2_sync_a_pins
[] = {
2609 static const unsigned int msiof2_sync_a_mux
[] = {
2612 static const unsigned int msiof2_ss1_a_pins
[] = {
2616 static const unsigned int msiof2_ss1_a_mux
[] = {
2619 static const unsigned int msiof2_ss2_a_pins
[] = {
2623 static const unsigned int msiof2_ss2_a_mux
[] = {
2626 static const unsigned int msiof2_txd_a_pins
[] = {
2630 static const unsigned int msiof2_txd_a_mux
[] = {
2633 static const unsigned int msiof2_rxd_a_pins
[] = {
2637 static const unsigned int msiof2_rxd_a_mux
[] = {
2640 static const unsigned int msiof2_clk_b_pins
[] = {
2644 static const unsigned int msiof2_clk_b_mux
[] = {
2647 static const unsigned int msiof2_sync_b_pins
[] = {
2651 static const unsigned int msiof2_sync_b_mux
[] = {
2654 static const unsigned int msiof2_ss1_b_pins
[] = {
2658 static const unsigned int msiof2_ss1_b_mux
[] = {
2661 static const unsigned int msiof2_ss2_b_pins
[] = {
2665 static const unsigned int msiof2_ss2_b_mux
[] = {
2668 static const unsigned int msiof2_txd_b_pins
[] = {
2672 static const unsigned int msiof2_txd_b_mux
[] = {
2675 static const unsigned int msiof2_rxd_b_pins
[] = {
2679 static const unsigned int msiof2_rxd_b_mux
[] = {
2682 static const unsigned int msiof2_clk_c_pins
[] = {
2686 static const unsigned int msiof2_clk_c_mux
[] = {
2689 static const unsigned int msiof2_sync_c_pins
[] = {
2693 static const unsigned int msiof2_sync_c_mux
[] = {
2696 static const unsigned int msiof2_ss1_c_pins
[] = {
2700 static const unsigned int msiof2_ss1_c_mux
[] = {
2703 static const unsigned int msiof2_ss2_c_pins
[] = {
2707 static const unsigned int msiof2_ss2_c_mux
[] = {
2710 static const unsigned int msiof2_txd_c_pins
[] = {
2714 static const unsigned int msiof2_txd_c_mux
[] = {
2717 static const unsigned int msiof2_rxd_c_pins
[] = {
2721 static const unsigned int msiof2_rxd_c_mux
[] = {
2724 static const unsigned int msiof2_clk_d_pins
[] = {
2728 static const unsigned int msiof2_clk_d_mux
[] = {
2731 static const unsigned int msiof2_sync_d_pins
[] = {
2735 static const unsigned int msiof2_sync_d_mux
[] = {
2738 static const unsigned int msiof2_ss1_d_pins
[] = {
2742 static const unsigned int msiof2_ss1_d_mux
[] = {
2745 static const unsigned int msiof2_ss2_d_pins
[] = {
2749 static const unsigned int msiof2_ss2_d_mux
[] = {
2752 static const unsigned int msiof2_txd_d_pins
[] = {
2756 static const unsigned int msiof2_txd_d_mux
[] = {
2759 static const unsigned int msiof2_rxd_d_pins
[] = {
2763 static const unsigned int msiof2_rxd_d_mux
[] = {
2766 /* - MSIOF3 ----------------------------------------------------------------- */
2767 static const unsigned int msiof3_clk_a_pins
[] = {
2771 static const unsigned int msiof3_clk_a_mux
[] = {
2774 static const unsigned int msiof3_sync_a_pins
[] = {
2778 static const unsigned int msiof3_sync_a_mux
[] = {
2781 static const unsigned int msiof3_ss1_a_pins
[] = {
2785 static const unsigned int msiof3_ss1_a_mux
[] = {
2788 static const unsigned int msiof3_ss2_a_pins
[] = {
2792 static const unsigned int msiof3_ss2_a_mux
[] = {
2795 static const unsigned int msiof3_txd_a_pins
[] = {
2799 static const unsigned int msiof3_txd_a_mux
[] = {
2802 static const unsigned int msiof3_rxd_a_pins
[] = {
2806 static const unsigned int msiof3_rxd_a_mux
[] = {
2809 static const unsigned int msiof3_clk_b_pins
[] = {
2813 static const unsigned int msiof3_clk_b_mux
[] = {
2816 static const unsigned int msiof3_sync_b_pins
[] = {
2820 static const unsigned int msiof3_sync_b_mux
[] = {
2823 static const unsigned int msiof3_ss1_b_pins
[] = {
2827 static const unsigned int msiof3_ss1_b_mux
[] = {
2830 static const unsigned int msiof3_ss2_b_pins
[] = {
2834 static const unsigned int msiof3_ss2_b_mux
[] = {
2837 static const unsigned int msiof3_txd_b_pins
[] = {
2841 static const unsigned int msiof3_txd_b_mux
[] = {
2844 static const unsigned int msiof3_rxd_b_pins
[] = {
2848 static const unsigned int msiof3_rxd_b_mux
[] = {
2851 static const unsigned int msiof3_clk_c_pins
[] = {
2855 static const unsigned int msiof3_clk_c_mux
[] = {
2858 static const unsigned int msiof3_sync_c_pins
[] = {
2862 static const unsigned int msiof3_sync_c_mux
[] = {
2865 static const unsigned int msiof3_txd_c_pins
[] = {
2869 static const unsigned int msiof3_txd_c_mux
[] = {
2872 static const unsigned int msiof3_rxd_c_pins
[] = {
2876 static const unsigned int msiof3_rxd_c_mux
[] = {
2879 static const unsigned int msiof3_clk_d_pins
[] = {
2883 static const unsigned int msiof3_clk_d_mux
[] = {
2886 static const unsigned int msiof3_sync_d_pins
[] = {
2890 static const unsigned int msiof3_sync_d_mux
[] = {
2893 static const unsigned int msiof3_ss1_d_pins
[] = {
2897 static const unsigned int msiof3_ss1_d_mux
[] = {
2900 static const unsigned int msiof3_txd_d_pins
[] = {
2904 static const unsigned int msiof3_txd_d_mux
[] = {
2907 static const unsigned int msiof3_rxd_d_pins
[] = {
2911 static const unsigned int msiof3_rxd_d_mux
[] = {
2915 static const unsigned int msiof3_clk_e_pins
[] = {
2919 static const unsigned int msiof3_clk_e_mux
[] = {
2922 static const unsigned int msiof3_sync_e_pins
[] = {
2926 static const unsigned int msiof3_sync_e_mux
[] = {
2929 static const unsigned int msiof3_ss1_e_pins
[] = {
2933 static const unsigned int msiof3_ss1_e_mux
[] = {
2936 static const unsigned int msiof3_ss2_e_pins
[] = {
2940 static const unsigned int msiof3_ss2_e_mux
[] = {
2943 static const unsigned int msiof3_txd_e_pins
[] = {
2947 static const unsigned int msiof3_txd_e_mux
[] = {
2950 static const unsigned int msiof3_rxd_e_pins
[] = {
2954 static const unsigned int msiof3_rxd_e_mux
[] = {
2958 /* - SCIF0 ------------------------------------------------------------------ */
2959 static const unsigned int scif0_data_pins
[] = {
2961 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2963 static const unsigned int scif0_data_mux
[] = {
2966 static const unsigned int scif0_clk_pins
[] = {
2970 static const unsigned int scif0_clk_mux
[] = {
2973 static const unsigned int scif0_ctrl_pins
[] = {
2975 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2977 static const unsigned int scif0_ctrl_mux
[] = {
2978 RTS0_N_TANS_MARK
, CTS0_N_MARK
,
2980 /* - SCIF1 ------------------------------------------------------------------ */
2981 static const unsigned int scif1_data_a_pins
[] = {
2983 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2985 static const unsigned int scif1_data_a_mux
[] = {
2986 RX1_A_MARK
, TX1_A_MARK
,
2988 static const unsigned int scif1_clk_pins
[] = {
2992 static const unsigned int scif1_clk_mux
[] = {
2995 static const unsigned int scif1_ctrl_pins
[] = {
2997 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2999 static const unsigned int scif1_ctrl_mux
[] = {
3000 RTS1_N_TANS_MARK
, CTS1_N_MARK
,
3003 static const unsigned int scif1_data_b_pins
[] = {
3005 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3007 static const unsigned int scif1_data_b_mux
[] = {
3008 RX1_B_MARK
, TX1_B_MARK
,
3010 /* - SCIF2 ------------------------------------------------------------------ */
3011 static const unsigned int scif2_data_a_pins
[] = {
3013 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3015 static const unsigned int scif2_data_a_mux
[] = {
3016 RX2_A_MARK
, TX2_A_MARK
,
3018 static const unsigned int scif2_clk_pins
[] = {
3022 static const unsigned int scif2_clk_mux
[] = {
3025 static const unsigned int scif2_data_b_pins
[] = {
3027 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3029 static const unsigned int scif2_data_b_mux
[] = {
3030 RX2_B_MARK
, TX2_B_MARK
,
3032 /* - SCIF3 ------------------------------------------------------------------ */
3033 static const unsigned int scif3_data_a_pins
[] = {
3035 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3037 static const unsigned int scif3_data_a_mux
[] = {
3038 RX3_A_MARK
, TX3_A_MARK
,
3040 static const unsigned int scif3_clk_pins
[] = {
3044 static const unsigned int scif3_clk_mux
[] = {
3047 static const unsigned int scif3_ctrl_pins
[] = {
3049 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3051 static const unsigned int scif3_ctrl_mux
[] = {
3052 RTS3_N_TANS_MARK
, CTS3_N_MARK
,
3054 static const unsigned int scif3_data_b_pins
[] = {
3056 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3058 static const unsigned int scif3_data_b_mux
[] = {
3059 RX3_B_MARK
, TX3_B_MARK
,
3061 /* - SCIF4 ------------------------------------------------------------------ */
3062 static const unsigned int scif4_data_a_pins
[] = {
3064 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3066 static const unsigned int scif4_data_a_mux
[] = {
3067 RX4_A_MARK
, TX4_A_MARK
,
3069 static const unsigned int scif4_clk_a_pins
[] = {
3073 static const unsigned int scif4_clk_a_mux
[] = {
3076 static const unsigned int scif4_ctrl_a_pins
[] = {
3078 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3080 static const unsigned int scif4_ctrl_a_mux
[] = {
3081 RTS4_N_TANS_A_MARK
, CTS4_N_A_MARK
,
3083 static const unsigned int scif4_data_b_pins
[] = {
3085 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3087 static const unsigned int scif4_data_b_mux
[] = {
3088 RX4_B_MARK
, TX4_B_MARK
,
3090 static const unsigned int scif4_clk_b_pins
[] = {
3094 static const unsigned int scif4_clk_b_mux
[] = {
3097 static const unsigned int scif4_ctrl_b_pins
[] = {
3099 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3101 static const unsigned int scif4_ctrl_b_mux
[] = {
3102 RTS4_N_TANS_B_MARK
, CTS4_N_B_MARK
,
3104 static const unsigned int scif4_data_c_pins
[] = {
3106 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3108 static const unsigned int scif4_data_c_mux
[] = {
3109 RX4_C_MARK
, TX4_C_MARK
,
3111 static const unsigned int scif4_clk_c_pins
[] = {
3115 static const unsigned int scif4_clk_c_mux
[] = {
3118 static const unsigned int scif4_ctrl_c_pins
[] = {
3120 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3122 static const unsigned int scif4_ctrl_c_mux
[] = {
3123 RTS4_N_TANS_C_MARK
, CTS4_N_C_MARK
,
3125 /* - SCIF5 ------------------------------------------------------------------ */
3126 static const unsigned int scif5_data_a_pins
[] = {
3128 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3130 static const unsigned int scif5_data_a_mux
[] = {
3131 RX5_A_MARK
, TX5_A_MARK
,
3133 static const unsigned int scif5_clk_a_pins
[] = {
3137 static const unsigned int scif5_clk_a_mux
[] = {
3141 static const unsigned int scif5_data_b_pins
[] = {
3143 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3145 static const unsigned int scif5_data_b_mux
[] = {
3146 RX5_B_MARK
, TX5_B_MARK
,
3148 static const unsigned int scif5_clk_b_pins
[] = {
3152 static const unsigned int scif5_clk_b_mux
[] = {
3156 /* - SCIF Clock ------------------------------------------------------------- */
3157 static const unsigned int scif_clk_a_pins
[] = {
3161 static const unsigned int scif_clk_a_mux
[] = {
3164 static const unsigned int scif_clk_b_pins
[] = {
3168 static const unsigned int scif_clk_b_mux
[] = {
3172 /* - SDHI0 ------------------------------------------------------------------ */
3173 static const unsigned int sdhi0_data1_pins
[] = {
3177 static const unsigned int sdhi0_data1_mux
[] = {
3180 static const unsigned int sdhi0_data4_pins
[] = {
3182 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3183 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3185 static const unsigned int sdhi0_data4_mux
[] = {
3186 SD0_DAT0_MARK
, SD0_DAT1_MARK
,
3187 SD0_DAT2_MARK
, SD0_DAT3_MARK
,
3189 static const unsigned int sdhi0_ctrl_pins
[] = {
3191 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3193 static const unsigned int sdhi0_ctrl_mux
[] = {
3194 SD0_CLK_MARK
, SD0_CMD_MARK
,
3196 static const unsigned int sdhi0_cd_pins
[] = {
3200 static const unsigned int sdhi0_cd_mux
[] = {
3203 static const unsigned int sdhi0_wp_pins
[] = {
3207 static const unsigned int sdhi0_wp_mux
[] = {
3210 /* - SDHI1 ------------------------------------------------------------------ */
3211 static const unsigned int sdhi1_data1_pins
[] = {
3215 static const unsigned int sdhi1_data1_mux
[] = {
3218 static const unsigned int sdhi1_data4_pins
[] = {
3220 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3221 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3223 static const unsigned int sdhi1_data4_mux
[] = {
3224 SD1_DAT0_MARK
, SD1_DAT1_MARK
,
3225 SD1_DAT2_MARK
, SD1_DAT3_MARK
,
3227 static const unsigned int sdhi1_ctrl_pins
[] = {
3229 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3231 static const unsigned int sdhi1_ctrl_mux
[] = {
3232 SD1_CLK_MARK
, SD1_CMD_MARK
,
3234 static const unsigned int sdhi1_cd_pins
[] = {
3238 static const unsigned int sdhi1_cd_mux
[] = {
3241 static const unsigned int sdhi1_wp_pins
[] = {
3245 static const unsigned int sdhi1_wp_mux
[] = {
3248 /* - SDHI2 ------------------------------------------------------------------ */
3249 static const unsigned int sdhi2_data1_pins
[] = {
3253 static const unsigned int sdhi2_data1_mux
[] = {
3256 static const unsigned int sdhi2_data4_pins
[] = {
3258 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3259 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3261 static const unsigned int sdhi2_data4_mux
[] = {
3262 SD2_DAT0_MARK
, SD2_DAT1_MARK
,
3263 SD2_DAT2_MARK
, SD2_DAT3_MARK
,
3265 static const unsigned int sdhi2_data8_pins
[] = {
3267 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3268 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3269 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3270 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3272 static const unsigned int sdhi2_data8_mux
[] = {
3273 SD2_DAT0_MARK
, SD2_DAT1_MARK
,
3274 SD2_DAT2_MARK
, SD2_DAT3_MARK
,
3275 SD2_DAT4_MARK
, SD2_DAT5_MARK
,
3276 SD2_DAT6_MARK
, SD2_DAT7_MARK
,
3278 static const unsigned int sdhi2_ctrl_pins
[] = {
3280 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3282 static const unsigned int sdhi2_ctrl_mux
[] = {
3283 SD2_CLK_MARK
, SD2_CMD_MARK
,
3285 static const unsigned int sdhi2_cd_a_pins
[] = {
3289 static const unsigned int sdhi2_cd_a_mux
[] = {
3292 static const unsigned int sdhi2_cd_b_pins
[] = {
3296 static const unsigned int sdhi2_cd_b_mux
[] = {
3299 static const unsigned int sdhi2_wp_a_pins
[] = {
3303 static const unsigned int sdhi2_wp_a_mux
[] = {
3306 static const unsigned int sdhi2_wp_b_pins
[] = {
3310 static const unsigned int sdhi2_wp_b_mux
[] = {
3313 static const unsigned int sdhi2_ds_pins
[] = {
3317 static const unsigned int sdhi2_ds_mux
[] = {
3320 /* - SDHI3 ------------------------------------------------------------------ */
3321 static const unsigned int sdhi3_data1_pins
[] = {
3325 static const unsigned int sdhi3_data1_mux
[] = {
3328 static const unsigned int sdhi3_data4_pins
[] = {
3330 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3331 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3333 static const unsigned int sdhi3_data4_mux
[] = {
3334 SD3_DAT0_MARK
, SD3_DAT1_MARK
,
3335 SD3_DAT2_MARK
, SD3_DAT3_MARK
,
3337 static const unsigned int sdhi3_data8_pins
[] = {
3339 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3340 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3341 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3342 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3344 static const unsigned int sdhi3_data8_mux
[] = {
3345 SD3_DAT0_MARK
, SD3_DAT1_MARK
,
3346 SD3_DAT2_MARK
, SD3_DAT3_MARK
,
3347 SD3_DAT4_MARK
, SD3_DAT5_MARK
,
3348 SD3_DAT6_MARK
, SD3_DAT7_MARK
,
3350 static const unsigned int sdhi3_ctrl_pins
[] = {
3352 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3354 static const unsigned int sdhi3_ctrl_mux
[] = {
3355 SD3_CLK_MARK
, SD3_CMD_MARK
,
3357 static const unsigned int sdhi3_cd_pins
[] = {
3361 static const unsigned int sdhi3_cd_mux
[] = {
3364 static const unsigned int sdhi3_wp_pins
[] = {
3368 static const unsigned int sdhi3_wp_mux
[] = {
3371 static const unsigned int sdhi3_ds_pins
[] = {
3375 static const unsigned int sdhi3_ds_mux
[] = {
3379 static const struct sh_pfc_pin_group pinmux_groups
[] = {
3380 SH_PFC_PIN_GROUP(avb_link
),
3381 SH_PFC_PIN_GROUP(avb_magic
),
3382 SH_PFC_PIN_GROUP(avb_phy_int
),
3383 SH_PFC_PIN_GROUP(avb_mdc
),
3384 SH_PFC_PIN_GROUP(avb_avtp_pps
),
3385 SH_PFC_PIN_GROUP(avb_avtp_match_a
),
3386 SH_PFC_PIN_GROUP(avb_avtp_capture_a
),
3387 SH_PFC_PIN_GROUP(avb_avtp_match_b
),
3388 SH_PFC_PIN_GROUP(avb_avtp_capture_b
),
3389 SH_PFC_PIN_GROUP(can0_data_a
),
3390 SH_PFC_PIN_GROUP(can0_data_b
),
3391 SH_PFC_PIN_GROUP(can1_data
),
3392 SH_PFC_PIN_GROUP(can_clk
),
3393 SH_PFC_PIN_GROUP(canfd0_data_a
),
3394 SH_PFC_PIN_GROUP(canfd0_data_b
),
3395 SH_PFC_PIN_GROUP(canfd1_data
),
3396 SH_PFC_PIN_GROUP(drif0_ctrl_a
),
3397 SH_PFC_PIN_GROUP(drif0_data0_a
),
3398 SH_PFC_PIN_GROUP(drif0_data1_a
),
3399 SH_PFC_PIN_GROUP(drif0_ctrl_b
),
3400 SH_PFC_PIN_GROUP(drif0_data0_b
),
3401 SH_PFC_PIN_GROUP(drif0_data1_b
),
3402 SH_PFC_PIN_GROUP(drif0_ctrl_c
),
3403 SH_PFC_PIN_GROUP(drif0_data0_c
),
3404 SH_PFC_PIN_GROUP(drif0_data1_c
),
3405 SH_PFC_PIN_GROUP(drif1_ctrl_a
),
3406 SH_PFC_PIN_GROUP(drif1_data0_a
),
3407 SH_PFC_PIN_GROUP(drif1_data1_a
),
3408 SH_PFC_PIN_GROUP(drif1_ctrl_b
),
3409 SH_PFC_PIN_GROUP(drif1_data0_b
),
3410 SH_PFC_PIN_GROUP(drif1_data1_b
),
3411 SH_PFC_PIN_GROUP(drif1_ctrl_c
),
3412 SH_PFC_PIN_GROUP(drif1_data0_c
),
3413 SH_PFC_PIN_GROUP(drif1_data1_c
),
3414 SH_PFC_PIN_GROUP(drif2_ctrl_a
),
3415 SH_PFC_PIN_GROUP(drif2_data0_a
),
3416 SH_PFC_PIN_GROUP(drif2_data1_a
),
3417 SH_PFC_PIN_GROUP(drif2_ctrl_b
),
3418 SH_PFC_PIN_GROUP(drif2_data0_b
),
3419 SH_PFC_PIN_GROUP(drif2_data1_b
),
3420 SH_PFC_PIN_GROUP(drif3_ctrl_a
),
3421 SH_PFC_PIN_GROUP(drif3_data0_a
),
3422 SH_PFC_PIN_GROUP(drif3_data1_a
),
3423 SH_PFC_PIN_GROUP(drif3_ctrl_b
),
3424 SH_PFC_PIN_GROUP(drif3_data0_b
),
3425 SH_PFC_PIN_GROUP(drif3_data1_b
),
3426 SH_PFC_PIN_GROUP(du_rgb666
),
3427 SH_PFC_PIN_GROUP(du_rgb888
),
3428 SH_PFC_PIN_GROUP(du_clk_out_0
),
3429 SH_PFC_PIN_GROUP(du_clk_out_1
),
3430 SH_PFC_PIN_GROUP(du_sync
),
3431 SH_PFC_PIN_GROUP(du_oddf
),
3432 SH_PFC_PIN_GROUP(du_cde
),
3433 SH_PFC_PIN_GROUP(du_disp
),
3434 SH_PFC_PIN_GROUP(hscif0_data
),
3435 SH_PFC_PIN_GROUP(hscif0_clk
),
3436 SH_PFC_PIN_GROUP(hscif0_ctrl
),
3437 SH_PFC_PIN_GROUP(hscif1_data_a
),
3438 SH_PFC_PIN_GROUP(hscif1_clk_a
),
3439 SH_PFC_PIN_GROUP(hscif1_ctrl_a
),
3440 SH_PFC_PIN_GROUP(hscif1_data_b
),
3441 SH_PFC_PIN_GROUP(hscif1_clk_b
),
3442 SH_PFC_PIN_GROUP(hscif1_ctrl_b
),
3443 SH_PFC_PIN_GROUP(hscif2_data_a
),
3444 SH_PFC_PIN_GROUP(hscif2_clk_a
),
3445 SH_PFC_PIN_GROUP(hscif2_ctrl_a
),
3446 SH_PFC_PIN_GROUP(hscif2_data_b
),
3447 SH_PFC_PIN_GROUP(hscif2_clk_b
),
3448 SH_PFC_PIN_GROUP(hscif2_ctrl_b
),
3449 SH_PFC_PIN_GROUP(hscif2_data_c
),
3450 SH_PFC_PIN_GROUP(hscif2_clk_c
),
3451 SH_PFC_PIN_GROUP(hscif2_ctrl_c
),
3452 SH_PFC_PIN_GROUP(hscif3_data_a
),
3453 SH_PFC_PIN_GROUP(hscif3_clk
),
3454 SH_PFC_PIN_GROUP(hscif3_ctrl
),
3455 SH_PFC_PIN_GROUP(hscif3_data_b
),
3456 SH_PFC_PIN_GROUP(hscif3_data_c
),
3457 SH_PFC_PIN_GROUP(hscif3_data_d
),
3458 SH_PFC_PIN_GROUP(hscif4_data_a
),
3459 SH_PFC_PIN_GROUP(hscif4_clk
),
3460 SH_PFC_PIN_GROUP(hscif4_ctrl
),
3461 SH_PFC_PIN_GROUP(hscif4_data_b
),
3462 SH_PFC_PIN_GROUP(i2c1_a
),
3463 SH_PFC_PIN_GROUP(i2c1_b
),
3464 SH_PFC_PIN_GROUP(i2c2_a
),
3465 SH_PFC_PIN_GROUP(i2c2_b
),
3466 SH_PFC_PIN_GROUP(i2c6_a
),
3467 SH_PFC_PIN_GROUP(i2c6_b
),
3468 SH_PFC_PIN_GROUP(i2c6_c
),
3469 SH_PFC_PIN_GROUP(msiof0_clk
),
3470 SH_PFC_PIN_GROUP(msiof0_sync
),
3471 SH_PFC_PIN_GROUP(msiof0_ss1
),
3472 SH_PFC_PIN_GROUP(msiof0_ss2
),
3473 SH_PFC_PIN_GROUP(msiof0_txd
),
3474 SH_PFC_PIN_GROUP(msiof0_rxd
),
3475 SH_PFC_PIN_GROUP(msiof1_clk_a
),
3476 SH_PFC_PIN_GROUP(msiof1_sync_a
),
3477 SH_PFC_PIN_GROUP(msiof1_ss1_a
),
3478 SH_PFC_PIN_GROUP(msiof1_ss2_a
),
3479 SH_PFC_PIN_GROUP(msiof1_txd_a
),
3480 SH_PFC_PIN_GROUP(msiof1_rxd_a
),
3481 SH_PFC_PIN_GROUP(msiof1_clk_b
),
3482 SH_PFC_PIN_GROUP(msiof1_sync_b
),
3483 SH_PFC_PIN_GROUP(msiof1_ss1_b
),
3484 SH_PFC_PIN_GROUP(msiof1_ss2_b
),
3485 SH_PFC_PIN_GROUP(msiof1_txd_b
),
3486 SH_PFC_PIN_GROUP(msiof1_rxd_b
),
3487 SH_PFC_PIN_GROUP(msiof1_clk_c
),
3488 SH_PFC_PIN_GROUP(msiof1_sync_c
),
3489 SH_PFC_PIN_GROUP(msiof1_ss1_c
),
3490 SH_PFC_PIN_GROUP(msiof1_ss2_c
),
3491 SH_PFC_PIN_GROUP(msiof1_txd_c
),
3492 SH_PFC_PIN_GROUP(msiof1_rxd_c
),
3493 SH_PFC_PIN_GROUP(msiof1_clk_d
),
3494 SH_PFC_PIN_GROUP(msiof1_sync_d
),
3495 SH_PFC_PIN_GROUP(msiof1_ss1_d
),
3496 SH_PFC_PIN_GROUP(msiof1_ss2_d
),
3497 SH_PFC_PIN_GROUP(msiof1_txd_d
),
3498 SH_PFC_PIN_GROUP(msiof1_rxd_d
),
3499 SH_PFC_PIN_GROUP(msiof1_clk_e
),
3500 SH_PFC_PIN_GROUP(msiof1_sync_e
),
3501 SH_PFC_PIN_GROUP(msiof1_ss1_e
),
3502 SH_PFC_PIN_GROUP(msiof1_ss2_e
),
3503 SH_PFC_PIN_GROUP(msiof1_txd_e
),
3504 SH_PFC_PIN_GROUP(msiof1_rxd_e
),
3505 SH_PFC_PIN_GROUP(msiof1_clk_f
),
3506 SH_PFC_PIN_GROUP(msiof1_sync_f
),
3507 SH_PFC_PIN_GROUP(msiof1_ss1_f
),
3508 SH_PFC_PIN_GROUP(msiof1_ss2_f
),
3509 SH_PFC_PIN_GROUP(msiof1_txd_f
),
3510 SH_PFC_PIN_GROUP(msiof1_rxd_f
),
3511 SH_PFC_PIN_GROUP(msiof1_clk_g
),
3512 SH_PFC_PIN_GROUP(msiof1_sync_g
),
3513 SH_PFC_PIN_GROUP(msiof1_ss1_g
),
3514 SH_PFC_PIN_GROUP(msiof1_ss2_g
),
3515 SH_PFC_PIN_GROUP(msiof1_txd_g
),
3516 SH_PFC_PIN_GROUP(msiof1_rxd_g
),
3517 SH_PFC_PIN_GROUP(msiof2_clk_a
),
3518 SH_PFC_PIN_GROUP(msiof2_sync_a
),
3519 SH_PFC_PIN_GROUP(msiof2_ss1_a
),
3520 SH_PFC_PIN_GROUP(msiof2_ss2_a
),
3521 SH_PFC_PIN_GROUP(msiof2_txd_a
),
3522 SH_PFC_PIN_GROUP(msiof2_rxd_a
),
3523 SH_PFC_PIN_GROUP(msiof2_clk_b
),
3524 SH_PFC_PIN_GROUP(msiof2_sync_b
),
3525 SH_PFC_PIN_GROUP(msiof2_ss1_b
),
3526 SH_PFC_PIN_GROUP(msiof2_ss2_b
),
3527 SH_PFC_PIN_GROUP(msiof2_txd_b
),
3528 SH_PFC_PIN_GROUP(msiof2_rxd_b
),
3529 SH_PFC_PIN_GROUP(msiof2_clk_c
),
3530 SH_PFC_PIN_GROUP(msiof2_sync_c
),
3531 SH_PFC_PIN_GROUP(msiof2_ss1_c
),
3532 SH_PFC_PIN_GROUP(msiof2_ss2_c
),
3533 SH_PFC_PIN_GROUP(msiof2_txd_c
),
3534 SH_PFC_PIN_GROUP(msiof2_rxd_c
),
3535 SH_PFC_PIN_GROUP(msiof2_clk_d
),
3536 SH_PFC_PIN_GROUP(msiof2_sync_d
),
3537 SH_PFC_PIN_GROUP(msiof2_ss1_d
),
3538 SH_PFC_PIN_GROUP(msiof2_ss2_d
),
3539 SH_PFC_PIN_GROUP(msiof2_txd_d
),
3540 SH_PFC_PIN_GROUP(msiof2_rxd_d
),
3541 SH_PFC_PIN_GROUP(msiof3_clk_a
),
3542 SH_PFC_PIN_GROUP(msiof3_sync_a
),
3543 SH_PFC_PIN_GROUP(msiof3_ss1_a
),
3544 SH_PFC_PIN_GROUP(msiof3_ss2_a
),
3545 SH_PFC_PIN_GROUP(msiof3_txd_a
),
3546 SH_PFC_PIN_GROUP(msiof3_rxd_a
),
3547 SH_PFC_PIN_GROUP(msiof3_clk_b
),
3548 SH_PFC_PIN_GROUP(msiof3_sync_b
),
3549 SH_PFC_PIN_GROUP(msiof3_ss1_b
),
3550 SH_PFC_PIN_GROUP(msiof3_ss2_b
),
3551 SH_PFC_PIN_GROUP(msiof3_txd_b
),
3552 SH_PFC_PIN_GROUP(msiof3_rxd_b
),
3553 SH_PFC_PIN_GROUP(msiof3_clk_c
),
3554 SH_PFC_PIN_GROUP(msiof3_sync_c
),
3555 SH_PFC_PIN_GROUP(msiof3_txd_c
),
3556 SH_PFC_PIN_GROUP(msiof3_rxd_c
),
3557 SH_PFC_PIN_GROUP(msiof3_clk_d
),
3558 SH_PFC_PIN_GROUP(msiof3_sync_d
),
3559 SH_PFC_PIN_GROUP(msiof3_ss1_d
),
3560 SH_PFC_PIN_GROUP(msiof3_txd_d
),
3561 SH_PFC_PIN_GROUP(msiof3_rxd_d
),
3562 SH_PFC_PIN_GROUP(msiof3_clk_e
),
3563 SH_PFC_PIN_GROUP(msiof3_sync_e
),
3564 SH_PFC_PIN_GROUP(msiof3_ss1_e
),
3565 SH_PFC_PIN_GROUP(msiof3_ss2_e
),
3566 SH_PFC_PIN_GROUP(msiof3_txd_e
),
3567 SH_PFC_PIN_GROUP(msiof3_rxd_e
),
3568 SH_PFC_PIN_GROUP(scif0_data
),
3569 SH_PFC_PIN_GROUP(scif0_clk
),
3570 SH_PFC_PIN_GROUP(scif0_ctrl
),
3571 SH_PFC_PIN_GROUP(scif1_data_a
),
3572 SH_PFC_PIN_GROUP(scif1_clk
),
3573 SH_PFC_PIN_GROUP(scif1_ctrl
),
3574 SH_PFC_PIN_GROUP(scif1_data_b
),
3575 SH_PFC_PIN_GROUP(scif2_data_a
),
3576 SH_PFC_PIN_GROUP(scif2_clk
),
3577 SH_PFC_PIN_GROUP(scif2_data_b
),
3578 SH_PFC_PIN_GROUP(scif3_data_a
),
3579 SH_PFC_PIN_GROUP(scif3_clk
),
3580 SH_PFC_PIN_GROUP(scif3_ctrl
),
3581 SH_PFC_PIN_GROUP(scif3_data_b
),
3582 SH_PFC_PIN_GROUP(scif4_data_a
),
3583 SH_PFC_PIN_GROUP(scif4_clk_a
),
3584 SH_PFC_PIN_GROUP(scif4_ctrl_a
),
3585 SH_PFC_PIN_GROUP(scif4_data_b
),
3586 SH_PFC_PIN_GROUP(scif4_clk_b
),
3587 SH_PFC_PIN_GROUP(scif4_ctrl_b
),
3588 SH_PFC_PIN_GROUP(scif4_data_c
),
3589 SH_PFC_PIN_GROUP(scif4_clk_c
),
3590 SH_PFC_PIN_GROUP(scif4_ctrl_c
),
3591 SH_PFC_PIN_GROUP(scif5_data_a
),
3592 SH_PFC_PIN_GROUP(scif5_clk_a
),
3593 SH_PFC_PIN_GROUP(scif5_data_b
),
3594 SH_PFC_PIN_GROUP(scif5_clk_b
),
3595 SH_PFC_PIN_GROUP(scif_clk_a
),
3596 SH_PFC_PIN_GROUP(scif_clk_b
),
3597 SH_PFC_PIN_GROUP(sdhi0_data1
),
3598 SH_PFC_PIN_GROUP(sdhi0_data4
),
3599 SH_PFC_PIN_GROUP(sdhi0_ctrl
),
3600 SH_PFC_PIN_GROUP(sdhi0_cd
),
3601 SH_PFC_PIN_GROUP(sdhi0_wp
),
3602 SH_PFC_PIN_GROUP(sdhi1_data1
),
3603 SH_PFC_PIN_GROUP(sdhi1_data4
),
3604 SH_PFC_PIN_GROUP(sdhi1_ctrl
),
3605 SH_PFC_PIN_GROUP(sdhi1_cd
),
3606 SH_PFC_PIN_GROUP(sdhi1_wp
),
3607 SH_PFC_PIN_GROUP(sdhi2_data1
),
3608 SH_PFC_PIN_GROUP(sdhi2_data4
),
3609 SH_PFC_PIN_GROUP(sdhi2_data8
),
3610 SH_PFC_PIN_GROUP(sdhi2_ctrl
),
3611 SH_PFC_PIN_GROUP(sdhi2_cd_a
),
3612 SH_PFC_PIN_GROUP(sdhi2_wp_a
),
3613 SH_PFC_PIN_GROUP(sdhi2_cd_b
),
3614 SH_PFC_PIN_GROUP(sdhi2_wp_b
),
3615 SH_PFC_PIN_GROUP(sdhi2_ds
),
3616 SH_PFC_PIN_GROUP(sdhi3_data1
),
3617 SH_PFC_PIN_GROUP(sdhi3_data4
),
3618 SH_PFC_PIN_GROUP(sdhi3_data8
),
3619 SH_PFC_PIN_GROUP(sdhi3_ctrl
),
3620 SH_PFC_PIN_GROUP(sdhi3_cd
),
3621 SH_PFC_PIN_GROUP(sdhi3_wp
),
3622 SH_PFC_PIN_GROUP(sdhi3_ds
),
3625 static const char * const avb_groups
[] = {
3632 "avb_avtp_capture_a",
3634 "avb_avtp_capture_b",
3637 static const char * const can0_groups
[] = {
3642 static const char * const can1_groups
[] = {
3646 static const char * const can_clk_groups
[] = {
3650 static const char * const canfd0_groups
[] = {
3655 static const char * const canfd1_groups
[] = {
3659 static const char * const drif0_groups
[] = {
3671 static const char * const drif1_groups
[] = {
3683 static const char * const drif2_groups
[] = {
3692 static const char * const drif3_groups
[] = {
3701 static const char * const du_groups
[] = {
3712 static const char * const hscif0_groups
[] = {
3718 static const char * const hscif1_groups
[] = {
3727 static const char * const hscif2_groups
[] = {
3739 static const char * const hscif3_groups
[] = {
3748 static const char * const hscif4_groups
[] = {
3755 static const char * const i2c1_groups
[] = {
3760 static const char * const i2c2_groups
[] = {
3765 static const char * const i2c6_groups
[] = {
3771 static const char * const msiof0_groups
[] = {
3780 static const char * const msiof1_groups
[] = {
3825 static const char * const msiof2_groups
[] = {
3852 static const char * const msiof3_groups
[] = {
3882 static const char * const scif0_groups
[] = {
3888 static const char * const scif1_groups
[] = {
3895 static const char * const scif2_groups
[] = {
3901 static const char * const scif3_groups
[] = {
3908 static const char * const scif4_groups
[] = {
3920 static const char * const scif5_groups
[] = {
3927 static const char * const scif_clk_groups
[] = {
3932 static const char * const sdhi0_groups
[] = {
3940 static const char * const sdhi1_groups
[] = {
3948 static const char * const sdhi2_groups
[] = {
3960 static const char * const sdhi3_groups
[] = {
3970 static const struct sh_pfc_function pinmux_functions
[] = {
3971 SH_PFC_FUNCTION(avb
),
3972 SH_PFC_FUNCTION(can0
),
3973 SH_PFC_FUNCTION(can1
),
3974 SH_PFC_FUNCTION(can_clk
),
3975 SH_PFC_FUNCTION(canfd0
),
3976 SH_PFC_FUNCTION(canfd1
),
3977 SH_PFC_FUNCTION(drif0
),
3978 SH_PFC_FUNCTION(drif1
),
3979 SH_PFC_FUNCTION(drif2
),
3980 SH_PFC_FUNCTION(drif3
),
3981 SH_PFC_FUNCTION(du
),
3982 SH_PFC_FUNCTION(hscif0
),
3983 SH_PFC_FUNCTION(hscif1
),
3984 SH_PFC_FUNCTION(hscif2
),
3985 SH_PFC_FUNCTION(hscif3
),
3986 SH_PFC_FUNCTION(hscif4
),
3987 SH_PFC_FUNCTION(i2c1
),
3988 SH_PFC_FUNCTION(i2c2
),
3989 SH_PFC_FUNCTION(i2c6
),
3990 SH_PFC_FUNCTION(msiof0
),
3991 SH_PFC_FUNCTION(msiof1
),
3992 SH_PFC_FUNCTION(msiof2
),
3993 SH_PFC_FUNCTION(msiof3
),
3994 SH_PFC_FUNCTION(scif0
),
3995 SH_PFC_FUNCTION(scif1
),
3996 SH_PFC_FUNCTION(scif2
),
3997 SH_PFC_FUNCTION(scif3
),
3998 SH_PFC_FUNCTION(scif4
),
3999 SH_PFC_FUNCTION(scif5
),
4000 SH_PFC_FUNCTION(scif_clk
),
4001 SH_PFC_FUNCTION(sdhi0
),
4002 SH_PFC_FUNCTION(sdhi1
),
4003 SH_PFC_FUNCTION(sdhi2
),
4004 SH_PFC_FUNCTION(sdhi3
),
4007 static const struct pinmux_cfg_reg pinmux_config_regs
[] = {
4008 #define F_(x, y) FN_##y
4009 #define FM(x) FN_##x
4010 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4027 GP_0_15_FN
, GPSR0_15
,
4028 GP_0_14_FN
, GPSR0_14
,
4029 GP_0_13_FN
, GPSR0_13
,
4030 GP_0_12_FN
, GPSR0_12
,
4031 GP_0_11_FN
, GPSR0_11
,
4032 GP_0_10_FN
, GPSR0_10
,
4042 GP_0_0_FN
, GPSR0_0
, }
4044 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4048 GP_1_28_FN
, GPSR1_28
,
4049 GP_1_27_FN
, GPSR1_27
,
4050 GP_1_26_FN
, GPSR1_26
,
4051 GP_1_25_FN
, GPSR1_25
,
4052 GP_1_24_FN
, GPSR1_24
,
4053 GP_1_23_FN
, GPSR1_23
,
4054 GP_1_22_FN
, GPSR1_22
,
4055 GP_1_21_FN
, GPSR1_21
,
4056 GP_1_20_FN
, GPSR1_20
,
4057 GP_1_19_FN
, GPSR1_19
,
4058 GP_1_18_FN
, GPSR1_18
,
4059 GP_1_17_FN
, GPSR1_17
,
4060 GP_1_16_FN
, GPSR1_16
,
4061 GP_1_15_FN
, GPSR1_15
,
4062 GP_1_14_FN
, GPSR1_14
,
4063 GP_1_13_FN
, GPSR1_13
,
4064 GP_1_12_FN
, GPSR1_12
,
4065 GP_1_11_FN
, GPSR1_11
,
4066 GP_1_10_FN
, GPSR1_10
,
4076 GP_1_0_FN
, GPSR1_0
, }
4078 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4096 GP_2_14_FN
, GPSR2_14
,
4097 GP_2_13_FN
, GPSR2_13
,
4098 GP_2_12_FN
, GPSR2_12
,
4099 GP_2_11_FN
, GPSR2_11
,
4100 GP_2_10_FN
, GPSR2_10
,
4110 GP_2_0_FN
, GPSR2_0
, }
4112 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4129 GP_3_15_FN
, GPSR3_15
,
4130 GP_3_14_FN
, GPSR3_14
,
4131 GP_3_13_FN
, GPSR3_13
,
4132 GP_3_12_FN
, GPSR3_12
,
4133 GP_3_11_FN
, GPSR3_11
,
4134 GP_3_10_FN
, GPSR3_10
,
4144 GP_3_0_FN
, GPSR3_0
, }
4146 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4161 GP_4_17_FN
, GPSR4_17
,
4162 GP_4_16_FN
, GPSR4_16
,
4163 GP_4_15_FN
, GPSR4_15
,
4164 GP_4_14_FN
, GPSR4_14
,
4165 GP_4_13_FN
, GPSR4_13
,
4166 GP_4_12_FN
, GPSR4_12
,
4167 GP_4_11_FN
, GPSR4_11
,
4168 GP_4_10_FN
, GPSR4_10
,
4178 GP_4_0_FN
, GPSR4_0
, }
4180 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4187 GP_5_25_FN
, GPSR5_25
,
4188 GP_5_24_FN
, GPSR5_24
,
4189 GP_5_23_FN
, GPSR5_23
,
4190 GP_5_22_FN
, GPSR5_22
,
4191 GP_5_21_FN
, GPSR5_21
,
4192 GP_5_20_FN
, GPSR5_20
,
4193 GP_5_19_FN
, GPSR5_19
,
4194 GP_5_18_FN
, GPSR5_18
,
4195 GP_5_17_FN
, GPSR5_17
,
4196 GP_5_16_FN
, GPSR5_16
,
4197 GP_5_15_FN
, GPSR5_15
,
4198 GP_5_14_FN
, GPSR5_14
,
4199 GP_5_13_FN
, GPSR5_13
,
4200 GP_5_12_FN
, GPSR5_12
,
4201 GP_5_11_FN
, GPSR5_11
,
4202 GP_5_10_FN
, GPSR5_10
,
4212 GP_5_0_FN
, GPSR5_0
, }
4214 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4215 GP_6_31_FN
, GPSR6_31
,
4216 GP_6_30_FN
, GPSR6_30
,
4217 GP_6_29_FN
, GPSR6_29
,
4218 GP_6_28_FN
, GPSR6_28
,
4219 GP_6_27_FN
, GPSR6_27
,
4220 GP_6_26_FN
, GPSR6_26
,
4221 GP_6_25_FN
, GPSR6_25
,
4222 GP_6_24_FN
, GPSR6_24
,
4223 GP_6_23_FN
, GPSR6_23
,
4224 GP_6_22_FN
, GPSR6_22
,
4225 GP_6_21_FN
, GPSR6_21
,
4226 GP_6_20_FN
, GPSR6_20
,
4227 GP_6_19_FN
, GPSR6_19
,
4228 GP_6_18_FN
, GPSR6_18
,
4229 GP_6_17_FN
, GPSR6_17
,
4230 GP_6_16_FN
, GPSR6_16
,
4231 GP_6_15_FN
, GPSR6_15
,
4232 GP_6_14_FN
, GPSR6_14
,
4233 GP_6_13_FN
, GPSR6_13
,
4234 GP_6_12_FN
, GPSR6_12
,
4235 GP_6_11_FN
, GPSR6_11
,
4236 GP_6_10_FN
, GPSR6_10
,
4246 GP_6_0_FN
, GPSR6_0
, }
4248 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4280 GP_7_0_FN
, GPSR7_0
, }
4286 #define FM(x) FN_##x,
4287 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4297 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4307 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4317 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4327 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4337 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4347 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4357 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4367 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4377 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4387 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4397 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4407 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4417 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4427 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4437 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4447 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4457 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4467 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
4468 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4469 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4470 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4471 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4472 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4473 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4481 #define FM(x) FN_##x,
4482 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4483 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
4484 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
4504 /* RESERVED 2, 1, 0 */
4505 0, 0, 0, 0, 0, 0, 0, 0 }
4507 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4508 2, 3, 1, 2, 3, 1, 1, 2, 1,
4509 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4525 0, 0, 0, 0, /* RESERVED 8, 7 */
4534 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4535 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4551 /* RESERVED 15, 14, 13, 12 */
4552 0, 0, 0, 0, 0, 0, 0, 0,
4553 0, 0, 0, 0, 0, 0, 0, 0,
4554 /* RESERVED 11, 10, 9, 8 */
4555 0, 0, 0, 0, 0, 0, 0, 0,
4556 0, 0, 0, 0, 0, 0, 0, 0,
4557 /* RESERVED 7, 6, 5, 4 */
4558 0, 0, 0, 0, 0, 0, 0, 0,
4559 0, 0, 0, 0, 0, 0, 0, 0,
4560 /* RESERVED 3, 2, 1 */
4561 0, 0, 0, 0, 0, 0, 0, 0,
4567 static const struct pinmux_drive_reg pinmux_drive_regs
[] = {
4568 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4569 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
4570 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
4571 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
4572 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
4573 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
4574 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
4575 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
4576 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
4578 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
4579 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
4580 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
4581 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
4582 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
4583 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
4584 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
4585 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
4586 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
4588 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
4589 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
4590 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
4591 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
4592 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
4593 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
4594 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
4595 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
4596 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
4598 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4599 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
4600 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
4601 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
4602 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
4603 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
4604 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4605 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4606 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4608 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4609 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4610 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4611 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4612 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4613 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4614 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4615 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4616 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4618 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4619 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4620 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4621 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4622 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4623 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4624 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4625 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4626 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4628 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4629 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4630 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4631 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4632 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4633 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4634 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4635 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4636 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4638 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4639 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4640 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4641 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4642 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4643 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4644 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4645 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4646 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4648 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4649 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
4650 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4651 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4652 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4653 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4654 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4655 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4656 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4658 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4659 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4660 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
4661 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4662 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4663 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4664 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4665 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4666 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4668 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4669 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4670 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4671 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4672 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4673 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4674 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4675 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4676 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4678 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4679 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4680 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4681 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4682 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4683 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4684 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
4685 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
4686 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
4688 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
4689 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
4690 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
4691 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
4693 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4694 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
4695 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
4696 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4697 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4698 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4699 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4700 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4701 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4703 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4704 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4705 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4706 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4707 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4708 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4709 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4710 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4711 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4713 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4714 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4715 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4716 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4717 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4718 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4719 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4720 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4721 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4723 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4724 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4725 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4726 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4727 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4728 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4729 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4730 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4731 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4733 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4734 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4735 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4736 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4737 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4738 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4739 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4740 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4741 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4743 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4744 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4745 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4746 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4747 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4748 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4749 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4750 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4751 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4753 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4754 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4755 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4756 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4757 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4758 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4759 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4760 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4761 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4763 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4764 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4765 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4766 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4767 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4768 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4769 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4770 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
4771 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4773 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4774 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4775 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4776 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4777 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4778 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
4779 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
4780 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4781 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4783 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4784 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4785 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4786 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4787 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4788 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4789 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4790 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4791 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4793 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4794 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4795 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4796 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4797 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4798 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4799 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4800 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4801 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4803 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4804 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4805 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4806 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4807 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4808 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4809 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
4810 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
4815 static int r8a7796_pin_to_pocctrl(struct sh_pfc
*pfc
, unsigned int pin
, u32
*pocctrl
)
4819 *pocctrl
= 0xe6060380;
4821 if (pin
>= RCAR_GP_PIN(3, 0) && pin
<= RCAR_GP_PIN(3, 11))
4824 if (pin
>= RCAR_GP_PIN(4, 0) && pin
<= RCAR_GP_PIN(4, 17))
4825 bit
= (pin
& 0x1f) + 12;
4830 #define PUEN 0xe6060400
4831 #define PUD 0xe6060440
4841 static const struct sh_pfc_bias_info bias_info
[] = {
4842 { RCAR_GP_PIN(2, 11), PU0
, 31 }, /* AVB_PHY_INT */
4843 { RCAR_GP_PIN(2, 10), PU0
, 30 }, /* AVB_MAGIC */
4844 { RCAR_GP_PIN(2, 9), PU0
, 29 }, /* AVB_MDC */
4845 { PIN_NUMBER('A', 9), PU0
, 28 }, /* AVB_MDIO */
4846 { PIN_NUMBER('A', 12), PU0
, 27 }, /* AVB_TXCREFCLK */
4847 { PIN_NUMBER('B', 17), PU0
, 26 }, /* AVB_TD3 */
4848 { PIN_NUMBER('A', 17), PU0
, 25 }, /* AVB_TD2 */
4849 { PIN_NUMBER('B', 18), PU0
, 24 }, /* AVB_TD1 */
4850 { PIN_NUMBER('A', 18), PU0
, 23 }, /* AVB_TD0 */
4851 { PIN_NUMBER('A', 19), PU0
, 22 }, /* AVB_TXC */
4852 { PIN_NUMBER('A', 8), PU0
, 21 }, /* AVB_TX_CTL */
4853 { PIN_NUMBER('B', 14), PU0
, 20 }, /* AVB_RD3 */
4854 { PIN_NUMBER('A', 14), PU0
, 19 }, /* AVB_RD2 */
4855 { PIN_NUMBER('B', 13), PU0
, 18 }, /* AVB_RD1 */
4856 { PIN_NUMBER('A', 13), PU0
, 17 }, /* AVB_RD0 */
4857 { PIN_NUMBER('B', 19), PU0
, 16 }, /* AVB_RXC */
4858 { PIN_NUMBER('A', 16), PU0
, 15 }, /* AVB_RX_CTL */
4859 { PIN_NUMBER('V', 7), PU0
, 14 }, /* RPC_RESET# */
4860 { PIN_NUMBER('V', 6), PU0
, 13 }, /* RPC_WP# */
4861 { PIN_NUMBER('Y', 7), PU0
, 12 }, /* RPC_INT# */
4862 { PIN_NUMBER('V', 5), PU0
, 11 }, /* QSPI1_SSL */
4863 { PIN_A_NUMBER('C', 3), PU0
, 10 }, /* QSPI1_IO3 */
4864 { PIN_A_NUMBER('E', 4), PU0
, 9 }, /* QSPI1_IO2 */
4865 { PIN_A_NUMBER('E', 5), PU0
, 8 }, /* QSPI1_MISO_IO1 */
4866 { PIN_A_NUMBER('C', 7), PU0
, 7 }, /* QSPI1_MOSI_IO0 */
4867 { PIN_NUMBER('V', 3), PU0
, 6 }, /* QSPI1_SPCLK */
4868 { PIN_NUMBER('Y', 3), PU0
, 5 }, /* QSPI0_SSL */
4869 { PIN_A_NUMBER('B', 6), PU0
, 4 }, /* QSPI0_IO3 */
4870 { PIN_NUMBER('Y', 6), PU0
, 3 }, /* QSPI0_IO2 */
4871 { PIN_A_NUMBER('B', 4), PU0
, 2 }, /* QSPI0_MISO_IO1 */
4872 { PIN_A_NUMBER('C', 5), PU0
, 1 }, /* QSPI0_MOSI_IO0 */
4873 { PIN_NUMBER('W', 3), PU0
, 0 }, /* QSPI0_SPCLK */
4875 { RCAR_GP_PIN(1, 19), PU1
, 31 }, /* A19 */
4876 { RCAR_GP_PIN(1, 18), PU1
, 30 }, /* A18 */
4877 { RCAR_GP_PIN(1, 17), PU1
, 29 }, /* A17 */
4878 { RCAR_GP_PIN(1, 16), PU1
, 28 }, /* A16 */
4879 { RCAR_GP_PIN(1, 15), PU1
, 27 }, /* A15 */
4880 { RCAR_GP_PIN(1, 14), PU1
, 26 }, /* A14 */
4881 { RCAR_GP_PIN(1, 13), PU1
, 25 }, /* A13 */
4882 { RCAR_GP_PIN(1, 12), PU1
, 24 }, /* A12 */
4883 { RCAR_GP_PIN(1, 11), PU1
, 23 }, /* A11 */
4884 { RCAR_GP_PIN(1, 10), PU1
, 22 }, /* A10 */
4885 { RCAR_GP_PIN(1, 9), PU1
, 21 }, /* A9 */
4886 { RCAR_GP_PIN(1, 8), PU1
, 20 }, /* A8 */
4887 { RCAR_GP_PIN(1, 7), PU1
, 19 }, /* A7 */
4888 { RCAR_GP_PIN(1, 6), PU1
, 18 }, /* A6 */
4889 { RCAR_GP_PIN(1, 5), PU1
, 17 }, /* A5 */
4890 { RCAR_GP_PIN(1, 4), PU1
, 16 }, /* A4 */
4891 { RCAR_GP_PIN(1, 3), PU1
, 15 }, /* A3 */
4892 { RCAR_GP_PIN(1, 2), PU1
, 14 }, /* A2 */
4893 { RCAR_GP_PIN(1, 1), PU1
, 13 }, /* A1 */
4894 { RCAR_GP_PIN(1, 0), PU1
, 12 }, /* A0 */
4895 { RCAR_GP_PIN(2, 8), PU1
, 11 }, /* PWM2_A */
4896 { RCAR_GP_PIN(2, 7), PU1
, 10 }, /* PWM1_A */
4897 { RCAR_GP_PIN(2, 6), PU1
, 9 }, /* PWM0 */
4898 { RCAR_GP_PIN(2, 5), PU1
, 8 }, /* IRQ5 */
4899 { RCAR_GP_PIN(2, 4), PU1
, 7 }, /* IRQ4 */
4900 { RCAR_GP_PIN(2, 3), PU1
, 6 }, /* IRQ3 */
4901 { RCAR_GP_PIN(2, 2), PU1
, 5 }, /* IRQ2 */
4902 { RCAR_GP_PIN(2, 1), PU1
, 4 }, /* IRQ1 */
4903 { RCAR_GP_PIN(2, 0), PU1
, 3 }, /* IRQ0 */
4904 { RCAR_GP_PIN(2, 14), PU1
, 2 }, /* AVB_AVTP_CAPTURE_A */
4905 { RCAR_GP_PIN(2, 13), PU1
, 1 }, /* AVB_AVTP_MATCH_A */
4906 { RCAR_GP_PIN(2, 12), PU1
, 0 }, /* AVB_LINK */
4908 { PIN_A_NUMBER('P', 8), PU2
, 31 }, /* DU_DOTCLKIN1 */
4909 { PIN_A_NUMBER('P', 7), PU2
, 30 }, /* DU_DOTCLKIN0 */
4910 { RCAR_GP_PIN(7, 3), PU2
, 29 }, /* GP7_03 */
4911 { RCAR_GP_PIN(7, 2), PU2
, 28 }, /* HDMI0_CEC */
4912 { RCAR_GP_PIN(7, 1), PU2
, 27 }, /* AVS2 */
4913 { RCAR_GP_PIN(7, 0), PU2
, 26 }, /* AVS1 */
4914 { RCAR_GP_PIN(0, 15), PU2
, 25 }, /* D15 */
4915 { RCAR_GP_PIN(0, 14), PU2
, 24 }, /* D14 */
4916 { RCAR_GP_PIN(0, 13), PU2
, 23 }, /* D13 */
4917 { RCAR_GP_PIN(0, 12), PU2
, 22 }, /* D12 */
4918 { RCAR_GP_PIN(0, 11), PU2
, 21 }, /* D11 */
4919 { RCAR_GP_PIN(0, 10), PU2
, 20 }, /* D10 */
4920 { RCAR_GP_PIN(0, 9), PU2
, 19 }, /* D9 */
4921 { RCAR_GP_PIN(0, 8), PU2
, 18 }, /* D8 */
4922 { RCAR_GP_PIN(0, 7), PU2
, 17 }, /* D7 */
4923 { RCAR_GP_PIN(0, 6), PU2
, 16 }, /* D6 */
4924 { RCAR_GP_PIN(0, 5), PU2
, 15 }, /* D5 */
4925 { RCAR_GP_PIN(0, 4), PU2
, 14 }, /* D4 */
4926 { RCAR_GP_PIN(0, 3), PU2
, 13 }, /* D3 */
4927 { RCAR_GP_PIN(0, 2), PU2
, 12 }, /* D2 */
4928 { RCAR_GP_PIN(0, 1), PU2
, 11 }, /* D1 */
4929 { RCAR_GP_PIN(0, 0), PU2
, 10 }, /* D0 */
4930 { PIN_NUMBER('C', 1), PU2
, 9 }, /* PRESETOUT# */
4931 { RCAR_GP_PIN(1, 27), PU2
, 8 }, /* EX_WAIT0_A */
4932 { RCAR_GP_PIN(1, 26), PU2
, 7 }, /* WE1_N */
4933 { RCAR_GP_PIN(1, 25), PU2
, 6 }, /* WE0_N */
4934 { RCAR_GP_PIN(1, 24), PU2
, 5 }, /* RD_WR_N */
4935 { RCAR_GP_PIN(1, 23), PU2
, 4 }, /* RD_N */
4936 { RCAR_GP_PIN(1, 22), PU2
, 3 }, /* BS_N */
4937 { RCAR_GP_PIN(1, 21), PU2
, 2 }, /* CS1_N_A26 */
4938 { RCAR_GP_PIN(1, 20), PU2
, 1 }, /* CS0_N */
4939 { RCAR_GP_PIN(1, 28), PU2
, 0 }, /* CLKOUT */
4941 { RCAR_GP_PIN(4, 9), PU3
, 31 }, /* SD3_DAT0 */
4942 { RCAR_GP_PIN(4, 8), PU3
, 30 }, /* SD3_CMD */
4943 { RCAR_GP_PIN(4, 7), PU3
, 29 }, /* SD3_CLK */
4944 { RCAR_GP_PIN(4, 6), PU3
, 28 }, /* SD2_DS */
4945 { RCAR_GP_PIN(4, 5), PU3
, 27 }, /* SD2_DAT3 */
4946 { RCAR_GP_PIN(4, 4), PU3
, 26 }, /* SD2_DAT2 */
4947 { RCAR_GP_PIN(4, 3), PU3
, 25 }, /* SD2_DAT1 */
4948 { RCAR_GP_PIN(4, 2), PU3
, 24 }, /* SD2_DAT0 */
4949 { RCAR_GP_PIN(4, 1), PU3
, 23 }, /* SD2_CMD */
4950 { RCAR_GP_PIN(4, 0), PU3
, 22 }, /* SD2_CLK */
4951 { RCAR_GP_PIN(3, 11), PU3
, 21 }, /* SD1_DAT3 */
4952 { RCAR_GP_PIN(3, 10), PU3
, 20 }, /* SD1_DAT2 */
4953 { RCAR_GP_PIN(3, 9), PU3
, 19 }, /* SD1_DAT1 */
4954 { RCAR_GP_PIN(3, 8), PU3
, 18 }, /* SD1_DAT0 */
4955 { RCAR_GP_PIN(3, 7), PU3
, 17 }, /* SD1_CMD */
4956 { RCAR_GP_PIN(3, 6), PU3
, 16 }, /* SD1_CLK */
4957 { RCAR_GP_PIN(3, 5), PU3
, 15 }, /* SD0_DAT3 */
4958 { RCAR_GP_PIN(3, 4), PU3
, 14 }, /* SD0_DAT2 */
4959 { RCAR_GP_PIN(3, 3), PU3
, 13 }, /* SD0_DAT1 */
4960 { RCAR_GP_PIN(3, 2), PU3
, 12 }, /* SD0_DAT0 */
4961 { RCAR_GP_PIN(3, 1), PU3
, 11 }, /* SD0_CMD */
4962 { RCAR_GP_PIN(3, 0), PU3
, 10 }, /* SD0_CLK */
4963 { PIN_A_NUMBER('T', 30), PU3
, 9 }, /* ASEBRK */
4965 { PIN_A_NUMBER('R', 29), PU3
, 7 }, /* TDI */
4966 { PIN_A_NUMBER('R', 30), PU3
, 6 }, /* TMS */
4967 { PIN_A_NUMBER('T', 27), PU3
, 5 }, /* TCK */
4968 { PIN_A_NUMBER('R', 26), PU3
, 4 }, /* TRST# */
4969 { PIN_A_NUMBER('D', 39), PU3
, 3 }, /* EXTALR*/
4970 { PIN_A_NUMBER('D', 38), PU3
, 2 }, /* FSCLKST */
4971 /* bit 1 n/a on M3*/
4972 { PIN_A_NUMBER('R', 8), PU3
, 0 }, /* DU_DOTCLKIN2 */
4974 { RCAR_GP_PIN(5, 19), PU4
, 31 }, /* MSIOF0_SS1 */
4975 { RCAR_GP_PIN(5, 18), PU4
, 30 }, /* MSIOF0_SYNC */
4976 { RCAR_GP_PIN(5, 17), PU4
, 29 }, /* MSIOF0_SCK */
4977 { RCAR_GP_PIN(5, 16), PU4
, 28 }, /* HRTS0_N */
4978 { RCAR_GP_PIN(5, 15), PU4
, 27 }, /* HCTS0_N */
4979 { RCAR_GP_PIN(5, 14), PU4
, 26 }, /* HTX0 */
4980 { RCAR_GP_PIN(5, 13), PU4
, 25 }, /* HRX0 */
4981 { RCAR_GP_PIN(5, 12), PU4
, 24 }, /* HSCK0 */
4982 { RCAR_GP_PIN(5, 11), PU4
, 23 }, /* RX2_A */
4983 { RCAR_GP_PIN(5, 10), PU4
, 22 }, /* TX2_A */
4984 { RCAR_GP_PIN(5, 9), PU4
, 21 }, /* SCK2 */
4985 { RCAR_GP_PIN(5, 8), PU4
, 20 }, /* RTS1_N_TANS */
4986 { RCAR_GP_PIN(5, 7), PU4
, 19 }, /* CTS1_N */
4987 { RCAR_GP_PIN(5, 6), PU4
, 18 }, /* TX1_A */
4988 { RCAR_GP_PIN(5, 5), PU4
, 17 }, /* RX1_A */
4989 { RCAR_GP_PIN(5, 4), PU4
, 16 }, /* RTS0_N_TANS */
4990 { RCAR_GP_PIN(5, 3), PU4
, 15 }, /* CTS0_N */
4991 { RCAR_GP_PIN(5, 2), PU4
, 14 }, /* TX0 */
4992 { RCAR_GP_PIN(5, 1), PU4
, 13 }, /* RX0 */
4993 { RCAR_GP_PIN(5, 0), PU4
, 12 }, /* SCK0 */
4994 { RCAR_GP_PIN(3, 15), PU4
, 11 }, /* SD1_WP */
4995 { RCAR_GP_PIN(3, 14), PU4
, 10 }, /* SD1_CD */
4996 { RCAR_GP_PIN(3, 13), PU4
, 9 }, /* SD0_WP */
4997 { RCAR_GP_PIN(3, 12), PU4
, 8 }, /* SD0_CD */
4998 { RCAR_GP_PIN(4, 17), PU4
, 7 }, /* SD3_DS */
4999 { RCAR_GP_PIN(4, 16), PU4
, 6 }, /* SD3_DAT7 */
5000 { RCAR_GP_PIN(4, 15), PU4
, 5 }, /* SD3_DAT6 */
5001 { RCAR_GP_PIN(4, 14), PU4
, 4 }, /* SD3_DAT5 */
5002 { RCAR_GP_PIN(4, 13), PU4
, 3 }, /* SD3_DAT4 */
5003 { RCAR_GP_PIN(4, 12), PU4
, 2 }, /* SD3_DAT3 */
5004 { RCAR_GP_PIN(4, 11), PU4
, 1 }, /* SD3_DAT2 */
5005 { RCAR_GP_PIN(4, 10), PU4
, 0 }, /* SD3_DAT1 */
5007 { RCAR_GP_PIN(6, 24), PU5
, 31 }, /* USB0_PWEN */
5008 { RCAR_GP_PIN(6, 23), PU5
, 30 }, /* AUDIO_CLKB_B */
5009 { RCAR_GP_PIN(6, 22), PU5
, 29 }, /* AUDIO_CLKA_A */
5010 { RCAR_GP_PIN(6, 21), PU5
, 28 }, /* SSI_SDATA9_A */
5011 { RCAR_GP_PIN(6, 20), PU5
, 27 }, /* SSI_SDATA8 */
5012 { RCAR_GP_PIN(6, 19), PU5
, 26 }, /* SSI_SDATA7 */
5013 { RCAR_GP_PIN(6, 18), PU5
, 25 }, /* SSI_WS78 */
5014 { RCAR_GP_PIN(6, 17), PU5
, 24 }, /* SSI_SCK78 */
5015 { RCAR_GP_PIN(6, 16), PU5
, 23 }, /* SSI_SDATA6 */
5016 { RCAR_GP_PIN(6, 15), PU5
, 22 }, /* SSI_WS6 */
5017 { RCAR_GP_PIN(6, 14), PU5
, 21 }, /* SSI_SCK6 */
5018 { RCAR_GP_PIN(6, 13), PU5
, 20 }, /* SSI_SDATA5 */
5019 { RCAR_GP_PIN(6, 12), PU5
, 19 }, /* SSI_WS5 */
5020 { RCAR_GP_PIN(6, 11), PU5
, 18 }, /* SSI_SCK5 */
5021 { RCAR_GP_PIN(6, 10), PU5
, 17 }, /* SSI_SDATA4 */
5022 { RCAR_GP_PIN(6, 9), PU5
, 16 }, /* SSI_WS4 */
5023 { RCAR_GP_PIN(6, 8), PU5
, 15 }, /* SSI_SCK4 */
5024 { RCAR_GP_PIN(6, 7), PU5
, 14 }, /* SSI_SDATA3 */
5025 { RCAR_GP_PIN(6, 6), PU5
, 13 }, /* SSI_WS34 */
5026 { RCAR_GP_PIN(6, 5), PU5
, 12 }, /* SSI_SCK34 */
5027 { RCAR_GP_PIN(6, 4), PU5
, 11 }, /* SSI_SDATA2_A */
5028 { RCAR_GP_PIN(6, 3), PU5
, 10 }, /* SSI_SDATA1_A */
5029 { RCAR_GP_PIN(6, 2), PU5
, 9 }, /* SSI_SDATA0 */
5030 { RCAR_GP_PIN(6, 1), PU5
, 8 }, /* SSI_WS01239 */
5031 { RCAR_GP_PIN(6, 0), PU5
, 7 }, /* SSI_SCK01239 */
5032 { PIN_NUMBER('H', 37), PU5
, 6 }, /* MLB_REF */
5033 { RCAR_GP_PIN(5, 25), PU5
, 5 }, /* MLB_DAT */
5034 { RCAR_GP_PIN(5, 24), PU5
, 4 }, /* MLB_SIG */
5035 { RCAR_GP_PIN(5, 23), PU5
, 3 }, /* MLB_CLK */
5036 { RCAR_GP_PIN(5, 22), PU5
, 2 }, /* MSIOF0_RXD */
5037 { RCAR_GP_PIN(5, 21), PU5
, 1 }, /* MSIOF0_SS2 */
5038 { RCAR_GP_PIN(5, 20), PU5
, 0 }, /* MSIOF0_TXD */
5040 { RCAR_GP_PIN(6, 31), PU6
, 6 }, /* GP6_31 */
5041 { RCAR_GP_PIN(6, 30), PU6
, 5 }, /* GP6_30 */
5042 { RCAR_GP_PIN(6, 29), PU6
, 4 }, /* USB30_OVC */
5043 { RCAR_GP_PIN(6, 28), PU6
, 3 }, /* USB30_PWEN */
5044 { RCAR_GP_PIN(6, 27), PU6
, 2 }, /* USB1_OVC */
5045 { RCAR_GP_PIN(6, 26), PU6
, 1 }, /* USB1_PWEN */
5046 { RCAR_GP_PIN(6, 25), PU6
, 0 }, /* USB0_OVC */
5049 static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc
*pfc
,
5052 const struct sh_pfc_bias_info
*info
;
5056 info
= sh_pfc_pin_to_bias_info(bias_info
, ARRAY_SIZE(bias_info
), pin
);
5058 return PIN_CONFIG_BIAS_DISABLE
;
5061 bit
= BIT(info
->bit
);
5063 if (!(sh_pfc_read_reg(pfc
, PUEN
+ reg
, 32) & bit
))
5064 return PIN_CONFIG_BIAS_DISABLE
;
5065 else if (sh_pfc_read_reg(pfc
, PUD
+ reg
, 32) & bit
)
5066 return PIN_CONFIG_BIAS_PULL_UP
;
5068 return PIN_CONFIG_BIAS_PULL_DOWN
;
5071 static void r8a7796_pinmux_set_bias(struct sh_pfc
*pfc
, unsigned int pin
,
5074 const struct sh_pfc_bias_info
*info
;
5079 info
= sh_pfc_pin_to_bias_info(bias_info
, ARRAY_SIZE(bias_info
), pin
);
5084 bit
= BIT(info
->bit
);
5086 enable
= sh_pfc_read_reg(pfc
, PUEN
+ reg
, 32) & ~bit
;
5087 if (bias
!= PIN_CONFIG_BIAS_DISABLE
)
5090 updown
= sh_pfc_read_reg(pfc
, PUD
+ reg
, 32) & ~bit
;
5091 if (bias
== PIN_CONFIG_BIAS_PULL_UP
)
5094 sh_pfc_write_reg(pfc
, PUD
+ reg
, 32, updown
);
5095 sh_pfc_write_reg(pfc
, PUEN
+ reg
, 32, enable
);
5098 static const struct sh_pfc_soc_operations r8a7796_pinmux_ops
= {
5099 .pin_to_pocctrl
= r8a7796_pin_to_pocctrl
,
5100 .get_bias
= r8a7796_pinmux_get_bias
,
5101 .set_bias
= r8a7796_pinmux_set_bias
,
5104 const struct sh_pfc_soc_info r8a7796_pinmux_info
= {
5105 .name
= "r8a77960_pfc",
5106 .ops
= &r8a7796_pinmux_ops
,
5107 .unlock_reg
= 0xe6060000, /* PMMR */
5109 .function
= { PINMUX_FUNCTION_BEGIN
, PINMUX_FUNCTION_END
},
5111 .pins
= pinmux_pins
,
5112 .nr_pins
= ARRAY_SIZE(pinmux_pins
),
5113 .groups
= pinmux_groups
,
5114 .nr_groups
= ARRAY_SIZE(pinmux_groups
),
5115 .functions
= pinmux_functions
,
5116 .nr_functions
= ARRAY_SIZE(pinmux_functions
),
5118 .cfg_regs
= pinmux_config_regs
,
5119 .drive_regs
= pinmux_drive_regs
,
5121 .pinmux_data
= pinmux_data
,
5122 .pinmux_data_size
= ARRAY_SIZE(pinmux_data
),