drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2014-2015 Cogent Embedded, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2
   9  * as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13
  14 #include "sh_pfc.h"
  15
  16 /*
  17  * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
  18  * which case they support both 3.3V and 1.8V signalling.
  19  */
  20 #define CPU_ALL_PORT(fn, sfx)                                           \
  21         PORT_GP_32(0, fn, sfx),                                         \
  22         PORT_GP_26(1, fn, sfx),                                         \
  23         PORT_GP_32(2, fn, sfx),                                         \
  24         PORT_GP_32(3, fn, sfx),                                         \
  25         PORT_GP_32(4, fn, sfx),                                         \
  26         PORT_GP_32(5, fn, sfx),                                         \
  27         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  28         PORT_GP_1(6, 24, fn, sfx),                                      \
  29         PORT_GP_1(6, 25, fn, sfx),                                      \
  30         PORT_GP_1(6, 26, fn, sfx),                                      \
  31         PORT_GP_1(6, 27, fn, sfx),                                      \
  32         PORT_GP_1(6, 28, fn, sfx),                                      \
  33         PORT_GP_1(6, 29, fn, sfx),                                      \
  34         PORT_GP_1(6, 30, fn, sfx),                                      \
  35         PORT_GP_1(6, 31, fn, sfx),                                      \
  36         PORT_GP_26(7, fn, sfx)
  37
  38 enum {
  39         PINMUX_RESERVED = 0,
  40
  41         PINMUX_DATA_BEGIN,
  42         GP_ALL(DATA),
  43         PINMUX_DATA_END,
  44
  45         PINMUX_FUNCTION_BEGIN,
  46         GP_ALL(FN),
  47
  48         /* GPSR0 */
  49         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  50         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  51         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  52         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  53         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  54         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  55
  56         /* GPSR1 */
  57         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  58         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  59         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  60         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  61         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  62         FN_IP3_21_20,
  63
  64         /* GPSR2 */
  65         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  66         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  67         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  68         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  69         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  70         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  71         FN_IP6_5_3, FN_IP6_7_6,
  72
  73         /* GPSR3 */
  74         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  75         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  76         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  77         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  78         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  79         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  80         FN_IP9_18_17,
  81
  82         /* GPSR4 */
  83         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  84         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  85         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  86         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  87         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  88         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  89         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  90         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  91
  92         /* GPSR5 */
  93         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  94         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  95         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  96         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  97         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  98         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  99         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
 100
 101         /* GPSR6 */
 102         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
 103         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
 104         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
 105         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
 106         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
 107         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
 108         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
 109         FN_USB1_OVC, FN_DU0_DOTCLKIN,
 110
 111         /* GPSR7 */
 112         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 113         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 114         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 115         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 116         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 117         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 118
 119         /* IPSR0 */
 120         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 121         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 122         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 123         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 124         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 125         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 126
 127         /* IPSR1 */
 128         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 129         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 130         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 131         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 132         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 133         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 134         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 135         FN_A15, FN_BPFCLK_C,
 136         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 137         FN_A17, FN_DACK2_B, FN_SDA0_C,
 138         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 139
 140         /* IPSR2 */
 141         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 142         FN_A20, FN_SPCLK,
 143         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 144         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 145         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 146         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 147         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 148         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 149         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 150         FN_EX_CS1_N, FN_MSIOF2_SCK,
 151         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 152         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 153
 154         /* IPSR3 */
 155         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 156         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 157         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 158         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 159         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 160         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 161         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 162         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 163         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 164         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 165         FN_DACK0, FN_DRACK0, FN_REMOCON,
 166         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 167         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 168         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 169         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 170
 171         /* IPSR4 */
 172         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 173         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 174         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 175         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 176         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 177         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 178         FN_GLO_Q1_D, FN_HCTS1_N_E,
 179         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 180         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 181         FN_SSI_SCK4, FN_GLO_SS_D,
 182         FN_SSI_WS4, FN_GLO_RFON_D,
 183         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 184         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 185         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 186
 187         /* IPSR5 */
 188         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 189         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 190         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 191         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 192         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 193         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 194         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 195         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 196         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 197         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 198         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 199         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 200         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 201         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 202         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 203
 204         /* IPSR6 */
 205         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 206         FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
 207         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 208         FN_SCIFA2_RXD, FN_FMIN_E,
 209         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 210         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 211         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 212         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 213         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 214         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 215         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 216         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 217         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 218         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 219
 220         /* IPSR7 */
 221         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 222         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 223         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 224         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 225         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 226         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 227         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 228         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 229         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 230         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 231         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 232         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 233         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 234         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 235         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 236         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 237         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 238         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 239
 240         /* IPSR8 */
 241         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 242         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 243         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 244         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 245         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 246         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 247         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 248         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 249         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 250         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 251         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 252         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 253         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 254         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 255         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 256         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 257         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 258
 259         /* IPSR9 */
 260         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 261         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 262         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 263         FN_DU1_DOTCLKOUT0, FN_QCLK,
 264         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 265         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 266         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 267         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 268         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 269         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 270         FN_DU1_DISP, FN_QPOLA,
 271         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 272         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 273         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 274         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 275         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 276         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 277         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 278         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 279
 280         /* IPSR10 */
 281         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 282         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 283         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 284         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 285         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 286         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 287         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 288         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 289         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 290         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 291         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 292         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 293         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 294         FN_TS_SDATA0_C, FN_ATACS11_N,
 295         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 296         FN_TS_SCK0_C, FN_ATAG1_N,
 297         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 298         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 299         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 300
 301         /* IPSR11 */
 302         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 303         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 304         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 305         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 306         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 307         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 308         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 309         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 310         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 311         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 312         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 313         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 314         FN_VI1_DATA7, FN_AVB_MDC,
 315         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 316         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 317
 318         /* IPSR12 */
 319         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 320         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 321         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 322         FN_SCL2_D, FN_MSIOF1_RXD_E,
 323         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 324         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 325         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 326         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 327         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 328         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 329         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 330         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 331         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 332         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 333         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 334         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 335         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 336
 337         /* IPSR13 */
 338         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 339         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 340         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 341         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 342         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 343         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 344         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 345         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 346         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 347         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 348         FN_SCIFA5_TXD_B, FN_TX3_C,
 349         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 350         FN_SCIFA5_RXD_B, FN_RX3_C,
 351         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 352         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 353         FN_SD1_DATA3, FN_IERX_B,
 354         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 355
 356         /* IPSR14 */
 357         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 358         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 359         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 360         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 361         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 362         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 363         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 364         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 365         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 366         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 367         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 368         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 369         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 370         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 371
 372         /* IPSR15 */
 373         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 374         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 375         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 376         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 377         FN_PWM5_B, FN_SCIFA3_TXD_C,
 378         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 379         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 380         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 381         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 382         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 383         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 384         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 385         FN_TCLK2, FN_VI1_DATA3_C,
 386         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 387         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 388
 389         /* IPSR16 */
 390         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 391         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 392         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
 393         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 394         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 395
 396         /* MOD_SEL */
 397         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 398         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 399         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 400         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 401         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 402         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 403         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 404         FN_SEL_QSP_0, FN_SEL_QSP_1,
 405         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 406         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 407         FN_SEL_HSCIF1_4,
 408         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 409         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 410         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 411         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 412         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 413
 414         /* MOD_SEL2 */
 415         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 416         FN_SEL_SCIF0_4,
 417         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 418         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 419         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 420         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 421         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 422         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 423         FN_SEL_ADG_0, FN_SEL_ADG_1,
 424         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 425         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 426         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 427         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 428         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 429         FN_SEL_SIM_0, FN_SEL_SIM_1,
 430         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 431
 432         /* MOD_SEL3 */
 433         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 434         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 435         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 436         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 437         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 438         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 439         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 440         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 441         FN_SEL_MMC_0, FN_SEL_MMC_1,
 442         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 443         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 444         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 445         FN_SEL_IIC1_4,
 446         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 447
 448         /* MOD_SEL4 */
 449         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 450         FN_SEL_SOF1_4,
 451         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 452         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 453         FN_SEL_RAD_0, FN_SEL_RAD_1,
 454         FN_SEL_RCN_0, FN_SEL_RCN_1,
 455         FN_SEL_RSP_0, FN_SEL_RSP_1,
 456         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 457         FN_SEL_SCIF2_4,
 458         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 459         FN_SEL_SOF2_4,
 460         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 461         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 462         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 463         PINMUX_FUNCTION_END,
 464
 465         PINMUX_MARK_BEGIN,
 466
 467         EX_CS0_N_MARK, RD_N_MARK,
 468
 469         AUDIO_CLKA_MARK,
 470
 471         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 472         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 473         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 474
 475         SD1_CLK_MARK,
 476
 477         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 478         DU0_DOTCLKIN_MARK,
 479
 480         /* IPSR0 */
 481         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 482         D6_MARK, D7_MARK, D8_MARK,
 483         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 484         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 485         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 486         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 487         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 488
 489         /* IPSR1 */
 490         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 491         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 492         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 493         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 494         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 495         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 496         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 497         A15_MARK, BPFCLK_C_MARK,
 498         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 499         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 500         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 501
 502         /* IPSR2 */
 503         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 504         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 505         A20_MARK, SPCLK_MARK,
 506         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 507         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 508         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 509         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 510         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 511         RX1_MARK, SCIFA1_RXD_MARK,
 512         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 513         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 514         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 515         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 516         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 517         ATAG0_N_MARK, EX_WAIT1_MARK,
 518
 519         /* IPSR3 */
 520         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 521         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 522         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 523         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 524         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 525         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 526         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 527         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 528         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 529         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 530         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 531         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 532         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 533         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 534         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 535         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 536         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 537         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 538
 539         /* IPSR4 */
 540         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 541         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 542         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 543         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 544         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 545         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 546         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 547         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 548         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 549         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 550         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 551         SSI_SCK4_MARK, GLO_SS_D_MARK,
 552         SSI_WS4_MARK, GLO_RFON_D_MARK,
 553         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 554         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 555         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 556
 557         /* IPSR5 */
 558         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 559         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 560         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 561         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 562         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 563         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 564         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 565         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 566         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 567         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 568         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 569         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 570         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 571         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 572         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 573
 574         /* IPSR6 */
 575         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 576         SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
 577         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 578         SCIFA2_RXD_MARK, FMIN_E_MARK,
 579         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 580         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 581         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 582         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 583         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 584         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 585         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 586         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 587         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 588         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 589         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 590         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 591         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 592         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 593
 594         /* IPSR7 */
 595         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 596         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 597         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 598         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 599         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 600         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 601         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 602         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 603         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 604         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 605         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 606         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 607         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 608         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 609         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 610         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 611         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 612         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 613
 614         /* IPSR8 */
 615         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 616         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 617         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 618         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 619         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 620         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 621         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 622         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 623         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 624         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 625         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 626         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 627         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 628         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 629         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 630         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 631         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 632         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 633
 634         /* IPSR9 */
 635         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 636         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 637         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 638         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 639         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 640         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 641         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 642         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 643         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 644         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 645         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 646         DU1_DISP_MARK, QPOLA_MARK,
 647         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 648         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 649         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 650         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 651         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 652         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 653         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 654         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 655
 656         /* IPSR10 */
 657         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 658         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 659         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 660         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 661         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 662         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 663         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 664         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 665         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 666         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 667         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 668         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 669         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 670         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 671         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 672         TS_SCK0_C_MARK, ATAG1_N_MARK,
 673         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 674         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 675         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 676
 677         /* IPSR11 */
 678         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 679         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 680         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 681         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 682         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 683         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 684         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 685         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 686         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 687         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 688         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 689         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 690         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 691         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 692         VI1_DATA7_MARK, AVB_MDC_MARK,
 693         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 694         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 695
 696         /* IPSR12 */
 697         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 698         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 699         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 700         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 701         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 702         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 703         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 704         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 705         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 706         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 707         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 708         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 709         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 710         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 711         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 712         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 713         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 714         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 715
 716         /* IPSR13 */
 717         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 718         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 719         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 720         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 721         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 722         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 723         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 724         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 725         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 726         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 727         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 728         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 729         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 730         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 731         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 732         SD1_DATA3_MARK, IERX_B_MARK,
 733         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 734
 735         /* IPSR14 */
 736         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 737         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 738         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 739         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 740         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 741         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 742         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 743         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 744         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 745         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 746         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 747         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 748         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 749         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 750         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 751         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 752
 753         /* IPSR15 */
 754         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 755         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 756         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 757         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 758         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 759         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 760         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 761         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 762         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 763         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 764         TCLK1_MARK, VI1_DATA1_C_MARK,
 765         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 766         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 767         TCLK2_MARK, VI1_DATA3_C_MARK,
 768         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 769         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 770         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 771         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 772
 773         /* IPSR16 */
 774         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 775         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 776         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 777         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 778         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
 779         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 780         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 781         PINMUX_MARK_END,
 782 };
 783
 784 static const u16 pinmux_data[] = {
 785         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 786
 787         PINMUX_SINGLE(EX_CS0_N),
 788         PINMUX_SINGLE(RD_N),
 789         PINMUX_SINGLE(AUDIO_CLKA),
 790         PINMUX_SINGLE(VI0_CLK),
 791         PINMUX_SINGLE(VI0_DATA0_VI0_B0),
 792         PINMUX_SINGLE(VI0_DATA1_VI0_B1),
 793         PINMUX_SINGLE(VI0_DATA2_VI0_B2),
 794         PINMUX_SINGLE(VI0_DATA4_VI0_B4),
 795         PINMUX_SINGLE(VI0_DATA5_VI0_B5),
 796         PINMUX_SINGLE(VI0_DATA6_VI0_B6),
 797         PINMUX_SINGLE(VI0_DATA7_VI0_B7),
 798         PINMUX_SINGLE(USB0_PWEN),
 799         PINMUX_SINGLE(USB0_OVC),
 800         PINMUX_SINGLE(USB1_PWEN),
 801         PINMUX_SINGLE(USB1_OVC),
 802         PINMUX_SINGLE(DU0_DOTCLKIN),
 803         PINMUX_SINGLE(SD1_CLK),
 804
 805         /* IPSR0 */
 806         PINMUX_IPSR_GPSR(IP0_0, D0),
 807         PINMUX_IPSR_GPSR(IP0_1, D1),
 808         PINMUX_IPSR_GPSR(IP0_2, D2),
 809         PINMUX_IPSR_GPSR(IP0_3, D3),
 810         PINMUX_IPSR_GPSR(IP0_4, D4),
 811         PINMUX_IPSR_GPSR(IP0_5, D5),
 812         PINMUX_IPSR_GPSR(IP0_6, D6),
 813         PINMUX_IPSR_GPSR(IP0_7, D7),
 814         PINMUX_IPSR_GPSR(IP0_8, D8),
 815         PINMUX_IPSR_GPSR(IP0_9, D9),
 816         PINMUX_IPSR_GPSR(IP0_10, D10),
 817         PINMUX_IPSR_GPSR(IP0_11, D11),
 818         PINMUX_IPSR_GPSR(IP0_12, D12),
 819         PINMUX_IPSR_GPSR(IP0_13, D13),
 820         PINMUX_IPSR_GPSR(IP0_14, D14),
 821         PINMUX_IPSR_GPSR(IP0_15, D15),
 822         PINMUX_IPSR_GPSR(IP0_18_16, A0),
 823         PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 824         PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 825         PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
 826         PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
 827         PINMUX_IPSR_GPSR(IP0_20_19, A1),
 828         PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 829         PINMUX_IPSR_GPSR(IP0_22_21, A2),
 830         PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 831         PINMUX_IPSR_GPSR(IP0_24_23, A3),
 832         PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 833         PINMUX_IPSR_GPSR(IP0_26_25, A4),
 834         PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 835         PINMUX_IPSR_GPSR(IP0_28_27, A5),
 836         PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 837         PINMUX_IPSR_GPSR(IP0_30_29, A6),
 838         PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 839
 840         /* IPSR1 */
 841         PINMUX_IPSR_GPSR(IP1_1_0, A7),
 842         PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 843         PINMUX_IPSR_GPSR(IP1_3_2, A8),
 844         PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 845         PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
 846         PINMUX_IPSR_GPSR(IP1_5_4, A9),
 847         PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 848         PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
 849         PINMUX_IPSR_GPSR(IP1_7_6, A10),
 850         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 851         PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 852         PINMUX_IPSR_GPSR(IP1_10_8, A11),
 853         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 854         PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
 855         PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 856         PINMUX_IPSR_GPSR(IP1_13_11, A12),
 857         PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
 858         PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
 859         PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 860         PINMUX_IPSR_GPSR(IP1_16_14, A13),
 861         PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 862         PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
 863         PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 864         PINMUX_IPSR_GPSR(IP1_19_17, A14),
 865         PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 866         PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
 867         PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
 868         PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 869         PINMUX_IPSR_GPSR(IP1_22_20, A15),
 870         PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
 871         PINMUX_IPSR_GPSR(IP1_25_23, A16),
 872         PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
 873         PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
 874         PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 875         PINMUX_IPSR_GPSR(IP1_28_26, A17),
 876         PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
 877         PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
 878         PINMUX_IPSR_GPSR(IP1_31_29, A18),
 879         PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
 880         PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 881         PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 882
 883         /* IPSR2 */
 884         PINMUX_IPSR_GPSR(IP2_2_0, A19),
 885         PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
 886         PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 887         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 888         PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
 889         PINMUX_IPSR_GPSR(IP2_2_0, A20),
 890         PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
 891         PINMUX_IPSR_GPSR(IP2_6_5, A21),
 892         PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 893         PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 894         PINMUX_IPSR_GPSR(IP2_9_7, A22),
 895         PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
 896         PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
 897         PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
 898         PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 899         PINMUX_IPSR_GPSR(IP2_12_10, A23),
 900         PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
 901         PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
 902         PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
 903         PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 904         PINMUX_IPSR_GPSR(IP2_15_13, A24),
 905         PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
 906         PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
 907         PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
 908         PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 909         PINMUX_IPSR_GPSR(IP2_18_16, A25),
 910         PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
 911         PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
 912         PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
 913         PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
 914         PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 915         PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
 916         PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 917         PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
 918         PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
 919         PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 920         PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
 921         PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
 922         PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 923         PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
 924         PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 925         PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 926         PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
 927         PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 928         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 929         PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
 930         PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
 931
 932         /* IPSR3 */
 933         PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
 934         PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
 935         PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 936         PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
 937         PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
 938         PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
 939         PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 940         PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 941         PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 942         PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
 943         PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
 944         PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
 945         PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
 946         PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 947         PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 948         PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 949         PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
 950         PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
 951         PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
 952         PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 953         PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
 954         PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 955         PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
 956         PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
 957         PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 958         PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 959         PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
 960         PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 961         PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 962         PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 963         PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
 964         PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 965         PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 966         PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
 967         PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
 968         PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
 969         PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
 970         PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
 971         PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
 972         PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
 973         PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 974         PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 975         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 976         PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 977         PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
 978         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 979         PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 980         PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 981         PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 982         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 983         PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 984         PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 985         PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 986         PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 987         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 988         PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 989
 990         /* IPSR4 */
 991         PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 992         PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1),
 993         PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1),
 994         PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 995         PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 996         PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1),
 997         PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1),
 998         PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
 999         PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1000         PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1001         PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1),
1002         PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1),
1003         PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1004         PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1005         PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1006         PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
1007         PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
1008         PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1009         PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1010         PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
1011         PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1012         PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1013         PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1014         PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1015         PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
1016         PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1017         PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1018         PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1019         PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1020         PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1021         PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1022         PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1023         PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1024         PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1025         PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1026         PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1027         PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1028         PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1029         PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1030         PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1031         PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1032         PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1033         PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1034         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1035         PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1036         PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1037         PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1038         PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1039
1040         /* IPSR5 */
1041         PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1042         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1043         PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1044         PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1045         PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1046         PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1047         PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1048         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1049         PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1050         PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1051         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1052         PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1053         PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1054         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1055         PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1056         PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1057         PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1058         PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1059         PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1060         PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1061         PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1062         PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1063         PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1064         PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1065         PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1066         PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1067         PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1068         PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1069         PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1070         PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1071         PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1072         PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1073         PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1074         PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1075         PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1076         PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1077         PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1078         PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1079         PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1080         PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1081         PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1082         PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1083         PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1084         PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1085         PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1086         PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1087         PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1088         PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1089         PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1090
1091         /* IPSR6 */
1092         PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1093         PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1094         PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1095         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1096         PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1097         PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1098         PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1099         PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1100         PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1101         PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1102         PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1103         PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1104         PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1105         PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1106         PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1107         PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1108         PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1109         PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1110         PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1111         PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1112         PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1113         PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1114         PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1115         PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1116         PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1117         PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1118         PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
1119         PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1120         PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1121         PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1122         PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1123         PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
1124         PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1125         PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1126         PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1127         PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1128         PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
1129         PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1130         PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1131         PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1132         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1133         PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
1134         PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1135         PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1136         PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1137         PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1138         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1139         PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1140         PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1141         PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1142         PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1143         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1144         PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1145
1146         /* IPSR7 */
1147         PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1148         PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1149         PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1150         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1151         PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1152         PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1153         PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1154         PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1155         PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1156         PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1157         PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1158         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1159         PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1160         PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1161         PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1162         PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1163         PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1164         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1165         PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1166         PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1167         PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1168         PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1169         PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1170         PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1171         PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1172         PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1173         PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1174         PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1175         PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1176         PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1177         PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1178         PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1179         PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1180         PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1181         PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1182         PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1183         PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1184         PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1185         PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1186         PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1187         PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1188         PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1189         PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1190         PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1191         PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1192         PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1193         PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1194         PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1195         PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1196         PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1197         PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1198         PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1199         PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1200         PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1201
1202         /* IPSR8 */
1203         PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1204         PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1205         PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1206         PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1207         PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1208         PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1209         PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1210         PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1211         PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1212         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1213         PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1214         PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1215         PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1216         PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1217         PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1218         PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1219         PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1220         PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1221         PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1222         PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1223         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1224         PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1225         PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1226         PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1227         PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1228         PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1229         PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1230         PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1231         PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1232         PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1233         PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1234         PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1235         PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1236         PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1237         PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1238         PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1239         PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1240         PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1241         PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1242         PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1243         PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1244         PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1245         PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1246         PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1247         PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1248         PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1249         PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1250         PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1251         PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1252         PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1253         PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1254         PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1255         PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1256         PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1257         PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1258         PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1259
1260         /* IPSR9 */
1261         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1262         PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1263         PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
1264         PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1265         PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1266         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1267         PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1268         PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
1269         PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1270         PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1271         PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1272         PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1273         PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1274         PINMUX_IPSR_GPSR(IP9_7, QCLK),
1275         PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1276         PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1277         PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1278         PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1279         PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
1280         PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1281         PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1282         PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1283         PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1284         PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1285         PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1286         PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1287         PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1288         PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1289         PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
1290         PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1291         PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1292         PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1293         PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1294         PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1295         PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1296         PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1297         PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1298         PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1299         PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1300         PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1301         PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1302         PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1303         PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1304         PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1305         PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1306         PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1307         PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1308         PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1309         PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1310         PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1311         PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1312         PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1313         PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1314         PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1315         PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
1316         PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1317         PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
1318         PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1319         PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1320         PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1321
1322         /* IPSR10 */
1323         PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1324         PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
1325         PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1326         PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
1327         PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1328         PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1329         PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1330         PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1331         PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1332         PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1333         PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
1334         PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1335         PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1336         PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1337         PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1338         PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1339         PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1340         PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
1341         PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1342         PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1343         PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1344         PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1345         PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1346         PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1347         PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1348         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1349         PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1350         PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1351         PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1352         PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1353         PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1354         PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1355         PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1356         PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1357         PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1358         PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1359         PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1360         PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1361         PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1362         PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1363         PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1364         PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1365         PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1366         PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1367         PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1368         PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1369         PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1370         PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1371         PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1372         PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1373         PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1374         PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1375         PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1376         PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1377         PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1378         PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1379         PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1380         PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1381         PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1382         PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1383         PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1384         PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1385         PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
1386
1387         /* IPSR11 */
1388         PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1389         PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1390         PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1391         PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1392         PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
1393         PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1394         PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1395         PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1396         PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1397         PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
1398         PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1399         PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1400         PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1401         PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1402         PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1),
1403         PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1404         PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1405         PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1406         PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1407         PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1408         PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1409         PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1410         PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1411         PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1412         PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1413         PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1414         PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1415         PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1416         PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1417         PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1418         PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1419         PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1420         PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1421         PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1422         PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1423         PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1424         PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1425         PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1426         PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1427         PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1428         PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1429         PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1430         PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1431         PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1432         PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1433         PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1434         PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1435         PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1436         PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1437         PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1438         PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1439         PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1440         PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1441         PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
1442         PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1443         PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1444         PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
1445
1446         /* IPSR12 */
1447         PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1448         PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1449         PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
1450         PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
1451         PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1452         PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1453         PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
1454         PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
1455         PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1456         PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1457         PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1458         PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
1459         PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1460         PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1461         PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1462         PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1463         PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
1464         PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1465         PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1466         PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1467         PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1468         PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1469         PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1470         PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1471         PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1472         PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1473         PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1474         PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1475         PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1476         PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1477         PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1478         PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1479         PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1480         PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1481         PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1482         PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1483         PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1484         PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1485         PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1486         PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1487         PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1488         PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1489         PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1490         PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1491         PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1492         PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1493         PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1494         PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1495         PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1496         PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1497         PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1498
1499         /* IPSR13 */
1500         PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1501         PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1502         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1503         PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1504         PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1505         PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1506         PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1507         PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1508         PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1509         PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1510         PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1511         PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1512         PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1513         PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1514         PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1515         PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1516         PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1517         PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1518         PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1519         PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1520         PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1521         PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1522         PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1523         PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1524         PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1525         PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1526         PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1527         PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1528         PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1529         PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1530         PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1531         PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1532         PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1533         PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1534         PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1535         PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1536         PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1537         PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1538         PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1539         PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1540         PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1541         PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1542         PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1543         PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1544         PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1545         PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1546         PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1547         PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1548         PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1549         PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1550         PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1551         PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1552         PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1553         PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1554         PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1555         PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
1556
1557         /* IPSR14 */
1558         PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1559         PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1560         PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
1561         PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1562         PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1563         PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1564         PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1565         PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1566         PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1567         PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1568         PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1569         PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1570         PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1571         PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1572         PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1573         PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1574         PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1575         PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
1576         PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1577         PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1578         PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1579         PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1580         PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
1581         PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1582         PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1583         PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1584         PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1585         PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1586         PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1587         PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1588         PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1589         PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1590         PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1591         PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1592         PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1593         PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1594         PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1595         PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1596         PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1597         PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1598         PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1599         PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1600         PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1601         PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1602         PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1603         PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1604         PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1605         PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1606         PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
1607         PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1608         PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1609         PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1610         PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1611         PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1612         PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1613         PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
1614         PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1615
1616         /* IPSR15 */
1617         PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1618         PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1619         PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1620         PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1621         PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1622         PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1623         PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1624         PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1625         PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1626         PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1627         PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1628         PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1629         PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1630         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1631         PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1632         PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1633         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1634         PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1635         PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1636         PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1637         PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1638         PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1639         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1640         PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1641         PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1642         PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1643         PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1644         PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1645         PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1646         PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1647         PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1648         PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1649         PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1650         PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1651         PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1652         PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1653         PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1654         PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1655         PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1656         PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1657         PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1658         PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1659         PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1660         PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1661         PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1662         PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1663         PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1664         PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1665         PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1666         PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1667         PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1668
1669         /* IPSR16 */
1670         PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1671         PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1672         PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1673         PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1674         PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1675         PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1676         PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1677         PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1678         PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1679         PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1680         PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1681         PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1682         PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1683         PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1684         PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1685         PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1686         PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1687         PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1688         PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1689         PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1690         PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1691         PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1692 };
1693
1694 static const struct sh_pfc_pin pinmux_pins[] = {
1695         PINMUX_GPIO_GP_ALL(),
1696 };
1697
1698 /* - ADI -------------------------------------------------------------------- */
1699 static const unsigned int adi_common_pins[] = {
1700         /* ADIDATA, ADICS/SAMP, ADICLK */
1701         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1702 };
1703 static const unsigned int adi_common_mux[] = {
1704         /* ADIDATA, ADICS/SAMP, ADICLK */
1705         ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1706 };
1707 static const unsigned int adi_chsel0_pins[] = {
1708         /* ADICHS 0 */
1709         RCAR_GP_PIN(6, 27),
1710 };
1711 static const unsigned int adi_chsel0_mux[] = {
1712         /* ADICHS 0 */
1713         ADICHS0_MARK,
1714 };
1715 static const unsigned int adi_chsel1_pins[] = {
1716         /* ADICHS 1 */
1717         RCAR_GP_PIN(6, 28),
1718 };
1719 static const unsigned int adi_chsel1_mux[] = {
1720         /* ADICHS 1 */
1721         ADICHS1_MARK,
1722 };
1723 static const unsigned int adi_chsel2_pins[] = {
1724         /* ADICHS 2 */
1725         RCAR_GP_PIN(6, 29),
1726 };
1727 static const unsigned int adi_chsel2_mux[] = {
1728         /* ADICHS 2 */
1729         ADICHS2_MARK,
1730 };
1731 static const unsigned int adi_common_b_pins[] = {
1732         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1733         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1734 };
1735 static const unsigned int adi_common_b_mux[] = {
1736         /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1737         ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1738 };
1739 static const unsigned int adi_chsel0_b_pins[] = {
1740         /* ADICHS B 0 */
1741         RCAR_GP_PIN(5, 28),
1742 };
1743 static const unsigned int adi_chsel0_b_mux[] = {
1744         /* ADICHS B 0 */
1745         ADICHS0_B_MARK,
1746 };
1747 static const unsigned int adi_chsel1_b_pins[] = {
1748         /* ADICHS B 1 */
1749         RCAR_GP_PIN(5, 29),
1750 };
1751 static const unsigned int adi_chsel1_b_mux[] = {
1752         /* ADICHS B 1 */
1753         ADICHS1_B_MARK,
1754 };
1755 static const unsigned int adi_chsel2_b_pins[] = {
1756         /* ADICHS B 2 */
1757         RCAR_GP_PIN(5, 30),
1758 };
1759 static const unsigned int adi_chsel2_b_mux[] = {
1760         /* ADICHS B 2 */
1761         ADICHS2_B_MARK,
1762 };
1763
1764 /* - Audio Clock ------------------------------------------------------------ */
1765 static const unsigned int audio_clk_a_pins[] = {
1766         /* CLK */
1767         RCAR_GP_PIN(2, 28),
1768 };
1769
1770 static const unsigned int audio_clk_a_mux[] = {
1771         AUDIO_CLKA_MARK,
1772 };
1773
1774 static const unsigned int audio_clk_b_pins[] = {
1775         /* CLK */
1776         RCAR_GP_PIN(2, 29),
1777 };
1778
1779 static const unsigned int audio_clk_b_mux[] = {
1780         AUDIO_CLKB_MARK,
1781 };
1782
1783 static const unsigned int audio_clk_b_b_pins[] = {
1784         /* CLK */
1785         RCAR_GP_PIN(7, 20),
1786 };
1787
1788 static const unsigned int audio_clk_b_b_mux[] = {
1789         AUDIO_CLKB_B_MARK,
1790 };
1791
1792 static const unsigned int audio_clk_c_pins[] = {
1793         /* CLK */
1794         RCAR_GP_PIN(2, 30),
1795 };
1796
1797 static const unsigned int audio_clk_c_mux[] = {
1798         AUDIO_CLKC_MARK,
1799 };
1800
1801 static const unsigned int audio_clkout_pins[] = {
1802         /* CLK */
1803         RCAR_GP_PIN(2, 31),
1804 };
1805
1806 static const unsigned int audio_clkout_mux[] = {
1807         AUDIO_CLKOUT_MARK,
1808 };
1809
1810 /* - AVB -------------------------------------------------------------------- */
1811 static const unsigned int avb_link_pins[] = {
1812         RCAR_GP_PIN(5, 14),
1813 };
1814 static const unsigned int avb_link_mux[] = {
1815         AVB_LINK_MARK,
1816 };
1817 static const unsigned int avb_magic_pins[] = {
1818         RCAR_GP_PIN(5, 11),
1819 };
1820 static const unsigned int avb_magic_mux[] = {
1821         AVB_MAGIC_MARK,
1822 };
1823 static const unsigned int avb_phy_int_pins[] = {
1824         RCAR_GP_PIN(5, 16),
1825 };
1826 static const unsigned int avb_phy_int_mux[] = {
1827         AVB_PHY_INT_MARK,
1828 };
1829 static const unsigned int avb_mdio_pins[] = {
1830         RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1831 };
1832 static const unsigned int avb_mdio_mux[] = {
1833         AVB_MDC_MARK, AVB_MDIO_MARK,
1834 };
1835 static const unsigned int avb_mii_pins[] = {
1836         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1837         RCAR_GP_PIN(5, 21),
1838
1839         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1840         RCAR_GP_PIN(5, 3),
1841
1842         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1843         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1844         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1845 };
1846 static const unsigned int avb_mii_mux[] = {
1847         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1848         AVB_TXD3_MARK,
1849
1850         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1851         AVB_RXD3_MARK,
1852
1853         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1854         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1855         AVB_TX_CLK_MARK, AVB_COL_MARK,
1856 };
1857 static const unsigned int avb_gmii_pins[] = {
1858         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1859         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1860         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1861
1862         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1863         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1864         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1865
1866         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1867         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1868         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1869         RCAR_GP_PIN(5, 29),
1870 };
1871 static const unsigned int avb_gmii_mux[] = {
1872         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1873         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1874         AVB_TXD6_MARK, AVB_TXD7_MARK,
1875
1876         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1877         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1878         AVB_RXD6_MARK, AVB_RXD7_MARK,
1879
1880         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1881         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1882         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1883         AVB_COL_MARK,
1884 };
1885
1886 /* - CAN -------------------------------------------------------------------- */
1887
1888 static const unsigned int can0_data_pins[] = {
1889         /* TX, RX */
1890         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1891 };
1892
1893 static const unsigned int can0_data_mux[] = {
1894         CAN0_TX_MARK, CAN0_RX_MARK,
1895 };
1896
1897 static const unsigned int can0_data_b_pins[] = {
1898         /* TX, RX */
1899         RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1900 };
1901
1902 static const unsigned int can0_data_b_mux[] = {
1903         CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1904 };
1905
1906 static const unsigned int can0_data_c_pins[] = {
1907         /* TX, RX */
1908         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1909 };
1910
1911 static const unsigned int can0_data_c_mux[] = {
1912         CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1913 };
1914
1915 static const unsigned int can0_data_d_pins[] = {
1916         /* TX, RX */
1917         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1918 };
1919
1920 static const unsigned int can0_data_d_mux[] = {
1921         CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1922 };
1923
1924 static const unsigned int can0_data_e_pins[] = {
1925         /* TX, RX */
1926         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1927 };
1928
1929 static const unsigned int can0_data_e_mux[] = {
1930         CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1931 };
1932
1933 static const unsigned int can0_data_f_pins[] = {
1934         /* TX, RX */
1935         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1936 };
1937
1938 static const unsigned int can0_data_f_mux[] = {
1939         CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1940 };
1941
1942 static const unsigned int can1_data_pins[] = {
1943         /* TX, RX */
1944          RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1945 };
1946
1947 static const unsigned int can1_data_mux[] = {
1948         CAN1_TX_MARK, CAN1_RX_MARK,
1949 };
1950
1951 static const unsigned int can1_data_b_pins[] = {
1952         /* TX, RX */
1953         RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1954 };
1955
1956 static const unsigned int can1_data_b_mux[] = {
1957         CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1958 };
1959
1960 static const unsigned int can1_data_c_pins[] = {
1961         /* TX, RX */
1962         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1963 };
1964
1965 static const unsigned int can1_data_c_mux[] = {
1966         CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1967 };
1968
1969 static const unsigned int can1_data_d_pins[] = {
1970         /* TX, RX */
1971          RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1972 };
1973
1974 static const unsigned int can1_data_d_mux[] = {
1975         CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1976 };
1977
1978 static const unsigned int can_clk_pins[] = {
1979         /* CLK */
1980         RCAR_GP_PIN(7, 2),
1981 };
1982
1983 static const unsigned int can_clk_mux[] = {
1984         CAN_CLK_MARK,
1985 };
1986
1987 static const unsigned int can_clk_b_pins[] = {
1988         /* CLK */
1989         RCAR_GP_PIN(5, 21),
1990 };
1991
1992 static const unsigned int can_clk_b_mux[] = {
1993         CAN_CLK_B_MARK,
1994 };
1995
1996 static const unsigned int can_clk_c_pins[] = {
1997         /* CLK */
1998         RCAR_GP_PIN(4, 30),
1999 };
2000
2001 static const unsigned int can_clk_c_mux[] = {
2002         CAN_CLK_C_MARK,
2003 };
2004
2005 static const unsigned int can_clk_d_pins[] = {
2006         /* CLK */
2007         RCAR_GP_PIN(7, 19),
2008 };
2009
2010 static const unsigned int can_clk_d_mux[] = {
2011         CAN_CLK_D_MARK,
2012 };
2013
2014 /* - DU --------------------------------------------------------------------- */
2015 static const unsigned int du_rgb666_pins[] = {
2016         /* R[7:2], G[7:2], B[7:2] */
2017         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2018         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2019         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2020         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2021         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2022         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2023 };
2024 static const unsigned int du_rgb666_mux[] = {
2025         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2026         DU1_DR3_MARK, DU1_DR2_MARK,
2027         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2028         DU1_DG3_MARK, DU1_DG2_MARK,
2029         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2030         DU1_DB3_MARK, DU1_DB2_MARK,
2031 };
2032 static const unsigned int du_rgb888_pins[] = {
2033         /* R[7:0], G[7:0], B[7:0] */
2034         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
2035         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
2036         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
2037         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2038         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2039         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
2040         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2041         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2042         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2043 };
2044 static const unsigned int du_rgb888_mux[] = {
2045         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2046         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2047         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2048         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2049         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2050         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2051 };
2052 static const unsigned int du_clk_out_0_pins[] = {
2053         /* CLKOUT */
2054         RCAR_GP_PIN(3, 25),
2055 };
2056 static const unsigned int du_clk_out_0_mux[] = {
2057         DU1_DOTCLKOUT0_MARK
2058 };
2059 static const unsigned int du_clk_out_1_pins[] = {
2060         /* CLKOUT */
2061         RCAR_GP_PIN(3, 26),
2062 };
2063 static const unsigned int du_clk_out_1_mux[] = {
2064         DU1_DOTCLKOUT1_MARK
2065 };
2066 static const unsigned int du_sync_pins[] = {
2067         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2068         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2069 };
2070 static const unsigned int du_sync_mux[] = {
2071         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2072 };
2073 static const unsigned int du_oddf_pins[] = {
2074         /* EXDISP/EXODDF/EXCDE */
2075         RCAR_GP_PIN(3, 29),
2076 };
2077 static const unsigned int du_oddf_mux[] = {
2078         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2079 };
2080 static const unsigned int du_cde_pins[] = {
2081         /* CDE */
2082         RCAR_GP_PIN(3, 31),
2083 };
2084 static const unsigned int du_cde_mux[] = {
2085         DU1_CDE_MARK,
2086 };
2087 static const unsigned int du_disp_pins[] = {
2088         /* DISP */
2089         RCAR_GP_PIN(3, 30),
2090 };
2091 static const unsigned int du_disp_mux[] = {
2092         DU1_DISP_MARK,
2093 };
2094 static const unsigned int du0_clk_in_pins[] = {
2095         /* CLKIN */
2096         RCAR_GP_PIN(6, 31),
2097 };
2098 static const unsigned int du0_clk_in_mux[] = {
2099         DU0_DOTCLKIN_MARK
2100 };
2101 static const unsigned int du1_clk_in_pins[] = {
2102         /* CLKIN */
2103         RCAR_GP_PIN(3, 24),
2104 };
2105 static const unsigned int du1_clk_in_mux[] = {
2106         DU1_DOTCLKIN_MARK
2107 };
2108 static const unsigned int du1_clk_in_b_pins[] = {
2109         /* CLKIN */
2110         RCAR_GP_PIN(7, 19),
2111 };
2112 static const unsigned int du1_clk_in_b_mux[] = {
2113         DU1_DOTCLKIN_B_MARK,
2114 };
2115 static const unsigned int du1_clk_in_c_pins[] = {
2116         /* CLKIN */
2117         RCAR_GP_PIN(7, 20),
2118 };
2119 static const unsigned int du1_clk_in_c_mux[] = {
2120         DU1_DOTCLKIN_C_MARK,
2121 };
2122 /* - ETH -------------------------------------------------------------------- */
2123 static const unsigned int eth_link_pins[] = {
2124         /* LINK */
2125         RCAR_GP_PIN(5, 18),
2126 };
2127 static const unsigned int eth_link_mux[] = {
2128         ETH_LINK_MARK,
2129 };
2130 static const unsigned int eth_magic_pins[] = {
2131         /* MAGIC */
2132         RCAR_GP_PIN(5, 22),
2133 };
2134 static const unsigned int eth_magic_mux[] = {
2135         ETH_MAGIC_MARK,
2136 };
2137 static const unsigned int eth_mdio_pins[] = {
2138         /* MDC, MDIO */
2139         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2140 };
2141 static const unsigned int eth_mdio_mux[] = {
2142         ETH_MDC_MARK, ETH_MDIO_MARK,
2143 };
2144 static const unsigned int eth_rmii_pins[] = {
2145         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2146         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2147         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2148         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2149 };
2150 static const unsigned int eth_rmii_mux[] = {
2151         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2152         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2153 };
2154
2155 /* - HSCIF0 ----------------------------------------------------------------- */
2156 static const unsigned int hscif0_data_pins[] = {
2157         /* RX, TX */
2158         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2159 };
2160 static const unsigned int hscif0_data_mux[] = {
2161         HRX0_MARK, HTX0_MARK,
2162 };
2163 static const unsigned int hscif0_clk_pins[] = {
2164         /* SCK */
2165         RCAR_GP_PIN(7, 2),
2166 };
2167 static const unsigned int hscif0_clk_mux[] = {
2168         HSCK0_MARK,
2169 };
2170 static const unsigned int hscif0_ctrl_pins[] = {
2171         /* RTS, CTS */
2172         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2173 };
2174 static const unsigned int hscif0_ctrl_mux[] = {
2175         HRTS0_N_MARK, HCTS0_N_MARK,
2176 };
2177 static const unsigned int hscif0_data_b_pins[] = {
2178         /* RX, TX */
2179         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2180 };
2181 static const unsigned int hscif0_data_b_mux[] = {
2182         HRX0_B_MARK, HTX0_B_MARK,
2183 };
2184 static const unsigned int hscif0_ctrl_b_pins[] = {
2185         /* RTS, CTS */
2186         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2187 };
2188 static const unsigned int hscif0_ctrl_b_mux[] = {
2189         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2190 };
2191 static const unsigned int hscif0_data_c_pins[] = {
2192         /* RX, TX */
2193         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2194 };
2195 static const unsigned int hscif0_data_c_mux[] = {
2196         HRX0_C_MARK, HTX0_C_MARK,
2197 };
2198 static const unsigned int hscif0_clk_c_pins[] = {
2199         /* SCK */
2200         RCAR_GP_PIN(5, 31),
2201 };
2202 static const unsigned int hscif0_clk_c_mux[] = {
2203         HSCK0_C_MARK,
2204 };
2205 /* - HSCIF1 ----------------------------------------------------------------- */
2206 static const unsigned int hscif1_data_pins[] = {
2207         /* RX, TX */
2208         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2209 };
2210 static const unsigned int hscif1_data_mux[] = {
2211         HRX1_MARK, HTX1_MARK,
2212 };
2213 static const unsigned int hscif1_clk_pins[] = {
2214         /* SCK */
2215         RCAR_GP_PIN(7, 7),
2216 };
2217 static const unsigned int hscif1_clk_mux[] = {
2218         HSCK1_MARK,
2219 };
2220 static const unsigned int hscif1_ctrl_pins[] = {
2221         /* RTS, CTS */
2222         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2223 };
2224 static const unsigned int hscif1_ctrl_mux[] = {
2225         HRTS1_N_MARK, HCTS1_N_MARK,
2226 };
2227 static const unsigned int hscif1_data_b_pins[] = {
2228         /* RX, TX */
2229         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2230 };
2231 static const unsigned int hscif1_data_b_mux[] = {
2232         HRX1_B_MARK, HTX1_B_MARK,
2233 };
2234 static const unsigned int hscif1_data_c_pins[] = {
2235         /* RX, TX */
2236         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2237 };
2238 static const unsigned int hscif1_data_c_mux[] = {
2239         HRX1_C_MARK, HTX1_C_MARK,
2240 };
2241 static const unsigned int hscif1_clk_c_pins[] = {
2242         /* SCK */
2243         RCAR_GP_PIN(7, 16),
2244 };
2245 static const unsigned int hscif1_clk_c_mux[] = {
2246         HSCK1_C_MARK,
2247 };
2248 static const unsigned int hscif1_ctrl_c_pins[] = {
2249         /* RTS, CTS */
2250         RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2251 };
2252 static const unsigned int hscif1_ctrl_c_mux[] = {
2253         HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2254 };
2255 static const unsigned int hscif1_data_d_pins[] = {
2256         /* RX, TX */
2257         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2258 };
2259 static const unsigned int hscif1_data_d_mux[] = {
2260         HRX1_D_MARK, HTX1_D_MARK,
2261 };
2262 static const unsigned int hscif1_data_e_pins[] = {
2263         /* RX, TX */
2264         RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2265 };
2266 static const unsigned int hscif1_data_e_mux[] = {
2267         HRX1_C_MARK, HTX1_C_MARK,
2268 };
2269 static const unsigned int hscif1_clk_e_pins[] = {
2270         /* SCK */
2271         RCAR_GP_PIN(2, 6),
2272 };
2273 static const unsigned int hscif1_clk_e_mux[] = {
2274         HSCK1_E_MARK,
2275 };
2276 static const unsigned int hscif1_ctrl_e_pins[] = {
2277         /* RTS, CTS */
2278         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2279 };
2280 static const unsigned int hscif1_ctrl_e_mux[] = {
2281         HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2282 };
2283 /* - HSCIF2 ----------------------------------------------------------------- */
2284 static const unsigned int hscif2_data_pins[] = {
2285         /* RX, TX */
2286         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2287 };
2288 static const unsigned int hscif2_data_mux[] = {
2289         HRX2_MARK, HTX2_MARK,
2290 };
2291 static const unsigned int hscif2_clk_pins[] = {
2292         /* SCK */
2293         RCAR_GP_PIN(4, 15),
2294 };
2295 static const unsigned int hscif2_clk_mux[] = {
2296         HSCK2_MARK,
2297 };
2298 static const unsigned int hscif2_ctrl_pins[] = {
2299         /* RTS, CTS */
2300         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2301 };
2302 static const unsigned int hscif2_ctrl_mux[] = {
2303         HRTS2_N_MARK, HCTS2_N_MARK,
2304 };
2305 static const unsigned int hscif2_data_b_pins[] = {
2306         /* RX, TX */
2307         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2308 };
2309 static const unsigned int hscif2_data_b_mux[] = {
2310         HRX2_B_MARK, HTX2_B_MARK,
2311 };
2312 static const unsigned int hscif2_ctrl_b_pins[] = {
2313         /* RTS, CTS */
2314         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2315 };
2316 static const unsigned int hscif2_ctrl_b_mux[] = {
2317         HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2318 };
2319 static const unsigned int hscif2_data_c_pins[] = {
2320         /* RX, TX */
2321         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2322 };
2323 static const unsigned int hscif2_data_c_mux[] = {
2324         HRX2_C_MARK, HTX2_C_MARK,
2325 };
2326 static const unsigned int hscif2_clk_c_pins[] = {
2327         /* SCK */
2328         RCAR_GP_PIN(5, 31),
2329 };
2330 static const unsigned int hscif2_clk_c_mux[] = {
2331         HSCK2_C_MARK,
2332 };
2333 static const unsigned int hscif2_data_d_pins[] = {
2334         /* RX, TX */
2335         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2336 };
2337 static const unsigned int hscif2_data_d_mux[] = {
2338         HRX2_B_MARK, HTX2_D_MARK,
2339 };
2340 /* - I2C0 ------------------------------------------------------------------- */
2341 static const unsigned int i2c0_pins[] = {
2342         /* SCL, SDA */
2343         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2344 };
2345 static const unsigned int i2c0_mux[] = {
2346         SCL0_MARK, SDA0_MARK,
2347 };
2348 static const unsigned int i2c0_b_pins[] = {
2349         /* SCL, SDA */
2350         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2351 };
2352 static const unsigned int i2c0_b_mux[] = {
2353         SCL0_B_MARK, SDA0_B_MARK,
2354 };
2355 static const unsigned int i2c0_c_pins[] = {
2356         /* SCL, SDA */
2357         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2358 };
2359 static const unsigned int i2c0_c_mux[] = {
2360         SCL0_C_MARK, SDA0_C_MARK,
2361 };
2362 /* - I2C1 ------------------------------------------------------------------- */
2363 static const unsigned int i2c1_pins[] = {
2364         /* SCL, SDA */
2365         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2366 };
2367 static const unsigned int i2c1_mux[] = {
2368         SCL1_MARK, SDA1_MARK,
2369 };
2370 static const unsigned int i2c1_b_pins[] = {
2371         /* SCL, SDA */
2372         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2373 };
2374 static const unsigned int i2c1_b_mux[] = {
2375         SCL1_B_MARK, SDA1_B_MARK,
2376 };
2377 static const unsigned int i2c1_c_pins[] = {
2378         /* SCL, SDA */
2379         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2380 };
2381 static const unsigned int i2c1_c_mux[] = {
2382         SCL1_C_MARK, SDA1_C_MARK,
2383 };
2384 static const unsigned int i2c1_d_pins[] = {
2385         /* SCL, SDA */
2386         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2387 };
2388 static const unsigned int i2c1_d_mux[] = {
2389         SCL1_D_MARK, SDA1_D_MARK,
2390 };
2391 static const unsigned int i2c1_e_pins[] = {
2392         /* SCL, SDA */
2393         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2394 };
2395 static const unsigned int i2c1_e_mux[] = {
2396         SCL1_E_MARK, SDA1_E_MARK,
2397 };
2398 /* - I2C2 ------------------------------------------------------------------- */
2399 static const unsigned int i2c2_pins[] = {
2400         /* SCL, SDA */
2401         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2402 };
2403 static const unsigned int i2c2_mux[] = {
2404         SCL2_MARK, SDA2_MARK,
2405 };
2406 static const unsigned int i2c2_b_pins[] = {
2407         /* SCL, SDA */
2408         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2409 };
2410 static const unsigned int i2c2_b_mux[] = {
2411         SCL2_B_MARK, SDA2_B_MARK,
2412 };
2413 static const unsigned int i2c2_c_pins[] = {
2414         /* SCL, SDA */
2415         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2416 };
2417 static const unsigned int i2c2_c_mux[] = {
2418         SCL2_C_MARK, SDA2_C_MARK,
2419 };
2420 static const unsigned int i2c2_d_pins[] = {
2421         /* SCL, SDA */
2422         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2423 };
2424 static const unsigned int i2c2_d_mux[] = {
2425         SCL2_D_MARK, SDA2_D_MARK,
2426 };
2427 /* - I2C3 ------------------------------------------------------------------- */
2428 static const unsigned int i2c3_pins[] = {
2429         /* SCL, SDA */
2430         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2431 };
2432 static const unsigned int i2c3_mux[] = {
2433         SCL3_MARK, SDA3_MARK,
2434 };
2435 static const unsigned int i2c3_b_pins[] = {
2436         /* SCL, SDA */
2437         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2438 };
2439 static const unsigned int i2c3_b_mux[] = {
2440         SCL3_B_MARK, SDA3_B_MARK,
2441 };
2442 static const unsigned int i2c3_c_pins[] = {
2443         /* SCL, SDA */
2444         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2445 };
2446 static const unsigned int i2c3_c_mux[] = {
2447         SCL3_C_MARK, SDA3_C_MARK,
2448 };
2449 static const unsigned int i2c3_d_pins[] = {
2450         /* SCL, SDA */
2451         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2452 };
2453 static const unsigned int i2c3_d_mux[] = {
2454         SCL3_D_MARK, SDA3_D_MARK,
2455 };
2456 /* - I2C4 ------------------------------------------------------------------- */
2457 static const unsigned int i2c4_pins[] = {
2458         /* SCL, SDA */
2459         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2460 };
2461 static const unsigned int i2c4_mux[] = {
2462         SCL4_MARK, SDA4_MARK,
2463 };
2464 static const unsigned int i2c4_b_pins[] = {
2465         /* SCL, SDA */
2466         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2467 };
2468 static const unsigned int i2c4_b_mux[] = {
2469         SCL4_B_MARK, SDA4_B_MARK,
2470 };
2471 static const unsigned int i2c4_c_pins[] = {
2472         /* SCL, SDA */
2473         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2474 };
2475 static const unsigned int i2c4_c_mux[] = {
2476         SCL4_C_MARK, SDA4_C_MARK,
2477 };
2478 /* - I2C7 ------------------------------------------------------------------- */
2479 static const unsigned int i2c7_pins[] = {
2480         /* SCL, SDA */
2481         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2482 };
2483 static const unsigned int i2c7_mux[] = {
2484         SCL7_MARK, SDA7_MARK,
2485 };
2486 static const unsigned int i2c7_b_pins[] = {
2487         /* SCL, SDA */
2488         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2489 };
2490 static const unsigned int i2c7_b_mux[] = {
2491         SCL7_B_MARK, SDA7_B_MARK,
2492 };
2493 static const unsigned int i2c7_c_pins[] = {
2494         /* SCL, SDA */
2495         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2496 };
2497 static const unsigned int i2c7_c_mux[] = {
2498         SCL7_C_MARK, SDA7_C_MARK,
2499 };
2500 /* - I2C8 ------------------------------------------------------------------- */
2501 static const unsigned int i2c8_pins[] = {
2502         /* SCL, SDA */
2503         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2504 };
2505 static const unsigned int i2c8_mux[] = {
2506         SCL8_MARK, SDA8_MARK,
2507 };
2508 static const unsigned int i2c8_b_pins[] = {
2509         /* SCL, SDA */
2510         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2511 };
2512 static const unsigned int i2c8_b_mux[] = {
2513         SCL8_B_MARK, SDA8_B_MARK,
2514 };
2515 static const unsigned int i2c8_c_pins[] = {
2516         /* SCL, SDA */
2517         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2518 };
2519 static const unsigned int i2c8_c_mux[] = {
2520         SCL8_C_MARK, SDA8_C_MARK,
2521 };
2522 /* - INTC ------------------------------------------------------------------- */
2523 static const unsigned int intc_irq0_pins[] = {
2524         /* IRQ */
2525         RCAR_GP_PIN(7, 10),
2526 };
2527 static const unsigned int intc_irq0_mux[] = {
2528         IRQ0_MARK,
2529 };
2530 static const unsigned int intc_irq1_pins[] = {
2531         /* IRQ */
2532         RCAR_GP_PIN(7, 11),
2533 };
2534 static const unsigned int intc_irq1_mux[] = {
2535         IRQ1_MARK,
2536 };
2537 static const unsigned int intc_irq2_pins[] = {
2538         /* IRQ */
2539         RCAR_GP_PIN(7, 12),
2540 };
2541 static const unsigned int intc_irq2_mux[] = {
2542         IRQ2_MARK,
2543 };
2544 static const unsigned int intc_irq3_pins[] = {
2545         /* IRQ */
2546         RCAR_GP_PIN(7, 13),
2547 };
2548 static const unsigned int intc_irq3_mux[] = {
2549         IRQ3_MARK,
2550 };
2551 /* - MLB+ ------------------------------------------------------------------- */
2552 static const unsigned int mlb_3pin_pins[] = {
2553         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2554 };
2555 static const unsigned int mlb_3pin_mux[] = {
2556         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2557 };
2558 /* - MMCIF ------------------------------------------------------------------ */
2559 static const unsigned int mmc_data1_pins[] = {
2560         /* D[0] */
2561         RCAR_GP_PIN(6, 18),
2562 };
2563 static const unsigned int mmc_data1_mux[] = {
2564         MMC_D0_MARK,
2565 };
2566 static const unsigned int mmc_data4_pins[] = {
2567         /* D[0:3] */
2568         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2569         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2570 };
2571 static const unsigned int mmc_data4_mux[] = {
2572         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2573 };
2574 static const unsigned int mmc_data8_pins[] = {
2575         /* D[0:7] */
2576         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2577         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2578         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2579         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2580 };
2581 static const unsigned int mmc_data8_mux[] = {
2582         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2583         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2584 };
2585 static const unsigned int mmc_ctrl_pins[] = {
2586         /* CLK, CMD */
2587         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2588 };
2589 static const unsigned int mmc_ctrl_mux[] = {
2590         MMC_CLK_MARK, MMC_CMD_MARK,
2591 };
2592 /* - MSIOF0 ----------------------------------------------------------------- */
2593 static const unsigned int msiof0_clk_pins[] = {
2594         /* SCK */
2595         RCAR_GP_PIN(6, 24),
2596 };
2597 static const unsigned int msiof0_clk_mux[] = {
2598         MSIOF0_SCK_MARK,
2599 };
2600 static const unsigned int msiof0_sync_pins[] = {
2601         /* SYNC */
2602         RCAR_GP_PIN(6, 25),
2603 };
2604 static const unsigned int msiof0_sync_mux[] = {
2605         MSIOF0_SYNC_MARK,
2606 };
2607 static const unsigned int msiof0_ss1_pins[] = {
2608         /* SS1 */
2609         RCAR_GP_PIN(6, 28),
2610 };
2611 static const unsigned int msiof0_ss1_mux[] = {
2612         MSIOF0_SS1_MARK,
2613 };
2614 static const unsigned int msiof0_ss2_pins[] = {
2615         /* SS2 */
2616         RCAR_GP_PIN(6, 29),
2617 };
2618 static const unsigned int msiof0_ss2_mux[] = {
2619         MSIOF0_SS2_MARK,
2620 };
2621 static const unsigned int msiof0_rx_pins[] = {
2622         /* RXD */
2623         RCAR_GP_PIN(6, 27),
2624 };
2625 static const unsigned int msiof0_rx_mux[] = {
2626         MSIOF0_RXD_MARK,
2627 };
2628 static const unsigned int msiof0_tx_pins[] = {
2629         /* TXD */
2630         RCAR_GP_PIN(6, 26),
2631 };
2632 static const unsigned int msiof0_tx_mux[] = {
2633         MSIOF0_TXD_MARK,
2634 };
2635
2636 static const unsigned int msiof0_clk_b_pins[] = {
2637         /* SCK */
2638         RCAR_GP_PIN(0, 16),
2639 };
2640 static const unsigned int msiof0_clk_b_mux[] = {
2641         MSIOF0_SCK_B_MARK,
2642 };
2643 static const unsigned int msiof0_sync_b_pins[] = {
2644         /* SYNC */
2645         RCAR_GP_PIN(0, 17),
2646 };
2647 static const unsigned int msiof0_sync_b_mux[] = {
2648         MSIOF0_SYNC_B_MARK,
2649 };
2650 static const unsigned int msiof0_ss1_b_pins[] = {
2651         /* SS1 */
2652         RCAR_GP_PIN(0, 18),
2653 };
2654 static const unsigned int msiof0_ss1_b_mux[] = {
2655         MSIOF0_SS1_B_MARK,
2656 };
2657 static const unsigned int msiof0_ss2_b_pins[] = {
2658         /* SS2 */
2659         RCAR_GP_PIN(0, 19),
2660 };
2661 static const unsigned int msiof0_ss2_b_mux[] = {
2662         MSIOF0_SS2_B_MARK,
2663 };
2664 static const unsigned int msiof0_rx_b_pins[] = {
2665         /* RXD */
2666         RCAR_GP_PIN(0, 21),
2667 };
2668 static const unsigned int msiof0_rx_b_mux[] = {
2669         MSIOF0_RXD_B_MARK,
2670 };
2671 static const unsigned int msiof0_tx_b_pins[] = {
2672         /* TXD */
2673         RCAR_GP_PIN(0, 20),
2674 };
2675 static const unsigned int msiof0_tx_b_mux[] = {
2676         MSIOF0_TXD_B_MARK,
2677 };
2678
2679 static const unsigned int msiof0_clk_c_pins[] = {
2680         /* SCK */
2681         RCAR_GP_PIN(5, 26),
2682 };
2683 static const unsigned int msiof0_clk_c_mux[] = {
2684         MSIOF0_SCK_C_MARK,
2685 };
2686 static const unsigned int msiof0_sync_c_pins[] = {
2687         /* SYNC */
2688         RCAR_GP_PIN(5, 25),
2689 };
2690 static const unsigned int msiof0_sync_c_mux[] = {
2691         MSIOF0_SYNC_C_MARK,
2692 };
2693 static const unsigned int msiof0_ss1_c_pins[] = {
2694         /* SS1 */
2695         RCAR_GP_PIN(5, 27),
2696 };
2697 static const unsigned int msiof0_ss1_c_mux[] = {
2698         MSIOF0_SS1_C_MARK,
2699 };
2700 static const unsigned int msiof0_ss2_c_pins[] = {
2701         /* SS2 */
2702         RCAR_GP_PIN(5, 28),
2703 };
2704 static const unsigned int msiof0_ss2_c_mux[] = {
2705         MSIOF0_SS2_C_MARK,
2706 };
2707 static const unsigned int msiof0_rx_c_pins[] = {
2708         /* RXD */
2709         RCAR_GP_PIN(5, 29),
2710 };
2711 static const unsigned int msiof0_rx_c_mux[] = {
2712         MSIOF0_RXD_C_MARK,
2713 };
2714 static const unsigned int msiof0_tx_c_pins[] = {
2715         /* TXD */
2716         RCAR_GP_PIN(5, 30),
2717 };
2718 static const unsigned int msiof0_tx_c_mux[] = {
2719         MSIOF0_TXD_C_MARK,
2720 };
2721 /* - MSIOF1 ----------------------------------------------------------------- */
2722 static const unsigned int msiof1_clk_pins[] = {
2723         /* SCK */
2724         RCAR_GP_PIN(0, 22),
2725 };
2726 static const unsigned int msiof1_clk_mux[] = {
2727         MSIOF1_SCK_MARK,
2728 };
2729 static const unsigned int msiof1_sync_pins[] = {
2730         /* SYNC */
2731         RCAR_GP_PIN(0, 23),
2732 };
2733 static const unsigned int msiof1_sync_mux[] = {
2734         MSIOF1_SYNC_MARK,
2735 };
2736 static const unsigned int msiof1_ss1_pins[] = {
2737         /* SS1 */
2738         RCAR_GP_PIN(0, 24),
2739 };
2740 static const unsigned int msiof1_ss1_mux[] = {
2741         MSIOF1_SS1_MARK,
2742 };
2743 static const unsigned int msiof1_ss2_pins[] = {
2744         /* SS2 */
2745         RCAR_GP_PIN(0, 25),
2746 };
2747 static const unsigned int msiof1_ss2_mux[] = {
2748         MSIOF1_SS2_MARK,
2749 };
2750 static const unsigned int msiof1_rx_pins[] = {
2751         /* RXD */
2752         RCAR_GP_PIN(0, 27),
2753 };
2754 static const unsigned int msiof1_rx_mux[] = {
2755         MSIOF1_RXD_MARK,
2756 };
2757 static const unsigned int msiof1_tx_pins[] = {
2758         /* TXD */
2759         RCAR_GP_PIN(0, 26),
2760 };
2761 static const unsigned int msiof1_tx_mux[] = {
2762         MSIOF1_TXD_MARK,
2763 };
2764
2765 static const unsigned int msiof1_clk_b_pins[] = {
2766         /* SCK */
2767         RCAR_GP_PIN(2, 29),
2768 };
2769 static const unsigned int msiof1_clk_b_mux[] = {
2770         MSIOF1_SCK_B_MARK,
2771 };
2772 static const unsigned int msiof1_sync_b_pins[] = {
2773         /* SYNC */
2774         RCAR_GP_PIN(2, 30),
2775 };
2776 static const unsigned int msiof1_sync_b_mux[] = {
2777         MSIOF1_SYNC_B_MARK,
2778 };
2779 static const unsigned int msiof1_ss1_b_pins[] = {
2780         /* SS1 */
2781         RCAR_GP_PIN(2, 31),
2782 };
2783 static const unsigned int msiof1_ss1_b_mux[] = {
2784         MSIOF1_SS1_B_MARK,
2785 };
2786 static const unsigned int msiof1_ss2_b_pins[] = {
2787         /* SS2 */
2788         RCAR_GP_PIN(7, 16),
2789 };
2790 static const unsigned int msiof1_ss2_b_mux[] = {
2791         MSIOF1_SS2_B_MARK,
2792 };
2793 static const unsigned int msiof1_rx_b_pins[] = {
2794         /* RXD */
2795         RCAR_GP_PIN(7, 18),
2796 };
2797 static const unsigned int msiof1_rx_b_mux[] = {
2798         MSIOF1_RXD_B_MARK,
2799 };
2800 static const unsigned int msiof1_tx_b_pins[] = {
2801         /* TXD */
2802         RCAR_GP_PIN(7, 17),
2803 };
2804 static const unsigned int msiof1_tx_b_mux[] = {
2805         MSIOF1_TXD_B_MARK,
2806 };
2807
2808 static const unsigned int msiof1_clk_c_pins[] = {
2809         /* SCK */
2810         RCAR_GP_PIN(2, 15),
2811 };
2812 static const unsigned int msiof1_clk_c_mux[] = {
2813         MSIOF1_SCK_C_MARK,
2814 };
2815 static const unsigned int msiof1_sync_c_pins[] = {
2816         /* SYNC */
2817         RCAR_GP_PIN(2, 16),
2818 };
2819 static const unsigned int msiof1_sync_c_mux[] = {
2820         MSIOF1_SYNC_C_MARK,
2821 };
2822 static const unsigned int msiof1_rx_c_pins[] = {
2823         /* RXD */
2824         RCAR_GP_PIN(2, 18),
2825 };
2826 static const unsigned int msiof1_rx_c_mux[] = {
2827         MSIOF1_RXD_C_MARK,
2828 };
2829 static const unsigned int msiof1_tx_c_pins[] = {
2830         /* TXD */
2831         RCAR_GP_PIN(2, 17),
2832 };
2833 static const unsigned int msiof1_tx_c_mux[] = {
2834         MSIOF1_TXD_C_MARK,
2835 };
2836
2837 static const unsigned int msiof1_clk_d_pins[] = {
2838         /* SCK */
2839         RCAR_GP_PIN(0, 28),
2840 };
2841 static const unsigned int msiof1_clk_d_mux[] = {
2842         MSIOF1_SCK_D_MARK,
2843 };
2844 static const unsigned int msiof1_sync_d_pins[] = {
2845         /* SYNC */
2846         RCAR_GP_PIN(0, 30),
2847 };
2848 static const unsigned int msiof1_sync_d_mux[] = {
2849         MSIOF1_SYNC_D_MARK,
2850 };
2851 static const unsigned int msiof1_ss1_d_pins[] = {
2852         /* SS1 */
2853         RCAR_GP_PIN(0, 29),
2854 };
2855 static const unsigned int msiof1_ss1_d_mux[] = {
2856         MSIOF1_SS1_D_MARK,
2857 };
2858 static const unsigned int msiof1_rx_d_pins[] = {
2859         /* RXD */
2860         RCAR_GP_PIN(0, 27),
2861 };
2862 static const unsigned int msiof1_rx_d_mux[] = {
2863         MSIOF1_RXD_D_MARK,
2864 };
2865 static const unsigned int msiof1_tx_d_pins[] = {
2866         /* TXD */
2867         RCAR_GP_PIN(0, 26),
2868 };
2869 static const unsigned int msiof1_tx_d_mux[] = {
2870         MSIOF1_TXD_D_MARK,
2871 };
2872
2873 static const unsigned int msiof1_clk_e_pins[] = {
2874         /* SCK */
2875         RCAR_GP_PIN(5, 18),
2876 };
2877 static const unsigned int msiof1_clk_e_mux[] = {
2878         MSIOF1_SCK_E_MARK,
2879 };
2880 static const unsigned int msiof1_sync_e_pins[] = {
2881         /* SYNC */
2882         RCAR_GP_PIN(5, 19),
2883 };
2884 static const unsigned int msiof1_sync_e_mux[] = {
2885         MSIOF1_SYNC_E_MARK,
2886 };
2887 static const unsigned int msiof1_rx_e_pins[] = {
2888         /* RXD */
2889         RCAR_GP_PIN(5, 17),
2890 };
2891 static const unsigned int msiof1_rx_e_mux[] = {
2892         MSIOF1_RXD_E_MARK,
2893 };
2894 static const unsigned int msiof1_tx_e_pins[] = {
2895         /* TXD */
2896         RCAR_GP_PIN(5, 20),
2897 };
2898 static const unsigned int msiof1_tx_e_mux[] = {
2899         MSIOF1_TXD_E_MARK,
2900 };
2901 /* - MSIOF2 ----------------------------------------------------------------- */
2902 static const unsigned int msiof2_clk_pins[] = {
2903         /* SCK */
2904         RCAR_GP_PIN(1, 13),
2905 };
2906 static const unsigned int msiof2_clk_mux[] = {
2907         MSIOF2_SCK_MARK,
2908 };
2909 static const unsigned int msiof2_sync_pins[] = {
2910         /* SYNC */
2911         RCAR_GP_PIN(1, 14),
2912 };
2913 static const unsigned int msiof2_sync_mux[] = {
2914         MSIOF2_SYNC_MARK,
2915 };
2916 static const unsigned int msiof2_ss1_pins[] = {
2917         /* SS1 */
2918         RCAR_GP_PIN(1, 17),
2919 };
2920 static const unsigned int msiof2_ss1_mux[] = {
2921         MSIOF2_SS1_MARK,
2922 };
2923 static const unsigned int msiof2_ss2_pins[] = {
2924         /* SS2 */
2925         RCAR_GP_PIN(1, 18),
2926 };
2927 static const unsigned int msiof2_ss2_mux[] = {
2928         MSIOF2_SS2_MARK,
2929 };
2930 static const unsigned int msiof2_rx_pins[] = {
2931         /* RXD */
2932         RCAR_GP_PIN(1, 16),
2933 };
2934 static const unsigned int msiof2_rx_mux[] = {
2935         MSIOF2_RXD_MARK,
2936 };
2937 static const unsigned int msiof2_tx_pins[] = {
2938         /* TXD */
2939         RCAR_GP_PIN(1, 15),
2940 };
2941 static const unsigned int msiof2_tx_mux[] = {
2942         MSIOF2_TXD_MARK,
2943 };
2944
2945 static const unsigned int msiof2_clk_b_pins[] = {
2946         /* SCK */
2947         RCAR_GP_PIN(3, 0),
2948 };
2949 static const unsigned int msiof2_clk_b_mux[] = {
2950         MSIOF2_SCK_B_MARK,
2951 };
2952 static const unsigned int msiof2_sync_b_pins[] = {
2953         /* SYNC */
2954         RCAR_GP_PIN(3, 1),
2955 };
2956 static const unsigned int msiof2_sync_b_mux[] = {
2957         MSIOF2_SYNC_B_MARK,
2958 };
2959 static const unsigned int msiof2_ss1_b_pins[] = {
2960         /* SS1 */
2961         RCAR_GP_PIN(3, 8),
2962 };
2963 static const unsigned int msiof2_ss1_b_mux[] = {
2964         MSIOF2_SS1_B_MARK,
2965 };
2966 static const unsigned int msiof2_ss2_b_pins[] = {
2967         /* SS2 */
2968         RCAR_GP_PIN(3, 9),
2969 };
2970 static const unsigned int msiof2_ss2_b_mux[] = {
2971         MSIOF2_SS2_B_MARK,
2972 };
2973 static const unsigned int msiof2_rx_b_pins[] = {
2974         /* RXD */
2975         RCAR_GP_PIN(3, 17),
2976 };
2977 static const unsigned int msiof2_rx_b_mux[] = {
2978         MSIOF2_RXD_B_MARK,
2979 };
2980 static const unsigned int msiof2_tx_b_pins[] = {
2981         /* TXD */
2982         RCAR_GP_PIN(3, 16),
2983 };
2984 static const unsigned int msiof2_tx_b_mux[] = {
2985         MSIOF2_TXD_B_MARK,
2986 };
2987
2988 static const unsigned int msiof2_clk_c_pins[] = {
2989         /* SCK */
2990         RCAR_GP_PIN(2, 2),
2991 };
2992 static const unsigned int msiof2_clk_c_mux[] = {
2993         MSIOF2_SCK_C_MARK,
2994 };
2995 static const unsigned int msiof2_sync_c_pins[] = {
2996         /* SYNC */
2997         RCAR_GP_PIN(2, 3),
2998 };
2999 static const unsigned int msiof2_sync_c_mux[] = {
3000         MSIOF2_SYNC_C_MARK,
3001 };
3002 static const unsigned int msiof2_rx_c_pins[] = {
3003         /* RXD */
3004         RCAR_GP_PIN(2, 5),
3005 };
3006 static const unsigned int msiof2_rx_c_mux[] = {
3007         MSIOF2_RXD_C_MARK,
3008 };
3009 static const unsigned int msiof2_tx_c_pins[] = {
3010         /* TXD */
3011         RCAR_GP_PIN(2, 4),
3012 };
3013 static const unsigned int msiof2_tx_c_mux[] = {
3014         MSIOF2_TXD_C_MARK,
3015 };
3016
3017 static const unsigned int msiof2_clk_d_pins[] = {
3018         /* SCK */
3019         RCAR_GP_PIN(2, 14),
3020 };
3021 static const unsigned int msiof2_clk_d_mux[] = {
3022         MSIOF2_SCK_D_MARK,
3023 };
3024 static const unsigned int msiof2_sync_d_pins[] = {
3025         /* SYNC */
3026         RCAR_GP_PIN(2, 15),
3027 };
3028 static const unsigned int msiof2_sync_d_mux[] = {
3029         MSIOF2_SYNC_D_MARK,
3030 };
3031 static const unsigned int msiof2_ss1_d_pins[] = {
3032         /* SS1 */
3033         RCAR_GP_PIN(2, 17),
3034 };
3035 static const unsigned int msiof2_ss1_d_mux[] = {
3036         MSIOF2_SS1_D_MARK,
3037 };
3038 static const unsigned int msiof2_ss2_d_pins[] = {
3039         /* SS2 */
3040         RCAR_GP_PIN(2, 19),
3041 };
3042 static const unsigned int msiof2_ss2_d_mux[] = {
3043         MSIOF2_SS2_D_MARK,
3044 };
3045 static const unsigned int msiof2_rx_d_pins[] = {
3046         /* RXD */
3047         RCAR_GP_PIN(2, 18),
3048 };
3049 static const unsigned int msiof2_rx_d_mux[] = {
3050         MSIOF2_RXD_D_MARK,
3051 };
3052 static const unsigned int msiof2_tx_d_pins[] = {
3053         /* TXD */
3054         RCAR_GP_PIN(2, 16),
3055 };
3056 static const unsigned int msiof2_tx_d_mux[] = {
3057         MSIOF2_TXD_D_MARK,
3058 };
3059
3060 static const unsigned int msiof2_clk_e_pins[] = {
3061         /* SCK */
3062         RCAR_GP_PIN(7, 15),
3063 };
3064 static const unsigned int msiof2_clk_e_mux[] = {
3065         MSIOF2_SCK_E_MARK,
3066 };
3067 static const unsigned int msiof2_sync_e_pins[] = {
3068         /* SYNC */
3069         RCAR_GP_PIN(7, 16),
3070 };
3071 static const unsigned int msiof2_sync_e_mux[] = {
3072         MSIOF2_SYNC_E_MARK,
3073 };
3074 static const unsigned int msiof2_rx_e_pins[] = {
3075         /* RXD */
3076         RCAR_GP_PIN(7, 14),
3077 };
3078 static const unsigned int msiof2_rx_e_mux[] = {
3079         MSIOF2_RXD_E_MARK,
3080 };
3081 static const unsigned int msiof2_tx_e_pins[] = {
3082         /* TXD */
3083         RCAR_GP_PIN(7, 13),
3084 };
3085 static const unsigned int msiof2_tx_e_mux[] = {
3086         MSIOF2_TXD_E_MARK,
3087 };
3088 /* - PWM -------------------------------------------------------------------- */
3089 static const unsigned int pwm0_pins[] = {
3090         RCAR_GP_PIN(6, 14),
3091 };
3092 static const unsigned int pwm0_mux[] = {
3093         PWM0_MARK,
3094 };
3095 static const unsigned int pwm0_b_pins[] = {
3096         RCAR_GP_PIN(5, 30),
3097 };
3098 static const unsigned int pwm0_b_mux[] = {
3099         PWM0_B_MARK,
3100 };
3101 static const unsigned int pwm1_pins[] = {
3102         RCAR_GP_PIN(1, 17),
3103 };
3104 static const unsigned int pwm1_mux[] = {
3105         PWM1_MARK,
3106 };
3107 static const unsigned int pwm1_b_pins[] = {
3108         RCAR_GP_PIN(6, 15),
3109 };
3110 static const unsigned int pwm1_b_mux[] = {
3111         PWM1_B_MARK,
3112 };
3113 static const unsigned int pwm2_pins[] = {
3114         RCAR_GP_PIN(1, 18),
3115 };
3116 static const unsigned int pwm2_mux[] = {
3117         PWM2_MARK,
3118 };
3119 static const unsigned int pwm2_b_pins[] = {
3120         RCAR_GP_PIN(0, 16),
3121 };
3122 static const unsigned int pwm2_b_mux[] = {
3123         PWM2_B_MARK,
3124 };
3125 static const unsigned int pwm3_pins[] = {
3126         RCAR_GP_PIN(1, 24),
3127 };
3128 static const unsigned int pwm3_mux[] = {
3129         PWM3_MARK,
3130 };
3131 static const unsigned int pwm4_pins[] = {
3132         RCAR_GP_PIN(3, 26),
3133 };
3134 static const unsigned int pwm4_mux[] = {
3135         PWM4_MARK,
3136 };
3137 static const unsigned int pwm4_b_pins[] = {
3138         RCAR_GP_PIN(3, 31),
3139 };
3140 static const unsigned int pwm4_b_mux[] = {
3141         PWM4_B_MARK,
3142 };
3143 static const unsigned int pwm5_pins[] = {
3144         RCAR_GP_PIN(7, 21),
3145 };
3146 static const unsigned int pwm5_mux[] = {
3147         PWM5_MARK,
3148 };
3149 static const unsigned int pwm5_b_pins[] = {
3150         RCAR_GP_PIN(7, 20),
3151 };
3152 static const unsigned int pwm5_b_mux[] = {
3153         PWM5_B_MARK,
3154 };
3155 static const unsigned int pwm6_pins[] = {
3156         RCAR_GP_PIN(7, 22),
3157 };
3158 static const unsigned int pwm6_mux[] = {
3159         PWM6_MARK,
3160 };
3161 /* - QSPI ------------------------------------------------------------------- */
3162 static const unsigned int qspi_ctrl_pins[] = {
3163         /* SPCLK, SSL */
3164         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3165 };
3166 static const unsigned int qspi_ctrl_mux[] = {
3167         SPCLK_MARK, SSL_MARK,
3168 };
3169 static const unsigned int qspi_data2_pins[] = {
3170         /* MOSI_IO0, MISO_IO1 */
3171         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3172 };
3173 static const unsigned int qspi_data2_mux[] = {
3174         MOSI_IO0_MARK, MISO_IO1_MARK,
3175 };
3176 static const unsigned int qspi_data4_pins[] = {
3177         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3178         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3179         RCAR_GP_PIN(1, 8),
3180 };
3181 static const unsigned int qspi_data4_mux[] = {
3182         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3183 };
3184
3185 static const unsigned int qspi_ctrl_b_pins[] = {
3186         /* SPCLK, SSL */
3187         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3188 };
3189 static const unsigned int qspi_ctrl_b_mux[] = {
3190         SPCLK_B_MARK, SSL_B_MARK,
3191 };
3192 static const unsigned int qspi_data2_b_pins[] = {
3193         /* MOSI_IO0, MISO_IO1 */
3194         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3195 };
3196 static const unsigned int qspi_data2_b_mux[] = {
3197         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3198 };
3199 static const unsigned int qspi_data4_b_pins[] = {
3200         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3201         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3202         RCAR_GP_PIN(6, 4),
3203 };
3204 static const unsigned int qspi_data4_b_mux[] = {
3205         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3206         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3207 };
3208 /* - SCIF0 ------------------------------------------------------------------ */
3209 static const unsigned int scif0_data_pins[] = {
3210         /* RX, TX */
3211         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3212 };
3213 static const unsigned int scif0_data_mux[] = {
3214         RX0_MARK, TX0_MARK,
3215 };
3216 static const unsigned int scif0_data_b_pins[] = {
3217         /* RX, TX */
3218         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3219 };
3220 static const unsigned int scif0_data_b_mux[] = {
3221         RX0_B_MARK, TX0_B_MARK,
3222 };
3223 static const unsigned int scif0_data_c_pins[] = {
3224         /* RX, TX */
3225         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3226 };
3227 static const unsigned int scif0_data_c_mux[] = {
3228         RX0_C_MARK, TX0_C_MARK,
3229 };
3230 static const unsigned int scif0_data_d_pins[] = {
3231         /* RX, TX */
3232         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3233 };
3234 static const unsigned int scif0_data_d_mux[] = {
3235         RX0_D_MARK, TX0_D_MARK,
3236 };
3237 static const unsigned int scif0_data_e_pins[] = {
3238         /* RX, TX */
3239         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3240 };
3241 static const unsigned int scif0_data_e_mux[] = {
3242         RX0_E_MARK, TX0_E_MARK,
3243 };
3244 /* - SCIF1 ------------------------------------------------------------------ */
3245 static const unsigned int scif1_data_pins[] = {
3246         /* RX, TX */
3247         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3248 };
3249 static const unsigned int scif1_data_mux[] = {
3250         RX1_MARK, TX1_MARK,
3251 };
3252 static const unsigned int scif1_data_b_pins[] = {
3253         /* RX, TX */
3254         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3255 };
3256 static const unsigned int scif1_data_b_mux[] = {
3257         RX1_B_MARK, TX1_B_MARK,
3258 };
3259 static const unsigned int scif1_clk_b_pins[] = {
3260         /* SCK */
3261         RCAR_GP_PIN(3, 10),
3262 };
3263 static const unsigned int scif1_clk_b_mux[] = {
3264         SCIF1_SCK_B_MARK,
3265 };
3266 static const unsigned int scif1_data_c_pins[] = {
3267         /* RX, TX */
3268         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3269 };
3270 static const unsigned int scif1_data_c_mux[] = {
3271         RX1_C_MARK, TX1_C_MARK,
3272 };
3273 static const unsigned int scif1_data_d_pins[] = {
3274         /* RX, TX */
3275         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3276 };
3277 static const unsigned int scif1_data_d_mux[] = {
3278         RX1_D_MARK, TX1_D_MARK,
3279 };
3280 /* - SCIF2 ------------------------------------------------------------------ */
3281 static const unsigned int scif2_data_pins[] = {
3282         /* RX, TX */
3283         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3284 };
3285 static const unsigned int scif2_data_mux[] = {
3286         RX2_MARK, TX2_MARK,
3287 };
3288 static const unsigned int scif2_data_b_pins[] = {
3289         /* RX, TX */
3290         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3291 };
3292 static const unsigned int scif2_data_b_mux[] = {
3293         RX2_B_MARK, TX2_B_MARK,
3294 };
3295 static const unsigned int scif2_clk_b_pins[] = {
3296         /* SCK */
3297         RCAR_GP_PIN(3, 18),
3298 };
3299 static const unsigned int scif2_clk_b_mux[] = {
3300         SCIF2_SCK_B_MARK,
3301 };
3302 static const unsigned int scif2_data_c_pins[] = {
3303         /* RX, TX */
3304         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3305 };
3306 static const unsigned int scif2_data_c_mux[] = {
3307         RX2_C_MARK, TX2_C_MARK,
3308 };
3309 static const unsigned int scif2_data_e_pins[] = {
3310         /* RX, TX */
3311         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3312 };
3313 static const unsigned int scif2_data_e_mux[] = {
3314         RX2_E_MARK, TX2_E_MARK,
3315 };
3316 /* - SCIF3 ------------------------------------------------------------------ */
3317 static const unsigned int scif3_data_pins[] = {
3318         /* RX, TX */
3319         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3320 };
3321 static const unsigned int scif3_data_mux[] = {
3322         RX3_MARK, TX3_MARK,
3323 };
3324 static const unsigned int scif3_clk_pins[] = {
3325         /* SCK */
3326         RCAR_GP_PIN(3, 23),
3327 };
3328 static const unsigned int scif3_clk_mux[] = {
3329         SCIF3_SCK_MARK,
3330 };
3331 static const unsigned int scif3_data_b_pins[] = {
3332         /* RX, TX */
3333         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3334 };
3335 static const unsigned int scif3_data_b_mux[] = {
3336         RX3_B_MARK, TX3_B_MARK,
3337 };
3338 static const unsigned int scif3_clk_b_pins[] = {
3339         /* SCK */
3340         RCAR_GP_PIN(4, 8),
3341 };
3342 static const unsigned int scif3_clk_b_mux[] = {
3343         SCIF3_SCK_B_MARK,
3344 };
3345 static const unsigned int scif3_data_c_pins[] = {
3346         /* RX, TX */
3347         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3348 };
3349 static const unsigned int scif3_data_c_mux[] = {
3350         RX3_C_MARK, TX3_C_MARK,
3351 };
3352 static const unsigned int scif3_data_d_pins[] = {
3353         /* RX, TX */
3354         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3355 };
3356 static const unsigned int scif3_data_d_mux[] = {
3357         RX3_D_MARK, TX3_D_MARK,
3358 };
3359 /* - SCIF4 ------------------------------------------------------------------ */
3360 static const unsigned int scif4_data_pins[] = {
3361         /* RX, TX */
3362         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3363 };
3364 static const unsigned int scif4_data_mux[] = {
3365         RX4_MARK, TX4_MARK,
3366 };
3367 static const unsigned int scif4_data_b_pins[] = {
3368         /* RX, TX */
3369         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3370 };
3371 static const unsigned int scif4_data_b_mux[] = {
3372         RX4_B_MARK, TX4_B_MARK,
3373 };
3374 static const unsigned int scif4_data_c_pins[] = {
3375         /* RX, TX */
3376         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3377 };
3378 static const unsigned int scif4_data_c_mux[] = {
3379         RX4_C_MARK, TX4_C_MARK,
3380 };
3381 /* - SCIF5 ------------------------------------------------------------------ */
3382 static const unsigned int scif5_data_pins[] = {
3383         /* RX, TX */
3384         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3385 };
3386 static const unsigned int scif5_data_mux[] = {
3387         RX5_MARK, TX5_MARK,
3388 };
3389 static const unsigned int scif5_data_b_pins[] = {
3390         /* RX, TX */
3391         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3392 };
3393 static const unsigned int scif5_data_b_mux[] = {
3394         RX5_B_MARK, TX5_B_MARK,
3395 };
3396 /* - SCIFA0 ----------------------------------------------------------------- */
3397 static const unsigned int scifa0_data_pins[] = {
3398         /* RXD, TXD */
3399         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3400 };
3401 static const unsigned int scifa0_data_mux[] = {
3402         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3403 };
3404 static const unsigned int scifa0_data_b_pins[] = {
3405         /* RXD, TXD */
3406         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3407 };
3408 static const unsigned int scifa0_data_b_mux[] = {
3409         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3410 };
3411 /* - SCIFA1 ----------------------------------------------------------------- */
3412 static const unsigned int scifa1_data_pins[] = {
3413         /* RXD, TXD */
3414         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3415 };
3416 static const unsigned int scifa1_data_mux[] = {
3417         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3418 };
3419 static const unsigned int scifa1_clk_pins[] = {
3420         /* SCK */
3421         RCAR_GP_PIN(3, 10),
3422 };
3423 static const unsigned int scifa1_clk_mux[] = {
3424         SCIFA1_SCK_MARK,
3425 };
3426 static const unsigned int scifa1_data_b_pins[] = {
3427         /* RXD, TXD */
3428         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3429 };
3430 static const unsigned int scifa1_data_b_mux[] = {
3431         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3432 };
3433 static const unsigned int scifa1_clk_b_pins[] = {
3434         /* SCK */
3435         RCAR_GP_PIN(1, 0),
3436 };
3437 static const unsigned int scifa1_clk_b_mux[] = {
3438         SCIFA1_SCK_B_MARK,
3439 };
3440 static const unsigned int scifa1_data_c_pins[] = {
3441         /* RXD, TXD */
3442         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3443 };
3444 static const unsigned int scifa1_data_c_mux[] = {
3445         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3446 };
3447 /* - SCIFA2 ----------------------------------------------------------------- */
3448 static const unsigned int scifa2_data_pins[] = {
3449         /* RXD, TXD */
3450         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3451 };
3452 static const unsigned int scifa2_data_mux[] = {
3453         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3454 };
3455 static const unsigned int scifa2_clk_pins[] = {
3456         /* SCK */
3457         RCAR_GP_PIN(3, 18),
3458 };
3459 static const unsigned int scifa2_clk_mux[] = {
3460         SCIFA2_SCK_MARK,
3461 };
3462 static const unsigned int scifa2_data_b_pins[] = {
3463         /* RXD, TXD */
3464         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3465 };
3466 static const unsigned int scifa2_data_b_mux[] = {
3467         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3468 };
3469 /* - SCIFA3 ----------------------------------------------------------------- */
3470 static const unsigned int scifa3_data_pins[] = {
3471         /* RXD, TXD */
3472         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3473 };
3474 static const unsigned int scifa3_data_mux[] = {
3475         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3476 };
3477 static const unsigned int scifa3_clk_pins[] = {
3478         /* SCK */
3479         RCAR_GP_PIN(3, 23),
3480 };
3481 static const unsigned int scifa3_clk_mux[] = {
3482         SCIFA3_SCK_MARK,
3483 };
3484 static const unsigned int scifa3_data_b_pins[] = {
3485         /* RXD, TXD */
3486         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3487 };
3488 static const unsigned int scifa3_data_b_mux[] = {
3489         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3490 };
3491 static const unsigned int scifa3_clk_b_pins[] = {
3492         /* SCK */
3493         RCAR_GP_PIN(4, 8),
3494 };
3495 static const unsigned int scifa3_clk_b_mux[] = {
3496         SCIFA3_SCK_B_MARK,
3497 };
3498 static const unsigned int scifa3_data_c_pins[] = {
3499         /* RXD, TXD */
3500         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3501 };
3502 static const unsigned int scifa3_data_c_mux[] = {
3503         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3504 };
3505 static const unsigned int scifa3_clk_c_pins[] = {
3506         /* SCK */
3507         RCAR_GP_PIN(7, 22),
3508 };
3509 static const unsigned int scifa3_clk_c_mux[] = {
3510         SCIFA3_SCK_C_MARK,
3511 };
3512 /* - SCIFA4 ----------------------------------------------------------------- */
3513 static const unsigned int scifa4_data_pins[] = {
3514         /* RXD, TXD */
3515         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3516 };
3517 static const unsigned int scifa4_data_mux[] = {
3518         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3519 };
3520 static const unsigned int scifa4_data_b_pins[] = {
3521         /* RXD, TXD */
3522         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3523 };
3524 static const unsigned int scifa4_data_b_mux[] = {
3525         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3526 };
3527 static const unsigned int scifa4_data_c_pins[] = {
3528         /* RXD, TXD */
3529         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3530 };
3531 static const unsigned int scifa4_data_c_mux[] = {
3532         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3533 };
3534 /* - SCIFA5 ----------------------------------------------------------------- */
3535 static const unsigned int scifa5_data_pins[] = {
3536         /* RXD, TXD */
3537         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3538 };
3539 static const unsigned int scifa5_data_mux[] = {
3540         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3541 };
3542 static const unsigned int scifa5_data_b_pins[] = {
3543         /* RXD, TXD */
3544         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3545 };
3546 static const unsigned int scifa5_data_b_mux[] = {
3547         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3548 };
3549 static const unsigned int scifa5_data_c_pins[] = {
3550         /* RXD, TXD */
3551         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3552 };
3553 static const unsigned int scifa5_data_c_mux[] = {
3554         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3555 };
3556 /* - SCIFB0 ----------------------------------------------------------------- */
3557 static const unsigned int scifb0_data_pins[] = {
3558         /* RXD, TXD */
3559         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3560 };
3561 static const unsigned int scifb0_data_mux[] = {
3562         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3563 };
3564 static const unsigned int scifb0_clk_pins[] = {
3565         /* SCK */
3566         RCAR_GP_PIN(7, 2),
3567 };
3568 static const unsigned int scifb0_clk_mux[] = {
3569         SCIFB0_SCK_MARK,
3570 };
3571 static const unsigned int scifb0_ctrl_pins[] = {
3572         /* RTS, CTS */
3573         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3574 };
3575 static const unsigned int scifb0_ctrl_mux[] = {
3576         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3577 };
3578 static const unsigned int scifb0_data_b_pins[] = {
3579         /* RXD, TXD */
3580         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3581 };
3582 static const unsigned int scifb0_data_b_mux[] = {
3583         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3584 };
3585 static const unsigned int scifb0_clk_b_pins[] = {
3586         /* SCK */
3587         RCAR_GP_PIN(5, 31),
3588 };
3589 static const unsigned int scifb0_clk_b_mux[] = {
3590         SCIFB0_SCK_B_MARK,
3591 };
3592 static const unsigned int scifb0_ctrl_b_pins[] = {
3593         /* RTS, CTS */
3594         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3595 };
3596 static const unsigned int scifb0_ctrl_b_mux[] = {
3597         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3598 };
3599 static const unsigned int scifb0_data_c_pins[] = {
3600         /* RXD, TXD */
3601         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3602 };
3603 static const unsigned int scifb0_data_c_mux[] = {
3604         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3605 };
3606 static const unsigned int scifb0_clk_c_pins[] = {
3607         /* SCK */
3608         RCAR_GP_PIN(2, 30),
3609 };
3610 static const unsigned int scifb0_clk_c_mux[] = {
3611         SCIFB0_SCK_C_MARK,
3612 };
3613 static const unsigned int scifb0_data_d_pins[] = {
3614         /* RXD, TXD */
3615         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3616 };
3617 static const unsigned int scifb0_data_d_mux[] = {
3618         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3619 };
3620 static const unsigned int scifb0_clk_d_pins[] = {
3621         /* SCK */
3622         RCAR_GP_PIN(4, 17),
3623 };
3624 static const unsigned int scifb0_clk_d_mux[] = {
3625         SCIFB0_SCK_D_MARK,
3626 };
3627 /* - SCIFB1 ----------------------------------------------------------------- */
3628 static const unsigned int scifb1_data_pins[] = {
3629         /* RXD, TXD */
3630         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3631 };
3632 static const unsigned int scifb1_data_mux[] = {
3633         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3634 };
3635 static const unsigned int scifb1_clk_pins[] = {
3636         /* SCK */
3637         RCAR_GP_PIN(7, 7),
3638 };
3639 static const unsigned int scifb1_clk_mux[] = {
3640         SCIFB1_SCK_MARK,
3641 };
3642 static const unsigned int scifb1_ctrl_pins[] = {
3643         /* RTS, CTS */
3644         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3645 };
3646 static const unsigned int scifb1_ctrl_mux[] = {
3647         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3648 };
3649 static const unsigned int scifb1_data_b_pins[] = {
3650         /* RXD, TXD */
3651         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3652 };
3653 static const unsigned int scifb1_data_b_mux[] = {
3654         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3655 };
3656 static const unsigned int scifb1_clk_b_pins[] = {
3657         /* SCK */
3658         RCAR_GP_PIN(1, 3),
3659 };
3660 static const unsigned int scifb1_clk_b_mux[] = {
3661         SCIFB1_SCK_B_MARK,
3662 };
3663 static const unsigned int scifb1_data_c_pins[] = {
3664         /* RXD, TXD */
3665         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3666 };
3667 static const unsigned int scifb1_data_c_mux[] = {
3668         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3669 };
3670 static const unsigned int scifb1_clk_c_pins[] = {
3671         /* SCK */
3672         RCAR_GP_PIN(7, 11),
3673 };
3674 static const unsigned int scifb1_clk_c_mux[] = {
3675         SCIFB1_SCK_C_MARK,
3676 };
3677 static const unsigned int scifb1_data_d_pins[] = {
3678         /* RXD, TXD */
3679         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3680 };
3681 static const unsigned int scifb1_data_d_mux[] = {
3682         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3683 };
3684 /* - SCIFB2 ----------------------------------------------------------------- */
3685 static const unsigned int scifb2_data_pins[] = {
3686         /* RXD, TXD */
3687         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3688 };
3689 static const unsigned int scifb2_data_mux[] = {
3690         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3691 };
3692 static const unsigned int scifb2_clk_pins[] = {
3693         /* SCK */
3694         RCAR_GP_PIN(4, 15),
3695 };
3696 static const unsigned int scifb2_clk_mux[] = {
3697         SCIFB2_SCK_MARK,
3698 };
3699 static const unsigned int scifb2_ctrl_pins[] = {
3700         /* RTS, CTS */
3701         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3702 };
3703 static const unsigned int scifb2_ctrl_mux[] = {
3704         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3705 };
3706 static const unsigned int scifb2_data_b_pins[] = {
3707         /* RXD, TXD */
3708         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3709 };
3710 static const unsigned int scifb2_data_b_mux[] = {
3711         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3712 };
3713 static const unsigned int scifb2_clk_b_pins[] = {
3714         /* SCK */
3715         RCAR_GP_PIN(5, 31),
3716 };
3717 static const unsigned int scifb2_clk_b_mux[] = {
3718         SCIFB2_SCK_B_MARK,
3719 };
3720 static const unsigned int scifb2_ctrl_b_pins[] = {
3721         /* RTS, CTS */
3722         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3723 };
3724 static const unsigned int scifb2_ctrl_b_mux[] = {
3725         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3726 };
3727 static const unsigned int scifb2_data_c_pins[] = {
3728         /* RXD, TXD */
3729         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3730 };
3731 static const unsigned int scifb2_data_c_mux[] = {
3732         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3733 };
3734 static const unsigned int scifb2_clk_c_pins[] = {
3735         /* SCK */
3736         RCAR_GP_PIN(5, 27),
3737 };
3738 static const unsigned int scifb2_clk_c_mux[] = {
3739         SCIFB2_SCK_C_MARK,
3740 };
3741 static const unsigned int scifb2_data_d_pins[] = {
3742         /* RXD, TXD */
3743         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3744 };
3745 static const unsigned int scifb2_data_d_mux[] = {
3746         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3747 };
3748
3749 /* - SCIF Clock ------------------------------------------------------------- */
3750 static const unsigned int scif_clk_pins[] = {
3751         /* SCIF_CLK */
3752         RCAR_GP_PIN(2, 29),
3753 };
3754 static const unsigned int scif_clk_mux[] = {
3755         SCIF_CLK_MARK,
3756 };
3757 static const unsigned int scif_clk_b_pins[] = {
3758         /* SCIF_CLK */
3759         RCAR_GP_PIN(7, 19),
3760 };
3761 static const unsigned int scif_clk_b_mux[] = {
3762         SCIF_CLK_B_MARK,
3763 };
3764
3765 /* - SDHI0 ------------------------------------------------------------------ */
3766 static const unsigned int sdhi0_data1_pins[] = {
3767         /* D0 */
3768         RCAR_GP_PIN(6, 2),
3769 };
3770 static const unsigned int sdhi0_data1_mux[] = {
3771         SD0_DATA0_MARK,
3772 };
3773 static const unsigned int sdhi0_data4_pins[] = {
3774         /* D[0:3] */
3775         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3776         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3777 };
3778 static const unsigned int sdhi0_data4_mux[] = {
3779         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3780 };
3781 static const unsigned int sdhi0_ctrl_pins[] = {
3782         /* CLK, CMD */
3783         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3784 };
3785 static const unsigned int sdhi0_ctrl_mux[] = {
3786         SD0_CLK_MARK, SD0_CMD_MARK,
3787 };
3788 static const unsigned int sdhi0_cd_pins[] = {
3789         /* CD */
3790         RCAR_GP_PIN(6, 6),
3791 };
3792 static const unsigned int sdhi0_cd_mux[] = {
3793         SD0_CD_MARK,
3794 };
3795 static const unsigned int sdhi0_wp_pins[] = {
3796         /* WP */
3797         RCAR_GP_PIN(6, 7),
3798 };
3799 static const unsigned int sdhi0_wp_mux[] = {
3800         SD0_WP_MARK,
3801 };
3802 /* - SDHI1 ------------------------------------------------------------------ */
3803 static const unsigned int sdhi1_data1_pins[] = {
3804         /* D0 */
3805         RCAR_GP_PIN(6, 10),
3806 };
3807 static const unsigned int sdhi1_data1_mux[] = {
3808         SD1_DATA0_MARK,
3809 };
3810 static const unsigned int sdhi1_data4_pins[] = {
3811         /* D[0:3] */
3812         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3813         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3814 };
3815 static const unsigned int sdhi1_data4_mux[] = {
3816         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3817 };
3818 static const unsigned int sdhi1_ctrl_pins[] = {
3819         /* CLK, CMD */
3820         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3821 };
3822 static const unsigned int sdhi1_ctrl_mux[] = {
3823         SD1_CLK_MARK, SD1_CMD_MARK,
3824 };
3825 static const unsigned int sdhi1_cd_pins[] = {
3826         /* CD */
3827         RCAR_GP_PIN(6, 14),
3828 };
3829 static const unsigned int sdhi1_cd_mux[] = {
3830         SD1_CD_MARK,
3831 };
3832 static const unsigned int sdhi1_wp_pins[] = {
3833         /* WP */
3834         RCAR_GP_PIN(6, 15),
3835 };
3836 static const unsigned int sdhi1_wp_mux[] = {
3837         SD1_WP_MARK,
3838 };
3839 /* - SDHI2 ------------------------------------------------------------------ */
3840 static const unsigned int sdhi2_data1_pins[] = {
3841         /* D0 */
3842         RCAR_GP_PIN(6, 18),
3843 };
3844 static const unsigned int sdhi2_data1_mux[] = {
3845         SD2_DATA0_MARK,
3846 };
3847 static const unsigned int sdhi2_data4_pins[] = {
3848         /* D[0:3] */
3849         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3850         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3851 };
3852 static const unsigned int sdhi2_data4_mux[] = {
3853         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3854 };
3855 static const unsigned int sdhi2_ctrl_pins[] = {
3856         /* CLK, CMD */
3857         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3858 };
3859 static const unsigned int sdhi2_ctrl_mux[] = {
3860         SD2_CLK_MARK, SD2_CMD_MARK,
3861 };
3862 static const unsigned int sdhi2_cd_pins[] = {
3863         /* CD */
3864         RCAR_GP_PIN(6, 22),
3865 };
3866 static const unsigned int sdhi2_cd_mux[] = {
3867         SD2_CD_MARK,
3868 };
3869 static const unsigned int sdhi2_wp_pins[] = {
3870         /* WP */
3871         RCAR_GP_PIN(6, 23),
3872 };
3873 static const unsigned int sdhi2_wp_mux[] = {
3874         SD2_WP_MARK,
3875 };
3876
3877 /* - SSI -------------------------------------------------------------------- */
3878 static const unsigned int ssi0_data_pins[] = {
3879         /* SDATA */
3880         RCAR_GP_PIN(2, 2),
3881 };
3882
3883 static const unsigned int ssi0_data_mux[] = {
3884         SSI_SDATA0_MARK,
3885 };
3886
3887 static const unsigned int ssi0_data_b_pins[] = {
3888         /* SDATA */
3889         RCAR_GP_PIN(3, 4),
3890 };
3891
3892 static const unsigned int ssi0_data_b_mux[] = {
3893         SSI_SDATA0_B_MARK,
3894 };
3895
3896 static const unsigned int ssi0129_ctrl_pins[] = {
3897         /* SCK, WS */
3898         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3899 };
3900
3901 static const unsigned int ssi0129_ctrl_mux[] = {
3902         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3903 };
3904
3905 static const unsigned int ssi0129_ctrl_b_pins[] = {
3906         /* SCK, WS */
3907         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3908 };
3909
3910 static const unsigned int ssi0129_ctrl_b_mux[] = {
3911         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3912 };
3913
3914 static const unsigned int ssi1_data_pins[] = {
3915         /* SDATA */
3916         RCAR_GP_PIN(2, 5),
3917 };
3918
3919 static const unsigned int ssi1_data_mux[] = {
3920         SSI_SDATA1_MARK,
3921 };
3922
3923 static const unsigned int ssi1_data_b_pins[] = {
3924         /* SDATA */
3925         RCAR_GP_PIN(3, 7),
3926 };
3927
3928 static const unsigned int ssi1_data_b_mux[] = {
3929         SSI_SDATA1_B_MARK,
3930 };
3931
3932 static const unsigned int ssi1_ctrl_pins[] = {
3933         /* SCK, WS */
3934         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3935 };
3936
3937 static const unsigned int ssi1_ctrl_mux[] = {
3938         SSI_SCK1_MARK, SSI_WS1_MARK,
3939 };
3940
3941 static const unsigned int ssi1_ctrl_b_pins[] = {
3942         /* SCK, WS */
3943         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3944 };
3945
3946 static const unsigned int ssi1_ctrl_b_mux[] = {
3947         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3948 };
3949
3950 static const unsigned int ssi2_data_pins[] = {
3951         /* SDATA */
3952         RCAR_GP_PIN(2, 8),
3953 };
3954
3955 static const unsigned int ssi2_data_mux[] = {
3956         SSI_SDATA2_MARK,
3957 };
3958
3959 static const unsigned int ssi2_ctrl_pins[] = {
3960         /* SCK, WS */
3961         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3962 };
3963
3964 static const unsigned int ssi2_ctrl_mux[] = {
3965         SSI_SCK2_MARK, SSI_WS2_MARK,
3966 };
3967
3968 static const unsigned int ssi3_data_pins[] = {
3969         /* SDATA */
3970         RCAR_GP_PIN(2, 11),
3971 };
3972
3973 static const unsigned int ssi3_data_mux[] = {
3974         SSI_SDATA3_MARK,
3975 };
3976
3977 static const unsigned int ssi34_ctrl_pins[] = {
3978         /* SCK, WS */
3979         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3980 };
3981
3982 static const unsigned int ssi34_ctrl_mux[] = {
3983         SSI_SCK34_MARK, SSI_WS34_MARK,
3984 };
3985
3986 static const unsigned int ssi4_data_pins[] = {
3987         /* SDATA */
3988         RCAR_GP_PIN(2, 14),
3989 };
3990
3991 static const unsigned int ssi4_data_mux[] = {
3992         SSI_SDATA4_MARK,
3993 };
3994
3995 static const unsigned int ssi4_ctrl_pins[] = {
3996         /* SCK, WS */
3997         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3998 };
3999
4000 static const unsigned int ssi4_ctrl_mux[] = {
4001         SSI_SCK4_MARK, SSI_WS4_MARK,
4002 };
4003
4004 static const unsigned int ssi5_data_pins[] = {
4005         /* SDATA */
4006         RCAR_GP_PIN(2, 17),
4007 };
4008
4009 static const unsigned int ssi5_data_mux[] = {
4010         SSI_SDATA5_MARK,
4011 };
4012
4013 static const unsigned int ssi5_ctrl_pins[] = {
4014         /* SCK, WS */
4015         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4016 };
4017
4018 static const unsigned int ssi5_ctrl_mux[] = {
4019         SSI_SCK5_MARK, SSI_WS5_MARK,
4020 };
4021
4022 static const unsigned int ssi6_data_pins[] = {
4023         /* SDATA */
4024         RCAR_GP_PIN(2, 20),
4025 };
4026
4027 static const unsigned int ssi6_data_mux[] = {
4028         SSI_SDATA6_MARK,
4029 };
4030
4031 static const unsigned int ssi6_ctrl_pins[] = {
4032         /* SCK, WS */
4033         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4034 };
4035
4036 static const unsigned int ssi6_ctrl_mux[] = {
4037         SSI_SCK6_MARK, SSI_WS6_MARK,
4038 };
4039
4040 static const unsigned int ssi7_data_pins[] = {
4041         /* SDATA */
4042         RCAR_GP_PIN(2, 23),
4043 };
4044
4045 static const unsigned int ssi7_data_mux[] = {
4046         SSI_SDATA7_MARK,
4047 };
4048
4049 static const unsigned int ssi7_data_b_pins[] = {
4050         /* SDATA */
4051         RCAR_GP_PIN(3, 12),
4052 };
4053
4054 static const unsigned int ssi7_data_b_mux[] = {
4055         SSI_SDATA7_B_MARK,
4056 };
4057
4058 static const unsigned int ssi78_ctrl_pins[] = {
4059         /* SCK, WS */
4060         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4061 };
4062
4063 static const unsigned int ssi78_ctrl_mux[] = {
4064         SSI_SCK78_MARK, SSI_WS78_MARK,
4065 };
4066
4067 static const unsigned int ssi78_ctrl_b_pins[] = {
4068         /* SCK, WS */
4069         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4070 };
4071
4072 static const unsigned int ssi78_ctrl_b_mux[] = {
4073         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4074 };
4075
4076 static const unsigned int ssi8_data_pins[] = {
4077         /* SDATA */
4078         RCAR_GP_PIN(2, 24),
4079 };
4080
4081 static const unsigned int ssi8_data_mux[] = {
4082         SSI_SDATA8_MARK,
4083 };
4084
4085 static const unsigned int ssi8_data_b_pins[] = {
4086         /* SDATA */
4087         RCAR_GP_PIN(3, 13),
4088 };
4089
4090 static const unsigned int ssi8_data_b_mux[] = {
4091         SSI_SDATA8_B_MARK,
4092 };
4093
4094 static const unsigned int ssi9_data_pins[] = {
4095         /* SDATA */
4096         RCAR_GP_PIN(2, 27),
4097 };
4098
4099 static const unsigned int ssi9_data_mux[] = {
4100         SSI_SDATA9_MARK,
4101 };
4102
4103 static const unsigned int ssi9_data_b_pins[] = {
4104         /* SDATA */
4105         RCAR_GP_PIN(3, 18),
4106 };
4107
4108 static const unsigned int ssi9_data_b_mux[] = {
4109         SSI_SDATA9_B_MARK,
4110 };
4111
4112 static const unsigned int ssi9_ctrl_pins[] = {
4113         /* SCK, WS */
4114         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4115 };
4116
4117 static const unsigned int ssi9_ctrl_mux[] = {
4118         SSI_SCK9_MARK, SSI_WS9_MARK,
4119 };
4120
4121 static const unsigned int ssi9_ctrl_b_pins[] = {
4122         /* SCK, WS */
4123         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4124 };
4125
4126 static const unsigned int ssi9_ctrl_b_mux[] = {
4127         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4128 };
4129
4130 /* - USB0 ------------------------------------------------------------------- */
4131 static const unsigned int usb0_pins[] = {
4132         RCAR_GP_PIN(7, 23), /* PWEN */
4133         RCAR_GP_PIN(7, 24), /* OVC */
4134 };
4135 static const unsigned int usb0_mux[] = {
4136         USB0_PWEN_MARK,
4137         USB0_OVC_MARK,
4138 };
4139 /* - USB1 ------------------------------------------------------------------- */
4140 static const unsigned int usb1_pins[] = {
4141         RCAR_GP_PIN(7, 25), /* PWEN */
4142         RCAR_GP_PIN(6, 30), /* OVC */
4143 };
4144 static const unsigned int usb1_mux[] = {
4145         USB1_PWEN_MARK,
4146         USB1_OVC_MARK,
4147 };
4148 /* - VIN0 ------------------------------------------------------------------- */
4149 static const union vin_data vin0_data_pins = {
4150         .data24 = {
4151                 /* B */
4152                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4153                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4154                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4155                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4156                 /* G */
4157                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4158                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4159                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4160                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4161                 /* R */
4162                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4163                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4164                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4165                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4166         },
4167 };
4168 static const union vin_data vin0_data_mux = {
4169         .data24 = {
4170                 /* B */
4171                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4172                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4173                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4174                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4175                 /* G */
4176                 VI0_G0_MARK, VI0_G1_MARK,
4177                 VI0_G2_MARK, VI0_G3_MARK,
4178                 VI0_G4_MARK, VI0_G5_MARK,
4179                 VI0_G6_MARK, VI0_G7_MARK,
4180                 /* R */
4181                 VI0_R0_MARK, VI0_R1_MARK,
4182                 VI0_R2_MARK, VI0_R3_MARK,
4183                 VI0_R4_MARK, VI0_R5_MARK,
4184                 VI0_R6_MARK, VI0_R7_MARK,
4185         },
4186 };
4187 static const unsigned int vin0_data18_pins[] = {
4188         /* B */
4189         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4190         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4191         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4192         /* G */
4193         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4194         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4195         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4196         /* R */
4197         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4198         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4199         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4200 };
4201 static const unsigned int vin0_data18_mux[] = {
4202         /* B */
4203         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4204         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4205         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4206         /* G */
4207         VI0_G2_MARK, VI0_G3_MARK,
4208         VI0_G4_MARK, VI0_G5_MARK,
4209         VI0_G6_MARK, VI0_G7_MARK,
4210         /* R */
4211         VI0_R2_MARK, VI0_R3_MARK,
4212         VI0_R4_MARK, VI0_R5_MARK,
4213         VI0_R6_MARK, VI0_R7_MARK,
4214 };
4215 static const unsigned int vin0_sync_pins[] = {
4216         RCAR_GP_PIN(4, 3), /* HSYNC */
4217         RCAR_GP_PIN(4, 4), /* VSYNC */
4218 };
4219 static const unsigned int vin0_sync_mux[] = {
4220         VI0_HSYNC_N_MARK,
4221         VI0_VSYNC_N_MARK,
4222 };
4223 static const unsigned int vin0_field_pins[] = {
4224         RCAR_GP_PIN(4, 2),
4225 };
4226 static const unsigned int vin0_field_mux[] = {
4227         VI0_FIELD_MARK,
4228 };
4229 static const unsigned int vin0_clkenb_pins[] = {
4230         RCAR_GP_PIN(4, 1),
4231 };
4232 static const unsigned int vin0_clkenb_mux[] = {
4233         VI0_CLKENB_MARK,
4234 };
4235 static const unsigned int vin0_clk_pins[] = {
4236         RCAR_GP_PIN(4, 0),
4237 };
4238 static const unsigned int vin0_clk_mux[] = {
4239         VI0_CLK_MARK,
4240 };
4241 /* - VIN1 ----------------------------------------------------------------- */
4242 static const unsigned int vin1_data8_pins[] = {
4243         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4244         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4245         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4246         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4247 };
4248 static const unsigned int vin1_data8_mux[] = {
4249         VI1_DATA0_MARK, VI1_DATA1_MARK,
4250         VI1_DATA2_MARK, VI1_DATA3_MARK,
4251         VI1_DATA4_MARK, VI1_DATA5_MARK,
4252         VI1_DATA6_MARK, VI1_DATA7_MARK,
4253 };
4254 static const unsigned int vin1_sync_pins[] = {
4255         RCAR_GP_PIN(5, 0), /* HSYNC */
4256         RCAR_GP_PIN(5, 1), /* VSYNC */
4257 };
4258 static const unsigned int vin1_sync_mux[] = {
4259         VI1_HSYNC_N_MARK,
4260         VI1_VSYNC_N_MARK,
4261 };
4262 static const unsigned int vin1_field_pins[] = {
4263         RCAR_GP_PIN(5, 3),
4264 };
4265 static const unsigned int vin1_field_mux[] = {
4266         VI1_FIELD_MARK,
4267 };
4268 static const unsigned int vin1_clkenb_pins[] = {
4269         RCAR_GP_PIN(5, 2),
4270 };
4271 static const unsigned int vin1_clkenb_mux[] = {
4272         VI1_CLKENB_MARK,
4273 };
4274 static const unsigned int vin1_clk_pins[] = {
4275         RCAR_GP_PIN(5, 4),
4276 };
4277 static const unsigned int vin1_clk_mux[] = {
4278         VI1_CLK_MARK,
4279 };
4280 static const union vin_data vin1_b_data_pins = {
4281         .data24 = {
4282                 /* B */
4283                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4284                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4285                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4286                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4287                 /* G */
4288                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4289                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4290                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4291                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4292                 /* R */
4293                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4294                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4295                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4296                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4297         },
4298 };
4299 static const union vin_data vin1_b_data_mux = {
4300         .data24 = {
4301                 /* B */
4302                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4303                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4304                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4305                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4306                 /* G */
4307                 VI1_G0_B_MARK, VI1_G1_B_MARK,
4308                 VI1_G2_B_MARK, VI1_G3_B_MARK,
4309                 VI1_G4_B_MARK, VI1_G5_B_MARK,
4310                 VI1_G6_B_MARK, VI1_G7_B_MARK,
4311                 /* R */
4312                 VI1_R0_B_MARK, VI1_R1_B_MARK,
4313                 VI1_R2_B_MARK, VI1_R3_B_MARK,
4314                 VI1_R4_B_MARK, VI1_R5_B_MARK,
4315                 VI1_R6_B_MARK, VI1_R7_B_MARK,
4316         },
4317 };
4318 static const unsigned int vin1_b_data18_pins[] = {
4319         /* B */
4320         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4321         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4322         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4323         /* G */
4324         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4325         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4326         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4327         /* R */
4328         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4329         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4330         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4331 };
4332 static const unsigned int vin1_b_data18_mux[] = {
4333         /* B */
4334         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4335         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4336         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4337         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4338         /* G */
4339         VI1_G0_B_MARK, VI1_G1_B_MARK,
4340         VI1_G2_B_MARK, VI1_G3_B_MARK,
4341         VI1_G4_B_MARK, VI1_G5_B_MARK,
4342         VI1_G6_B_MARK, VI1_G7_B_MARK,
4343         /* R */
4344         VI1_R0_B_MARK, VI1_R1_B_MARK,
4345         VI1_R2_B_MARK, VI1_R3_B_MARK,
4346         VI1_R4_B_MARK, VI1_R5_B_MARK,
4347         VI1_R6_B_MARK, VI1_R7_B_MARK,
4348 };
4349 static const unsigned int vin1_b_sync_pins[] = {
4350         RCAR_GP_PIN(3, 17), /* HSYNC */
4351         RCAR_GP_PIN(3, 18), /* VSYNC */
4352 };
4353 static const unsigned int vin1_b_sync_mux[] = {
4354         VI1_HSYNC_N_B_MARK,
4355         VI1_VSYNC_N_B_MARK,
4356 };
4357 static const unsigned int vin1_b_field_pins[] = {
4358         RCAR_GP_PIN(3, 20),
4359 };
4360 static const unsigned int vin1_b_field_mux[] = {
4361         VI1_FIELD_B_MARK,
4362 };
4363 static const unsigned int vin1_b_clkenb_pins[] = {
4364         RCAR_GP_PIN(3, 19),
4365 };
4366 static const unsigned int vin1_b_clkenb_mux[] = {
4367         VI1_CLKENB_B_MARK,
4368 };
4369 static const unsigned int vin1_b_clk_pins[] = {
4370         RCAR_GP_PIN(3, 16),
4371 };
4372 static const unsigned int vin1_b_clk_mux[] = {
4373         VI1_CLK_B_MARK,
4374 };
4375 /* - VIN2 ----------------------------------------------------------------- */
4376 static const unsigned int vin2_data8_pins[] = {
4377         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4378         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4379         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4380         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4381 };
4382 static const unsigned int vin2_data8_mux[] = {
4383         VI2_DATA0_MARK, VI2_DATA1_MARK,
4384         VI2_DATA2_MARK, VI2_DATA3_MARK,
4385         VI2_DATA4_MARK, VI2_DATA5_MARK,
4386         VI2_DATA6_MARK, VI2_DATA7_MARK,
4387 };
4388 static const unsigned int vin2_sync_pins[] = {
4389         RCAR_GP_PIN(4, 15), /* HSYNC */
4390         RCAR_GP_PIN(4, 16), /* VSYNC */
4391 };
4392 static const unsigned int vin2_sync_mux[] = {
4393         VI2_HSYNC_N_MARK,
4394         VI2_VSYNC_N_MARK,
4395 };
4396 static const unsigned int vin2_field_pins[] = {
4397         RCAR_GP_PIN(4, 18),
4398 };
4399 static const unsigned int vin2_field_mux[] = {
4400         VI2_FIELD_MARK,
4401 };
4402 static const unsigned int vin2_clkenb_pins[] = {
4403         RCAR_GP_PIN(4, 17),
4404 };
4405 static const unsigned int vin2_clkenb_mux[] = {
4406         VI2_CLKENB_MARK,
4407 };
4408 static const unsigned int vin2_clk_pins[] = {
4409         RCAR_GP_PIN(4, 19),
4410 };
4411 static const unsigned int vin2_clk_mux[] = {
4412         VI2_CLK_MARK,
4413 };
4414
4415 static const struct sh_pfc_pin_group pinmux_groups[] = {
4416         SH_PFC_PIN_GROUP(adi_common),
4417         SH_PFC_PIN_GROUP(adi_chsel0),
4418         SH_PFC_PIN_GROUP(adi_chsel1),
4419         SH_PFC_PIN_GROUP(adi_chsel2),
4420         SH_PFC_PIN_GROUP(adi_common_b),
4421         SH_PFC_PIN_GROUP(adi_chsel0_b),
4422         SH_PFC_PIN_GROUP(adi_chsel1_b),
4423         SH_PFC_PIN_GROUP(adi_chsel2_b),
4424         SH_PFC_PIN_GROUP(audio_clk_a),
4425         SH_PFC_PIN_GROUP(audio_clk_b),
4426         SH_PFC_PIN_GROUP(audio_clk_b_b),
4427         SH_PFC_PIN_GROUP(audio_clk_c),
4428         SH_PFC_PIN_GROUP(audio_clkout),
4429         SH_PFC_PIN_GROUP(avb_link),
4430         SH_PFC_PIN_GROUP(avb_magic),
4431         SH_PFC_PIN_GROUP(avb_phy_int),
4432         SH_PFC_PIN_GROUP(avb_mdio),
4433         SH_PFC_PIN_GROUP(avb_mii),
4434         SH_PFC_PIN_GROUP(avb_gmii),
4435         SH_PFC_PIN_GROUP(can0_data),
4436         SH_PFC_PIN_GROUP(can0_data_b),
4437         SH_PFC_PIN_GROUP(can0_data_c),
4438         SH_PFC_PIN_GROUP(can0_data_d),
4439         SH_PFC_PIN_GROUP(can0_data_e),
4440         SH_PFC_PIN_GROUP(can0_data_f),
4441         SH_PFC_PIN_GROUP(can1_data),
4442         SH_PFC_PIN_GROUP(can1_data_b),
4443         SH_PFC_PIN_GROUP(can1_data_c),
4444         SH_PFC_PIN_GROUP(can1_data_d),
4445         SH_PFC_PIN_GROUP(can_clk),
4446         SH_PFC_PIN_GROUP(can_clk_b),
4447         SH_PFC_PIN_GROUP(can_clk_c),
4448         SH_PFC_PIN_GROUP(can_clk_d),
4449         SH_PFC_PIN_GROUP(du_rgb666),
4450         SH_PFC_PIN_GROUP(du_rgb888),
4451         SH_PFC_PIN_GROUP(du_clk_out_0),
4452         SH_PFC_PIN_GROUP(du_clk_out_1),
4453         SH_PFC_PIN_GROUP(du_sync),
4454         SH_PFC_PIN_GROUP(du_oddf),
4455         SH_PFC_PIN_GROUP(du_cde),
4456         SH_PFC_PIN_GROUP(du_disp),
4457         SH_PFC_PIN_GROUP(du0_clk_in),
4458         SH_PFC_PIN_GROUP(du1_clk_in),
4459         SH_PFC_PIN_GROUP(du1_clk_in_b),
4460         SH_PFC_PIN_GROUP(du1_clk_in_c),
4461         SH_PFC_PIN_GROUP(eth_link),
4462         SH_PFC_PIN_GROUP(eth_magic),
4463         SH_PFC_PIN_GROUP(eth_mdio),
4464         SH_PFC_PIN_GROUP(eth_rmii),
4465         SH_PFC_PIN_GROUP(hscif0_data),
4466         SH_PFC_PIN_GROUP(hscif0_clk),
4467         SH_PFC_PIN_GROUP(hscif0_ctrl),
4468         SH_PFC_PIN_GROUP(hscif0_data_b),
4469         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4470         SH_PFC_PIN_GROUP(hscif0_data_c),
4471         SH_PFC_PIN_GROUP(hscif0_clk_c),
4472         SH_PFC_PIN_GROUP(hscif1_data),
4473         SH_PFC_PIN_GROUP(hscif1_clk),
4474         SH_PFC_PIN_GROUP(hscif1_ctrl),
4475         SH_PFC_PIN_GROUP(hscif1_data_b),
4476         SH_PFC_PIN_GROUP(hscif1_data_c),
4477         SH_PFC_PIN_GROUP(hscif1_clk_c),
4478         SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4479         SH_PFC_PIN_GROUP(hscif1_data_d),
4480         SH_PFC_PIN_GROUP(hscif1_data_e),
4481         SH_PFC_PIN_GROUP(hscif1_clk_e),
4482         SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4483         SH_PFC_PIN_GROUP(hscif2_data),
4484         SH_PFC_PIN_GROUP(hscif2_clk),
4485         SH_PFC_PIN_GROUP(hscif2_ctrl),
4486         SH_PFC_PIN_GROUP(hscif2_data_b),
4487         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4488         SH_PFC_PIN_GROUP(hscif2_data_c),
4489         SH_PFC_PIN_GROUP(hscif2_clk_c),
4490         SH_PFC_PIN_GROUP(hscif2_data_d),
4491         SH_PFC_PIN_GROUP(i2c0),
4492         SH_PFC_PIN_GROUP(i2c0_b),
4493         SH_PFC_PIN_GROUP(i2c0_c),
4494         SH_PFC_PIN_GROUP(i2c1),
4495         SH_PFC_PIN_GROUP(i2c1_b),
4496         SH_PFC_PIN_GROUP(i2c1_c),
4497         SH_PFC_PIN_GROUP(i2c1_d),
4498         SH_PFC_PIN_GROUP(i2c1_e),
4499         SH_PFC_PIN_GROUP(i2c2),
4500         SH_PFC_PIN_GROUP(i2c2_b),
4501         SH_PFC_PIN_GROUP(i2c2_c),
4502         SH_PFC_PIN_GROUP(i2c2_d),
4503         SH_PFC_PIN_GROUP(i2c3),
4504         SH_PFC_PIN_GROUP(i2c3_b),
4505         SH_PFC_PIN_GROUP(i2c3_c),
4506         SH_PFC_PIN_GROUP(i2c3_d),
4507         SH_PFC_PIN_GROUP(i2c4),
4508         SH_PFC_PIN_GROUP(i2c4_b),
4509         SH_PFC_PIN_GROUP(i2c4_c),
4510         SH_PFC_PIN_GROUP(i2c7),
4511         SH_PFC_PIN_GROUP(i2c7_b),
4512         SH_PFC_PIN_GROUP(i2c7_c),
4513         SH_PFC_PIN_GROUP(i2c8),
4514         SH_PFC_PIN_GROUP(i2c8_b),
4515         SH_PFC_PIN_GROUP(i2c8_c),
4516         SH_PFC_PIN_GROUP(intc_irq0),
4517         SH_PFC_PIN_GROUP(intc_irq1),
4518         SH_PFC_PIN_GROUP(intc_irq2),
4519         SH_PFC_PIN_GROUP(intc_irq3),
4520         SH_PFC_PIN_GROUP(mlb_3pin),
4521         SH_PFC_PIN_GROUP(mmc_data1),
4522         SH_PFC_PIN_GROUP(mmc_data4),
4523         SH_PFC_PIN_GROUP(mmc_data8),
4524         SH_PFC_PIN_GROUP(mmc_ctrl),
4525         SH_PFC_PIN_GROUP(msiof0_clk),
4526         SH_PFC_PIN_GROUP(msiof0_sync),
4527         SH_PFC_PIN_GROUP(msiof0_ss1),
4528         SH_PFC_PIN_GROUP(msiof0_ss2),
4529         SH_PFC_PIN_GROUP(msiof0_rx),
4530         SH_PFC_PIN_GROUP(msiof0_tx),
4531         SH_PFC_PIN_GROUP(msiof0_clk_b),
4532         SH_PFC_PIN_GROUP(msiof0_sync_b),
4533         SH_PFC_PIN_GROUP(msiof0_ss1_b),
4534         SH_PFC_PIN_GROUP(msiof0_ss2_b),
4535         SH_PFC_PIN_GROUP(msiof0_rx_b),
4536         SH_PFC_PIN_GROUP(msiof0_tx_b),
4537         SH_PFC_PIN_GROUP(msiof0_clk_c),
4538         SH_PFC_PIN_GROUP(msiof0_sync_c),
4539         SH_PFC_PIN_GROUP(msiof0_ss1_c),
4540         SH_PFC_PIN_GROUP(msiof0_ss2_c),
4541         SH_PFC_PIN_GROUP(msiof0_rx_c),
4542         SH_PFC_PIN_GROUP(msiof0_tx_c),
4543         SH_PFC_PIN_GROUP(msiof1_clk),
4544         SH_PFC_PIN_GROUP(msiof1_sync),
4545         SH_PFC_PIN_GROUP(msiof1_ss1),
4546         SH_PFC_PIN_GROUP(msiof1_ss2),
4547         SH_PFC_PIN_GROUP(msiof1_rx),
4548         SH_PFC_PIN_GROUP(msiof1_tx),
4549         SH_PFC_PIN_GROUP(msiof1_clk_b),
4550         SH_PFC_PIN_GROUP(msiof1_sync_b),
4551         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4552         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4553         SH_PFC_PIN_GROUP(msiof1_rx_b),
4554         SH_PFC_PIN_GROUP(msiof1_tx_b),
4555         SH_PFC_PIN_GROUP(msiof1_clk_c),
4556         SH_PFC_PIN_GROUP(msiof1_sync_c),
4557         SH_PFC_PIN_GROUP(msiof1_rx_c),
4558         SH_PFC_PIN_GROUP(msiof1_tx_c),
4559         SH_PFC_PIN_GROUP(msiof1_clk_d),
4560         SH_PFC_PIN_GROUP(msiof1_sync_d),
4561         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4562         SH_PFC_PIN_GROUP(msiof1_rx_d),
4563         SH_PFC_PIN_GROUP(msiof1_tx_d),
4564         SH_PFC_PIN_GROUP(msiof1_clk_e),
4565         SH_PFC_PIN_GROUP(msiof1_sync_e),
4566         SH_PFC_PIN_GROUP(msiof1_rx_e),
4567         SH_PFC_PIN_GROUP(msiof1_tx_e),
4568         SH_PFC_PIN_GROUP(msiof2_clk),
4569         SH_PFC_PIN_GROUP(msiof2_sync),
4570         SH_PFC_PIN_GROUP(msiof2_ss1),
4571         SH_PFC_PIN_GROUP(msiof2_ss2),
4572         SH_PFC_PIN_GROUP(msiof2_rx),
4573         SH_PFC_PIN_GROUP(msiof2_tx),
4574         SH_PFC_PIN_GROUP(msiof2_clk_b),
4575         SH_PFC_PIN_GROUP(msiof2_sync_b),
4576         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4577         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4578         SH_PFC_PIN_GROUP(msiof2_rx_b),
4579         SH_PFC_PIN_GROUP(msiof2_tx_b),
4580         SH_PFC_PIN_GROUP(msiof2_clk_c),
4581         SH_PFC_PIN_GROUP(msiof2_sync_c),
4582         SH_PFC_PIN_GROUP(msiof2_rx_c),
4583         SH_PFC_PIN_GROUP(msiof2_tx_c),
4584         SH_PFC_PIN_GROUP(msiof2_clk_d),
4585         SH_PFC_PIN_GROUP(msiof2_sync_d),
4586         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4587         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4588         SH_PFC_PIN_GROUP(msiof2_rx_d),
4589         SH_PFC_PIN_GROUP(msiof2_tx_d),
4590         SH_PFC_PIN_GROUP(msiof2_clk_e),
4591         SH_PFC_PIN_GROUP(msiof2_sync_e),
4592         SH_PFC_PIN_GROUP(msiof2_rx_e),
4593         SH_PFC_PIN_GROUP(msiof2_tx_e),
4594         SH_PFC_PIN_GROUP(pwm0),
4595         SH_PFC_PIN_GROUP(pwm0_b),
4596         SH_PFC_PIN_GROUP(pwm1),
4597         SH_PFC_PIN_GROUP(pwm1_b),
4598         SH_PFC_PIN_GROUP(pwm2),
4599         SH_PFC_PIN_GROUP(pwm2_b),
4600         SH_PFC_PIN_GROUP(pwm3),
4601         SH_PFC_PIN_GROUP(pwm4),
4602         SH_PFC_PIN_GROUP(pwm4_b),
4603         SH_PFC_PIN_GROUP(pwm5),
4604         SH_PFC_PIN_GROUP(pwm5_b),
4605         SH_PFC_PIN_GROUP(pwm6),
4606         SH_PFC_PIN_GROUP(qspi_ctrl),
4607         SH_PFC_PIN_GROUP(qspi_data2),
4608         SH_PFC_PIN_GROUP(qspi_data4),
4609         SH_PFC_PIN_GROUP(qspi_ctrl_b),
4610         SH_PFC_PIN_GROUP(qspi_data2_b),
4611         SH_PFC_PIN_GROUP(qspi_data4_b),
4612         SH_PFC_PIN_GROUP(scif0_data),
4613         SH_PFC_PIN_GROUP(scif0_data_b),
4614         SH_PFC_PIN_GROUP(scif0_data_c),
4615         SH_PFC_PIN_GROUP(scif0_data_d),
4616         SH_PFC_PIN_GROUP(scif0_data_e),
4617         SH_PFC_PIN_GROUP(scif1_data),
4618         SH_PFC_PIN_GROUP(scif1_data_b),
4619         SH_PFC_PIN_GROUP(scif1_clk_b),
4620         SH_PFC_PIN_GROUP(scif1_data_c),
4621         SH_PFC_PIN_GROUP(scif1_data_d),
4622         SH_PFC_PIN_GROUP(scif2_data),
4623         SH_PFC_PIN_GROUP(scif2_data_b),
4624         SH_PFC_PIN_GROUP(scif2_clk_b),
4625         SH_PFC_PIN_GROUP(scif2_data_c),
4626         SH_PFC_PIN_GROUP(scif2_data_e),
4627         SH_PFC_PIN_GROUP(scif3_data),
4628         SH_PFC_PIN_GROUP(scif3_clk),
4629         SH_PFC_PIN_GROUP(scif3_data_b),
4630         SH_PFC_PIN_GROUP(scif3_clk_b),
4631         SH_PFC_PIN_GROUP(scif3_data_c),
4632         SH_PFC_PIN_GROUP(scif3_data_d),
4633         SH_PFC_PIN_GROUP(scif4_data),
4634         SH_PFC_PIN_GROUP(scif4_data_b),
4635         SH_PFC_PIN_GROUP(scif4_data_c),
4636         SH_PFC_PIN_GROUP(scif5_data),
4637         SH_PFC_PIN_GROUP(scif5_data_b),
4638         SH_PFC_PIN_GROUP(scifa0_data),
4639         SH_PFC_PIN_GROUP(scifa0_data_b),
4640         SH_PFC_PIN_GROUP(scifa1_data),
4641         SH_PFC_PIN_GROUP(scifa1_clk),
4642         SH_PFC_PIN_GROUP(scifa1_data_b),
4643         SH_PFC_PIN_GROUP(scifa1_clk_b),
4644         SH_PFC_PIN_GROUP(scifa1_data_c),
4645         SH_PFC_PIN_GROUP(scifa2_data),
4646         SH_PFC_PIN_GROUP(scifa2_clk),
4647         SH_PFC_PIN_GROUP(scifa2_data_b),
4648         SH_PFC_PIN_GROUP(scifa3_data),
4649         SH_PFC_PIN_GROUP(scifa3_clk),
4650         SH_PFC_PIN_GROUP(scifa3_data_b),
4651         SH_PFC_PIN_GROUP(scifa3_clk_b),
4652         SH_PFC_PIN_GROUP(scifa3_data_c),
4653         SH_PFC_PIN_GROUP(scifa3_clk_c),
4654         SH_PFC_PIN_GROUP(scifa4_data),
4655         SH_PFC_PIN_GROUP(scifa4_data_b),
4656         SH_PFC_PIN_GROUP(scifa4_data_c),
4657         SH_PFC_PIN_GROUP(scifa5_data),
4658         SH_PFC_PIN_GROUP(scifa5_data_b),
4659         SH_PFC_PIN_GROUP(scifa5_data_c),
4660         SH_PFC_PIN_GROUP(scifb0_data),
4661         SH_PFC_PIN_GROUP(scifb0_clk),
4662         SH_PFC_PIN_GROUP(scifb0_ctrl),
4663         SH_PFC_PIN_GROUP(scifb0_data_b),
4664         SH_PFC_PIN_GROUP(scifb0_clk_b),
4665         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4666         SH_PFC_PIN_GROUP(scifb0_data_c),
4667         SH_PFC_PIN_GROUP(scifb0_clk_c),
4668         SH_PFC_PIN_GROUP(scifb0_data_d),
4669         SH_PFC_PIN_GROUP(scifb0_clk_d),
4670         SH_PFC_PIN_GROUP(scifb1_data),
4671         SH_PFC_PIN_GROUP(scifb1_clk),
4672         SH_PFC_PIN_GROUP(scifb1_ctrl),
4673         SH_PFC_PIN_GROUP(scifb1_data_b),
4674         SH_PFC_PIN_GROUP(scifb1_clk_b),
4675         SH_PFC_PIN_GROUP(scifb1_data_c),
4676         SH_PFC_PIN_GROUP(scifb1_clk_c),
4677         SH_PFC_PIN_GROUP(scifb1_data_d),
4678         SH_PFC_PIN_GROUP(scifb2_data),
4679         SH_PFC_PIN_GROUP(scifb2_clk),
4680         SH_PFC_PIN_GROUP(scifb2_ctrl),
4681         SH_PFC_PIN_GROUP(scifb2_data_b),
4682         SH_PFC_PIN_GROUP(scifb2_clk_b),
4683         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4684         SH_PFC_PIN_GROUP(scifb2_data_c),
4685         SH_PFC_PIN_GROUP(scifb2_clk_c),
4686         SH_PFC_PIN_GROUP(scifb2_data_d),
4687         SH_PFC_PIN_GROUP(scif_clk),
4688         SH_PFC_PIN_GROUP(scif_clk_b),
4689         SH_PFC_PIN_GROUP(sdhi0_data1),
4690         SH_PFC_PIN_GROUP(sdhi0_data4),
4691         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4692         SH_PFC_PIN_GROUP(sdhi0_cd),
4693         SH_PFC_PIN_GROUP(sdhi0_wp),
4694         SH_PFC_PIN_GROUP(sdhi1_data1),
4695         SH_PFC_PIN_GROUP(sdhi1_data4),
4696         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4697         SH_PFC_PIN_GROUP(sdhi1_cd),
4698         SH_PFC_PIN_GROUP(sdhi1_wp),
4699         SH_PFC_PIN_GROUP(sdhi2_data1),
4700         SH_PFC_PIN_GROUP(sdhi2_data4),
4701         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4702         SH_PFC_PIN_GROUP(sdhi2_cd),
4703         SH_PFC_PIN_GROUP(sdhi2_wp),
4704         SH_PFC_PIN_GROUP(ssi0_data),
4705         SH_PFC_PIN_GROUP(ssi0_data_b),
4706         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4707         SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4708         SH_PFC_PIN_GROUP(ssi1_data),
4709         SH_PFC_PIN_GROUP(ssi1_data_b),
4710         SH_PFC_PIN_GROUP(ssi1_ctrl),
4711         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4712         SH_PFC_PIN_GROUP(ssi2_data),
4713         SH_PFC_PIN_GROUP(ssi2_ctrl),
4714         SH_PFC_PIN_GROUP(ssi3_data),
4715         SH_PFC_PIN_GROUP(ssi34_ctrl),
4716         SH_PFC_PIN_GROUP(ssi4_data),
4717         SH_PFC_PIN_GROUP(ssi4_ctrl),
4718         SH_PFC_PIN_GROUP(ssi5_data),
4719         SH_PFC_PIN_GROUP(ssi5_ctrl),
4720         SH_PFC_PIN_GROUP(ssi6_data),
4721         SH_PFC_PIN_GROUP(ssi6_ctrl),
4722         SH_PFC_PIN_GROUP(ssi7_data),
4723         SH_PFC_PIN_GROUP(ssi7_data_b),
4724         SH_PFC_PIN_GROUP(ssi78_ctrl),
4725         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4726         SH_PFC_PIN_GROUP(ssi8_data),
4727         SH_PFC_PIN_GROUP(ssi8_data_b),
4728         SH_PFC_PIN_GROUP(ssi9_data),
4729         SH_PFC_PIN_GROUP(ssi9_data_b),
4730         SH_PFC_PIN_GROUP(ssi9_ctrl),
4731         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4732         SH_PFC_PIN_GROUP(usb0),
4733         SH_PFC_PIN_GROUP(usb1),
4734         VIN_DATA_PIN_GROUP(vin0_data, 24),
4735         VIN_DATA_PIN_GROUP(vin0_data, 20),
4736         SH_PFC_PIN_GROUP(vin0_data18),
4737         VIN_DATA_PIN_GROUP(vin0_data, 16),
4738         VIN_DATA_PIN_GROUP(vin0_data, 12),
4739         VIN_DATA_PIN_GROUP(vin0_data, 10),
4740         VIN_DATA_PIN_GROUP(vin0_data, 8),
4741         SH_PFC_PIN_GROUP(vin0_sync),
4742         SH_PFC_PIN_GROUP(vin0_field),
4743         SH_PFC_PIN_GROUP(vin0_clkenb),
4744         SH_PFC_PIN_GROUP(vin0_clk),
4745         SH_PFC_PIN_GROUP(vin1_data8),
4746         SH_PFC_PIN_GROUP(vin1_sync),
4747         SH_PFC_PIN_GROUP(vin1_field),
4748         SH_PFC_PIN_GROUP(vin1_clkenb),
4749         SH_PFC_PIN_GROUP(vin1_clk),
4750         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4751         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4752         SH_PFC_PIN_GROUP(vin1_b_data18),
4753         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4754         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4755         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4756         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4757         SH_PFC_PIN_GROUP(vin1_b_sync),
4758         SH_PFC_PIN_GROUP(vin1_b_field),
4759         SH_PFC_PIN_GROUP(vin1_b_clkenb),
4760         SH_PFC_PIN_GROUP(vin1_b_clk),
4761         SH_PFC_PIN_GROUP(vin2_data8),
4762         SH_PFC_PIN_GROUP(vin2_sync),
4763         SH_PFC_PIN_GROUP(vin2_field),
4764         SH_PFC_PIN_GROUP(vin2_clkenb),
4765         SH_PFC_PIN_GROUP(vin2_clk),
4766 };
4767
4768 static const char * const adi_groups[] = {
4769         "adi_common",
4770         "adi_chsel0",
4771         "adi_chsel1",
4772         "adi_chsel2",
4773         "adi_common_b",
4774         "adi_chsel0_b",
4775         "adi_chsel1_b",
4776         "adi_chsel2_b",
4777 };
4778
4779 static const char * const audio_clk_groups[] = {
4780         "audio_clk_a",
4781         "audio_clk_b",
4782         "audio_clk_b_b",
4783         "audio_clk_c",
4784         "audio_clkout",
4785 };
4786
4787 static const char * const avb_groups[] = {
4788         "avb_link",
4789         "avb_magic",
4790         "avb_phy_int",
4791         "avb_mdio",
4792         "avb_mii",
4793         "avb_gmii",
4794 };
4795
4796 static const char * const can0_groups[] = {
4797         "can0_data",
4798         "can0_data_b",
4799         "can0_data_c",
4800         "can0_data_d",
4801         "can0_data_e",
4802         "can0_data_f",
4803         "can_clk",
4804         "can_clk_b",
4805         "can_clk_c",
4806         "can_clk_d",
4807 };
4808
4809 static const char * const can1_groups[] = {
4810         "can1_data",
4811         "can1_data_b",
4812         "can1_data_c",
4813         "can1_data_d",
4814         "can_clk",
4815         "can_clk_b",
4816         "can_clk_c",
4817         "can_clk_d",
4818 };
4819
4820 static const char * const du_groups[] = {
4821         "du_rgb666",
4822         "du_rgb888",
4823         "du_clk_out_0",
4824         "du_clk_out_1",
4825         "du_sync",
4826         "du_oddf",
4827         "du_cde",
4828         "du_disp",
4829 };
4830
4831 static const char * const du0_groups[] = {
4832         "du0_clk_in",
4833 };
4834
4835 static const char * const du1_groups[] = {
4836         "du1_clk_in",
4837         "du1_clk_in_b",
4838         "du1_clk_in_c",
4839 };
4840
4841 static const char * const eth_groups[] = {
4842         "eth_link",
4843         "eth_magic",
4844         "eth_mdio",
4845         "eth_rmii",
4846 };
4847
4848 static const char * const hscif0_groups[] = {
4849         "hscif0_data",
4850         "hscif0_clk",
4851         "hscif0_ctrl",
4852         "hscif0_data_b",
4853         "hscif0_ctrl_b",
4854         "hscif0_data_c",
4855         "hscif0_clk_c",
4856 };
4857
4858 static const char * const hscif1_groups[] = {
4859         "hscif1_data",
4860         "hscif1_clk",
4861         "hscif1_ctrl",
4862         "hscif1_data_b",
4863         "hscif1_data_c",
4864         "hscif1_clk_c",
4865         "hscif1_ctrl_c",
4866         "hscif1_data_d",
4867         "hscif1_data_e",
4868         "hscif1_clk_e",
4869         "hscif1_ctrl_e",
4870 };
4871
4872 static const char * const hscif2_groups[] = {
4873         "hscif2_data",
4874         "hscif2_clk",
4875         "hscif2_ctrl",
4876         "hscif2_data_b",
4877         "hscif2_ctrl_b",
4878         "hscif2_data_c",
4879         "hscif2_clk_c",
4880         "hscif2_data_d",
4881 };
4882
4883 static const char * const i2c0_groups[] = {
4884         "i2c0",
4885         "i2c0_b",
4886         "i2c0_c",
4887 };
4888
4889 static const char * const i2c1_groups[] = {
4890         "i2c1",
4891         "i2c1_b",
4892         "i2c1_c",
4893         "i2c1_d",
4894         "i2c1_e",
4895 };
4896
4897 static const char * const i2c2_groups[] = {
4898         "i2c2",
4899         "i2c2_b",
4900         "i2c2_c",
4901         "i2c2_d",
4902 };
4903
4904 static const char * const i2c3_groups[] = {
4905         "i2c3",
4906         "i2c3_b",
4907         "i2c3_c",
4908         "i2c3_d",
4909 };
4910
4911 static const char * const i2c4_groups[] = {
4912         "i2c4",
4913         "i2c4_b",
4914         "i2c4_c",
4915 };
4916
4917 static const char * const i2c7_groups[] = {
4918         "i2c7",
4919         "i2c7_b",
4920         "i2c7_c",
4921 };
4922
4923 static const char * const i2c8_groups[] = {
4924         "i2c8",
4925         "i2c8_b",
4926         "i2c8_c",
4927 };
4928
4929 static const char * const intc_groups[] = {
4930         "intc_irq0",
4931         "intc_irq1",
4932         "intc_irq2",
4933         "intc_irq3",
4934 };
4935
4936 static const char * const mlb_groups[] = {
4937         "mlb_3pin",
4938 };
4939
4940 static const char * const mmc_groups[] = {
4941         "mmc_data1",
4942         "mmc_data4",
4943         "mmc_data8",
4944         "mmc_ctrl",
4945 };
4946
4947 static const char * const msiof0_groups[] = {
4948         "msiof0_clk",
4949         "msiof0_sync",
4950         "msiof0_ss1",
4951         "msiof0_ss2",
4952         "msiof0_rx",
4953         "msiof0_tx",
4954         "msiof0_clk_b",
4955         "msiof0_sync_b",
4956         "msiof0_ss1_b",
4957         "msiof0_ss2_b",
4958         "msiof0_rx_b",
4959         "msiof0_tx_b",
4960         "msiof0_clk_c",
4961         "msiof0_sync_c",
4962         "msiof0_ss1_c",
4963         "msiof0_ss2_c",
4964         "msiof0_rx_c",
4965         "msiof0_tx_c",
4966 };
4967
4968 static const char * const msiof1_groups[] = {
4969         "msiof1_clk",
4970         "msiof1_sync",
4971         "msiof1_ss1",
4972         "msiof1_ss2",
4973         "msiof1_rx",
4974         "msiof1_tx",
4975         "msiof1_clk_b",
4976         "msiof1_sync_b",
4977         "msiof1_ss1_b",
4978         "msiof1_ss2_b",
4979         "msiof1_rx_b",
4980         "msiof1_tx_b",
4981         "msiof1_clk_c",
4982         "msiof1_sync_c",
4983         "msiof1_rx_c",
4984         "msiof1_tx_c",
4985         "msiof1_clk_d",
4986         "msiof1_sync_d",
4987         "msiof1_ss1_d",
4988         "msiof1_rx_d",
4989         "msiof1_tx_d",
4990         "msiof1_clk_e",
4991         "msiof1_sync_e",
4992         "msiof1_rx_e",
4993         "msiof1_tx_e",
4994 };
4995
4996 static const char * const msiof2_groups[] = {
4997         "msiof2_clk",
4998         "msiof2_sync",
4999         "msiof2_ss1",
5000         "msiof2_ss2",
5001         "msiof2_rx",
5002         "msiof2_tx",
5003         "msiof2_clk_b",
5004         "msiof2_sync_b",
5005         "msiof2_ss1_b",
5006         "msiof2_ss2_b",
5007         "msiof2_rx_b",
5008         "msiof2_tx_b",
5009         "msiof2_clk_c",
5010         "msiof2_sync_c",
5011         "msiof2_rx_c",
5012         "msiof2_tx_c",
5013         "msiof2_clk_d",
5014         "msiof2_sync_d",
5015         "msiof2_ss1_d",
5016         "msiof2_ss2_d",
5017         "msiof2_rx_d",
5018         "msiof2_tx_d",
5019         "msiof2_clk_e",
5020         "msiof2_sync_e",
5021         "msiof2_rx_e",
5022         "msiof2_tx_e",
5023 };
5024
5025 static const char * const pwm0_groups[] = {
5026         "pwm0",
5027         "pwm0_b",
5028 };
5029
5030 static const char * const pwm1_groups[] = {
5031         "pwm1",
5032         "pwm1_b",
5033 };
5034
5035 static const char * const pwm2_groups[] = {
5036         "pwm2",
5037         "pwm2_b",
5038 };
5039
5040 static const char * const pwm3_groups[] = {
5041         "pwm3",
5042 };
5043
5044 static const char * const pwm4_groups[] = {
5045         "pwm4",
5046         "pwm4_b",
5047 };
5048
5049 static const char * const pwm5_groups[] = {
5050         "pwm5",
5051         "pwm5_b",
5052 };
5053
5054 static const char * const pwm6_groups[] = {
5055         "pwm6",
5056 };
5057
5058 static const char * const qspi_groups[] = {
5059         "qspi_ctrl",
5060         "qspi_data2",
5061         "qspi_data4",
5062         "qspi_ctrl_b",
5063         "qspi_data2_b",
5064         "qspi_data4_b",
5065 };
5066
5067 static const char * const scif0_groups[] = {
5068         "scif0_data",
5069         "scif0_data_b",
5070         "scif0_data_c",
5071         "scif0_data_d",
5072         "scif0_data_e",
5073 };
5074
5075 static const char * const scif1_groups[] = {
5076         "scif1_data",
5077         "scif1_data_b",
5078         "scif1_clk_b",
5079         "scif1_data_c",
5080         "scif1_data_d",
5081 };
5082
5083 static const char * const scif2_groups[] = {
5084         "scif2_data",
5085         "scif2_data_b",
5086         "scif2_clk_b",
5087         "scif2_data_c",
5088         "scif2_data_e",
5089 };
5090 static const char * const scif3_groups[] = {
5091         "scif3_data",
5092         "scif3_clk",
5093         "scif3_data_b",
5094         "scif3_clk_b",
5095         "scif3_data_c",
5096         "scif3_data_d",
5097 };
5098 static const char * const scif4_groups[] = {
5099         "scif4_data",
5100         "scif4_data_b",
5101         "scif4_data_c",
5102 };
5103 static const char * const scif5_groups[] = {
5104         "scif5_data",
5105         "scif5_data_b",
5106 };
5107 static const char * const scifa0_groups[] = {
5108         "scifa0_data",
5109         "scifa0_data_b",
5110 };
5111 static const char * const scifa1_groups[] = {
5112         "scifa1_data",
5113         "scifa1_clk",
5114         "scifa1_data_b",
5115         "scifa1_clk_b",
5116         "scifa1_data_c",
5117 };
5118 static const char * const scifa2_groups[] = {
5119         "scifa2_data",
5120         "scifa2_clk",
5121         "scifa2_data_b",
5122 };
5123 static const char * const scifa3_groups[] = {
5124         "scifa3_data",
5125         "scifa3_clk",
5126         "scifa3_data_b",
5127         "scifa3_clk_b",
5128         "scifa3_data_c",
5129         "scifa3_clk_c",
5130 };
5131 static const char * const scifa4_groups[] = {
5132         "scifa4_data",
5133         "scifa4_data_b",
5134         "scifa4_data_c",
5135 };
5136 static const char * const scifa5_groups[] = {
5137         "scifa5_data",
5138         "scifa5_data_b",
5139         "scifa5_data_c",
5140 };
5141 static const char * const scifb0_groups[] = {
5142         "scifb0_data",
5143         "scifb0_clk",
5144         "scifb0_ctrl",
5145         "scifb0_data_b",
5146         "scifb0_clk_b",
5147         "scifb0_ctrl_b",
5148         "scifb0_data_c",
5149         "scifb0_clk_c",
5150         "scifb0_data_d",
5151         "scifb0_clk_d",
5152 };
5153 static const char * const scifb1_groups[] = {
5154         "scifb1_data",
5155         "scifb1_clk",
5156         "scifb1_ctrl",
5157         "scifb1_data_b",
5158         "scifb1_clk_b",
5159         "scifb1_data_c",
5160         "scifb1_clk_c",
5161         "scifb1_data_d",
5162 };
5163 static const char * const scifb2_groups[] = {
5164         "scifb2_data",
5165         "scifb2_clk",
5166         "scifb2_ctrl",
5167         "scifb2_data_b",
5168         "scifb2_clk_b",
5169         "scifb2_ctrl_b",
5170         "scifb0_data_c",
5171         "scifb2_clk_c",
5172         "scifb2_data_d",
5173 };
5174
5175 static const char * const scif_clk_groups[] = {
5176         "scif_clk",
5177         "scif_clk_b",
5178 };
5179
5180 static const char * const sdhi0_groups[] = {
5181         "sdhi0_data1",
5182         "sdhi0_data4",
5183         "sdhi0_ctrl",
5184         "sdhi0_cd",
5185         "sdhi0_wp",
5186 };
5187
5188 static const char * const sdhi1_groups[] = {
5189         "sdhi1_data1",
5190         "sdhi1_data4",
5191         "sdhi1_ctrl",
5192         "sdhi1_cd",
5193         "sdhi1_wp",
5194 };
5195
5196 static const char * const sdhi2_groups[] = {
5197         "sdhi2_data1",
5198         "sdhi2_data4",
5199         "sdhi2_ctrl",
5200         "sdhi2_cd",
5201         "sdhi2_wp",
5202 };
5203
5204 static const char * const ssi_groups[] = {
5205         "ssi0_data",
5206         "ssi0_data_b",
5207         "ssi0129_ctrl",
5208         "ssi0129_ctrl_b",
5209         "ssi1_data",
5210         "ssi1_data_b",
5211         "ssi1_ctrl",
5212         "ssi1_ctrl_b",
5213         "ssi2_data",
5214         "ssi2_ctrl",
5215         "ssi3_data",
5216         "ssi34_ctrl",
5217         "ssi4_data",
5218         "ssi4_ctrl",
5219         "ssi5_data",
5220         "ssi5_ctrl",
5221         "ssi6_data",
5222         "ssi6_ctrl",
5223         "ssi7_data",
5224         "ssi7_data_b",
5225         "ssi78_ctrl",
5226         "ssi78_ctrl_b",
5227         "ssi8_data",
5228         "ssi8_data_b",
5229         "ssi9_data",
5230         "ssi9_data_b",
5231         "ssi9_ctrl",
5232         "ssi9_ctrl_b",
5233 };
5234
5235 static const char * const usb0_groups[] = {
5236         "usb0",
5237 };
5238 static const char * const usb1_groups[] = {
5239         "usb1",
5240 };
5241
5242 static const char * const vin0_groups[] = {
5243         "vin0_data24",
5244         "vin0_data20",
5245         "vin0_data18",
5246         "vin0_data16",
5247         "vin0_data12",
5248         "vin0_data10",
5249         "vin0_data8",
5250         "vin0_sync",
5251         "vin0_field",
5252         "vin0_clkenb",
5253         "vin0_clk",
5254 };
5255
5256 static const char * const vin1_groups[] = {
5257         "vin1_data8",
5258         "vin1_sync",
5259         "vin1_field",
5260         "vin1_clkenb",
5261         "vin1_clk",
5262         "vin1_b_data24",
5263         "vin1_b_data20",
5264         "vin1_b_data18",
5265         "vin1_b_data16",
5266         "vin1_b_data12",
5267         "vin1_b_data10",
5268         "vin1_b_data8",
5269         "vin1_b_sync",
5270         "vin1_b_field",
5271         "vin1_b_clkenb",
5272         "vin1_b_clk",
5273 };
5274
5275 static const char * const vin2_groups[] = {
5276         "vin2_data8",
5277         "vin2_sync",
5278         "vin2_field",
5279         "vin2_clkenb",
5280         "vin2_clk",
5281 };
5282
5283 static const struct sh_pfc_function pinmux_functions[] = {
5284         SH_PFC_FUNCTION(adi),
5285         SH_PFC_FUNCTION(audio_clk),
5286         SH_PFC_FUNCTION(avb),
5287         SH_PFC_FUNCTION(can0),
5288         SH_PFC_FUNCTION(can1),
5289         SH_PFC_FUNCTION(du),
5290         SH_PFC_FUNCTION(du0),
5291         SH_PFC_FUNCTION(du1),
5292         SH_PFC_FUNCTION(eth),
5293         SH_PFC_FUNCTION(hscif0),
5294         SH_PFC_FUNCTION(hscif1),
5295         SH_PFC_FUNCTION(hscif2),
5296         SH_PFC_FUNCTION(i2c0),
5297         SH_PFC_FUNCTION(i2c1),
5298         SH_PFC_FUNCTION(i2c2),
5299         SH_PFC_FUNCTION(i2c3),
5300         SH_PFC_FUNCTION(i2c4),
5301         SH_PFC_FUNCTION(i2c7),
5302         SH_PFC_FUNCTION(i2c8),
5303         SH_PFC_FUNCTION(intc),
5304         SH_PFC_FUNCTION(mlb),
5305         SH_PFC_FUNCTION(mmc),
5306         SH_PFC_FUNCTION(msiof0),
5307         SH_PFC_FUNCTION(msiof1),
5308         SH_PFC_FUNCTION(msiof2),
5309         SH_PFC_FUNCTION(pwm0),
5310         SH_PFC_FUNCTION(pwm1),
5311         SH_PFC_FUNCTION(pwm2),
5312         SH_PFC_FUNCTION(pwm3),
5313         SH_PFC_FUNCTION(pwm4),
5314         SH_PFC_FUNCTION(pwm5),
5315         SH_PFC_FUNCTION(pwm6),
5316         SH_PFC_FUNCTION(qspi),
5317         SH_PFC_FUNCTION(scif0),
5318         SH_PFC_FUNCTION(scif1),
5319         SH_PFC_FUNCTION(scif2),
5320         SH_PFC_FUNCTION(scif3),
5321         SH_PFC_FUNCTION(scif4),
5322         SH_PFC_FUNCTION(scif5),
5323         SH_PFC_FUNCTION(scifa0),
5324         SH_PFC_FUNCTION(scifa1),
5325         SH_PFC_FUNCTION(scifa2),
5326         SH_PFC_FUNCTION(scifa3),
5327         SH_PFC_FUNCTION(scifa4),
5328         SH_PFC_FUNCTION(scifa5),
5329         SH_PFC_FUNCTION(scifb0),
5330         SH_PFC_FUNCTION(scifb1),
5331         SH_PFC_FUNCTION(scifb2),
5332         SH_PFC_FUNCTION(scif_clk),
5333         SH_PFC_FUNCTION(sdhi0),
5334         SH_PFC_FUNCTION(sdhi1),
5335         SH_PFC_FUNCTION(sdhi2),
5336         SH_PFC_FUNCTION(ssi),
5337         SH_PFC_FUNCTION(usb0),
5338         SH_PFC_FUNCTION(usb1),
5339         SH_PFC_FUNCTION(vin0),
5340         SH_PFC_FUNCTION(vin1),
5341         SH_PFC_FUNCTION(vin2),
5342 };
5343
5344 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5345         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5346                 GP_0_31_FN, FN_IP1_22_20,
5347                 GP_0_30_FN, FN_IP1_19_17,
5348                 GP_0_29_FN, FN_IP1_16_14,
5349                 GP_0_28_FN, FN_IP1_13_11,
5350                 GP_0_27_FN, FN_IP1_10_8,
5351                 GP_0_26_FN, FN_IP1_7_6,
5352                 GP_0_25_FN, FN_IP1_5_4,
5353                 GP_0_24_FN, FN_IP1_3_2,
5354                 GP_0_23_FN, FN_IP1_1_0,
5355                 GP_0_22_FN, FN_IP0_30_29,
5356                 GP_0_21_FN, FN_IP0_28_27,
5357                 GP_0_20_FN, FN_IP0_26_25,
5358                 GP_0_19_FN, FN_IP0_24_23,
5359                 GP_0_18_FN, FN_IP0_22_21,
5360                 GP_0_17_FN, FN_IP0_20_19,
5361                 GP_0_16_FN, FN_IP0_18_16,
5362                 GP_0_15_FN, FN_IP0_15,
5363                 GP_0_14_FN, FN_IP0_14,
5364                 GP_0_13_FN, FN_IP0_13,
5365                 GP_0_12_FN, FN_IP0_12,
5366                 GP_0_11_FN, FN_IP0_11,
5367                 GP_0_10_FN, FN_IP0_10,
5368                 GP_0_9_FN, FN_IP0_9,
5369                 GP_0_8_FN, FN_IP0_8,
5370                 GP_0_7_FN, FN_IP0_7,
5371                 GP_0_6_FN, FN_IP0_6,
5372                 GP_0_5_FN, FN_IP0_5,
5373                 GP_0_4_FN, FN_IP0_4,
5374                 GP_0_3_FN, FN_IP0_3,
5375                 GP_0_2_FN, FN_IP0_2,
5376                 GP_0_1_FN, FN_IP0_1,
5377                 GP_0_0_FN, FN_IP0_0, }
5378         },
5379         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5380                 0, 0,
5381                 0, 0,
5382                 0, 0,
5383                 0, 0,
5384                 0, 0,
5385                 0, 0,
5386                 GP_1_25_FN, FN_IP3_21_20,
5387                 GP_1_24_FN, FN_IP3_19_18,
5388                 GP_1_23_FN, FN_IP3_17_16,
5389                 GP_1_22_FN, FN_IP3_15_14,
5390                 GP_1_21_FN, FN_IP3_13_12,
5391                 GP_1_20_FN, FN_IP3_11_9,
5392                 GP_1_19_FN, FN_RD_N,
5393                 GP_1_18_FN, FN_IP3_8_6,
5394                 GP_1_17_FN, FN_IP3_5_3,
5395                 GP_1_16_FN, FN_IP3_2_0,
5396                 GP_1_15_FN, FN_IP2_29_27,
5397                 GP_1_14_FN, FN_IP2_26_25,
5398                 GP_1_13_FN, FN_IP2_24_23,
5399                 GP_1_12_FN, FN_EX_CS0_N,
5400                 GP_1_11_FN, FN_IP2_22_21,
5401                 GP_1_10_FN, FN_IP2_20_19,
5402                 GP_1_9_FN, FN_IP2_18_16,
5403                 GP_1_8_FN, FN_IP2_15_13,
5404                 GP_1_7_FN, FN_IP2_12_10,
5405                 GP_1_6_FN, FN_IP2_9_7,
5406                 GP_1_5_FN, FN_IP2_6_5,
5407                 GP_1_4_FN, FN_IP2_4_3,
5408                 GP_1_3_FN, FN_IP2_2_0,
5409                 GP_1_2_FN, FN_IP1_31_29,
5410                 GP_1_1_FN, FN_IP1_28_26,
5411                 GP_1_0_FN, FN_IP1_25_23, }
5412         },
5413         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5414                 GP_2_31_FN, FN_IP6_7_6,
5415                 GP_2_30_FN, FN_IP6_5_3,
5416                 GP_2_29_FN, FN_IP6_2_0,
5417                 GP_2_28_FN, FN_AUDIO_CLKA,
5418                 GP_2_27_FN, FN_IP5_31_29,
5419                 GP_2_26_FN, FN_IP5_28_26,
5420                 GP_2_25_FN, FN_IP5_25_24,
5421                 GP_2_24_FN, FN_IP5_23_22,
5422                 GP_2_23_FN, FN_IP5_21_20,
5423                 GP_2_22_FN, FN_IP5_19_17,
5424                 GP_2_21_FN, FN_IP5_16_15,
5425                 GP_2_20_FN, FN_IP5_14_12,
5426                 GP_2_19_FN, FN_IP5_11_9,
5427                 GP_2_18_FN, FN_IP5_8_6,
5428                 GP_2_17_FN, FN_IP5_5_3,
5429                 GP_2_16_FN, FN_IP5_2_0,
5430                 GP_2_15_FN, FN_IP4_30_28,
5431                 GP_2_14_FN, FN_IP4_27_26,
5432                 GP_2_13_FN, FN_IP4_25_24,
5433                 GP_2_12_FN, FN_IP4_23_22,
5434                 GP_2_11_FN, FN_IP4_21,
5435                 GP_2_10_FN, FN_IP4_20,
5436                 GP_2_9_FN, FN_IP4_19,
5437                 GP_2_8_FN, FN_IP4_18_16,
5438                 GP_2_7_FN, FN_IP4_15_13,
5439                 GP_2_6_FN, FN_IP4_12_10,
5440                 GP_2_5_FN, FN_IP4_9_8,
5441                 GP_2_4_FN, FN_IP4_7_5,
5442                 GP_2_3_FN, FN_IP4_4_2,
5443                 GP_2_2_FN, FN_IP4_1_0,
5444                 GP_2_1_FN, FN_IP3_30_28,
5445                 GP_2_0_FN, FN_IP3_27_25 }
5446         },
5447         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5448                 GP_3_31_FN, FN_IP9_18_17,
5449                 GP_3_30_FN, FN_IP9_16,
5450                 GP_3_29_FN, FN_IP9_15_13,
5451                 GP_3_28_FN, FN_IP9_12,
5452                 GP_3_27_FN, FN_IP9_11,
5453                 GP_3_26_FN, FN_IP9_10_8,
5454                 GP_3_25_FN, FN_IP9_7,
5455                 GP_3_24_FN, FN_IP9_6,
5456                 GP_3_23_FN, FN_IP9_5_3,
5457                 GP_3_22_FN, FN_IP9_2_0,
5458                 GP_3_21_FN, FN_IP8_30_28,
5459                 GP_3_20_FN, FN_IP8_27_26,
5460                 GP_3_19_FN, FN_IP8_25_24,
5461                 GP_3_18_FN, FN_IP8_23_21,
5462                 GP_3_17_FN, FN_IP8_20_18,
5463                 GP_3_16_FN, FN_IP8_17_15,
5464                 GP_3_15_FN, FN_IP8_14_12,
5465                 GP_3_14_FN, FN_IP8_11_9,
5466                 GP_3_13_FN, FN_IP8_8_6,
5467                 GP_3_12_FN, FN_IP8_5_3,
5468                 GP_3_11_FN, FN_IP8_2_0,
5469                 GP_3_10_FN, FN_IP7_29_27,
5470                 GP_3_9_FN, FN_IP7_26_24,
5471                 GP_3_8_FN, FN_IP7_23_21,
5472                 GP_3_7_FN, FN_IP7_20_19,
5473                 GP_3_6_FN, FN_IP7_18_17,
5474                 GP_3_5_FN, FN_IP7_16_15,
5475                 GP_3_4_FN, FN_IP7_14_13,
5476                 GP_3_3_FN, FN_IP7_12_11,
5477                 GP_3_2_FN, FN_IP7_10_9,
5478                 GP_3_1_FN, FN_IP7_8_6,
5479                 GP_3_0_FN, FN_IP7_5_3 }
5480         },
5481         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5482                 GP_4_31_FN, FN_IP15_5_4,
5483                 GP_4_30_FN, FN_IP15_3_2,
5484                 GP_4_29_FN, FN_IP15_1_0,
5485                 GP_4_28_FN, FN_IP11_8_6,
5486                 GP_4_27_FN, FN_IP11_5_3,
5487                 GP_4_26_FN, FN_IP11_2_0,
5488                 GP_4_25_FN, FN_IP10_31_29,
5489                 GP_4_24_FN, FN_IP10_28_27,
5490                 GP_4_23_FN, FN_IP10_26_25,
5491                 GP_4_22_FN, FN_IP10_24_22,
5492                 GP_4_21_FN, FN_IP10_21_19,
5493                 GP_4_20_FN, FN_IP10_18_17,
5494                 GP_4_19_FN, FN_IP10_16_15,
5495                 GP_4_18_FN, FN_IP10_14_12,
5496                 GP_4_17_FN, FN_IP10_11_9,
5497                 GP_4_16_FN, FN_IP10_8_6,
5498                 GP_4_15_FN, FN_IP10_5_3,
5499                 GP_4_14_FN, FN_IP10_2_0,
5500                 GP_4_13_FN, FN_IP9_31_29,
5501                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5502                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5503                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5504                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5505                 GP_4_8_FN, FN_IP9_28_27,
5506                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5507                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5508                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5509                 GP_4_4_FN, FN_IP9_26_25,
5510                 GP_4_3_FN, FN_IP9_24_23,
5511                 GP_4_2_FN, FN_IP9_22_21,
5512                 GP_4_1_FN, FN_IP9_20_19,
5513                 GP_4_0_FN, FN_VI0_CLK }
5514         },
5515         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5516                 GP_5_31_FN, FN_IP3_24_22,
5517                 GP_5_30_FN, FN_IP13_9_7,
5518                 GP_5_29_FN, FN_IP13_6_5,
5519                 GP_5_28_FN, FN_IP13_4_3,
5520                 GP_5_27_FN, FN_IP13_2_0,
5521                 GP_5_26_FN, FN_IP12_29_27,
5522                 GP_5_25_FN, FN_IP12_26_24,
5523                 GP_5_24_FN, FN_IP12_23_22,
5524                 GP_5_23_FN, FN_IP12_21_20,
5525                 GP_5_22_FN, FN_IP12_19_18,
5526                 GP_5_21_FN, FN_IP12_17_16,
5527                 GP_5_20_FN, FN_IP12_15_13,
5528                 GP_5_19_FN, FN_IP12_12_10,
5529                 GP_5_18_FN, FN_IP12_9_7,
5530                 GP_5_17_FN, FN_IP12_6_4,
5531                 GP_5_16_FN, FN_IP12_3_2,
5532                 GP_5_15_FN, FN_IP12_1_0,
5533                 GP_5_14_FN, FN_IP11_31_30,
5534                 GP_5_13_FN, FN_IP11_29_28,
5535                 GP_5_12_FN, FN_IP11_27,
5536                 GP_5_11_FN, FN_IP11_26,
5537                 GP_5_10_FN, FN_IP11_25,
5538                 GP_5_9_FN, FN_IP11_24,
5539                 GP_5_8_FN, FN_IP11_23,
5540                 GP_5_7_FN, FN_IP11_22,
5541                 GP_5_6_FN, FN_IP11_21,
5542                 GP_5_5_FN, FN_IP11_20,
5543                 GP_5_4_FN, FN_IP11_19,
5544                 GP_5_3_FN, FN_IP11_18_17,
5545                 GP_5_2_FN, FN_IP11_16_15,
5546                 GP_5_1_FN, FN_IP11_14_12,
5547                 GP_5_0_FN, FN_IP11_11_9 }
5548         },
5549         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5550                 GP_6_31_FN, FN_DU0_DOTCLKIN,
5551                 GP_6_30_FN, FN_USB1_OVC,
5552                 GP_6_29_FN, FN_IP14_31_29,
5553                 GP_6_28_FN, FN_IP14_28_26,
5554                 GP_6_27_FN, FN_IP14_25_23,
5555                 GP_6_26_FN, FN_IP14_22_20,
5556                 GP_6_25_FN, FN_IP14_19_17,
5557                 GP_6_24_FN, FN_IP14_16_14,
5558                 GP_6_23_FN, FN_IP14_13_11,
5559                 GP_6_22_FN, FN_IP14_10_8,
5560                 GP_6_21_FN, FN_IP14_7,
5561                 GP_6_20_FN, FN_IP14_6,
5562                 GP_6_19_FN, FN_IP14_5,
5563                 GP_6_18_FN, FN_IP14_4,
5564                 GP_6_17_FN, FN_IP14_3,
5565                 GP_6_16_FN, FN_IP14_2,
5566                 GP_6_15_FN, FN_IP14_1_0,
5567                 GP_6_14_FN, FN_IP13_30_28,
5568                 GP_6_13_FN, FN_IP13_27,
5569                 GP_6_12_FN, FN_IP13_26,
5570                 GP_6_11_FN, FN_IP13_25,
5571                 GP_6_10_FN, FN_IP13_24_23,
5572                 GP_6_9_FN, FN_IP13_22,
5573                 GP_6_8_FN, FN_SD1_CLK,
5574                 GP_6_7_FN, FN_IP13_21_19,
5575                 GP_6_6_FN, FN_IP13_18_16,
5576                 GP_6_5_FN, FN_IP13_15,
5577                 GP_6_4_FN, FN_IP13_14,
5578                 GP_6_3_FN, FN_IP13_13,
5579                 GP_6_2_FN, FN_IP13_12,
5580                 GP_6_1_FN, FN_IP13_11,
5581                 GP_6_0_FN, FN_IP13_10 }
5582         },
5583         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5584                 0, 0,
5585                 0, 0,
5586                 0, 0,
5587                 0, 0,
5588                 0, 0,
5589                 0, 0,
5590                 GP_7_25_FN, FN_USB1_PWEN,
5591                 GP_7_24_FN, FN_USB0_OVC,
5592                 GP_7_23_FN, FN_USB0_PWEN,
5593                 GP_7_22_FN, FN_IP15_14_12,
5594                 GP_7_21_FN, FN_IP15_11_9,
5595                 GP_7_20_FN, FN_IP15_8_6,
5596                 GP_7_19_FN, FN_IP7_2_0,
5597                 GP_7_18_FN, FN_IP6_29_27,
5598                 GP_7_17_FN, FN_IP6_26_24,
5599                 GP_7_16_FN, FN_IP6_23_21,
5600                 GP_7_15_FN, FN_IP6_20_19,
5601                 GP_7_14_FN, FN_IP6_18_16,
5602                 GP_7_13_FN, FN_IP6_15_14,
5603                 GP_7_12_FN, FN_IP6_13_12,
5604                 GP_7_11_FN, FN_IP6_11_10,
5605                 GP_7_10_FN, FN_IP6_9_8,
5606                 GP_7_9_FN, FN_IP16_11_10,
5607                 GP_7_8_FN, FN_IP16_9_8,
5608                 GP_7_7_FN, FN_IP16_7_6,
5609                 GP_7_6_FN, FN_IP16_5_3,
5610                 GP_7_5_FN, FN_IP16_2_0,
5611                 GP_7_4_FN, FN_IP15_29_27,
5612                 GP_7_3_FN, FN_IP15_26_24,
5613                 GP_7_2_FN, FN_IP15_23_21,
5614                 GP_7_1_FN, FN_IP15_20_18,
5615                 GP_7_0_FN, FN_IP15_17_15 }
5616         },
5617         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5618                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5619                              1, 1, 1, 1, 1, 1, 1, 1) {
5620                 /* IP0_31 [1] */
5621                 0, 0,
5622                 /* IP0_30_29 [2] */
5623                 FN_A6, FN_MSIOF1_SCK,
5624                 0, 0,
5625                 /* IP0_28_27 [2] */
5626                 FN_A5, FN_MSIOF0_RXD_B,
5627                 0, 0,
5628                 /* IP0_26_25 [2] */
5629                 FN_A4, FN_MSIOF0_TXD_B,
5630                 0, 0,
5631                 /* IP0_24_23 [2] */
5632                 FN_A3, FN_MSIOF0_SS2_B,
5633                 0, 0,
5634                 /* IP0_22_21 [2] */
5635                 FN_A2, FN_MSIOF0_SS1_B,
5636                 0, 0,
5637                 /* IP0_20_19 [2] */
5638                 FN_A1, FN_MSIOF0_SYNC_B,
5639                 0, 0,
5640                 /* IP0_18_16 [3] */
5641                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
5642                 0, 0, 0,
5643                 /* IP0_15 [1] */
5644                 FN_D15, 0,
5645                 /* IP0_14 [1] */
5646                 FN_D14, 0,
5647                 /* IP0_13 [1] */
5648                 FN_D13, 0,
5649                 /* IP0_12 [1] */
5650                 FN_D12, 0,
5651                 /* IP0_11 [1] */
5652                 FN_D11, 0,
5653                 /* IP0_10 [1] */
5654                 FN_D10, 0,
5655                 /* IP0_9 [1] */
5656                 FN_D9, 0,
5657                 /* IP0_8 [1] */
5658                 FN_D8, 0,
5659                 /* IP0_7 [1] */
5660                 FN_D7, 0,
5661                 /* IP0_6 [1] */
5662                 FN_D6, 0,
5663                 /* IP0_5 [1] */
5664                 FN_D5, 0,
5665                 /* IP0_4 [1] */
5666                 FN_D4, 0,
5667                 /* IP0_3 [1] */
5668                 FN_D3, 0,
5669                 /* IP0_2 [1] */
5670                 FN_D2, 0,
5671                 /* IP0_1 [1] */
5672                 FN_D1, 0,
5673                 /* IP0_0 [1] */
5674                 FN_D0, 0, }
5675         },
5676         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5677                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5678                 /* IP1_31_29 [3] */
5679                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5680                 0, 0, 0,
5681                 /* IP1_28_26 [3] */
5682                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
5683                 0, 0, 0, 0,
5684                 /* IP1_25_23 [3] */
5685                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5686                 0, 0, 0,
5687                 /* IP1_22_20 [3] */
5688                 FN_A15, FN_BPFCLK_C,
5689                 0, 0, 0, 0, 0, 0,
5690                 /* IP1_19_17 [3] */
5691                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5692                 0, 0, 0,
5693                 /* IP1_16_14 [3] */
5694                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5695                 0, 0, 0, 0,
5696                 /* IP1_13_11 [3] */
5697                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
5698                 0, 0, 0, 0,
5699                 /* IP1_10_8 [3] */
5700                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
5701                 0, 0, 0, 0,
5702                 /* IP1_7_6 [2] */
5703                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5704                 /* IP1_5_4 [2] */
5705                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
5706                 /* IP1_3_2 [2] */
5707                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
5708                 /* IP1_1_0 [2] */
5709                 FN_A7, FN_MSIOF1_SYNC,
5710                 0, 0, }
5711         },
5712         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5713                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5714                 /* IP2_31_30 [2] */
5715                 0, 0, 0, 0,
5716                 /* IP2_29_27 [3] */
5717                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5718                 FN_ATAG0_N, 0, FN_EX_WAIT1,
5719                 0, 0,
5720                 /* IP2_26_25 [2] */
5721                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5722                 /* IP2_24_23 [2] */
5723                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5724                 /* IP2_22_21 [2] */
5725                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
5726                 /* IP2_20_19 [2] */
5727                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
5728                 /* IP2_18_16 [3] */
5729                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5730                 0, 0,
5731                 /* IP2_15_13 [3] */
5732                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5733                 0, 0, 0,
5734                 /* IP2_12_10 [3] */
5735                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5736                 0, 0, 0,
5737                 /* IP2_9_7 [3] */
5738                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5739                 0, 0, 0,
5740                 /* IP2_6_5 [2] */
5741                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5742                 /* IP2_4_3 [2] */
5743                 FN_A20, FN_SPCLK, 0, 0,
5744                 /* IP2_2_0 [3] */
5745                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5746                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5747         },
5748         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5749                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5750                 /* IP3_31 [1] */
5751                 0, 0,
5752                 /* IP3_30_28 [3] */
5753                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5754                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5755                 0, 0, 0,
5756                 /* IP3_27_25 [3] */
5757                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5758                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5759                 0, 0, 0,
5760                 /* IP3_24_22 [3] */
5761                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5762                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5763                 /* IP3_21_20 [2] */
5764                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5765                 /* IP3_19_18 [2] */
5766                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5767                 /* IP3_17_16 [2] */
5768                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5769                 /* IP3_15_14 [2] */
5770                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5771                 /* IP3_13_12 [2] */
5772                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5773                 /* IP3_11_9 [3] */
5774                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5775                 0, 0, 0,
5776                 /* IP3_8_6 [3] */
5777                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5778                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5779                 /* IP3_5_3 [3] */
5780                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5781                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5782                 /* IP3_2_0 [3] */
5783                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5784                 0, 0, 0, }
5785         },
5786         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5787                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5788                 /* IP4_31 [1] */
5789                 0, 0,
5790                 /* IP4_30_28 [3] */
5791                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5792                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5793                 0, 0,
5794                 /* IP4_27_26 [2] */
5795                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5796                 /* IP4_25_24 [2] */
5797                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5798                 /* IP4_23_22 [2] */
5799                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5800                 /* IP4_21 [1] */
5801                 FN_SSI_SDATA3, 0,
5802                 /* IP4_20 [1] */
5803                 FN_SSI_WS34, 0,
5804                 /* IP4_19 [1] */
5805                 FN_SSI_SCK34, 0,
5806                 /* IP4_18_16 [3] */
5807                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5808                 0, 0, 0, 0,
5809                 /* IP4_15_13 [3] */
5810                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
5811                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5812                 0, 0,
5813                 /* IP4_12_10 [3] */
5814                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5815                 0, 0, 0,
5816                 /* IP4_9_8 [2] */
5817                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
5818                 /* IP4_7_5 [3] */
5819                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
5820                 0, 0, 0,
5821                 /* IP4_4_2 [3] */
5822                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
5823                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5824                 0, 0, 0,
5825                 /* IP4_1_0 [2] */
5826                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
5827         },
5828         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5829                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5830                 /* IP5_31_29 [3] */
5831                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5832                 0, 0, 0, 0, 0,
5833                 /* IP5_28_26 [3] */
5834                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5835                 0, 0, 0, 0,
5836                 /* IP5_25_24 [2] */
5837                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5838                 /* IP5_23_22 [2] */
5839                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5840                 /* IP5_21_20 [2] */
5841                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5842                 /* IP5_19_17 [3] */
5843                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5844                 0, 0, 0, 0,
5845                 /* IP5_16_15 [2] */
5846                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5847                 /* IP5_14_12 [3] */
5848                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5849                 0, 0, 0, 0,
5850                 /* IP5_11_9 [3] */
5851                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5852                 0, 0, 0, 0,
5853                 /* IP5_8_6 [3] */
5854                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5855                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5856                 0, 0,
5857                 /* IP5_5_3 [3] */
5858                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5859                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5860                 0, 0,
5861                 /* IP5_2_0 [3] */
5862                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5863                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5864                 0, 0, }
5865         },
5866         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5867                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5868                 /* IP6_31_30 [2] */
5869                 0, 0, 0, 0,
5870                 /* IP6_29_27 [3] */
5871                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5872                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5873                 0, 0, 0,
5874                 /* IP6_26_24 [3] */
5875                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5876                 FN_GPS_CLK_C, FN_GPS_CLK_D,
5877                 0, 0, 0,
5878                 /* IP6_23_21 [3] */
5879                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5880                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
5881                 0, 0, 0,
5882                 /* IP6_20_19 [2] */
5883                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
5884                 /* IP6_18_16 [3] */
5885                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
5886                 0, 0, 0,
5887                 /* IP6_15_14 [2] */
5888                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5889                 /* IP6_13_12 [2] */
5890                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5891                 /* IP6_11_10 [2] */
5892                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5893                 /* IP6_9_8 [2] */
5894                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5895                 /* IP6_7_6 [2] */
5896                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5897                 /* IP6_5_3 [3] */
5898                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5899                 FN_SCIFA2_RXD, FN_FMIN_E,
5900                 0, 0,
5901                 /* IP6_2_0 [3] */
5902                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5903                 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5904                 0, 0, }
5905         },
5906         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5907                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5908                 /* IP7_31_30 [2] */
5909                 0, 0, 0, 0,
5910                 /* IP7_29_27 [3] */
5911                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5912                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5913                 0, 0,
5914                 /* IP7_26_24 [3] */
5915                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5916                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5917                 0, 0,
5918                 /* IP7_23_21 [3] */
5919                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5920                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5921                 0, 0,
5922                 /* IP7_20_19 [2] */
5923                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5924                 /* IP7_18_17 [2] */
5925                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5926                 /* IP7_16_15 [2] */
5927                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5928                 /* IP7_14_13 [2] */
5929                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5930                 /* IP7_12_11 [2] */
5931                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5932                 /* IP7_10_9 [2] */
5933                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5934                 /* IP7_8_6 [3] */
5935                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5936                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5937                 0, 0,
5938                 /* IP7_5_3 [3] */
5939                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5940                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5941                 0, 0,
5942                 /* IP7_2_0 [3] */
5943                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5944                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5945                 0, 0, }
5946         },
5947         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5948                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5949                 /* IP8_31 [1] */
5950                 0, 0,
5951                 /* IP8_30_28 [3] */
5952                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5953                 0, 0, 0,
5954                 /* IP8_27_26 [2] */
5955                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5956                 /* IP8_25_24 [2] */
5957                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5958                 /* IP8_23_21 [3] */
5959                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5960                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5961                 0, 0,
5962                 /* IP8_20_18 [3] */
5963                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5964                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
5965                 0, 0,
5966                 /* IP8_17_15 [3] */
5967                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
5968                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
5969                 0, 0,
5970                 /* IP8_14_12 [3] */
5971                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
5972                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
5973                 0, 0, 0,
5974                 /* IP8_11_9 [3] */
5975                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
5976                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
5977                 0, 0, 0,
5978                 /* IP8_8_6 [3] */
5979                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
5980                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
5981                 0, 0,
5982                 /* IP8_5_3 [3] */
5983                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
5984                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
5985                 0, 0,
5986                 /* IP8_2_0 [3] */
5987                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
5988                 0, 0, 0, }
5989         },
5990         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5991                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
5992                 /* IP9_31_29 [3] */
5993                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
5994                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
5995                 /* IP9_28_27 [2] */
5996                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
5997                 /* IP9_26_25 [2] */
5998                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
5999                 /* IP9_24_23 [2] */
6000                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6001                 /* IP9_22_21 [2] */
6002                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6003                 /* IP9_20_19 [2] */
6004                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6005                 /* IP9_18_17 [2] */
6006                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6007                 /* IP9_16 [1] */
6008                 FN_DU1_DISP, FN_QPOLA,
6009                 /* IP9_15_13 [3] */
6010                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6011                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
6012                 0, 0, 0,
6013                 /* IP9_12 [1] */
6014                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6015                 /* IP9_11 [1] */
6016                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6017                 /* IP9_10_8 [3] */
6018                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6019                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
6020                 0, 0,
6021                 /* IP9_7 [1] */
6022                 FN_DU1_DOTCLKOUT0, FN_QCLK,
6023                 /* IP9_6 [1] */
6024                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6025                 /* IP9_5_3 [3] */
6026                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
6027                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6028                 0, 0, 0,
6029                 /* IP9_2_0 [3] */
6030                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
6031                 0, 0, 0, }
6032         },
6033         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6034                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
6035                 /* IP10_31_29 [3] */
6036                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
6037                 0, 0, 0,
6038                 /* IP10_28_27 [2] */
6039                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6040                 /* IP10_26_25 [2] */
6041                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6042                 /* IP10_24_22 [3] */
6043                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6044                 0, 0, 0,
6045                 /* IP10_21_19 [3] */
6046                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6047                 FN_TS_SDATA0_C, FN_ATACS11_N,
6048                 0, 0, 0,
6049                 /* IP10_18_17 [2] */
6050                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6051                 /* IP10_16_15 [2] */
6052                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6053                 /* IP10_14_12 [3] */
6054                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6055                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6056                 /* IP10_11_9 [3] */
6057                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6058                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6059                 0, 0,
6060                 /* IP10_8_6 [3] */
6061                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
6062                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6063                 /* IP10_5_3 [3] */
6064                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
6065                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6066                 /* IP10_2_0 [3] */
6067                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
6068                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
6069         },
6070         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6071                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
6072                              3, 3, 3, 3, 3) {
6073                 /* IP11_31_30 [2] */
6074                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
6075                 /* IP11_29_28 [2] */
6076                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
6077                 /* IP11_27 [1] */
6078                 FN_VI1_DATA7, FN_AVB_MDC,
6079                 /* IP11_26 [1] */
6080                 FN_VI1_DATA6, FN_AVB_MAGIC,
6081                 /* IP11_25 [1] */
6082                 FN_VI1_DATA5, FN_AVB_RX_DV,
6083                 /* IP11_24 [1] */
6084                 FN_VI1_DATA4, FN_AVB_MDIO,
6085                 /* IP11_23 [1] */
6086                 FN_VI1_DATA3, FN_AVB_RX_ER,
6087                 /* IP11_22 [1] */
6088                 FN_VI1_DATA2, FN_AVB_RXD7,
6089                 /* IP11_21 [1] */
6090                 FN_VI1_DATA1, FN_AVB_RXD6,
6091                 /* IP11_20 [1] */
6092                 FN_VI1_DATA0, FN_AVB_RXD5,
6093                 /* IP11_19 [1] */
6094                 FN_VI1_CLK, FN_AVB_RXD4,
6095                 /* IP11_18_17 [2] */
6096                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6097                 /* IP11_16_15 [2] */
6098                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6099                 /* IP11_14_12 [3] */
6100                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6101                 FN_RX4_B, FN_SCIFA4_RXD_B,
6102                 0, 0, 0,
6103                 /* IP11_11_9 [3] */
6104                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6105                 FN_TX4_B, FN_SCIFA4_TXD_B,
6106                 0, 0, 0,
6107                 /* IP11_8_6 [3] */
6108                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6109                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6110                 /* IP11_5_3 [3] */
6111                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
6112                 0, 0, 0,
6113                 /* IP11_2_0 [3] */
6114                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
6115                 0, 0, 0, }
6116         },
6117         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6118                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6119                 /* IP12_31_30 [2] */
6120                 0, 0, 0, 0,
6121                 /* IP12_29_27 [3] */
6122                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6123                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6124                 0, 0, 0,
6125                 /* IP12_26_24 [3] */
6126                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6127                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6128                 0, 0, 0,
6129                 /* IP12_23_22 [2] */
6130                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6131                 /* IP12_21_20 [2] */
6132                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6133                 /* IP12_19_18 [2] */
6134                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6135                 /* IP12_17_16 [2] */
6136                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6137                 /* IP12_15_13 [3] */
6138                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6139                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6140                 0, 0, 0,
6141                 /* IP12_12_10 [3] */
6142                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6143                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6144                 0, 0, 0,
6145                 /* IP12_9_7 [3] */
6146                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6147                 FN_SDA2_D, FN_MSIOF1_SCK_E,
6148                 0, 0, 0,
6149                 /* IP12_6_4 [3] */
6150                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6151                 FN_SCL2_D, FN_MSIOF1_RXD_E,
6152                 0, 0, 0,
6153                 /* IP12_3_2 [2] */
6154                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
6155                 /* IP12_1_0 [2] */
6156                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
6157         },
6158         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6159                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6160                              3, 2, 2, 3) {
6161                 /* IP13_31 [1] */
6162                 0, 0,
6163                 /* IP13_30_28 [3] */
6164                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
6165                 0, 0, 0, 0,
6166                 /* IP13_27 [1] */
6167                 FN_SD1_DATA3, FN_IERX_B,
6168                 /* IP13_26 [1] */
6169                 FN_SD1_DATA2, FN_IECLK_B,
6170                 /* IP13_25 [1] */
6171                 FN_SD1_DATA1, FN_IETX_B,
6172                 /* IP13_24_23 [2] */
6173                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6174                 /* IP13_22 [1] */
6175                 FN_SD1_CMD, FN_REMOCON_B,
6176                 /* IP13_21_19 [3] */
6177                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6178                 FN_SCIFA5_RXD_B, FN_RX3_C,
6179                 0, 0,
6180                 /* IP13_18_16 [3] */
6181                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6182                 FN_SCIFA5_TXD_B, FN_TX3_C,
6183                 0, 0,
6184                 /* IP13_15 [1] */
6185                 FN_SD0_DATA3, FN_SSL_B,
6186                 /* IP13_14 [1] */
6187                 FN_SD0_DATA2, FN_IO3_B,
6188                 /* IP13_13 [1] */
6189                 FN_SD0_DATA1, FN_IO2_B,
6190                 /* IP13_12 [1] */
6191                 FN_SD0_DATA0, FN_MISO_IO1_B,
6192                 /* IP13_11 [1] */
6193                 FN_SD0_CMD, FN_MOSI_IO0_B,
6194                 /* IP13_10 [1] */
6195                 FN_SD0_CLK, FN_SPCLK_B,
6196                 /* IP13_9_7 [3] */
6197                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6198                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6199                 0, 0, 0,
6200                 /* IP13_6_5 [2] */
6201                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6202                 /* IP13_4_3 [2] */
6203                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6204                 /* IP13_2_0 [3] */
6205                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6206                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6207                 0, 0, 0, }
6208         },
6209         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6210                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6211                 /* IP14_31_29 [3] */
6212                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6213                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
6214                 /* IP14_28_26 [3] */
6215                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6216                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
6217                 /* IP14_25_23 [3] */
6218                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6219                 0, 0, 0,
6220                 /* IP14_22_20 [3] */
6221                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6222                 0, 0, 0,
6223                 /* IP14_19_17 [3] */
6224                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6225                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6226                 0, 0,
6227                 /* IP14_16_14 [3] */
6228                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6229                 FN_VI1_CLK_C, FN_VI1_G0_B,
6230                 0, 0,
6231                 /* IP14_13_11 [3] */
6232                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6233                 0, 0, 0,
6234                 /* IP14_10_8 [3] */
6235                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6236                 0, 0, 0,
6237                 /* IP14_7 [1] */
6238                 FN_SD2_DATA3, FN_MMC_D3,
6239                 /* IP14_6 [1] */
6240                 FN_SD2_DATA2, FN_MMC_D2,
6241                 /* IP14_5 [1] */
6242                 FN_SD2_DATA1, FN_MMC_D1,
6243                 /* IP14_4 [1] */
6244                 FN_SD2_DATA0, FN_MMC_D0,
6245                 /* IP14_3 [1] */
6246                 FN_SD2_CMD, FN_MMC_CMD,
6247                 /* IP14_2 [1] */
6248                 FN_SD2_CLK, FN_MMC_CLK,
6249                 /* IP14_1_0 [2] */
6250                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
6251         },
6252         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6253                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6254                 /* IP15_31_30 [2] */
6255                 0, 0, 0, 0,
6256                 /* IP15_29_27 [3] */
6257                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6258                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6259                 0, 0,
6260                 /* IP15_26_24 [3] */
6261                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6262                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6263                 0, 0,
6264                 /* IP15_23_21 [3] */
6265                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6266                 FN_TCLK2, FN_VI1_DATA3_C, 0,
6267                 /* IP15_20_18 [3] */
6268                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6269                 0, 0, 0,
6270                 /* IP15_17_15 [3] */
6271                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6272                 FN_TCLK1, FN_VI1_DATA1_C,
6273                 0, 0,
6274                 /* IP15_14_12 [3] */
6275                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6276                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6277                 0, 0,
6278                 /* IP15_11_9 [3] */
6279                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6280                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6281                 0, 0,
6282                 /* IP15_8_6 [3] */
6283                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6284                 FN_PWM5_B, FN_SCIFA3_TXD_C,
6285                 0, 0, 0,
6286                 /* IP15_5_4 [2] */
6287                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6288                 /* IP15_3_2 [2] */
6289                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6290                 /* IP15_1_0 [2] */
6291                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6292         },
6293         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6294                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6295                 /* IP16_31_28 [4] */
6296                 0, 0, 0, 0, 0, 0, 0, 0,
6297                 0, 0, 0, 0, 0, 0, 0, 0,
6298                 /* IP16_27_24 [4] */
6299                 0, 0, 0, 0, 0, 0, 0, 0,
6300                 0, 0, 0, 0, 0, 0, 0, 0,
6301                 /* IP16_23_20 [4] */
6302                 0, 0, 0, 0, 0, 0, 0, 0,
6303                 0, 0, 0, 0, 0, 0, 0, 0,
6304                 /* IP16_19_16 [4] */
6305                 0, 0, 0, 0, 0, 0, 0, 0,
6306                 0, 0, 0, 0, 0, 0, 0, 0,
6307                 /* IP16_15_12 [4] */
6308                 0, 0, 0, 0, 0, 0, 0, 0,
6309                 0, 0, 0, 0, 0, 0, 0, 0,
6310                 /* IP16_11_10 [2] */
6311                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6312                 /* IP16_9_8 [2] */
6313                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6314                 /* IP16_7_6 [2] */
6315                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6316                 /* IP16_5_3 [3] */
6317                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6318                 FN_GLO_SS_C, FN_VI1_DATA7_C,
6319                 0, 0, 0,
6320                 /* IP16_2_0 [3] */
6321                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6322                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6323                 0, 0, 0, }
6324         },
6325         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6326                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6327                              3, 2, 2, 2, 1, 2, 2, 2) {
6328                 /* RESERVED [1] */
6329                 0, 0,
6330                 /* SEL_SCIF1 [2] */
6331                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6332                 /* SEL_SCIFB [2] */
6333                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6334                 /* SEL_SCIFB2 [2] */
6335                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6336                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6337                 /* SEL_SCIFB1 [3] */
6338                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6339                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6340                 0, 0, 0, 0,
6341                 /* SEL_SCIFA1 [2] */
6342                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6343                 /* SEL_SSI9 [1] */
6344                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6345                 /* SEL_SCFA [1] */
6346                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6347                 /* SEL_QSP [1] */
6348                 FN_SEL_QSP_0, FN_SEL_QSP_1,
6349                 /* SEL_SSI7 [1] */
6350                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6351                 /* SEL_HSCIF1 [3] */
6352                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6353                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6354                 0, 0, 0,
6355                 /* RESERVED [2] */
6356                 0, 0, 0, 0,
6357                 /* SEL_VI1 [2] */
6358                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6359                 /* RESERVED [2] */
6360                 0, 0, 0, 0,
6361                 /* SEL_TMU [1] */
6362                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6363                 /* SEL_LBS [2] */
6364                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6365                 /* SEL_TSIF0 [2] */
6366                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6367                 /* SEL_SOF0 [2] */
6368                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6369         },
6370         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6371                              3, 1, 1, 3, 2, 1, 1, 2, 2,
6372                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6373                 /* SEL_SCIF0 [3] */
6374                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6375                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6376                 0, 0, 0,
6377                 /* RESERVED [1] */
6378                 0, 0,
6379                 /* SEL_SCIF [1] */
6380                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6381                 /* SEL_CAN0 [3] */
6382                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6383                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6384                 0, 0,
6385                 /* SEL_CAN1 [2] */
6386                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6387                 /* RESERVED [1] */
6388                 0, 0,
6389                 /* SEL_SCIFA2 [1] */
6390                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6391                 /* SEL_SCIF4 [2] */
6392                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6393                 /* RESERVED [2] */
6394                 0, 0, 0, 0,
6395                 /* SEL_ADG [1] */
6396                 FN_SEL_ADG_0, FN_SEL_ADG_1,
6397                 /* SEL_FM [3] */
6398                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6399                 FN_SEL_FM_3, FN_SEL_FM_4,
6400                 0, 0, 0,
6401                 /* SEL_SCIFA5 [2] */
6402                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6403                 /* RESERVED [1] */
6404                 0, 0,
6405                 /* SEL_GPS [2] */
6406                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6407                 /* SEL_SCIFA4 [2] */
6408                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6409                 /* SEL_SCIFA3 [2] */
6410                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6411                 /* SEL_SIM [1] */
6412                 FN_SEL_SIM_0, FN_SEL_SIM_1,
6413                 /* RESERVED [1] */
6414                 0, 0,
6415                 /* SEL_SSI8 [1] */
6416                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6417         },
6418         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6419                              2, 2, 2, 2, 2, 2, 2, 2,
6420                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
6421                 /* SEL_HSCIF2 [2] */
6422                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6423                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6424                 /* SEL_CANCLK [2] */
6425                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6426                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6427                 /* SEL_IIC8 [2] */
6428                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
6429                 /* SEL_IIC7 [2] */
6430                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
6431                 /* SEL_IIC4 [2] */
6432                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
6433                 /* SEL_IIC3 [2] */
6434                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
6435                 /* SEL_SCIF3 [2] */
6436                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6437                 /* SEL_IEB [2] */
6438                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6439                 /* SEL_MMC [1] */
6440                 FN_SEL_MMC_0, FN_SEL_MMC_1,
6441                 /* SEL_SCIF5 [1] */
6442                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6443                 /* RESERVED [2] */
6444                 0, 0, 0, 0,
6445                 /* SEL_IIC2 [2] */
6446                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
6447                 /* SEL_IIC1 [3] */
6448                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
6449                 FN_SEL_IIC1_4,
6450                 0, 0, 0,
6451                 /* SEL_IIC0 [2] */
6452                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6453                 /* RESERVED [2] */
6454                 0, 0, 0, 0,
6455                 /* RESERVED [2] */
6456                 0, 0, 0, 0,
6457                 /* RESERVED [1] */
6458                 0, 0, }
6459         },
6460         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6461                              3, 2, 2, 1, 1, 1, 1, 3, 2,
6462                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
6463                 /* SEL_SOF1 [3] */
6464                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6465                 FN_SEL_SOF1_4,
6466                 0, 0, 0,
6467                 /* SEL_HSCIF0 [2] */
6468                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6469                 /* SEL_DIS [2] */
6470                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6471                 /* RESERVED [1] */
6472                 0, 0,
6473                 /* SEL_RAD [1] */
6474                 FN_SEL_RAD_0, FN_SEL_RAD_1,
6475                 /* SEL_RCN [1] */
6476                 FN_SEL_RCN_0, FN_SEL_RCN_1,
6477                 /* SEL_RSP [1] */
6478                 FN_SEL_RSP_0, FN_SEL_RSP_1,
6479                 /* SEL_SCIF2 [3] */
6480                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6481                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6482                 0, 0, 0,
6483                 /* RESERVED [2] */
6484                 0, 0, 0, 0,
6485                 /* RESERVED [2] */
6486                 0, 0, 0, 0,
6487                 /* SEL_SOF2 [3] */
6488                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6489                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6490                 0, 0, 0,
6491                 /* RESERVED [1] */
6492                 0, 0,
6493                 /* SEL_SSI1 [1] */
6494                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6495                 /* SEL_SSI0 [1] */
6496                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6497                 /* SEL_SSP [2] */
6498                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6499                 /* RESERVED [2] */
6500                 0, 0, 0, 0,
6501                 /* RESERVED [2] */
6502                 0, 0, 0, 0,
6503                 /* RESERVED [2] */
6504                 0, 0, 0, 0, }
6505         },
6506         { },
6507 };
6508
6509 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6510 {
6511         if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6512                 return -EINVAL;
6513
6514         *pocctrl = 0xe606008c;
6515
6516         return 31 - (pin & 0x1f);
6517 }
6518
6519 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6520         .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6521 };
6522
6523 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6524 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6525         .name = "r8a77910_pfc",
6526         .ops = &r8a7791_pinmux_ops,
6527         .unlock_reg = 0xe6060000, /* PMMR */
6528
6529         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6530
6531         .pins = pinmux_pins,
6532         .nr_pins = ARRAY_SIZE(pinmux_pins),
6533         .groups = pinmux_groups,
6534         .nr_groups = ARRAY_SIZE(pinmux_groups),
6535         .functions = pinmux_functions,
6536         .nr_functions = ARRAY_SIZE(pinmux_functions),
6537
6538         .cfg_regs = pinmux_config_regs,
6539
6540         .pinmux_data = pinmux_data,
6541         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6542 };
6543 #endif
6544
6545 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6546 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6547         .name = "r8a77930_pfc",
6548         .ops = &r8a7791_pinmux_ops,
6549         .unlock_reg = 0xe6060000, /* PMMR */
6550
6551         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6552
6553         .pins = pinmux_pins,
6554         .nr_pins = ARRAY_SIZE(pinmux_pins),
6555         .groups = pinmux_groups,
6556         .nr_groups = ARRAY_SIZE(pinmux_groups),
6557         .functions = pinmux_functions,
6558         .nr_functions = ARRAY_SIZE(pinmux_functions),
6559
6560         .cfg_regs = pinmux_config_regs,
6561
6562         .pinmux_data = pinmux_data,
6563         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6564 };
6565 #endif