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Merge commit 'v3.7-rc1' into stable/for-linus-3.7
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-nomadik.c
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/mfd/dbx500-prcmu.h>
34
35 #include <asm/mach/irq.h>
36
37 #include <plat/pincfg.h>
38 #include <plat/gpio-nomadik.h>
39
40 #include "pinctrl-nomadik.h"
41
42 /*
43 * The GPIO module in the Nomadik family of Systems-on-Chip is an
44 * AMBA device, managing 32 pins and alternate functions. The logic block
45 * is currently used in the Nomadik and ux500.
46 *
47 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
48 */
49
50 #define NMK_GPIO_PER_CHIP 32
51
52 struct nmk_gpio_chip {
53 struct gpio_chip chip;
54 struct irq_domain *domain;
55 void __iomem *addr;
56 struct clk *clk;
57 unsigned int bank;
58 unsigned int parent_irq;
59 int secondary_parent_irq;
60 u32 (*get_secondary_status)(unsigned int bank);
61 void (*set_ioforce)(bool enable);
62 spinlock_t lock;
63 bool sleepmode;
64 /* Keep track of configured edges */
65 u32 edge_rising;
66 u32 edge_falling;
67 u32 real_wake;
68 u32 rwimsc;
69 u32 fwimsc;
70 u32 rimsc;
71 u32 fimsc;
72 u32 pull_up;
73 u32 lowemi;
74 };
75
76 struct nmk_pinctrl {
77 struct device *dev;
78 struct pinctrl_dev *pctl;
79 const struct nmk_pinctrl_soc_data *soc;
80 };
81
82 static struct nmk_gpio_chip *
83 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
84
85 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
86
87 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
88
89 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
90 unsigned offset, int gpio_mode)
91 {
92 u32 bit = 1 << offset;
93 u32 afunc, bfunc;
94
95 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
96 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
97 if (gpio_mode & NMK_GPIO_ALT_A)
98 afunc |= bit;
99 if (gpio_mode & NMK_GPIO_ALT_B)
100 bfunc |= bit;
101 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
102 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
103 }
104
105 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
106 unsigned offset, enum nmk_gpio_slpm mode)
107 {
108 u32 bit = 1 << offset;
109 u32 slpm;
110
111 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
112 if (mode == NMK_GPIO_SLPM_NOCHANGE)
113 slpm |= bit;
114 else
115 slpm &= ~bit;
116 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
117 }
118
119 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
120 unsigned offset, enum nmk_gpio_pull pull)
121 {
122 u32 bit = 1 << offset;
123 u32 pdis;
124
125 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
126 if (pull == NMK_GPIO_PULL_NONE) {
127 pdis |= bit;
128 nmk_chip->pull_up &= ~bit;
129 } else {
130 pdis &= ~bit;
131 }
132
133 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
134
135 if (pull == NMK_GPIO_PULL_UP) {
136 nmk_chip->pull_up |= bit;
137 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
138 } else if (pull == NMK_GPIO_PULL_DOWN) {
139 nmk_chip->pull_up &= ~bit;
140 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
141 }
142 }
143
144 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
145 unsigned offset, bool lowemi)
146 {
147 u32 bit = BIT(offset);
148 bool enabled = nmk_chip->lowemi & bit;
149
150 if (lowemi == enabled)
151 return;
152
153 if (lowemi)
154 nmk_chip->lowemi |= bit;
155 else
156 nmk_chip->lowemi &= ~bit;
157
158 writel_relaxed(nmk_chip->lowemi,
159 nmk_chip->addr + NMK_GPIO_LOWEMI);
160 }
161
162 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
163 unsigned offset)
164 {
165 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
166 }
167
168 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
169 unsigned offset, int val)
170 {
171 if (val)
172 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
173 else
174 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
175 }
176
177 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
178 unsigned offset, int val)
179 {
180 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
181 __nmk_gpio_set_output(nmk_chip, offset, val);
182 }
183
184 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
185 unsigned offset, int gpio_mode,
186 bool glitch)
187 {
188 u32 rwimsc = nmk_chip->rwimsc;
189 u32 fwimsc = nmk_chip->fwimsc;
190
191 if (glitch && nmk_chip->set_ioforce) {
192 u32 bit = BIT(offset);
193
194 /* Prevent spurious wakeups */
195 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
196 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
197
198 nmk_chip->set_ioforce(true);
199 }
200
201 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
202
203 if (glitch && nmk_chip->set_ioforce) {
204 nmk_chip->set_ioforce(false);
205
206 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
207 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
208 }
209 }
210
211 static void
212 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
213 {
214 u32 falling = nmk_chip->fimsc & BIT(offset);
215 u32 rising = nmk_chip->rimsc & BIT(offset);
216 int gpio = nmk_chip->chip.base + offset;
217 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
218 struct irq_data *d = irq_get_irq_data(irq);
219
220 if (!rising && !falling)
221 return;
222
223 if (!d || !irqd_irq_disabled(d))
224 return;
225
226 if (rising) {
227 nmk_chip->rimsc &= ~BIT(offset);
228 writel_relaxed(nmk_chip->rimsc,
229 nmk_chip->addr + NMK_GPIO_RIMSC);
230 }
231
232 if (falling) {
233 nmk_chip->fimsc &= ~BIT(offset);
234 writel_relaxed(nmk_chip->fimsc,
235 nmk_chip->addr + NMK_GPIO_FIMSC);
236 }
237
238 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
239 }
240
241 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
242 unsigned offset, unsigned alt_num)
243 {
244 int i;
245 u16 reg;
246 u8 bit;
247 u8 alt_index;
248 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
249 const u16 *gpiocr_regs;
250
251 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
252 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
253 alt_num);
254 return;
255 }
256
257 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
258 if (npct->soc->altcx_pins[i].pin == offset)
259 break;
260 }
261 if (i == npct->soc->npins_altcx) {
262 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
263 offset);
264 return;
265 }
266
267 pin_desc = npct->soc->altcx_pins + i;
268 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
269
270 /*
271 * If alt_num is NULL, just clear current ALTCx selection
272 * to make sure we come back to a pure ALTC selection
273 */
274 if (!alt_num) {
275 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
276 if (pin_desc->altcx[i].used == true) {
277 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
278 bit = pin_desc->altcx[i].control_bit;
279 if (prcmu_read(reg) & BIT(bit)) {
280 prcmu_write_masked(reg, BIT(bit), 0);
281 dev_dbg(npct->dev,
282 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
283 offset, i+1);
284 }
285 }
286 }
287 return;
288 }
289
290 alt_index = alt_num - 1;
291 if (pin_desc->altcx[alt_index].used == false) {
292 dev_warn(npct->dev,
293 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
294 offset, alt_num);
295 return;
296 }
297
298 /*
299 * Check if any other ALTCx functions are activated on this pin
300 * and disable it first.
301 */
302 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
303 if (i == alt_index)
304 continue;
305 if (pin_desc->altcx[i].used == true) {
306 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
307 bit = pin_desc->altcx[i].control_bit;
308 if (prcmu_read(reg) & BIT(bit)) {
309 prcmu_write_masked(reg, BIT(bit), 0);
310 dev_dbg(npct->dev,
311 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
312 offset, i+1);
313 }
314 }
315 }
316
317 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
318 bit = pin_desc->altcx[alt_index].control_bit;
319 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
320 offset, alt_index+1);
321 prcmu_write_masked(reg, BIT(bit), BIT(bit));
322 }
323
324 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
325 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
326 {
327 static const char *afnames[] = {
328 [NMK_GPIO_ALT_GPIO] = "GPIO",
329 [NMK_GPIO_ALT_A] = "A",
330 [NMK_GPIO_ALT_B] = "B",
331 [NMK_GPIO_ALT_C] = "C"
332 };
333 static const char *pullnames[] = {
334 [NMK_GPIO_PULL_NONE] = "none",
335 [NMK_GPIO_PULL_UP] = "up",
336 [NMK_GPIO_PULL_DOWN] = "down",
337 [3] /* illegal */ = "??"
338 };
339 static const char *slpmnames[] = {
340 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
341 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
342 };
343
344 int pin = PIN_NUM(cfg);
345 int pull = PIN_PULL(cfg);
346 int af = PIN_ALT(cfg);
347 int slpm = PIN_SLPM(cfg);
348 int output = PIN_DIR(cfg);
349 int val = PIN_VAL(cfg);
350 bool glitch = af == NMK_GPIO_ALT_C;
351
352 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
353 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
354 output ? "output " : "input",
355 output ? (val ? "high" : "low") : "");
356
357 if (sleep) {
358 int slpm_pull = PIN_SLPM_PULL(cfg);
359 int slpm_output = PIN_SLPM_DIR(cfg);
360 int slpm_val = PIN_SLPM_VAL(cfg);
361
362 af = NMK_GPIO_ALT_GPIO;
363
364 /*
365 * The SLPM_* values are normal values + 1 to allow zero to
366 * mean "same as normal".
367 */
368 if (slpm_pull)
369 pull = slpm_pull - 1;
370 if (slpm_output)
371 output = slpm_output - 1;
372 if (slpm_val)
373 val = slpm_val - 1;
374
375 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
376 pin,
377 slpm_pull ? pullnames[pull] : "same",
378 slpm_output ? (output ? "output" : "input") : "same",
379 slpm_val ? (val ? "high" : "low") : "same");
380 }
381
382 if (output)
383 __nmk_gpio_make_output(nmk_chip, offset, val);
384 else {
385 __nmk_gpio_make_input(nmk_chip, offset);
386 __nmk_gpio_set_pull(nmk_chip, offset, pull);
387 }
388
389 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
390
391 /*
392 * If the pin is switching to altfunc, and there was an interrupt
393 * installed on it which has been lazy disabled, actually mask the
394 * interrupt to prevent spurious interrupts that would occur while the
395 * pin is under control of the peripheral. Only SKE does this.
396 */
397 if (af != NMK_GPIO_ALT_GPIO)
398 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
399
400 /*
401 * If we've backed up the SLPM registers (glitch workaround), modify
402 * the backups since they will be restored.
403 */
404 if (slpmregs) {
405 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
406 slpmregs[nmk_chip->bank] |= BIT(offset);
407 else
408 slpmregs[nmk_chip->bank] &= ~BIT(offset);
409 } else
410 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
411
412 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
413 }
414
415 /*
416 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
417 * - Save SLPM registers
418 * - Set SLPM=0 for the IOs you want to switch and others to 1
419 * - Configure the GPIO registers for the IOs that are being switched
420 * - Set IOFORCE=1
421 * - Modify the AFLSA/B registers for the IOs that are being switched
422 * - Set IOFORCE=0
423 * - Restore SLPM registers
424 * - Any spurious wake up event during switch sequence to be ignored and
425 * cleared
426 */
427 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
428 {
429 int i;
430
431 for (i = 0; i < NUM_BANKS; i++) {
432 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
433 unsigned int temp = slpm[i];
434
435 if (!chip)
436 break;
437
438 clk_enable(chip->clk);
439
440 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
441 writel(temp, chip->addr + NMK_GPIO_SLPC);
442 }
443 }
444
445 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
446 {
447 int i;
448
449 for (i = 0; i < NUM_BANKS; i++) {
450 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
451
452 if (!chip)
453 break;
454
455 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
456
457 clk_disable(chip->clk);
458 }
459 }
460
461 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
462 {
463 static unsigned int slpm[NUM_BANKS];
464 unsigned long flags;
465 bool glitch = false;
466 int ret = 0;
467 int i;
468
469 for (i = 0; i < num; i++) {
470 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
471 glitch = true;
472 break;
473 }
474 }
475
476 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
477
478 if (glitch) {
479 memset(slpm, 0xff, sizeof(slpm));
480
481 for (i = 0; i < num; i++) {
482 int pin = PIN_NUM(cfgs[i]);
483 int offset = pin % NMK_GPIO_PER_CHIP;
484
485 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
486 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
487 }
488
489 nmk_gpio_glitch_slpm_init(slpm);
490 }
491
492 for (i = 0; i < num; i++) {
493 struct nmk_gpio_chip *nmk_chip;
494 int pin = PIN_NUM(cfgs[i]);
495
496 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
497 if (!nmk_chip) {
498 ret = -EINVAL;
499 break;
500 }
501
502 clk_enable(nmk_chip->clk);
503 spin_lock(&nmk_chip->lock);
504 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
505 cfgs[i], sleep, glitch ? slpm : NULL);
506 spin_unlock(&nmk_chip->lock);
507 clk_disable(nmk_chip->clk);
508 }
509
510 if (glitch)
511 nmk_gpio_glitch_slpm_restore(slpm);
512
513 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
514
515 return ret;
516 }
517
518 /**
519 * nmk_config_pin - configure a pin's mux attributes
520 * @cfg: pin confguration
521 * @sleep: Non-zero to apply the sleep mode configuration
522 * Configures a pin's mode (alternate function or GPIO), its pull up status,
523 * and its sleep mode based on the specified configuration. The @cfg is
524 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
525 * are constructed using, and can be further enhanced with, the macros in
526 * plat/pincfg.h.
527 *
528 * If a pin's mode is set to GPIO, it is configured as an input to avoid
529 * side-effects. The gpio can be manipulated later using standard GPIO API
530 * calls.
531 */
532 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
533 {
534 return __nmk_config_pins(&cfg, 1, sleep);
535 }
536 EXPORT_SYMBOL(nmk_config_pin);
537
538 /**
539 * nmk_config_pins - configure several pins at once
540 * @cfgs: array of pin configurations
541 * @num: number of elments in the array
542 *
543 * Configures several pins using nmk_config_pin(). Refer to that function for
544 * further information.
545 */
546 int nmk_config_pins(pin_cfg_t *cfgs, int num)
547 {
548 return __nmk_config_pins(cfgs, num, false);
549 }
550 EXPORT_SYMBOL(nmk_config_pins);
551
552 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
553 {
554 return __nmk_config_pins(cfgs, num, true);
555 }
556 EXPORT_SYMBOL(nmk_config_pins_sleep);
557
558 /**
559 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
560 * @gpio: pin number
561 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
562 *
563 * This register is actually in the pinmux layer, not the GPIO block itself.
564 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
565 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
566 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
567 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
568 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
569 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
570 *
571 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
572 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
573 * entered) regardless of the altfunction selected. Also wake-up detection is
574 * ENABLED.
575 *
576 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
577 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
578 * (for altfunction GPIO) or respective on-chip peripherals (for other
579 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
580 *
581 * Note that enable_irq_wake() will automatically enable wakeup detection.
582 */
583 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
584 {
585 struct nmk_gpio_chip *nmk_chip;
586 unsigned long flags;
587
588 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
589 if (!nmk_chip)
590 return -EINVAL;
591
592 clk_enable(nmk_chip->clk);
593 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
594 spin_lock(&nmk_chip->lock);
595
596 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
597
598 spin_unlock(&nmk_chip->lock);
599 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
600 clk_disable(nmk_chip->clk);
601
602 return 0;
603 }
604
605 /**
606 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
607 * @gpio: pin number
608 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
609 *
610 * Enables/disables pull up/down on a specified pin. This only takes effect if
611 * the pin is configured as an input (either explicitly or by the alternate
612 * function).
613 *
614 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
615 * configured as an input. Otherwise, due to the way the controller registers
616 * work, this function will change the value output on the pin.
617 */
618 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
619 {
620 struct nmk_gpio_chip *nmk_chip;
621 unsigned long flags;
622
623 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
624 if (!nmk_chip)
625 return -EINVAL;
626
627 clk_enable(nmk_chip->clk);
628 spin_lock_irqsave(&nmk_chip->lock, flags);
629 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
630 spin_unlock_irqrestore(&nmk_chip->lock, flags);
631 clk_disable(nmk_chip->clk);
632
633 return 0;
634 }
635
636 /* Mode functions */
637 /**
638 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
639 * @gpio: pin number
640 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
641 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
642 *
643 * Sets the mode of the specified pin to one of the alternate functions or
644 * plain GPIO.
645 */
646 int nmk_gpio_set_mode(int gpio, int gpio_mode)
647 {
648 struct nmk_gpio_chip *nmk_chip;
649 unsigned long flags;
650
651 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
652 if (!nmk_chip)
653 return -EINVAL;
654
655 clk_enable(nmk_chip->clk);
656 spin_lock_irqsave(&nmk_chip->lock, flags);
657 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
658 spin_unlock_irqrestore(&nmk_chip->lock, flags);
659 clk_disable(nmk_chip->clk);
660
661 return 0;
662 }
663 EXPORT_SYMBOL(nmk_gpio_set_mode);
664
665 int nmk_gpio_get_mode(int gpio)
666 {
667 struct nmk_gpio_chip *nmk_chip;
668 u32 afunc, bfunc, bit;
669
670 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
671 if (!nmk_chip)
672 return -EINVAL;
673
674 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
675
676 clk_enable(nmk_chip->clk);
677
678 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
679 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
680
681 clk_disable(nmk_chip->clk);
682
683 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
684 }
685 EXPORT_SYMBOL(nmk_gpio_get_mode);
686
687
688 /* IRQ functions */
689 static inline int nmk_gpio_get_bitmask(int gpio)
690 {
691 return 1 << (gpio % NMK_GPIO_PER_CHIP);
692 }
693
694 static void nmk_gpio_irq_ack(struct irq_data *d)
695 {
696 struct nmk_gpio_chip *nmk_chip;
697
698 nmk_chip = irq_data_get_irq_chip_data(d);
699 if (!nmk_chip)
700 return;
701
702 clk_enable(nmk_chip->clk);
703 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
704 clk_disable(nmk_chip->clk);
705 }
706
707 enum nmk_gpio_irq_type {
708 NORMAL,
709 WAKE,
710 };
711
712 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
713 int gpio, enum nmk_gpio_irq_type which,
714 bool enable)
715 {
716 u32 bitmask = nmk_gpio_get_bitmask(gpio);
717 u32 *rimscval;
718 u32 *fimscval;
719 u32 rimscreg;
720 u32 fimscreg;
721
722 if (which == NORMAL) {
723 rimscreg = NMK_GPIO_RIMSC;
724 fimscreg = NMK_GPIO_FIMSC;
725 rimscval = &nmk_chip->rimsc;
726 fimscval = &nmk_chip->fimsc;
727 } else {
728 rimscreg = NMK_GPIO_RWIMSC;
729 fimscreg = NMK_GPIO_FWIMSC;
730 rimscval = &nmk_chip->rwimsc;
731 fimscval = &nmk_chip->fwimsc;
732 }
733
734 /* we must individually set/clear the two edges */
735 if (nmk_chip->edge_rising & bitmask) {
736 if (enable)
737 *rimscval |= bitmask;
738 else
739 *rimscval &= ~bitmask;
740 writel(*rimscval, nmk_chip->addr + rimscreg);
741 }
742 if (nmk_chip->edge_falling & bitmask) {
743 if (enable)
744 *fimscval |= bitmask;
745 else
746 *fimscval &= ~bitmask;
747 writel(*fimscval, nmk_chip->addr + fimscreg);
748 }
749 }
750
751 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
752 int gpio, bool on)
753 {
754 /*
755 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
756 * disabled, since setting SLPM to 1 increases power consumption, and
757 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
758 */
759 if (nmk_chip->sleepmode && on) {
760 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
761 NMK_GPIO_SLPM_WAKEUP_ENABLE);
762 }
763
764 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
765 }
766
767 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
768 {
769 struct nmk_gpio_chip *nmk_chip;
770 unsigned long flags;
771 u32 bitmask;
772
773 nmk_chip = irq_data_get_irq_chip_data(d);
774 bitmask = nmk_gpio_get_bitmask(d->hwirq);
775 if (!nmk_chip)
776 return -EINVAL;
777
778 clk_enable(nmk_chip->clk);
779 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
780 spin_lock(&nmk_chip->lock);
781
782 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
783
784 if (!(nmk_chip->real_wake & bitmask))
785 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
786
787 spin_unlock(&nmk_chip->lock);
788 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
789 clk_disable(nmk_chip->clk);
790
791 return 0;
792 }
793
794 static void nmk_gpio_irq_mask(struct irq_data *d)
795 {
796 nmk_gpio_irq_maskunmask(d, false);
797 }
798
799 static void nmk_gpio_irq_unmask(struct irq_data *d)
800 {
801 nmk_gpio_irq_maskunmask(d, true);
802 }
803
804 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
805 {
806 struct nmk_gpio_chip *nmk_chip;
807 unsigned long flags;
808 u32 bitmask;
809
810 nmk_chip = irq_data_get_irq_chip_data(d);
811 if (!nmk_chip)
812 return -EINVAL;
813 bitmask = nmk_gpio_get_bitmask(d->hwirq);
814
815 clk_enable(nmk_chip->clk);
816 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
817 spin_lock(&nmk_chip->lock);
818
819 if (irqd_irq_disabled(d))
820 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
821
822 if (on)
823 nmk_chip->real_wake |= bitmask;
824 else
825 nmk_chip->real_wake &= ~bitmask;
826
827 spin_unlock(&nmk_chip->lock);
828 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
829 clk_disable(nmk_chip->clk);
830
831 return 0;
832 }
833
834 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
835 {
836 bool enabled = !irqd_irq_disabled(d);
837 bool wake = irqd_is_wakeup_set(d);
838 struct nmk_gpio_chip *nmk_chip;
839 unsigned long flags;
840 u32 bitmask;
841
842 nmk_chip = irq_data_get_irq_chip_data(d);
843 bitmask = nmk_gpio_get_bitmask(d->hwirq);
844 if (!nmk_chip)
845 return -EINVAL;
846 if (type & IRQ_TYPE_LEVEL_HIGH)
847 return -EINVAL;
848 if (type & IRQ_TYPE_LEVEL_LOW)
849 return -EINVAL;
850
851 clk_enable(nmk_chip->clk);
852 spin_lock_irqsave(&nmk_chip->lock, flags);
853
854 if (enabled)
855 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
856
857 if (enabled || wake)
858 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
859
860 nmk_chip->edge_rising &= ~bitmask;
861 if (type & IRQ_TYPE_EDGE_RISING)
862 nmk_chip->edge_rising |= bitmask;
863
864 nmk_chip->edge_falling &= ~bitmask;
865 if (type & IRQ_TYPE_EDGE_FALLING)
866 nmk_chip->edge_falling |= bitmask;
867
868 if (enabled)
869 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
870
871 if (enabled || wake)
872 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
873
874 spin_unlock_irqrestore(&nmk_chip->lock, flags);
875 clk_disable(nmk_chip->clk);
876
877 return 0;
878 }
879
880 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
881 {
882 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
883
884 clk_enable(nmk_chip->clk);
885 nmk_gpio_irq_unmask(d);
886 return 0;
887 }
888
889 static void nmk_gpio_irq_shutdown(struct irq_data *d)
890 {
891 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
892
893 nmk_gpio_irq_mask(d);
894 clk_disable(nmk_chip->clk);
895 }
896
897 static struct irq_chip nmk_gpio_irq_chip = {
898 .name = "Nomadik-GPIO",
899 .irq_ack = nmk_gpio_irq_ack,
900 .irq_mask = nmk_gpio_irq_mask,
901 .irq_unmask = nmk_gpio_irq_unmask,
902 .irq_set_type = nmk_gpio_irq_set_type,
903 .irq_set_wake = nmk_gpio_irq_set_wake,
904 .irq_startup = nmk_gpio_irq_startup,
905 .irq_shutdown = nmk_gpio_irq_shutdown,
906 .flags = IRQCHIP_MASK_ON_SUSPEND,
907 };
908
909 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
910 u32 status)
911 {
912 struct nmk_gpio_chip *nmk_chip;
913 struct irq_chip *host_chip = irq_get_chip(irq);
914
915 chained_irq_enter(host_chip, desc);
916
917 nmk_chip = irq_get_handler_data(irq);
918 while (status) {
919 int bit = __ffs(status);
920
921 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
922 status &= ~BIT(bit);
923 }
924
925 chained_irq_exit(host_chip, desc);
926 }
927
928 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
929 {
930 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
931 u32 status;
932
933 clk_enable(nmk_chip->clk);
934 status = readl(nmk_chip->addr + NMK_GPIO_IS);
935 clk_disable(nmk_chip->clk);
936
937 __nmk_gpio_irq_handler(irq, desc, status);
938 }
939
940 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
941 struct irq_desc *desc)
942 {
943 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
944 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
945
946 __nmk_gpio_irq_handler(irq, desc, status);
947 }
948
949 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
950 {
951 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
952 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
953
954 if (nmk_chip->secondary_parent_irq >= 0) {
955 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
956 nmk_gpio_secondary_irq_handler);
957 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
958 }
959
960 return 0;
961 }
962
963 /* I/O Functions */
964
965 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
966 {
967 /*
968 * Map back to global GPIO space and request muxing, the direction
969 * parameter does not matter for this controller.
970 */
971 int gpio = chip->base + offset;
972
973 return pinctrl_request_gpio(gpio);
974 }
975
976 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
977 {
978 int gpio = chip->base + offset;
979
980 pinctrl_free_gpio(gpio);
981 }
982
983 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
984 {
985 struct nmk_gpio_chip *nmk_chip =
986 container_of(chip, struct nmk_gpio_chip, chip);
987
988 clk_enable(nmk_chip->clk);
989
990 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
991
992 clk_disable(nmk_chip->clk);
993
994 return 0;
995 }
996
997 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
998 {
999 struct nmk_gpio_chip *nmk_chip =
1000 container_of(chip, struct nmk_gpio_chip, chip);
1001 u32 bit = 1 << offset;
1002 int value;
1003
1004 clk_enable(nmk_chip->clk);
1005
1006 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1007
1008 clk_disable(nmk_chip->clk);
1009
1010 return value;
1011 }
1012
1013 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1014 int val)
1015 {
1016 struct nmk_gpio_chip *nmk_chip =
1017 container_of(chip, struct nmk_gpio_chip, chip);
1018
1019 clk_enable(nmk_chip->clk);
1020
1021 __nmk_gpio_set_output(nmk_chip, offset, val);
1022
1023 clk_disable(nmk_chip->clk);
1024 }
1025
1026 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1027 int val)
1028 {
1029 struct nmk_gpio_chip *nmk_chip =
1030 container_of(chip, struct nmk_gpio_chip, chip);
1031
1032 clk_enable(nmk_chip->clk);
1033
1034 __nmk_gpio_make_output(nmk_chip, offset, val);
1035
1036 clk_disable(nmk_chip->clk);
1037
1038 return 0;
1039 }
1040
1041 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1042 {
1043 struct nmk_gpio_chip *nmk_chip =
1044 container_of(chip, struct nmk_gpio_chip, chip);
1045
1046 return irq_find_mapping(nmk_chip->domain, offset);
1047 }
1048
1049 #ifdef CONFIG_DEBUG_FS
1050
1051 #include <linux/seq_file.h>
1052
1053 static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
1054 unsigned offset, unsigned gpio)
1055 {
1056 const char *label = gpiochip_is_requested(chip, offset);
1057 struct nmk_gpio_chip *nmk_chip =
1058 container_of(chip, struct nmk_gpio_chip, chip);
1059 int mode;
1060 bool is_out;
1061 bool pull;
1062 u32 bit = 1 << offset;
1063 const char *modes[] = {
1064 [NMK_GPIO_ALT_GPIO] = "gpio",
1065 [NMK_GPIO_ALT_A] = "altA",
1066 [NMK_GPIO_ALT_B] = "altB",
1067 [NMK_GPIO_ALT_C] = "altC",
1068 };
1069
1070 clk_enable(nmk_chip->clk);
1071 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1072 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1073 mode = nmk_gpio_get_mode(gpio);
1074
1075 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1076 gpio, label ?: "(none)",
1077 is_out ? "out" : "in ",
1078 chip->get
1079 ? (chip->get(chip, offset) ? "hi" : "lo")
1080 : "? ",
1081 (mode < 0) ? "unknown" : modes[mode],
1082 pull ? "pull" : "none");
1083
1084 if (label && !is_out) {
1085 int irq = gpio_to_irq(gpio);
1086 struct irq_desc *desc = irq_to_desc(irq);
1087
1088 /* This races with request_irq(), set_irq_type(),
1089 * and set_irq_wake() ... but those are "rare".
1090 */
1091 if (irq >= 0 && desc->action) {
1092 char *trigger;
1093 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1094
1095 if (nmk_chip->edge_rising & bitmask)
1096 trigger = "edge-rising";
1097 else if (nmk_chip->edge_falling & bitmask)
1098 trigger = "edge-falling";
1099 else
1100 trigger = "edge-undefined";
1101
1102 seq_printf(s, " irq-%d %s%s",
1103 irq, trigger,
1104 irqd_is_wakeup_set(&desc->irq_data)
1105 ? " wakeup" : "");
1106 }
1107 }
1108 clk_disable(nmk_chip->clk);
1109 }
1110
1111 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1112 {
1113 unsigned i;
1114 unsigned gpio = chip->base;
1115
1116 for (i = 0; i < chip->ngpio; i++, gpio++) {
1117 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1118 seq_printf(s, "\n");
1119 }
1120 }
1121
1122 #else
1123 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1124 struct gpio_chip *chip,
1125 unsigned offset, unsigned gpio)
1126 {
1127 }
1128 #define nmk_gpio_dbg_show NULL
1129 #endif
1130
1131 /* This structure is replicated for each GPIO block allocated at probe time */
1132 static struct gpio_chip nmk_gpio_template = {
1133 .request = nmk_gpio_request,
1134 .free = nmk_gpio_free,
1135 .direction_input = nmk_gpio_make_input,
1136 .get = nmk_gpio_get_input,
1137 .direction_output = nmk_gpio_make_output,
1138 .set = nmk_gpio_set_output,
1139 .to_irq = nmk_gpio_to_irq,
1140 .dbg_show = nmk_gpio_dbg_show,
1141 .can_sleep = 0,
1142 };
1143
1144 void nmk_gpio_clocks_enable(void)
1145 {
1146 int i;
1147
1148 for (i = 0; i < NUM_BANKS; i++) {
1149 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1150
1151 if (!chip)
1152 continue;
1153
1154 clk_enable(chip->clk);
1155 }
1156 }
1157
1158 void nmk_gpio_clocks_disable(void)
1159 {
1160 int i;
1161
1162 for (i = 0; i < NUM_BANKS; i++) {
1163 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1164
1165 if (!chip)
1166 continue;
1167
1168 clk_disable(chip->clk);
1169 }
1170 }
1171
1172 /*
1173 * Called from the suspend/resume path to only keep the real wakeup interrupts
1174 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1175 * and not the rest of the interrupts which we needed to have as wakeups for
1176 * cpuidle.
1177 *
1178 * PM ops are not used since this needs to be done at the end, after all the
1179 * other drivers are done with their suspend callbacks.
1180 */
1181 void nmk_gpio_wakeups_suspend(void)
1182 {
1183 int i;
1184
1185 for (i = 0; i < NUM_BANKS; i++) {
1186 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1187
1188 if (!chip)
1189 break;
1190
1191 clk_enable(chip->clk);
1192
1193 writel(chip->rwimsc & chip->real_wake,
1194 chip->addr + NMK_GPIO_RWIMSC);
1195 writel(chip->fwimsc & chip->real_wake,
1196 chip->addr + NMK_GPIO_FWIMSC);
1197
1198 clk_disable(chip->clk);
1199 }
1200 }
1201
1202 void nmk_gpio_wakeups_resume(void)
1203 {
1204 int i;
1205
1206 for (i = 0; i < NUM_BANKS; i++) {
1207 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1208
1209 if (!chip)
1210 break;
1211
1212 clk_enable(chip->clk);
1213
1214 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1215 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1216
1217 clk_disable(chip->clk);
1218 }
1219 }
1220
1221 /*
1222 * Read the pull up/pull down status.
1223 * A bit set in 'pull_up' means that pull up
1224 * is selected if pull is enabled in PDIS register.
1225 * Note: only pull up/down set via this driver can
1226 * be detected due to HW limitations.
1227 */
1228 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1229 {
1230 if (gpio_bank < NUM_BANKS) {
1231 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1232
1233 if (!chip)
1234 return;
1235
1236 *pull_up = chip->pull_up;
1237 }
1238 }
1239
1240 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1241 irq_hw_number_t hwirq)
1242 {
1243 struct nmk_gpio_chip *nmk_chip = d->host_data;
1244
1245 if (!nmk_chip)
1246 return -EINVAL;
1247
1248 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1249 set_irq_flags(irq, IRQF_VALID);
1250 irq_set_chip_data(irq, nmk_chip);
1251 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1252
1253 return 0;
1254 }
1255
1256 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1257 .map = nmk_gpio_irq_map,
1258 .xlate = irq_domain_xlate_twocell,
1259 };
1260
1261 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1262 {
1263 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1264 struct device_node *np = dev->dev.of_node;
1265 struct nmk_gpio_chip *nmk_chip;
1266 struct gpio_chip *chip;
1267 struct resource *res;
1268 struct clk *clk;
1269 int secondary_irq;
1270 void __iomem *base;
1271 int irq;
1272 int ret;
1273
1274 if (!pdata && !np) {
1275 dev_err(&dev->dev, "No platform data or device tree found\n");
1276 return -ENODEV;
1277 }
1278
1279 if (np) {
1280 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1281 if (!pdata)
1282 return -ENOMEM;
1283
1284 if (of_get_property(np, "st,supports-sleepmode", NULL))
1285 pdata->supports_sleepmode = true;
1286
1287 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1288 dev_err(&dev->dev, "gpio-bank property not found\n");
1289 ret = -EINVAL;
1290 goto out;
1291 }
1292
1293 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1294 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1295 }
1296
1297 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1298 if (!res) {
1299 ret = -ENOENT;
1300 goto out;
1301 }
1302
1303 irq = platform_get_irq(dev, 0);
1304 if (irq < 0) {
1305 ret = irq;
1306 goto out;
1307 }
1308
1309 secondary_irq = platform_get_irq(dev, 1);
1310 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1311 ret = -EINVAL;
1312 goto out;
1313 }
1314
1315 base = devm_request_and_ioremap(&dev->dev, res);
1316 if (!base) {
1317 ret = -ENOMEM;
1318 goto out;
1319 }
1320
1321 clk = devm_clk_get(&dev->dev, NULL);
1322 if (IS_ERR(clk)) {
1323 ret = PTR_ERR(clk);
1324 goto out;
1325 }
1326 clk_prepare(clk);
1327
1328 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1329 if (!nmk_chip) {
1330 ret = -ENOMEM;
1331 goto out;
1332 }
1333
1334 /*
1335 * The virt address in nmk_chip->addr is in the nomadik register space,
1336 * so we can simply convert the resource address, without remapping
1337 */
1338 nmk_chip->bank = dev->id;
1339 nmk_chip->clk = clk;
1340 nmk_chip->addr = base;
1341 nmk_chip->chip = nmk_gpio_template;
1342 nmk_chip->parent_irq = irq;
1343 nmk_chip->secondary_parent_irq = secondary_irq;
1344 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1345 nmk_chip->set_ioforce = pdata->set_ioforce;
1346 nmk_chip->sleepmode = pdata->supports_sleepmode;
1347 spin_lock_init(&nmk_chip->lock);
1348
1349 chip = &nmk_chip->chip;
1350 chip->base = pdata->first_gpio;
1351 chip->ngpio = pdata->num_gpio;
1352 chip->label = pdata->name ?: dev_name(&dev->dev);
1353 chip->dev = &dev->dev;
1354 chip->owner = THIS_MODULE;
1355
1356 clk_enable(nmk_chip->clk);
1357 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1358 clk_disable(nmk_chip->clk);
1359
1360 #ifdef CONFIG_OF_GPIO
1361 chip->of_node = np;
1362 #endif
1363
1364 ret = gpiochip_add(&nmk_chip->chip);
1365 if (ret)
1366 goto out;
1367
1368 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1369
1370 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1371
1372 platform_set_drvdata(dev, nmk_chip);
1373
1374 if (np) {
1375 /* The DT case will just grab a set of IRQ numbers */
1376 nmk_chip->domain = irq_domain_add_linear(np, NMK_GPIO_PER_CHIP,
1377 &nmk_gpio_irq_simple_ops, nmk_chip);
1378 } else {
1379 /* Non-DT legacy mode, use hardwired IRQ numbers */
1380 int irq_start;
1381
1382 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
1383 nmk_chip->domain = irq_domain_add_simple(NULL,
1384 NMK_GPIO_PER_CHIP, irq_start,
1385 &nmk_gpio_irq_simple_ops, nmk_chip);
1386 }
1387 if (!nmk_chip->domain) {
1388 dev_err(&dev->dev, "failed to create irqdomain\n");
1389 ret = -ENOSYS;
1390 goto out;
1391 }
1392
1393 nmk_gpio_init_irq(nmk_chip);
1394
1395 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1396
1397 return 0;
1398
1399 out:
1400 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1401 pdata->first_gpio, pdata->first_gpio+31);
1402
1403 return ret;
1404 }
1405
1406 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1407 {
1408 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1409
1410 return npct->soc->ngroups;
1411 }
1412
1413 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1414 unsigned selector)
1415 {
1416 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1417
1418 return npct->soc->groups[selector].name;
1419 }
1420
1421 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1422 const unsigned **pins,
1423 unsigned *num_pins)
1424 {
1425 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1426
1427 *pins = npct->soc->groups[selector].pins;
1428 *num_pins = npct->soc->groups[selector].npins;
1429 return 0;
1430 }
1431
1432 static struct pinctrl_gpio_range *
1433 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1434 {
1435 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1436 int i;
1437
1438 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1439 struct pinctrl_gpio_range *range;
1440
1441 range = &npct->soc->gpio_ranges[i];
1442 if (offset >= range->pin_base &&
1443 offset <= (range->pin_base + range->npins - 1))
1444 return range;
1445 }
1446 return NULL;
1447 }
1448
1449 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1450 unsigned offset)
1451 {
1452 struct pinctrl_gpio_range *range;
1453 struct gpio_chip *chip;
1454
1455 range = nmk_match_gpio_range(pctldev, offset);
1456 if (!range || !range->gc) {
1457 seq_printf(s, "invalid pin offset");
1458 return;
1459 }
1460 chip = range->gc;
1461 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1462 }
1463
1464 static struct pinctrl_ops nmk_pinctrl_ops = {
1465 .get_groups_count = nmk_get_groups_cnt,
1466 .get_group_name = nmk_get_group_name,
1467 .get_group_pins = nmk_get_group_pins,
1468 .pin_dbg_show = nmk_pin_dbg_show,
1469 };
1470
1471 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1472 {
1473 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1474
1475 return npct->soc->nfunctions;
1476 }
1477
1478 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1479 unsigned function)
1480 {
1481 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1482
1483 return npct->soc->functions[function].name;
1484 }
1485
1486 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1487 unsigned function,
1488 const char * const **groups,
1489 unsigned * const num_groups)
1490 {
1491 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1492
1493 *groups = npct->soc->functions[function].groups;
1494 *num_groups = npct->soc->functions[function].ngroups;
1495
1496 return 0;
1497 }
1498
1499 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1500 unsigned group)
1501 {
1502 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1503 const struct nmk_pingroup *g;
1504 static unsigned int slpm[NUM_BANKS];
1505 unsigned long flags;
1506 bool glitch;
1507 int ret = -EINVAL;
1508 int i;
1509
1510 g = &npct->soc->groups[group];
1511
1512 if (g->altsetting < 0)
1513 return -EINVAL;
1514
1515 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1516
1517 /*
1518 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1519 * we may pass through an undesired state. In this case we take
1520 * some extra care.
1521 *
1522 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1523 * - Save SLPM registers (since we have a shadow register in the
1524 * nmk_chip we're using that as backup)
1525 * - Set SLPM=0 for the IOs you want to switch and others to 1
1526 * - Configure the GPIO registers for the IOs that are being switched
1527 * - Set IOFORCE=1
1528 * - Modify the AFLSA/B registers for the IOs that are being switched
1529 * - Set IOFORCE=0
1530 * - Restore SLPM registers
1531 * - Any spurious wake up event during switch sequence to be ignored
1532 * and cleared
1533 *
1534 * We REALLY need to save ALL slpm registers, because the external
1535 * IOFORCE will switch *all* ports to their sleepmode setting to as
1536 * to avoid glitches. (Not just one port!)
1537 */
1538 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1539
1540 if (glitch) {
1541 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1542
1543 /* Initially don't put any pins to sleep when switching */
1544 memset(slpm, 0xff, sizeof(slpm));
1545
1546 /*
1547 * Then mask the pins that need to be sleeping now when we're
1548 * switching to the ALT C function.
1549 */
1550 for (i = 0; i < g->npins; i++)
1551 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1552 nmk_gpio_glitch_slpm_init(slpm);
1553 }
1554
1555 for (i = 0; i < g->npins; i++) {
1556 struct pinctrl_gpio_range *range;
1557 struct nmk_gpio_chip *nmk_chip;
1558 struct gpio_chip *chip;
1559 unsigned bit;
1560
1561 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1562 if (!range) {
1563 dev_err(npct->dev,
1564 "invalid pin offset %d in group %s at index %d\n",
1565 g->pins[i], g->name, i);
1566 goto out_glitch;
1567 }
1568 if (!range->gc) {
1569 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1570 g->pins[i], g->name, i);
1571 goto out_glitch;
1572 }
1573 chip = range->gc;
1574 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1575 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1576
1577 clk_enable(nmk_chip->clk);
1578 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1579 /*
1580 * If the pin is switching to altfunc, and there was an
1581 * interrupt installed on it which has been lazy disabled,
1582 * actually mask the interrupt to prevent spurious interrupts
1583 * that would occur while the pin is under control of the
1584 * peripheral. Only SKE does this.
1585 */
1586 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1587
1588 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1589 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1590 clk_disable(nmk_chip->clk);
1591
1592 /*
1593 * Call PRCM GPIOCR config function in case ALTC
1594 * has been selected:
1595 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1596 * must be set.
1597 * - If selection is pure ALTC and previous selection was ALTCx,
1598 * then some bits in PRCM GPIOCR registers must be cleared.
1599 */
1600 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1601 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1602 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1603 }
1604
1605 /* When all pins are successfully reconfigured we get here */
1606 ret = 0;
1607
1608 out_glitch:
1609 if (glitch) {
1610 nmk_gpio_glitch_slpm_restore(slpm);
1611 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1612 }
1613
1614 return ret;
1615 }
1616
1617 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1618 unsigned function, unsigned group)
1619 {
1620 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1621 const struct nmk_pingroup *g;
1622
1623 g = &npct->soc->groups[group];
1624
1625 if (g->altsetting < 0)
1626 return;
1627
1628 /* Poke out the mux, set the pin to some default state? */
1629 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1630 }
1631
1632 int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1633 struct pinctrl_gpio_range *range,
1634 unsigned offset)
1635 {
1636 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1637 struct nmk_gpio_chip *nmk_chip;
1638 struct gpio_chip *chip;
1639 unsigned bit;
1640
1641 if (!range) {
1642 dev_err(npct->dev, "invalid range\n");
1643 return -EINVAL;
1644 }
1645 if (!range->gc) {
1646 dev_err(npct->dev, "missing GPIO chip in range\n");
1647 return -EINVAL;
1648 }
1649 chip = range->gc;
1650 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1651
1652 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1653
1654 clk_enable(nmk_chip->clk);
1655 bit = offset % NMK_GPIO_PER_CHIP;
1656 /* There is no glitch when converting any pin to GPIO */
1657 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1658 clk_disable(nmk_chip->clk);
1659
1660 return 0;
1661 }
1662
1663 void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1664 struct pinctrl_gpio_range *range,
1665 unsigned offset)
1666 {
1667 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1668
1669 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1670 /* Set the pin to some default state, GPIO is usually default */
1671 }
1672
1673 static struct pinmux_ops nmk_pinmux_ops = {
1674 .get_functions_count = nmk_pmx_get_funcs_cnt,
1675 .get_function_name = nmk_pmx_get_func_name,
1676 .get_function_groups = nmk_pmx_get_func_groups,
1677 .enable = nmk_pmx_enable,
1678 .disable = nmk_pmx_disable,
1679 .gpio_request_enable = nmk_gpio_request_enable,
1680 .gpio_disable_free = nmk_gpio_disable_free,
1681 };
1682
1683 int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1684 unsigned pin,
1685 unsigned long *config)
1686 {
1687 /* Not implemented */
1688 return -EINVAL;
1689 }
1690
1691 int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1692 unsigned pin,
1693 unsigned long config)
1694 {
1695 static const char *pullnames[] = {
1696 [NMK_GPIO_PULL_NONE] = "none",
1697 [NMK_GPIO_PULL_UP] = "up",
1698 [NMK_GPIO_PULL_DOWN] = "down",
1699 [3] /* illegal */ = "??"
1700 };
1701 static const char *slpmnames[] = {
1702 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1703 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1704 };
1705 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1706 struct nmk_gpio_chip *nmk_chip;
1707 struct pinctrl_gpio_range *range;
1708 struct gpio_chip *chip;
1709 unsigned bit;
1710
1711 /*
1712 * The pin config contains pin number and altfunction fields, here
1713 * we just ignore that part. It's being handled by the framework and
1714 * pinmux callback respectively.
1715 */
1716 pin_cfg_t cfg = (pin_cfg_t) config;
1717 int pull = PIN_PULL(cfg);
1718 int slpm = PIN_SLPM(cfg);
1719 int output = PIN_DIR(cfg);
1720 int val = PIN_VAL(cfg);
1721 bool lowemi = PIN_LOWEMI(cfg);
1722 bool gpiomode = PIN_GPIOMODE(cfg);
1723 bool sleep = PIN_SLEEPMODE(cfg);
1724
1725 range = nmk_match_gpio_range(pctldev, pin);
1726 if (!range) {
1727 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1728 return -EINVAL;
1729 }
1730 if (!range->gc) {
1731 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1732 pin);
1733 return -EINVAL;
1734 }
1735 chip = range->gc;
1736 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1737
1738 if (sleep) {
1739 int slpm_pull = PIN_SLPM_PULL(cfg);
1740 int slpm_output = PIN_SLPM_DIR(cfg);
1741 int slpm_val = PIN_SLPM_VAL(cfg);
1742
1743 /* All pins go into GPIO mode at sleep */
1744 gpiomode = true;
1745
1746 /*
1747 * The SLPM_* values are normal values + 1 to allow zero to
1748 * mean "same as normal".
1749 */
1750 if (slpm_pull)
1751 pull = slpm_pull - 1;
1752 if (slpm_output)
1753 output = slpm_output - 1;
1754 if (slpm_val)
1755 val = slpm_val - 1;
1756
1757 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1758 pin,
1759 slpm_pull ? pullnames[pull] : "same",
1760 slpm_output ? (output ? "output" : "input") : "same",
1761 slpm_val ? (val ? "high" : "low") : "same");
1762 }
1763
1764 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1765 pin, cfg, pullnames[pull], slpmnames[slpm],
1766 output ? "output " : "input",
1767 output ? (val ? "high" : "low") : "",
1768 lowemi ? "on" : "off" );
1769
1770 clk_enable(nmk_chip->clk);
1771 bit = pin % NMK_GPIO_PER_CHIP;
1772 if (gpiomode)
1773 /* No glitch when going to GPIO mode */
1774 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1775 if (output)
1776 __nmk_gpio_make_output(nmk_chip, bit, val);
1777 else {
1778 __nmk_gpio_make_input(nmk_chip, bit);
1779 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1780 }
1781 /* TODO: isn't this only applicable on output pins? */
1782 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1783
1784 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1785 clk_disable(nmk_chip->clk);
1786 return 0;
1787 }
1788
1789 static struct pinconf_ops nmk_pinconf_ops = {
1790 .pin_config_get = nmk_pin_config_get,
1791 .pin_config_set = nmk_pin_config_set,
1792 };
1793
1794 static struct pinctrl_desc nmk_pinctrl_desc = {
1795 .name = "pinctrl-nomadik",
1796 .pctlops = &nmk_pinctrl_ops,
1797 .pmxops = &nmk_pinmux_ops,
1798 .confops = &nmk_pinconf_ops,
1799 .owner = THIS_MODULE,
1800 };
1801
1802 static const struct of_device_id nmk_pinctrl_match[] = {
1803 {
1804 .compatible = "stericsson,nmk_pinctrl",
1805 .data = (void *)PINCTRL_NMK_DB8500,
1806 },
1807 {},
1808 };
1809
1810 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1811 {
1812 const struct platform_device_id *platid = platform_get_device_id(pdev);
1813 struct device_node *np = pdev->dev.of_node;
1814 struct nmk_pinctrl *npct;
1815 unsigned int version = 0;
1816 int i;
1817
1818 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1819 if (!npct)
1820 return -ENOMEM;
1821
1822 if (platid)
1823 version = platid->driver_data;
1824 else if (np)
1825 version = (unsigned int)
1826 of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
1827
1828 /* Poke in other ASIC variants here */
1829 if (version == PINCTRL_NMK_STN8815)
1830 nmk_pinctrl_stn8815_init(&npct->soc);
1831 if (version == PINCTRL_NMK_DB8500)
1832 nmk_pinctrl_db8500_init(&npct->soc);
1833 if (version == PINCTRL_NMK_DB8540)
1834 nmk_pinctrl_db8540_init(&npct->soc);
1835
1836 /*
1837 * We need all the GPIO drivers to probe FIRST, or we will not be able
1838 * to obtain references to the struct gpio_chip * for them, and we
1839 * need this to proceed.
1840 */
1841 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1842 if (!nmk_gpio_chips[i]) {
1843 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1844 return -EPROBE_DEFER;
1845 }
1846 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1847 }
1848
1849 nmk_pinctrl_desc.pins = npct->soc->pins;
1850 nmk_pinctrl_desc.npins = npct->soc->npins;
1851 npct->dev = &pdev->dev;
1852 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1853 if (!npct->pctl) {
1854 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1855 return -EINVAL;
1856 }
1857
1858 /* We will handle a range of GPIO pins */
1859 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1860 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1861
1862 platform_set_drvdata(pdev, npct);
1863 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1864
1865 return 0;
1866 }
1867
1868 static const struct of_device_id nmk_gpio_match[] = {
1869 { .compatible = "st,nomadik-gpio", },
1870 {}
1871 };
1872
1873 static struct platform_driver nmk_gpio_driver = {
1874 .driver = {
1875 .owner = THIS_MODULE,
1876 .name = "gpio",
1877 .of_match_table = nmk_gpio_match,
1878 },
1879 .probe = nmk_gpio_probe,
1880 };
1881
1882 static const struct platform_device_id nmk_pinctrl_id[] = {
1883 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1884 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1885 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1886 };
1887
1888 static struct platform_driver nmk_pinctrl_driver = {
1889 .driver = {
1890 .owner = THIS_MODULE,
1891 .name = "pinctrl-nomadik",
1892 .of_match_table = nmk_pinctrl_match,
1893 },
1894 .probe = nmk_pinctrl_probe,
1895 .id_table = nmk_pinctrl_id,
1896 };
1897
1898 static int __init nmk_gpio_init(void)
1899 {
1900 int ret;
1901
1902 ret = platform_driver_register(&nmk_gpio_driver);
1903 if (ret)
1904 return ret;
1905 return platform_driver_register(&nmk_pinctrl_driver);
1906 }
1907
1908 core_initcall(nmk_gpio_init);
1909
1910 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1911 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1912 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)