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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pcmcia / m8xx_pcmcia.c
1 /*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@opensource.se>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
12 *
13 * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
15 *
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
20 *
21 * This controller does _not_ meet the ExCA standard.
22 *
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
28 *
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
35 */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/fcntl.h>
41 #include <linux/string.h>
42
43 #include <linux/kernel.h>
44 #include <linux/errno.h>
45 #include <linux/timer.h>
46 #include <linux/ioport.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <linux/fsl_devices.h>
50 #include <linux/bitops.h>
51 #include <linux/of_device.h>
52 #include <linux/of_platform.h>
53
54 #include <asm/io.h>
55 #include <asm/system.h>
56 #include <asm/time.h>
57 #include <asm/mpc8xx.h>
58 #include <asm/8xx_immap.h>
59 #include <asm/irq.h>
60 #include <asm/fs_pd.h>
61
62 #include <pcmcia/cs_types.h>
63 #include <pcmcia/cs.h>
64 #include <pcmcia/ss.h>
65
66 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
67 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
68
69 static const char *version = "Version 0.06, Aug 2005";
70 MODULE_LICENSE("Dual MPL/GPL");
71
72 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
73
74 /* The RPX series use SLOT_B */
75 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
76 #define CONFIG_PCMCIA_SLOT_B
77 #define CONFIG_BD_IS_MHZ
78 #endif
79
80 /* The ADS board use SLOT_A */
81 #ifdef CONFIG_ADS
82 #define CONFIG_PCMCIA_SLOT_A
83 #define CONFIG_BD_IS_MHZ
84 #endif
85
86 /* The FADS series are a mess */
87 #ifdef CONFIG_FADS
88 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
89 #define CONFIG_PCMCIA_SLOT_A
90 #else
91 #define CONFIG_PCMCIA_SLOT_B
92 #endif
93 #endif
94
95 #if defined(CONFIG_MPC885ADS)
96 #define CONFIG_PCMCIA_SLOT_A
97 #define PCMCIA_GLITCHY_CD
98 #endif
99
100 /* Cyclades ACS uses both slots */
101 #ifdef CONFIG_PRxK
102 #define CONFIG_PCMCIA_SLOT_A
103 #define CONFIG_PCMCIA_SLOT_B
104 #endif
105
106 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
107
108 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
109
110 #define PCMCIA_SOCKETS_NO 2
111 /* We have only 8 windows, dualsocket support will be limited. */
112 #define PCMCIA_MEM_WIN_NO 2
113 #define PCMCIA_IO_WIN_NO 2
114 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
115
116 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
117
118 #define PCMCIA_SOCKETS_NO 1
119 /* full support for one slot */
120 #define PCMCIA_MEM_WIN_NO 5
121 #define PCMCIA_IO_WIN_NO 2
122
123 /* define _slot_ to be able to optimize macros */
124
125 #ifdef CONFIG_PCMCIA_SLOT_A
126 #define _slot_ 0
127 #define PCMCIA_SLOT_MSG "SLOT_A"
128 #else
129 #define _slot_ 1
130 #define PCMCIA_SLOT_MSG "SLOT_B"
131 #endif
132
133 #else
134 #error m8xx_pcmcia: Bad configuration!
135 #endif
136
137 /* ------------------------------------------------------------------------- */
138
139 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
140 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
141 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
142 /* ------------------------------------------------------------------------- */
143
144 static int pcmcia_schlvl;
145
146 static DEFINE_SPINLOCK(events_lock);
147
148 #define PCMCIA_SOCKET_KEY_5V 1
149 #define PCMCIA_SOCKET_KEY_LV 2
150
151 /* look up table for pgcrx registers */
152 static u32 *m8xx_pgcrx[2];
153
154 /*
155 * This structure is used to address each window in the PCMCIA controller.
156 *
157 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
158 * after pcmcia_win[n]...
159 */
160
161 struct pcmcia_win {
162 u32 br;
163 u32 or;
164 };
165
166 /*
167 * For some reason the hardware guys decided to make both slots share
168 * some registers.
169 *
170 * Could someone invent object oriented hardware ?
171 *
172 * The macros are used to get the right bit from the registers.
173 * SLOT_A : slot = 0
174 * SLOT_B : slot = 1
175 */
176
177 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
178 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
179 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
180 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
181
182 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
183 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
184 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
185 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
186 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
187 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
188 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
189 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
190 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
191 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
192 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
193
194 #define M8XX_PCMCIA_POR_VALID 0x00000001
195 #define M8XX_PCMCIA_POR_WRPROT 0x00000002
196 #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
197 #define M8XX_PCMCIA_POR_IO 0x00000018
198 #define M8XX_PCMCIA_POR_16BIT 0x00000040
199
200 #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
201
202 #define M8XX_PGCRX_CXOE 0x00000080
203 #define M8XX_PGCRX_CXRESET 0x00000040
204
205 /* we keep one lookup table per socket to check flags */
206
207 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
208
209 struct event_table {
210 u32 regbit;
211 u32 eventbit;
212 };
213
214 static const char driver_name[] = "m8xx-pcmcia";
215
216 struct socket_info {
217 void (*handler) (void *info, u32 events);
218 void *info;
219
220 u32 slot;
221 pcmconf8xx_t *pcmcia;
222 u32 bus_freq;
223 int hwirq;
224
225 socket_state_t state;
226 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
227 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
228 struct event_table events[PCMCIA_EVENTS_MAX];
229 struct pcmcia_socket socket;
230 };
231
232 static struct socket_info socket[PCMCIA_SOCKETS_NO];
233
234 /*
235 * Search this table to see if the windowsize is
236 * supported...
237 */
238
239 #define M8XX_SIZES_NO 32
240
241 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
242 0x00000001, 0x00000002, 0x00000008, 0x00000004,
243 0x00000080, 0x00000040, 0x00000010, 0x00000020,
244 0x00008000, 0x00004000, 0x00001000, 0x00002000,
245 0x00000100, 0x00000200, 0x00000800, 0x00000400,
246
247 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
248 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
249 0x00010000, 0x00020000, 0x00080000, 0x00040000,
250 0x00800000, 0x00400000, 0x00100000, 0x00200000
251 };
252
253 /* ------------------------------------------------------------------------- */
254
255 static irqreturn_t m8xx_interrupt(int irq, void *dev);
256
257 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
258
259 /* ------------------------------------------------------------------------- */
260 /* board specific stuff: */
261 /* voltage_set(), hardware_enable() and hardware_disable() */
262 /* ------------------------------------------------------------------------- */
263 /* RPX Boards from Embedded Planet */
264
265 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
266
267 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
268 * SYPCR is write once only, therefore must the slowest memory be faster
269 * than the bus monitor or we will get a machine check due to the bus timeout.
270 */
271
272 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
273
274 #undef PCMCIA_BMT_LIMIT
275 #define PCMCIA_BMT_LIMIT (6*8)
276
277 static int voltage_set(int slot, int vcc, int vpp)
278 {
279 u32 reg = 0;
280
281 switch (vcc) {
282 case 0:
283 break;
284 case 33:
285 reg |= BCSR1_PCVCTL4;
286 break;
287 case 50:
288 reg |= BCSR1_PCVCTL5;
289 break;
290 default:
291 return 1;
292 }
293
294 switch (vpp) {
295 case 0:
296 break;
297 case 33:
298 case 50:
299 if (vcc == vpp)
300 reg |= BCSR1_PCVCTL6;
301 else
302 return 1;
303 break;
304 case 120:
305 reg |= BCSR1_PCVCTL7;
306 default:
307 return 1;
308 }
309
310 if (!((vcc == 50) || (vcc == 0)))
311 return 1;
312
313 /* first, turn off all power */
314
315 out_be32(((u32 *) RPX_CSR_ADDR),
316 in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
317 BCSR1_PCVCTL5 |
318 BCSR1_PCVCTL6 |
319 BCSR1_PCVCTL7));
320
321 /* enable new powersettings */
322
323 out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
324
325 return 0;
326 }
327
328 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
329 #define hardware_enable(_slot_) /* No hardware to enable */
330 #define hardware_disable(_slot_) /* No hardware to disable */
331
332 #endif /* CONFIG_RPXCLASSIC */
333
334 /* FADS Boards from Motorola */
335
336 #if defined(CONFIG_FADS)
337
338 #define PCMCIA_BOARD_MSG "FADS"
339
340 static int voltage_set(int slot, int vcc, int vpp)
341 {
342 u32 reg = 0;
343
344 switch (vcc) {
345 case 0:
346 break;
347 case 33:
348 reg |= BCSR1_PCCVCC0;
349 break;
350 case 50:
351 reg |= BCSR1_PCCVCC1;
352 break;
353 default:
354 return 1;
355 }
356
357 switch (vpp) {
358 case 0:
359 break;
360 case 33:
361 case 50:
362 if (vcc == vpp)
363 reg |= BCSR1_PCCVPP1;
364 else
365 return 1;
366 break;
367 case 120:
368 if ((vcc == 33) || (vcc == 50))
369 reg |= BCSR1_PCCVPP0;
370 else
371 return 1;
372 default:
373 return 1;
374 }
375
376 /* first, turn off all power */
377 out_be32((u32 *) BCSR1,
378 in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
379 BCSR1_PCCVPP_MASK));
380
381 /* enable new powersettings */
382 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
383
384 return 0;
385 }
386
387 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
388
389 static void hardware_enable(int slot)
390 {
391 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
392 }
393
394 static void hardware_disable(int slot)
395 {
396 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
397 }
398
399 #endif
400
401 /* MPC885ADS Boards */
402
403 #if defined(CONFIG_MPC885ADS)
404
405 #define PCMCIA_BOARD_MSG "MPC885ADS"
406 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
407
408 static inline void hardware_enable(int slot)
409 {
410 m8xx_pcmcia_ops.hw_ctrl(slot, 1);
411 }
412
413 static inline void hardware_disable(int slot)
414 {
415 m8xx_pcmcia_ops.hw_ctrl(slot, 0);
416 }
417
418 static inline int voltage_set(int slot, int vcc, int vpp)
419 {
420 return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
421 }
422
423 #endif
424
425 /* ------------------------------------------------------------------------- */
426 /* Motorola MBX860 */
427
428 #if defined(CONFIG_MBX)
429
430 #define PCMCIA_BOARD_MSG "MBX"
431
432 static int voltage_set(int slot, int vcc, int vpp)
433 {
434 u8 reg = 0;
435
436 switch (vcc) {
437 case 0:
438 break;
439 case 33:
440 reg |= CSR2_VCC_33;
441 break;
442 case 50:
443 reg |= CSR2_VCC_50;
444 break;
445 default:
446 return 1;
447 }
448
449 switch (vpp) {
450 case 0:
451 break;
452 case 33:
453 case 50:
454 if (vcc == vpp)
455 reg |= CSR2_VPP_VCC;
456 else
457 return 1;
458 break;
459 case 120:
460 if ((vcc == 33) || (vcc == 50))
461 reg |= CSR2_VPP_12;
462 else
463 return 1;
464 default:
465 return 1;
466 }
467
468 /* first, turn off all power */
469 out_8((u8 *) MBX_CSR2_ADDR,
470 in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
471
472 /* enable new powersettings */
473 out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
474
475 return 0;
476 }
477
478 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
479 #define hardware_enable(_slot_) /* No hardware to enable */
480 #define hardware_disable(_slot_) /* No hardware to disable */
481
482 #endif /* CONFIG_MBX */
483
484 #if defined(CONFIG_PRxK)
485 #include <asm/cpld.h>
486 extern volatile fpga_pc_regs *fpga_pc;
487
488 #define PCMCIA_BOARD_MSG "MPC855T"
489
490 static int voltage_set(int slot, int vcc, int vpp)
491 {
492 u8 reg = 0;
493 u8 regread;
494 cpld_regs *ccpld = get_cpld();
495
496 switch (vcc) {
497 case 0:
498 break;
499 case 33:
500 reg |= PCMCIA_VCC_33;
501 break;
502 case 50:
503 reg |= PCMCIA_VCC_50;
504 break;
505 default:
506 return 1;
507 }
508
509 switch (vpp) {
510 case 0:
511 break;
512 case 33:
513 case 50:
514 if (vcc == vpp)
515 reg |= PCMCIA_VPP_VCC;
516 else
517 return 1;
518 break;
519 case 120:
520 if ((vcc == 33) || (vcc == 50))
521 reg |= PCMCIA_VPP_12;
522 else
523 return 1;
524 default:
525 return 1;
526 }
527
528 reg = reg >> (slot << 2);
529 regread = in_8(&ccpld->fpga_pc_ctl);
530 if (reg !=
531 (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
532 /* enable new powersettings */
533 regread =
534 regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
535 (slot << 2));
536 out_8(&ccpld->fpga_pc_ctl, reg | regread);
537 msleep(100);
538 }
539
540 return 0;
541 }
542
543 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
544 #define hardware_enable(_slot_) /* No hardware to enable */
545 #define hardware_disable(_slot_) /* No hardware to disable */
546
547 #endif /* CONFIG_PRxK */
548
549 static u32 pending_events[PCMCIA_SOCKETS_NO];
550 static DEFINE_SPINLOCK(pending_event_lock);
551
552 static irqreturn_t m8xx_interrupt(int irq, void *dev)
553 {
554 struct socket_info *s;
555 struct event_table *e;
556 unsigned int i, events, pscr, pipr, per;
557 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
558
559 pr_debug("m8xx_pcmcia: Interrupt!\n");
560 /* get interrupt sources */
561
562 pscr = in_be32(&pcmcia->pcmc_pscr);
563 pipr = in_be32(&pcmcia->pcmc_pipr);
564 per = in_be32(&pcmcia->pcmc_per);
565
566 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
567 s = &socket[i];
568 e = &s->events[0];
569 events = 0;
570
571 while (e->regbit) {
572 if (pscr & e->regbit)
573 events |= e->eventbit;
574
575 e++;
576 }
577
578 /*
579 * report only if both card detect signals are the same
580 * not too nice done,
581 * we depend on that CD2 is the bit to the left of CD1...
582 */
583 if (events & SS_DETECT)
584 if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
585 (pipr & M8XX_PCMCIA_CD1(i))) {
586 events &= ~SS_DETECT;
587 }
588 #ifdef PCMCIA_GLITCHY_CD
589 /*
590 * I've experienced CD problems with my ADS board.
591 * We make an extra check to see if there was a
592 * real change of Card detection.
593 */
594
595 if ((events & SS_DETECT) &&
596 ((pipr &
597 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
598 (s->state.Vcc | s->state.Vpp)) {
599 events &= ~SS_DETECT;
600 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
601 (pipr & (M8XX_PCMCIA_CD2(i)
602 | M8XX_PCMCIA_CD1(i)))); */
603 }
604 #endif
605
606 /* call the handler */
607
608 pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, "
609 "pipr = 0x%08x\n", i, events, pscr, pipr);
610
611 if (events) {
612 spin_lock(&pending_event_lock);
613 pending_events[i] |= events;
614 spin_unlock(&pending_event_lock);
615 /*
616 * Turn off RDY_L bits in the PER mask on
617 * CD interrupt receival.
618 *
619 * They can generate bad interrupts on the
620 * ACS4,8,16,32. - marcelo
621 */
622 per &= ~M8XX_PCMCIA_RDY_L(0);
623 per &= ~M8XX_PCMCIA_RDY_L(1);
624
625 out_be32(&pcmcia->pcmc_per, per);
626
627 if (events)
628 pcmcia_parse_events(&socket[i].socket, events);
629 }
630 }
631
632 /* clear the interrupt sources */
633 out_be32(&pcmcia->pcmc_pscr, pscr);
634
635 pr_debug("m8xx_pcmcia: Interrupt done.\n");
636
637 return IRQ_HANDLED;
638 }
639
640 static u32 m8xx_get_graycode(u32 size)
641 {
642 u32 k;
643
644 for (k = 0; k < M8XX_SIZES_NO; k++)
645 if (m8xx_size_to_gray[k] == size)
646 break;
647
648 if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
649 k = -1;
650
651 return k;
652 }
653
654 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
655 {
656 u32 reg, clocks, psst, psl, psht;
657
658 if (!ns) {
659
660 /*
661 * We get called with IO maps setup to 0ns
662 * if not specified by the user.
663 * They should be 255ns.
664 */
665
666 if (is_io)
667 ns = 255;
668 else
669 ns = 100; /* fast memory if 0 */
670 }
671
672 /*
673 * In PSST, PSL, PSHT fields we tell the controller
674 * timing parameters in CLKOUT clock cycles.
675 * CLKOUT is the same as GCLK2_50.
676 */
677
678 /* how we want to adjust the timing - in percent */
679
680 #define ADJ 180 /* 80 % longer accesstime - to be sure */
681
682 clocks = ((bus_freq / 1000) * ns) / 1000;
683 clocks = (clocks * ADJ) / (100 * 1000);
684 if (clocks >= PCMCIA_BMT_LIMIT) {
685 printk("Max access time limit reached\n");
686 clocks = PCMCIA_BMT_LIMIT - 1;
687 }
688
689 psst = clocks / 7; /* setup time */
690 psht = clocks / 7; /* hold time */
691 psl = (clocks * 5) / 7; /* strobe length */
692
693 psst += clocks - (psst + psht + psl);
694
695 reg = psst << 12;
696 reg |= psl << 7;
697 reg |= psht << 16;
698
699 return reg;
700 }
701
702 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
703 {
704 int lsock = container_of(sock, struct socket_info, socket)->slot;
705 struct socket_info *s = &socket[lsock];
706 unsigned int pipr, reg;
707 pcmconf8xx_t *pcmcia = s->pcmcia;
708
709 pipr = in_be32(&pcmcia->pcmc_pipr);
710
711 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
712 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
713 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
714
715 if (s->state.flags & SS_IOCARD)
716 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
717 else {
718 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
719 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
720 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
721 }
722
723 if (s->state.Vcc | s->state.Vpp)
724 *value |= SS_POWERON;
725
726 /*
727 * Voltage detection:
728 * This driver only supports 16-Bit pc-cards.
729 * Cardbus is not handled here.
730 *
731 * To determine what voltage to use we must read the VS1 and VS2 pin.
732 * Depending on what socket type is present,
733 * different combinations mean different things.
734 *
735 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
736 *
737 * 5V 5V, LV* NC NC 5V only 5V (if available)
738 *
739 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
740 *
741 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
742 *
743 * LV* 5V - - shall not fit into socket
744 *
745 * LV* LV* GND NC 3.3V only 3.3V
746 *
747 * LV* LV* NC GND x.xV x.xV (if avail.)
748 *
749 * LV* LV* GND GND 3.3 or x.xV as low as possible
750 *
751 * *LV means Low Voltage
752 *
753 *
754 * That gives us the following table:
755 *
756 * Socket VS1 VS2 Voltage
757 *
758 * 5V NC NC 5V
759 * 5V NC GND none (should not be possible)
760 * 5V GND NC >= 3.3V
761 * 5V GND GND >= x.xV
762 *
763 * LV NC NC 5V (if available)
764 * LV NC GND x.xV (if available)
765 * LV GND NC 3.3V
766 * LV GND GND >= x.xV
767 *
768 * So, how do I determine if I have a 5V or a LV
769 * socket on my board? Look at the socket!
770 *
771 *
772 * Socket with 5V key:
773 * ++--------------------------------------------+
774 * || |
775 * || ||
776 * || ||
777 * | |
778 * +---------------------------------------------+
779 *
780 * Socket with LV key:
781 * ++--------------------------------------------+
782 * || |
783 * | ||
784 * | ||
785 * | |
786 * +---------------------------------------------+
787 *
788 *
789 * With other words - LV only cards does not fit
790 * into the 5V socket!
791 */
792
793 /* read out VS1 and VS2 */
794
795 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
796 >> M8XX_PCMCIA_VS_SHIFT(lsock);
797
798 if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
799 switch (reg) {
800 case 1:
801 *value |= SS_3VCARD;
802 break; /* GND, NC - 3.3V only */
803 case 2:
804 *value |= SS_XVCARD;
805 break; /* NC. GND - x.xV only */
806 };
807 }
808
809 pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value);
810 return 0;
811 }
812
813 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
814 {
815 int lsock = container_of(sock, struct socket_info, socket)->slot;
816 struct socket_info *s = &socket[lsock];
817 struct event_table *e;
818 unsigned int reg;
819 unsigned long flags;
820 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
821
822 pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
823 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
824 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
825
826 /* First, set voltage - bail out if invalid */
827 if (voltage_set(lsock, state->Vcc, state->Vpp))
828 return -EINVAL;
829
830 /* Take care of reset... */
831 if (state->flags & SS_RESET)
832 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
833 else
834 out_be32(M8XX_PGCRX(lsock),
835 in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
836
837 /* ... and output enable. */
838
839 /* The CxOE signal is connected to a 74541 on the ADS.
840 I guess most other boards used the ADS as a reference.
841 I tried to control the CxOE signal with SS_OUTPUT_ENA,
842 but the reset signal seems connected via the 541.
843 If the CxOE is left high are some signals tristated and
844 no pullups are present -> the cards act weird.
845 So right now the buffers are enabled if the power is on. */
846
847 if (state->Vcc || state->Vpp)
848 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
849 else
850 out_be32(M8XX_PGCRX(lsock),
851 in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
852
853 /*
854 * We'd better turn off interrupts before
855 * we mess with the events-table..
856 */
857
858 spin_lock_irqsave(&events_lock, flags);
859
860 /*
861 * Play around with the interrupt mask to be able to
862 * give the events the generic pcmcia driver wants us to.
863 */
864
865 e = &s->events[0];
866 reg = 0;
867
868 if (state->csc_mask & SS_DETECT) {
869 e->eventbit = SS_DETECT;
870 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
871 | M8XX_PCMCIA_CD1(lsock));
872 e++;
873 }
874 if (state->flags & SS_IOCARD) {
875 /*
876 * I/O card
877 */
878 if (state->csc_mask & SS_STSCHG) {
879 e->eventbit = SS_STSCHG;
880 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
881 e++;
882 }
883 /*
884 * If io_irq is non-zero we should enable irq.
885 */
886 if (state->io_irq) {
887 out_be32(M8XX_PGCRX(lsock),
888 in_be32(M8XX_PGCRX(lsock)) |
889 mk_int_int_mask(s->hwirq) << 24);
890 /*
891 * Strange thing here:
892 * The manual does not tell us which interrupt
893 * the sources generate.
894 * Anyhow, I found out that RDY_L generates IREQLVL.
895 *
896 * We use level triggerd interrupts, and they don't
897 * have to be cleared in PSCR in the interrupt handler.
898 */
899 reg |= M8XX_PCMCIA_RDY_L(lsock);
900 } else
901 out_be32(M8XX_PGCRX(lsock),
902 in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
903 } else {
904 /*
905 * Memory card
906 */
907 if (state->csc_mask & SS_BATDEAD) {
908 e->eventbit = SS_BATDEAD;
909 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
910 e++;
911 }
912 if (state->csc_mask & SS_BATWARN) {
913 e->eventbit = SS_BATWARN;
914 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
915 e++;
916 }
917 /* What should I trigger on - low/high,raise,fall? */
918 if (state->csc_mask & SS_READY) {
919 e->eventbit = SS_READY;
920 reg |= e->regbit = 0; //??
921 e++;
922 }
923 }
924
925 e->regbit = 0; /* terminate list */
926
927 /*
928 * Clear the status changed .
929 * Port A and Port B share the same port.
930 * Writing ones will clear the bits.
931 */
932
933 out_be32(&pcmcia->pcmc_pscr, reg);
934
935 /*
936 * Write the mask.
937 * Port A and Port B share the same port.
938 * Need for read-modify-write.
939 * Ones will enable the interrupt.
940 */
941
942 reg |=
943 in_be32(&pcmcia->
944 pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
945 out_be32(&pcmcia->pcmc_per, reg);
946
947 spin_unlock_irqrestore(&events_lock, flags);
948
949 /* copy the struct and modify the copy */
950
951 s->state = *state;
952
953 return 0;
954 }
955
956 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
957 {
958 int lsock = container_of(sock, struct socket_info, socket)->slot;
959
960 struct socket_info *s = &socket[lsock];
961 struct pcmcia_win *w;
962 unsigned int reg, winnr;
963 pcmconf8xx_t *pcmcia = s->pcmcia;
964
965 #define M8XX_SIZE (io->stop - io->start + 1)
966 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
967
968 pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, "
969 "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
970 io->speed, (unsigned long long)io->start,
971 (unsigned long long)io->stop);
972
973 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
974 || (io->stop > 0xffff) || (io->stop < io->start))
975 return -EINVAL;
976
977 if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
978 return -EINVAL;
979
980 if (io->flags & MAP_ACTIVE) {
981
982 pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n");
983
984 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
985 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
986
987 /* setup registers */
988
989 w = (void *)&pcmcia->pcmc_pbr0;
990 w += winnr;
991
992 out_be32(&w->or, 0); /* turn off window first */
993 out_be32(&w->br, M8XX_BASE);
994
995 reg <<= 27;
996 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
997
998 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
999
1000 if (io->flags & MAP_WRPROT)
1001 reg |= M8XX_PCMCIA_POR_WRPROT;
1002
1003 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1004 if (io->flags & MAP_16BIT)
1005 reg |= M8XX_PCMCIA_POR_16BIT;
1006
1007 if (io->flags & MAP_ACTIVE)
1008 reg |= M8XX_PCMCIA_POR_VALID;
1009
1010 out_be32(&w->or, reg);
1011
1012 pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at "
1013 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1014 } else {
1015 /* shutdown IO window */
1016 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1017 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1018
1019 /* setup registers */
1020
1021 w = (void *)&pcmcia->pcmc_pbr0;
1022 w += winnr;
1023
1024 out_be32(&w->or, 0); /* turn off window */
1025 out_be32(&w->br, 0); /* turn off base address */
1026
1027 pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at "
1028 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1029 }
1030
1031 /* copy the struct and modify the copy */
1032 s->io_win[io->map] = *io;
1033 s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1034 pr_debug("m8xx_pcmcia: SetIOMap exit\n");
1035
1036 return 0;
1037 }
1038
1039 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1040 struct pccard_mem_map *mem)
1041 {
1042 int lsock = container_of(sock, struct socket_info, socket)->slot;
1043 struct socket_info *s = &socket[lsock];
1044 struct pcmcia_win *w;
1045 struct pccard_mem_map *old;
1046 unsigned int reg, winnr;
1047 pcmconf8xx_t *pcmcia = s->pcmcia;
1048
1049 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1050 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1051 mem->speed, (unsigned long long)mem->static_start,
1052 mem->card_start);
1053
1054 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1055 // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1056 || (mem->card_start >= 0x04000000)
1057 || (mem->static_start & 0xfff) /* 4KByte resolution */
1058 ||(mem->card_start & 0xfff))
1059 return -EINVAL;
1060
1061 if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1062 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1063 return -EINVAL;
1064 }
1065 reg <<= 27;
1066
1067 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1068
1069 /* Setup the window in the pcmcia controller */
1070
1071 w = (void *)&pcmcia->pcmc_pbr0;
1072 w += winnr;
1073
1074 reg |= lsock << 2;
1075
1076 reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1077
1078 if (mem->flags & MAP_ATTRIB)
1079 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1080
1081 if (mem->flags & MAP_WRPROT)
1082 reg |= M8XX_PCMCIA_POR_WRPROT;
1083
1084 if (mem->flags & MAP_16BIT)
1085 reg |= M8XX_PCMCIA_POR_16BIT;
1086
1087 if (mem->flags & MAP_ACTIVE)
1088 reg |= M8XX_PCMCIA_POR_VALID;
1089
1090 out_be32(&w->or, reg);
1091
1092 pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, "
1093 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1094
1095 if (mem->flags & MAP_ACTIVE) {
1096 /* get the new base address */
1097 mem->static_start = PCMCIA_MEM_WIN_BASE +
1098 (PCMCIA_MEM_WIN_SIZE * winnr)
1099 + mem->card_start;
1100 }
1101
1102 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1103 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1104 mem->speed, (unsigned long long)mem->static_start,
1105 mem->card_start);
1106
1107 /* copy the struct and modify the copy */
1108
1109 old = &s->mem_win[mem->map];
1110
1111 *old = *mem;
1112 old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1113
1114 return 0;
1115 }
1116
1117 static int m8xx_sock_init(struct pcmcia_socket *sock)
1118 {
1119 int i;
1120 pccard_io_map io = { 0, 0, 0, 0, 1 };
1121 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1122
1123 pr_debug("m8xx_pcmcia: sock_init(%d)\n", s);
1124
1125 m8xx_set_socket(sock, &dead_socket);
1126 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1127 io.map = i;
1128 m8xx_set_io_map(sock, &io);
1129 }
1130 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1131 mem.map = i;
1132 m8xx_set_mem_map(sock, &mem);
1133 }
1134
1135 return 0;
1136
1137 }
1138
1139 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1140 {
1141 return m8xx_set_socket(sock, &dead_socket);
1142 }
1143
1144 static struct pccard_operations m8xx_services = {
1145 .init = m8xx_sock_init,
1146 .suspend = m8xx_sock_suspend,
1147 .get_status = m8xx_get_status,
1148 .set_socket = m8xx_set_socket,
1149 .set_io_map = m8xx_set_io_map,
1150 .set_mem_map = m8xx_set_mem_map,
1151 };
1152
1153 static int __init m8xx_probe(struct of_device *ofdev,
1154 const struct of_device_id *match)
1155 {
1156 struct pcmcia_win *w;
1157 unsigned int i, m, hwirq;
1158 pcmconf8xx_t *pcmcia;
1159 int status;
1160 struct device_node *np = ofdev->node;
1161
1162 pcmcia_info("%s\n", version);
1163
1164 pcmcia = of_iomap(np, 0);
1165 if (pcmcia == NULL)
1166 return -EINVAL;
1167
1168 pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1169 hwirq = irq_map[pcmcia_schlvl].hwirq;
1170 if (pcmcia_schlvl < 0) {
1171 iounmap(pcmcia);
1172 return -EINVAL;
1173 }
1174
1175 m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1176 m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1177
1178 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1179 " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq);
1180
1181 /* Configure Status change interrupt */
1182
1183 if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1184 driver_name, socket)) {
1185 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1186 pcmcia_schlvl);
1187 iounmap(pcmcia);
1188 return -1;
1189 }
1190
1191 w = (void *)&pcmcia->pcmc_pbr0;
1192
1193 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1194 clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1195
1196 /* connect interrupt and disable CxOE */
1197
1198 out_be32(M8XX_PGCRX(0),
1199 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1200 out_be32(M8XX_PGCRX(1),
1201 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1202
1203 /* intialize the fixed memory windows */
1204
1205 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1206 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1207 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1208 (PCMCIA_MEM_WIN_SIZE
1209 * (m + i * PCMCIA_MEM_WIN_NO)));
1210
1211 out_be32(&w->or, 0); /* set to not valid */
1212
1213 w++;
1214 }
1215 }
1216
1217 /* turn off voltage */
1218 voltage_set(0, 0, 0);
1219 voltage_set(1, 0, 0);
1220
1221 /* Enable external hardware */
1222 hardware_enable(0);
1223 hardware_enable(1);
1224
1225 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1226 socket[i].slot = i;
1227 socket[i].socket.owner = THIS_MODULE;
1228 socket[i].socket.features =
1229 SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1230 socket[i].socket.irq_mask = 0x000;
1231 socket[i].socket.map_size = 0x1000;
1232 socket[i].socket.io_offset = 0;
1233 socket[i].socket.pci_irq = pcmcia_schlvl;
1234 socket[i].socket.ops = &m8xx_services;
1235 socket[i].socket.resource_ops = &pccard_iodyn_ops;
1236 socket[i].socket.cb_dev = NULL;
1237 socket[i].socket.dev.parent = &ofdev->dev;
1238 socket[i].pcmcia = pcmcia;
1239 socket[i].bus_freq = ppc_proc_freq;
1240 socket[i].hwirq = hwirq;
1241
1242 }
1243
1244 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1245 status = pcmcia_register_socket(&socket[i].socket);
1246 if (status < 0)
1247 pcmcia_error("Socket register failed\n");
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int m8xx_remove(struct of_device *ofdev)
1254 {
1255 u32 m, i;
1256 struct pcmcia_win *w;
1257 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1258
1259 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1260 w = (void *)&pcmcia->pcmc_pbr0;
1261
1262 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1263 out_be32(&pcmcia->pcmc_per,
1264 in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1265
1266 /* turn off interrupt and disable CxOE */
1267 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1268
1269 /* turn off memory windows */
1270 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1271 out_be32(&w->or, 0); /* set to not valid */
1272 w++;
1273 }
1274
1275 /* turn off voltage */
1276 voltage_set(i, 0, 0);
1277
1278 /* disable external hardware */
1279 hardware_disable(i);
1280 }
1281 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1282 pcmcia_unregister_socket(&socket[i].socket);
1283 iounmap(pcmcia);
1284
1285 free_irq(pcmcia_schlvl, NULL);
1286
1287 return 0;
1288 }
1289
1290 static const struct of_device_id m8xx_pcmcia_match[] = {
1291 {
1292 .type = "pcmcia",
1293 .compatible = "fsl,pq-pcmcia",
1294 },
1295 {},
1296 };
1297
1298 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1299
1300 static struct of_platform_driver m8xx_pcmcia_driver = {
1301 .name = driver_name,
1302 .match_table = m8xx_pcmcia_match,
1303 .probe = m8xx_probe,
1304 .remove = m8xx_remove,
1305 };
1306
1307 static int __init m8xx_init(void)
1308 {
1309 return of_register_platform_driver(&m8xx_pcmcia_driver);
1310 }
1311
1312 static void __exit m8xx_exit(void)
1313 {
1314 of_unregister_platform_driver(&m8xx_pcmcia_driver);
1315 }
1316
1317 module_init(m8xx_init);
1318 module_exit(m8xx_exit);
kernel source for telekom puls (alcatel/mediatek)