2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 #define DEBUG_CONFIG 1
32 #define DBG(x...) printk(x)
37 #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
40 * FIXME: IO should be max 256 bytes. However, since we may
41 * have a P2P bridge below a cardbus bridge, we need 4K.
43 #define CARDBUS_IO_SIZE (4096)
44 #define CARDBUS_MEM_SIZE (32*1024*1024)
47 pbus_assign_resources_sorted(struct pci_bus
*bus
)
51 struct resource_list head
, *list
, *tmp
;
54 bus
->bridge_ctl
&= ~PCI_BRIDGE_CTL_VGA
;
57 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
58 u16
class = dev
->class >> 8;
60 /* Don't touch classless devices and host bridges. */
61 if (class == PCI_CLASS_NOT_DEFINED
||
62 class == PCI_CLASS_BRIDGE_HOST
)
65 if (class == PCI_CLASS_DISPLAY_VGA
||
66 class == PCI_CLASS_NOT_DEFINED_VGA
)
67 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_VGA
;
69 pdev_sort_resources(dev
, &head
);
72 for (list
= head
.next
; list
;) {
74 idx
= res
- &list
->dev
->resource
[0];
75 if (pci_assign_resource(list
->dev
, idx
)) {
86 pci_setup_cardbus(struct pci_bus
*bus
)
88 struct pci_dev
*bridge
= bus
->self
;
89 struct pci_bus_region region
;
91 printk("PCI: Bus %d, cardbus bridge: %s\n",
92 bus
->number
, pci_name(bridge
));
94 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[0]);
95 if (bus
->resource
[0]->flags
& IORESOURCE_IO
) {
97 * The IO resource is allocated a range twice as large as it
98 * would normally need. This allows us to set both IO regs.
100 printk(" IO window: %08lx-%08lx\n",
101 region
.start
, region
.end
);
102 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_0
,
104 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_0
,
108 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[1]);
109 if (bus
->resource
[1]->flags
& IORESOURCE_IO
) {
110 printk(" IO window: %08lx-%08lx\n",
111 region
.start
, region
.end
);
112 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_1
,
114 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_1
,
118 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[2]);
119 if (bus
->resource
[2]->flags
& IORESOURCE_MEM
) {
120 printk(" PREFETCH window: %08lx-%08lx\n",
121 region
.start
, region
.end
);
122 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_0
,
124 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_0
,
128 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[3]);
129 if (bus
->resource
[3]->flags
& IORESOURCE_MEM
) {
130 printk(" MEM window: %08lx-%08lx\n",
131 region
.start
, region
.end
);
132 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_1
,
134 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_1
,
139 /* Initialize bridges with base/limit values we have collected.
140 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
141 requires that if there is no I/O ports or memory behind the
142 bridge, corresponding range must be turned off by writing base
143 value greater than limit to the bridge's base/limit registers.
145 Note: care must be taken when updating I/O base/limit registers
146 of bridges which support 32-bit I/O. This update requires two
147 config space writes, so it's quite possible that an I/O window of
148 the bridge will have some undesirable address (e.g. 0) after the
149 first write. Ditto 64-bit prefetchable MMIO. */
150 static void __devinit
151 pci_setup_bridge(struct pci_bus
*bus
)
153 struct pci_dev
*bridge
= bus
->self
;
154 struct pci_bus_region region
;
157 DBG(KERN_INFO
"PCI: Bridge: %s\n", pci_name(bridge
));
159 /* Set up the top and bottom of the PCI I/O segment for this bus. */
160 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[0]);
161 if (bus
->resource
[0]->flags
& IORESOURCE_IO
) {
162 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
164 l
|= (region
.start
>> 8) & 0x00f0;
165 l
|= region
.end
& 0xf000;
166 /* Set up upper 16 bits of I/O base/limit. */
167 io_upper16
= (region
.end
& 0xffff0000) | (region
.start
>> 16);
168 DBG(KERN_INFO
" IO window: %04lx-%04lx\n",
169 region
.start
, region
.end
);
172 /* Clear upper 16 bits of I/O base/limit. */
175 DBG(KERN_INFO
" IO window: disabled.\n");
177 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
178 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, 0x0000ffff);
179 /* Update lower 16 bits of I/O base/limit. */
180 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
181 /* Update upper 16 bits of I/O base/limit. */
182 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, io_upper16
);
184 /* Set up the top and bottom of the PCI Memory segment
186 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[1]);
187 if (bus
->resource
[1]->flags
& IORESOURCE_MEM
) {
188 l
= (region
.start
>> 16) & 0xfff0;
189 l
|= region
.end
& 0xfff00000;
190 DBG(KERN_INFO
" MEM window: %08lx-%08lx\n",
191 region
.start
, region
.end
);
195 DBG(KERN_INFO
" MEM window: disabled.\n");
197 pci_write_config_dword(bridge
, PCI_MEMORY_BASE
, l
);
199 /* Clear out the upper 32 bits of PREF limit.
200 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
201 disables PREF range, which is ok. */
202 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, 0);
204 /* Set up PREF base/limit. */
205 pcibios_resource_to_bus(bridge
, ®ion
, bus
->resource
[2]);
206 if (bus
->resource
[2]->flags
& IORESOURCE_PREFETCH
) {
207 l
= (region
.start
>> 16) & 0xfff0;
208 l
|= region
.end
& 0xfff00000;
209 DBG(KERN_INFO
" PREFETCH window: %08lx-%08lx\n",
210 region
.start
, region
.end
);
214 DBG(KERN_INFO
" PREFETCH window: disabled.\n");
216 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, l
);
218 /* Clear out the upper 32 bits of PREF base. */
219 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, 0);
221 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, bus
->bridge_ctl
);
224 /* Check whether the bridge supports optional I/O and
225 prefetchable memory ranges. If not, the respective
226 base/limit registers must be read-only and read as 0. */
227 static void __devinit
228 pci_bridge_check_ranges(struct pci_bus
*bus
)
232 struct pci_dev
*bridge
= bus
->self
;
233 struct resource
*b_res
;
235 b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
236 b_res
[1].flags
|= IORESOURCE_MEM
;
238 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
240 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xf0f0);
241 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
242 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
245 b_res
[0].flags
|= IORESOURCE_IO
;
246 /* DECchip 21050 pass 2 errata: the bridge may miss an address
247 disconnect boundary by one PCI data phase.
248 Workaround: do not use prefetching on this device. */
249 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
251 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
253 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
255 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
256 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
259 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
262 /* Helper function for sizing routines: find first available
263 bus resource of a given type. Note: we intentionally skip
264 the bus resources which have already been assigned (that is,
265 have non-NULL parent resource). */
266 static struct resource
* __devinit
267 find_free_bus_resource(struct pci_bus
*bus
, unsigned long type
)
271 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
|
274 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
275 r
= bus
->resource
[i
];
276 if (r
== &ioport_resource
|| r
== &iomem_resource
)
278 if (r
&& (r
->flags
& type_mask
) == type
&& !r
->parent
)
284 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
285 since these windows have 4K granularity and the IO ranges
286 of non-bridge PCI devices are limited to 256 bytes.
287 We must be careful with the ISA aliasing though. */
288 static void __devinit
289 pbus_size_io(struct pci_bus
*bus
)
292 struct resource
*b_res
= find_free_bus_resource(bus
, IORESOURCE_IO
);
293 unsigned long size
= 0, size1
= 0;
298 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
301 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
302 struct resource
*r
= &dev
->resource
[i
];
303 unsigned long r_size
;
305 if (r
->parent
|| !(r
->flags
& IORESOURCE_IO
))
307 r_size
= r
->end
- r
->start
+ 1;
310 /* Might be re-aligned for ISA */
316 /* To be fixed in 2.5: we should have sort of HAVE_ISA
317 flag in the struct pci_bus. */
318 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
319 size
= (size
& 0xff) + ((size
& ~0xffUL
) << 2);
321 size
= ROUND_UP(size
+ size1
, 4096);
326 /* Alignment of the IO window is always 4K */
328 b_res
->end
= b_res
->start
+ size
- 1;
331 /* Calculate the size of the bus and minimal alignment which
332 guarantees that all child resources fit in this size. */
334 pbus_size_mem(struct pci_bus
*bus
, unsigned long mask
, unsigned long type
)
337 unsigned long min_align
, align
, size
;
338 unsigned long aligns
[12]; /* Alignments from 1Mb to 2Gb */
339 int order
, max_order
;
340 struct resource
*b_res
= find_free_bus_resource(bus
, type
);
345 memset(aligns
, 0, sizeof(aligns
));
349 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
352 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
353 struct resource
*r
= &dev
->resource
[i
];
354 unsigned long r_size
;
356 if (r
->parent
|| (r
->flags
& mask
) != type
)
358 r_size
= r
->end
- r
->start
+ 1;
359 /* For bridges size != alignment */
360 align
= (i
< PCI_BRIDGE_RESOURCES
) ? r_size
: r
->start
;
361 order
= __ffs(align
) - 20;
363 printk(KERN_WARNING
"PCI: region %s/%d "
364 "too large: %lx-%lx\n",
365 pci_name(dev
), i
, r
->start
, r
->end
);
372 /* Exclude ranges with size > align from
373 calculation of the alignment. */
375 aligns
[order
] += align
;
376 if (order
> max_order
)
383 for (order
= 0; order
<= max_order
; order
++) {
384 unsigned long align1
= 1UL << (order
+ 20);
388 else if (ROUND_UP(align
+ min_align
, min_align
) < align1
)
389 min_align
= align1
>> 1;
390 align
+= aligns
[order
];
392 size
= ROUND_UP(size
, min_align
);
397 b_res
->start
= min_align
;
398 b_res
->end
= size
+ min_align
- 1;
402 static void __devinit
403 pci_bus_size_cardbus(struct pci_bus
*bus
)
405 struct pci_dev
*bridge
= bus
->self
;
406 struct resource
*b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
410 * Reserve some resources for CardBus. We reserve
411 * a fixed amount of bus space for CardBus bridges.
413 b_res
[0].start
= CARDBUS_IO_SIZE
;
414 b_res
[0].end
= b_res
[0].start
+ CARDBUS_IO_SIZE
- 1;
415 b_res
[0].flags
|= IORESOURCE_IO
;
417 b_res
[1].start
= CARDBUS_IO_SIZE
;
418 b_res
[1].end
= b_res
[1].start
+ CARDBUS_IO_SIZE
- 1;
419 b_res
[1].flags
|= IORESOURCE_IO
;
422 * Check whether prefetchable memory is supported
425 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
426 if (!(ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
)) {
427 ctrl
|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
;
428 pci_write_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, ctrl
);
429 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
433 * If we have prefetchable memory support, allocate
434 * two regions. Otherwise, allocate one region of
437 if (ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
) {
438 b_res
[2].start
= CARDBUS_MEM_SIZE
;
439 b_res
[2].end
= b_res
[2].start
+ CARDBUS_MEM_SIZE
- 1;
440 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
442 b_res
[3].start
= CARDBUS_MEM_SIZE
;
443 b_res
[3].end
= b_res
[3].start
+ CARDBUS_MEM_SIZE
- 1;
444 b_res
[3].flags
|= IORESOURCE_MEM
;
446 b_res
[3].start
= CARDBUS_MEM_SIZE
* 2;
447 b_res
[3].end
= b_res
[3].start
+ CARDBUS_MEM_SIZE
* 2 - 1;
448 b_res
[3].flags
|= IORESOURCE_MEM
;
453 pci_bus_size_bridges(struct pci_bus
*bus
)
456 unsigned long mask
, prefmask
;
458 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
459 struct pci_bus
*b
= dev
->subordinate
;
463 switch (dev
->class >> 8) {
464 case PCI_CLASS_BRIDGE_CARDBUS
:
465 pci_bus_size_cardbus(b
);
468 case PCI_CLASS_BRIDGE_PCI
:
470 pci_bus_size_bridges(b
);
479 switch (bus
->self
->class >> 8) {
480 case PCI_CLASS_BRIDGE_CARDBUS
:
481 /* don't size cardbuses yet. */
484 case PCI_CLASS_BRIDGE_PCI
:
485 pci_bridge_check_ranges(bus
);
488 /* If the bridge supports prefetchable range, size it
489 separately. If it doesn't, or its prefetchable window
490 has already been allocated by arch code, try
491 non-prefetchable range for both types of PCI memory
493 mask
= IORESOURCE_MEM
;
494 prefmask
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
495 if (pbus_size_mem(bus
, prefmask
, prefmask
))
496 mask
= prefmask
; /* Success, size non-prefetch only. */
497 pbus_size_mem(bus
, mask
, IORESOURCE_MEM
);
501 EXPORT_SYMBOL(pci_bus_size_bridges
);
504 pci_bus_assign_resources(struct pci_bus
*bus
)
509 pbus_assign_resources_sorted(bus
);
511 if (bus
->bridge_ctl
& PCI_BRIDGE_CTL_VGA
) {
512 /* Propagate presence of the VGA to upstream bridges */
513 for (b
= bus
; b
->parent
; b
= b
->parent
) {
514 b
->bridge_ctl
|= PCI_BRIDGE_CTL_VGA
;
517 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
518 b
= dev
->subordinate
;
522 pci_bus_assign_resources(b
);
524 switch (dev
->class >> 8) {
525 case PCI_CLASS_BRIDGE_PCI
:
529 case PCI_CLASS_BRIDGE_CARDBUS
:
530 pci_setup_cardbus(b
);
534 printk(KERN_INFO
"PCI: not setting up bridge %s "
535 "for bus %d\n", pci_name(dev
), b
->number
);
540 EXPORT_SYMBOL(pci_bus_assign_resources
);
543 pci_assign_unassigned_resources(void)
547 /* Depth first, calculate sizes and alignments of all
548 subordinate buses. */
549 list_for_each_entry(bus
, &pci_root_buses
, node
) {
550 pci_bus_size_bridges(bus
);
552 /* Depth last, allocate resources and update the hardware. */
553 list_for_each_entry(bus
, &pci_root_buses
, node
) {
554 pci_bus_assign_resources(bus
);
555 pci_enable_bridges(bus
);