drivers/pci/setup-bus.c

   1 /*
   2  *      drivers/pci/setup-bus.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /*
  13  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  14  *           PCI-PCI bridges cleanup, sorted resource allocation.
  15  * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Converted to allocation in 3 passes, which gives
  17  *           tighter packing. Prefetchable range support.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/errno.h>
  25 #include <linux/ioport.h>
  26 #include <linux/cache.h>
  27 #include <linux/slab.h>
  28
  29
  30 #define DEBUG_CONFIG 1
  31 #if DEBUG_CONFIG
  32 #define DBG(x...)     printk(x)
  33 #else
  34 #define DBG(x...)
  35 #endif
  36
  37 #define ROUND_UP(x, a)          (((x) + (a) - 1) & ~((a) - 1))
  38
  39 /*
  40  * FIXME: IO should be max 256 bytes.  However, since we may
  41  * have a P2P bridge below a cardbus bridge, we need 4K.
  42  */
  43 #define CARDBUS_IO_SIZE         (4*1024)
  44 #define CARDBUS_MEM_SIZE        (32*1024*1024)
  45
  46 static void __devinit
  47 pbus_assign_resources_sorted(struct pci_bus *bus)
  48 {
  49         struct pci_dev *dev;
  50         struct resource *res;
  51         struct resource_list head, *list, *tmp;
  52         int idx;
  53
  54         head.next = NULL;
  55         list_for_each_entry(dev, &bus->devices, bus_list) {
  56                 u16 class = dev->class >> 8;
  57
  58                 /* Don't touch classless devices and host bridges.  */
  59                 if (class == PCI_CLASS_NOT_DEFINED ||
  60                     class == PCI_CLASS_BRIDGE_HOST)
  61                         continue;
  62
  63                 pdev_sort_resources(dev, &head);
  64         }
  65
  66         for (list = head.next; list;) {
  67                 res = list->res;
  68                 idx = res - &list->dev->resource[0];
  69                 if (pci_assign_resource(list->dev, idx)) {
  70                         res->start = 0;
  71                         res->end = 0;
  72                         res->flags = 0;
  73                 }
  74                 tmp = list;
  75                 list = list->next;
  76                 kfree(tmp);
  77         }
  78 }
  79
  80 void pci_setup_cardbus(struct pci_bus *bus)
  81 {
  82         struct pci_dev *bridge = bus->self;
  83         struct pci_bus_region region;
  84
  85         printk("PCI: Bus %d, cardbus bridge: %s\n",
  86                 bus->number, pci_name(bridge));
  87
  88         pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
  89         if (bus->resource[0]->flags & IORESOURCE_IO) {
  90                 /*
  91                  * The IO resource is allocated a range twice as large as it
  92                  * would normally need.  This allows us to set both IO regs.
  93                  */
  94                 printk("  IO window: %08lx-%08lx\n",
  95                         region.start, region.end);
  96                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
  97                                         region.start);
  98                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
  99                                         region.end);
 100         }
 101
 102         pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
 103         if (bus->resource[1]->flags & IORESOURCE_IO) {
 104                 printk("  IO window: %08lx-%08lx\n",
 105                         region.start, region.end);
 106                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 107                                         region.start);
 108                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 109                                         region.end);
 110         }
 111
 112         pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
 113         if (bus->resource[2]->flags & IORESOURCE_MEM) {
 114                 printk("  PREFETCH window: %08lx-%08lx\n",
 115                         region.start, region.end);
 116                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 117                                         region.start);
 118                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 119                                         region.end);
 120         }
 121
 122         pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
 123         if (bus->resource[3]->flags & IORESOURCE_MEM) {
 124                 printk("  MEM window: %08lx-%08lx\n",
 125                         region.start, region.end);
 126                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 127                                         region.start);
 128                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 129                                         region.end);
 130         }
 131 }
 132 EXPORT_SYMBOL(pci_setup_cardbus);
 133
 134 /* Initialize bridges with base/limit values we have collected.
 135    PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
 136    requires that if there is no I/O ports or memory behind the
 137    bridge, corresponding range must be turned off by writing base
 138    value greater than limit to the bridge's base/limit registers.
 139
 140    Note: care must be taken when updating I/O base/limit registers
 141    of bridges which support 32-bit I/O. This update requires two
 142    config space writes, so it's quite possible that an I/O window of
 143    the bridge will have some undesirable address (e.g. 0) after the
 144    first write. Ditto 64-bit prefetchable MMIO.  */
 145 static void __devinit
 146 pci_setup_bridge(struct pci_bus *bus)
 147 {
 148         struct pci_dev *bridge = bus->self;
 149         struct pci_bus_region region;
 150         u32 l, io_upper16;
 151
 152         DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
 153
 154         /* Set up the top and bottom of the PCI I/O segment for this bus. */
 155         pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
 156         if (bus->resource[0]->flags & IORESOURCE_IO) {
 157                 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
 158                 l &= 0xffff0000;
 159                 l |= (region.start >> 8) & 0x00f0;
 160                 l |= region.end & 0xf000;
 161                 /* Set up upper 16 bits of I/O base/limit. */
 162                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 163                 DBG(KERN_INFO "  IO window: %04lx-%04lx\n",
 164                                 region.start, region.end);
 165         }
 166         else {
 167                 /* Clear upper 16 bits of I/O base/limit. */
 168                 io_upper16 = 0;
 169                 l = 0x00f0;
 170                 DBG(KERN_INFO "  IO window: disabled.\n");
 171         }
 172         /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
 173         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 174         /* Update lower 16 bits of I/O base/limit. */
 175         pci_write_config_dword(bridge, PCI_IO_BASE, l);
 176         /* Update upper 16 bits of I/O base/limit. */
 177         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 178
 179         /* Set up the top and bottom of the PCI Memory segment
 180            for this bus. */
 181         pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
 182         if (bus->resource[1]->flags & IORESOURCE_MEM) {
 183                 l = (region.start >> 16) & 0xfff0;
 184                 l |= region.end & 0xfff00000;
 185                 DBG(KERN_INFO "  MEM window: %08lx-%08lx\n",
 186                                 region.start, region.end);
 187         }
 188         else {
 189                 l = 0x0000fff0;
 190                 DBG(KERN_INFO "  MEM window: disabled.\n");
 191         }
 192         pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 193
 194         /* Clear out the upper 32 bits of PREF limit.
 195            If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
 196            disables PREF range, which is ok. */
 197         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 198
 199         /* Set up PREF base/limit. */
 200         pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
 201         if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
 202                 l = (region.start >> 16) & 0xfff0;
 203                 l |= region.end & 0xfff00000;
 204                 DBG(KERN_INFO "  PREFETCH window: %08lx-%08lx\n",
 205                                 region.start, region.end);
 206         }
 207         else {
 208                 l = 0x0000fff0;
 209                 DBG(KERN_INFO "  PREFETCH window: disabled.\n");
 210         }
 211         pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 212
 213         /* Clear out the upper 32 bits of PREF base. */
 214         pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
 215
 216         pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 217 }
 218
 219 /* Check whether the bridge supports optional I/O and
 220    prefetchable memory ranges. If not, the respective
 221    base/limit registers must be read-only and read as 0. */
 222 static void __devinit
 223 pci_bridge_check_ranges(struct pci_bus *bus)
 224 {
 225         u16 io;
 226         u32 pmem;
 227         struct pci_dev *bridge = bus->self;
 228         struct resource *b_res;
 229
 230         b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 231         b_res[1].flags |= IORESOURCE_MEM;
 232
 233         pci_read_config_word(bridge, PCI_IO_BASE, &io);
 234         if (!io) {
 235                 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
 236                 pci_read_config_word(bridge, PCI_IO_BASE, &io);
 237                 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 238         }
 239         if (io)
 240                 b_res[0].flags |= IORESOURCE_IO;
 241         /*  DECchip 21050 pass 2 errata: the bridge may miss an address
 242             disconnect boundary by one PCI data phase.
 243             Workaround: do not use prefetching on this device. */
 244         if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
 245                 return;
 246         pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 247         if (!pmem) {
 248                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
 249                                                0xfff0fff0);
 250                 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 251                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
 252         }
 253         if (pmem)
 254                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 255 }
 256
 257 /* Helper function for sizing routines: find first available
 258    bus resource of a given type. Note: we intentionally skip
 259    the bus resources which have already been assigned (that is,
 260    have non-NULL parent resource). */
 261 static struct resource * __devinit
 262 find_free_bus_resource(struct pci_bus *bus, unsigned long type)
 263 {
 264         int i;
 265         struct resource *r;
 266         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
 267                                   IORESOURCE_PREFETCH;
 268
 269         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
 270                 r = bus->resource[i];
 271                 if (r == &ioport_resource || r == &iomem_resource)
 272                         continue;
 273                 if (r && (r->flags & type_mask) == type && !r->parent)
 274                         return r;
 275         }
 276         return NULL;
 277 }
 278
 279 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
 280    since these windows have 4K granularity and the IO ranges
 281    of non-bridge PCI devices are limited to 256 bytes.
 282    We must be careful with the ISA aliasing though. */
 283 static void __devinit
 284 pbus_size_io(struct pci_bus *bus)
 285 {
 286         struct pci_dev *dev;
 287         struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
 288         unsigned long size = 0, size1 = 0;
 289
 290         if (!b_res)
 291                 return;
 292
 293         list_for_each_entry(dev, &bus->devices, bus_list) {
 294                 int i;
 295
 296                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 297                         struct resource *r = &dev->resource[i];
 298                         unsigned long r_size;
 299
 300                         if (r->parent || !(r->flags & IORESOURCE_IO))
 301                                 continue;
 302                         r_size = r->end - r->start + 1;
 303
 304                         if (r_size < 0x400)
 305                                 /* Might be re-aligned for ISA */
 306                                 size += r_size;
 307                         else
 308                                 size1 += r_size;
 309                 }
 310         }
 311 /* To be fixed in 2.5: we should have sort of HAVE_ISA
 312    flag in the struct pci_bus. */
 313 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 314         size = (size & 0xff) + ((size & ~0xffUL) << 2);
 315 #endif
 316         size = ROUND_UP(size + size1, 4096);
 317         if (!size) {
 318                 b_res->flags = 0;
 319                 return;
 320         }
 321         /* Alignment of the IO window is always 4K */
 322         b_res->start = 4096;
 323         b_res->end = b_res->start + size - 1;
 324 }
 325
 326 /* Calculate the size of the bus and minimal alignment which
 327    guarantees that all child resources fit in this size. */
 328 static int __devinit
 329 pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
 330 {
 331         struct pci_dev *dev;
 332         unsigned long min_align, align, size;
 333         unsigned long aligns[12];       /* Alignments from 1Mb to 2Gb */
 334         int order, max_order;
 335         struct resource *b_res = find_free_bus_resource(bus, type);
 336
 337         if (!b_res)
 338                 return 0;
 339
 340         memset(aligns, 0, sizeof(aligns));
 341         max_order = 0;
 342         size = 0;
 343
 344         list_for_each_entry(dev, &bus->devices, bus_list) {
 345                 int i;
 346
 347                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 348                         struct resource *r = &dev->resource[i];
 349                         unsigned long r_size;
 350
 351                         if (r->parent || (r->flags & mask) != type)
 352                                 continue;
 353                         r_size = r->end - r->start + 1;
 354                         /* For bridges size != alignment */
 355                         align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
 356                         order = __ffs(align) - 20;
 357                         if (order > 11) {
 358                                 printk(KERN_WARNING "PCI: region %s/%d "
 359                                        "too large: %lx-%lx\n",
 360                                        pci_name(dev), i, r->start, r->end);
 361                                 r->flags = 0;
 362                                 continue;
 363                         }
 364                         size += r_size;
 365                         if (order < 0)
 366                                 order = 0;
 367                         /* Exclude ranges with size > align from
 368                            calculation of the alignment. */
 369                         if (r_size == align)
 370                                 aligns[order] += align;
 371                         if (order > max_order)
 372                                 max_order = order;
 373                 }
 374         }
 375
 376         align = 0;
 377         min_align = 0;
 378         for (order = 0; order <= max_order; order++) {
 379                 unsigned long align1 = 1UL << (order + 20);
 380
 381                 if (!align)
 382                         min_align = align1;
 383                 else if (ROUND_UP(align + min_align, min_align) < align1)
 384                         min_align = align1 >> 1;
 385                 align += aligns[order];
 386         }
 387         size = ROUND_UP(size, min_align);
 388         if (!size) {
 389                 b_res->flags = 0;
 390                 return 1;
 391         }
 392         b_res->start = min_align;
 393         b_res->end = size + min_align - 1;
 394         return 1;
 395 }
 396
 397 static void __devinit
 398 pci_bus_size_cardbus(struct pci_bus *bus)
 399 {
 400         struct pci_dev *bridge = bus->self;
 401         struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 402         u16 ctrl;
 403
 404         /*
 405          * Reserve some resources for CardBus.  We reserve
 406          * a fixed amount of bus space for CardBus bridges.
 407          */
 408         b_res[0].start = CARDBUS_IO_SIZE;
 409         b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1;
 410         b_res[0].flags |= IORESOURCE_IO;
 411
 412         b_res[1].start = CARDBUS_IO_SIZE;
 413         b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1;
 414         b_res[1].flags |= IORESOURCE_IO;
 415
 416         /*
 417          * Check whether prefetchable memory is supported
 418          * by this bridge.
 419          */
 420         pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
 421         if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
 422                 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
 423                 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
 424                 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
 425         }
 426
 427         /*
 428          * If we have prefetchable memory support, allocate
 429          * two regions.  Otherwise, allocate one region of
 430          * twice the size.
 431          */
 432         if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
 433                 b_res[2].start = CARDBUS_MEM_SIZE;
 434                 b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1;
 435                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 436
 437                 b_res[3].start = CARDBUS_MEM_SIZE;
 438                 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1;
 439                 b_res[3].flags |= IORESOURCE_MEM;
 440         } else {
 441                 b_res[3].start = CARDBUS_MEM_SIZE * 2;
 442                 b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1;
 443                 b_res[3].flags |= IORESOURCE_MEM;
 444         }
 445 }
 446
 447 void __devinit
 448 pci_bus_size_bridges(struct pci_bus *bus)
 449 {
 450         struct pci_dev *dev;
 451         unsigned long mask, prefmask;
 452
 453         list_for_each_entry(dev, &bus->devices, bus_list) {
 454                 struct pci_bus *b = dev->subordinate;
 455                 if (!b)
 456                         continue;
 457
 458                 switch (dev->class >> 8) {
 459                 case PCI_CLASS_BRIDGE_CARDBUS:
 460                         pci_bus_size_cardbus(b);
 461                         break;
 462
 463                 case PCI_CLASS_BRIDGE_PCI:
 464                 default:
 465                         pci_bus_size_bridges(b);
 466                         break;
 467                 }
 468         }
 469
 470         /* The root bus? */
 471         if (!bus->self)
 472                 return;
 473
 474         switch (bus->self->class >> 8) {
 475         case PCI_CLASS_BRIDGE_CARDBUS:
 476                 /* don't size cardbuses yet. */
 477                 break;
 478
 479         case PCI_CLASS_BRIDGE_PCI:
 480                 pci_bridge_check_ranges(bus);
 481         default:
 482                 pbus_size_io(bus);
 483                 /* If the bridge supports prefetchable range, size it
 484                    separately. If it doesn't, or its prefetchable window
 485                    has already been allocated by arch code, try
 486                    non-prefetchable range for both types of PCI memory
 487                    resources. */
 488                 mask = IORESOURCE_MEM;
 489                 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 490                 if (pbus_size_mem(bus, prefmask, prefmask))
 491                         mask = prefmask; /* Success, size non-prefetch only. */
 492                 pbus_size_mem(bus, mask, IORESOURCE_MEM);
 493                 break;
 494         }
 495 }
 496 EXPORT_SYMBOL(pci_bus_size_bridges);
 497
 498 void __devinit
 499 pci_bus_assign_resources(struct pci_bus *bus)
 500 {
 501         struct pci_bus *b;
 502         struct pci_dev *dev;
 503
 504         pbus_assign_resources_sorted(bus);
 505
 506         list_for_each_entry(dev, &bus->devices, bus_list) {
 507                 b = dev->subordinate;
 508                 if (!b)
 509                         continue;
 510
 511                 pci_bus_assign_resources(b);
 512
 513                 switch (dev->class >> 8) {
 514                 case PCI_CLASS_BRIDGE_PCI:
 515                         pci_setup_bridge(b);
 516                         break;
 517
 518                 case PCI_CLASS_BRIDGE_CARDBUS:
 519                         pci_setup_cardbus(b);
 520                         break;
 521
 522                 default:
 523                         printk(KERN_INFO "PCI: not setting up bridge %s "
 524                                "for bus %d\n", pci_name(dev), b->number);
 525                         break;
 526                 }
 527         }
 528 }
 529 EXPORT_SYMBOL(pci_bus_assign_resources);
 530
 531 void __init
 532 pci_assign_unassigned_resources(void)
 533 {
 534         struct pci_bus *bus;
 535
 536         /* Depth first, calculate sizes and alignments of all
 537            subordinate buses. */
 538         list_for_each_entry(bus, &pci_root_buses, node) {
 539                 pci_bus_size_bridges(bus);
 540         }
 541         /* Depth last, allocate resources and update the hardware. */
 542         list_for_each_entry(bus, &pci_root_buses, node) {
 543                 pci_bus_assign_resources(bus);
 544                 pci_enable_bridges(bus);
 545         }
 546 }