Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / pci.c
1 /*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pm.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
26 #include "pci.h"
27
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 };
31 EXPORT_SYMBOL_GPL(pci_power_names);
32
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36 int pci_pci_problems;
37 EXPORT_SYMBOL(pci_pci_problems);
38
39 unsigned int pci_pm_d3_delay;
40
41 static void pci_dev_d3_sleep(struct pci_dev *dev)
42 {
43 unsigned int delay = dev->d3_delay;
44
45 if (delay < pci_pm_d3_delay)
46 delay = pci_pm_d3_delay;
47
48 msleep(delay);
49 }
50
51 #ifdef CONFIG_PCI_DOMAINS
52 int pci_domains_supported = 1;
53 #endif
54
55 #define DEFAULT_CARDBUS_IO_SIZE (256)
56 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
57 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
58 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
59 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
60
61 #define DEFAULT_HOTPLUG_IO_SIZE (256)
62 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
63 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
64 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
65 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
66
67 /*
68 * The default CLS is used if arch didn't set CLS explicitly and not
69 * all pci devices agree on the same value. Arch can override either
70 * the dfl or actual value as it sees fit. Don't forget this is
71 * measured in 32-bit words, not bytes.
72 */
73 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
74 u8 pci_cache_line_size;
75
76 /**
77 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
78 * @bus: pointer to PCI bus structure to search
79 *
80 * Given a PCI bus, returns the highest PCI bus number present in the set
81 * including the given PCI bus and its list of child PCI buses.
82 */
83 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
84 {
85 struct list_head *tmp;
86 unsigned char max, n;
87
88 max = bus->subordinate;
89 list_for_each(tmp, &bus->children) {
90 n = pci_bus_max_busnr(pci_bus_b(tmp));
91 if(n > max)
92 max = n;
93 }
94 return max;
95 }
96 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
97
98 #ifdef CONFIG_HAS_IOMEM
99 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
100 {
101 /*
102 * Make sure the BAR is actually a memory resource, not an IO resource
103 */
104 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
105 WARN_ON(1);
106 return NULL;
107 }
108 return ioremap_nocache(pci_resource_start(pdev, bar),
109 pci_resource_len(pdev, bar));
110 }
111 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
112 #endif
113
114 #if 0
115 /**
116 * pci_max_busnr - returns maximum PCI bus number
117 *
118 * Returns the highest PCI bus number present in the system global list of
119 * PCI buses.
120 */
121 unsigned char __devinit
122 pci_max_busnr(void)
123 {
124 struct pci_bus *bus = NULL;
125 unsigned char max, n;
126
127 max = 0;
128 while ((bus = pci_find_next_bus(bus)) != NULL) {
129 n = pci_bus_max_busnr(bus);
130 if(n > max)
131 max = n;
132 }
133 return max;
134 }
135
136 #endif /* 0 */
137
138 #define PCI_FIND_CAP_TTL 48
139
140 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
141 u8 pos, int cap, int *ttl)
142 {
143 u8 id;
144
145 while ((*ttl)--) {
146 pci_bus_read_config_byte(bus, devfn, pos, &pos);
147 if (pos < 0x40)
148 break;
149 pos &= ~3;
150 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
151 &id);
152 if (id == 0xff)
153 break;
154 if (id == cap)
155 return pos;
156 pos += PCI_CAP_LIST_NEXT;
157 }
158 return 0;
159 }
160
161 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
162 u8 pos, int cap)
163 {
164 int ttl = PCI_FIND_CAP_TTL;
165
166 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
167 }
168
169 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
170 {
171 return __pci_find_next_cap(dev->bus, dev->devfn,
172 pos + PCI_CAP_LIST_NEXT, cap);
173 }
174 EXPORT_SYMBOL_GPL(pci_find_next_capability);
175
176 static int __pci_bus_find_cap_start(struct pci_bus *bus,
177 unsigned int devfn, u8 hdr_type)
178 {
179 u16 status;
180
181 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
182 if (!(status & PCI_STATUS_CAP_LIST))
183 return 0;
184
185 switch (hdr_type) {
186 case PCI_HEADER_TYPE_NORMAL:
187 case PCI_HEADER_TYPE_BRIDGE:
188 return PCI_CAPABILITY_LIST;
189 case PCI_HEADER_TYPE_CARDBUS:
190 return PCI_CB_CAPABILITY_LIST;
191 default:
192 return 0;
193 }
194
195 return 0;
196 }
197
198 /**
199 * pci_find_capability - query for devices' capabilities
200 * @dev: PCI device to query
201 * @cap: capability code
202 *
203 * Tell if a device supports a given PCI capability.
204 * Returns the address of the requested capability structure within the
205 * device's PCI configuration space or 0 in case the device does not
206 * support it. Possible values for @cap:
207 *
208 * %PCI_CAP_ID_PM Power Management
209 * %PCI_CAP_ID_AGP Accelerated Graphics Port
210 * %PCI_CAP_ID_VPD Vital Product Data
211 * %PCI_CAP_ID_SLOTID Slot Identification
212 * %PCI_CAP_ID_MSI Message Signalled Interrupts
213 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
214 * %PCI_CAP_ID_PCIX PCI-X
215 * %PCI_CAP_ID_EXP PCI Express
216 */
217 int pci_find_capability(struct pci_dev *dev, int cap)
218 {
219 int pos;
220
221 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
222 if (pos)
223 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
224
225 return pos;
226 }
227
228 /**
229 * pci_bus_find_capability - query for devices' capabilities
230 * @bus: the PCI bus to query
231 * @devfn: PCI device to query
232 * @cap: capability code
233 *
234 * Like pci_find_capability() but works for pci devices that do not have a
235 * pci_dev structure set up yet.
236 *
237 * Returns the address of the requested capability structure within the
238 * device's PCI configuration space or 0 in case the device does not
239 * support it.
240 */
241 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
242 {
243 int pos;
244 u8 hdr_type;
245
246 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
247
248 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
249 if (pos)
250 pos = __pci_find_next_cap(bus, devfn, pos, cap);
251
252 return pos;
253 }
254
255 /**
256 * pci_find_ext_capability - Find an extended capability
257 * @dev: PCI device to query
258 * @cap: capability code
259 *
260 * Returns the address of the requested extended capability structure
261 * within the device's PCI configuration space or 0 if the device does
262 * not support it. Possible values for @cap:
263 *
264 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
265 * %PCI_EXT_CAP_ID_VC Virtual Channel
266 * %PCI_EXT_CAP_ID_DSN Device Serial Number
267 * %PCI_EXT_CAP_ID_PWR Power Budgeting
268 */
269 int pci_find_ext_capability(struct pci_dev *dev, int cap)
270 {
271 u32 header;
272 int ttl;
273 int pos = PCI_CFG_SPACE_SIZE;
274
275 /* minimum 8 bytes per capability */
276 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277
278 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
279 return 0;
280
281 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
282 return 0;
283
284 /*
285 * If we have no capabilities, this is indicated by cap ID,
286 * cap version and next pointer all being 0.
287 */
288 if (header == 0)
289 return 0;
290
291 while (ttl-- > 0) {
292 if (PCI_EXT_CAP_ID(header) == cap)
293 return pos;
294
295 pos = PCI_EXT_CAP_NEXT(header);
296 if (pos < PCI_CFG_SPACE_SIZE)
297 break;
298
299 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
300 break;
301 }
302
303 return 0;
304 }
305 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
306
307 /**
308 * pci_bus_find_ext_capability - find an extended capability
309 * @bus: the PCI bus to query
310 * @devfn: PCI device to query
311 * @cap: capability code
312 *
313 * Like pci_find_ext_capability() but works for pci devices that do not have a
314 * pci_dev structure set up yet.
315 *
316 * Returns the address of the requested capability structure within the
317 * device's PCI configuration space or 0 in case the device does not
318 * support it.
319 */
320 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
321 int cap)
322 {
323 u32 header;
324 int ttl;
325 int pos = PCI_CFG_SPACE_SIZE;
326
327 /* minimum 8 bytes per capability */
328 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
329
330 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
331 return 0;
332 if (header == 0xffffffff || header == 0)
333 return 0;
334
335 while (ttl-- > 0) {
336 if (PCI_EXT_CAP_ID(header) == cap)
337 return pos;
338
339 pos = PCI_EXT_CAP_NEXT(header);
340 if (pos < PCI_CFG_SPACE_SIZE)
341 break;
342
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
344 break;
345 }
346
347 return 0;
348 }
349
350 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
351 {
352 int rc, ttl = PCI_FIND_CAP_TTL;
353 u8 cap, mask;
354
355 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
356 mask = HT_3BIT_CAP_MASK;
357 else
358 mask = HT_5BIT_CAP_MASK;
359
360 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
361 PCI_CAP_ID_HT, &ttl);
362 while (pos) {
363 rc = pci_read_config_byte(dev, pos + 3, &cap);
364 if (rc != PCIBIOS_SUCCESSFUL)
365 return 0;
366
367 if ((cap & mask) == ht_cap)
368 return pos;
369
370 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
371 pos + PCI_CAP_LIST_NEXT,
372 PCI_CAP_ID_HT, &ttl);
373 }
374
375 return 0;
376 }
377 /**
378 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
379 * @dev: PCI device to query
380 * @pos: Position from which to continue searching
381 * @ht_cap: Hypertransport capability code
382 *
383 * To be used in conjunction with pci_find_ht_capability() to search for
384 * all capabilities matching @ht_cap. @pos should always be a value returned
385 * from pci_find_ht_capability().
386 *
387 * NB. To be 100% safe against broken PCI devices, the caller should take
388 * steps to avoid an infinite loop.
389 */
390 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
391 {
392 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
393 }
394 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
395
396 /**
397 * pci_find_ht_capability - query a device's Hypertransport capabilities
398 * @dev: PCI device to query
399 * @ht_cap: Hypertransport capability code
400 *
401 * Tell if a device supports a given Hypertransport capability.
402 * Returns an address within the device's PCI configuration space
403 * or 0 in case the device does not support the request capability.
404 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
405 * which has a Hypertransport capability matching @ht_cap.
406 */
407 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
408 {
409 int pos;
410
411 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
412 if (pos)
413 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
414
415 return pos;
416 }
417 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
418
419 /**
420 * pci_find_parent_resource - return resource region of parent bus of given region
421 * @dev: PCI device structure contains resources to be searched
422 * @res: child resource record for which parent is sought
423 *
424 * For given resource region of given device, return the resource
425 * region of parent bus the given region is contained in or where
426 * it should be allocated from.
427 */
428 struct resource *
429 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
430 {
431 const struct pci_bus *bus = dev->bus;
432 int i;
433 struct resource *best = NULL, *r;
434
435 pci_bus_for_each_resource(bus, r, i) {
436 if (!r)
437 continue;
438 if (res->start && !(res->start >= r->start && res->end <= r->end))
439 continue; /* Not contained */
440 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
441 continue; /* Wrong type */
442 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
443 return r; /* Exact match */
444 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
445 if (r->flags & IORESOURCE_PREFETCH)
446 continue;
447 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
448 if (!best)
449 best = r;
450 }
451 return best;
452 }
453
454 /**
455 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
456 * @dev: PCI device to have its BARs restored
457 *
458 * Restore the BAR values for a given device, so as to make it
459 * accessible by its driver.
460 */
461 static void
462 pci_restore_bars(struct pci_dev *dev)
463 {
464 int i;
465
466 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
467 pci_update_resource(dev, i);
468 }
469
470 static struct pci_platform_pm_ops *pci_platform_pm;
471
472 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
473 {
474 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
475 || !ops->sleep_wake || !ops->can_wakeup)
476 return -EINVAL;
477 pci_platform_pm = ops;
478 return 0;
479 }
480
481 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
482 {
483 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
484 }
485
486 static inline int platform_pci_set_power_state(struct pci_dev *dev,
487 pci_power_t t)
488 {
489 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
490 }
491
492 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
493 {
494 return pci_platform_pm ?
495 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
496 }
497
498 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
499 {
500 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
501 }
502
503 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
504 {
505 return pci_platform_pm ?
506 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
507 }
508
509 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
510 {
511 return pci_platform_pm ?
512 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
513 }
514
515 /**
516 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
517 * given PCI device
518 * @dev: PCI device to handle.
519 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
520 *
521 * RETURN VALUE:
522 * -EINVAL if the requested state is invalid.
523 * -EIO if device does not support PCI PM or its PM capabilities register has a
524 * wrong version, or device doesn't support the requested state.
525 * 0 if device already is in the requested state.
526 * 0 if device's power state has been successfully changed.
527 */
528 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
529 {
530 u16 pmcsr;
531 bool need_restore = false;
532
533 /* Check if we're already there */
534 if (dev->current_state == state)
535 return 0;
536
537 if (!dev->pm_cap)
538 return -EIO;
539
540 if (state < PCI_D0 || state > PCI_D3hot)
541 return -EINVAL;
542
543 /* Validate current state:
544 * Can enter D0 from any state, but if we can only go deeper
545 * to sleep if we're already in a low power state
546 */
547 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
548 && dev->current_state > state) {
549 dev_err(&dev->dev, "invalid power transition "
550 "(from state %d to %d)\n", dev->current_state, state);
551 return -EINVAL;
552 }
553
554 /* check if this device supports the desired state */
555 if ((state == PCI_D1 && !dev->d1_support)
556 || (state == PCI_D2 && !dev->d2_support))
557 return -EIO;
558
559 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
560
561 /* If we're (effectively) in D3, force entire word to 0.
562 * This doesn't affect PME_Status, disables PME_En, and
563 * sets PowerState to 0.
564 */
565 switch (dev->current_state) {
566 case PCI_D0:
567 case PCI_D1:
568 case PCI_D2:
569 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
570 pmcsr |= state;
571 break;
572 case PCI_D3hot:
573 case PCI_D3cold:
574 case PCI_UNKNOWN: /* Boot-up */
575 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
576 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
577 need_restore = true;
578 /* Fall-through: force to D0 */
579 default:
580 pmcsr = 0;
581 break;
582 }
583
584 /* enter specified state */
585 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
586
587 /* Mandatory power management transition delays */
588 /* see PCI PM 1.1 5.6.1 table 18 */
589 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
590 pci_dev_d3_sleep(dev);
591 else if (state == PCI_D2 || dev->current_state == PCI_D2)
592 udelay(PCI_PM_D2_DELAY);
593
594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
596 if (dev->current_state != state && printk_ratelimit())
597 dev_info(&dev->dev, "Refused to change power state, "
598 "currently in D%d\n", dev->current_state);
599
600 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
601 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
602 * from D3hot to D0 _may_ perform an internal reset, thereby
603 * going to "D0 Uninitialized" rather than "D0 Initialized".
604 * For example, at least some versions of the 3c905B and the
605 * 3c556B exhibit this behaviour.
606 *
607 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
608 * devices in a D3hot state at boot. Consequently, we need to
609 * restore at least the BARs so that the device will be
610 * accessible to its driver.
611 */
612 if (need_restore)
613 pci_restore_bars(dev);
614
615 if (dev->bus->self)
616 pcie_aspm_pm_state_change(dev->bus->self);
617
618 return 0;
619 }
620
621 /**
622 * pci_update_current_state - Read PCI power state of given device from its
623 * PCI PM registers and cache it
624 * @dev: PCI device to handle.
625 * @state: State to cache in case the device doesn't have the PM capability
626 */
627 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
628 {
629 if (dev->pm_cap) {
630 u16 pmcsr;
631
632 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
633 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
634 } else {
635 dev->current_state = state;
636 }
637 }
638
639 /**
640 * pci_platform_power_transition - Use platform to change device power state
641 * @dev: PCI device to handle.
642 * @state: State to put the device into.
643 */
644 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
645 {
646 int error;
647
648 if (platform_pci_power_manageable(dev)) {
649 error = platform_pci_set_power_state(dev, state);
650 if (!error)
651 pci_update_current_state(dev, state);
652 } else {
653 error = -ENODEV;
654 /* Fall back to PCI_D0 if native PM is not supported */
655 if (!dev->pm_cap)
656 dev->current_state = PCI_D0;
657 }
658
659 return error;
660 }
661
662 /**
663 * __pci_start_power_transition - Start power transition of a PCI device
664 * @dev: PCI device to handle.
665 * @state: State to put the device into.
666 */
667 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
668 {
669 if (state == PCI_D0)
670 pci_platform_power_transition(dev, PCI_D0);
671 }
672
673 /**
674 * __pci_complete_power_transition - Complete power transition of a PCI device
675 * @dev: PCI device to handle.
676 * @state: State to put the device into.
677 *
678 * This function should not be called directly by device drivers.
679 */
680 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
681 {
682 return state >= PCI_D0 ?
683 pci_platform_power_transition(dev, state) : -EINVAL;
684 }
685 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
686
687 /**
688 * pci_set_power_state - Set the power state of a PCI device
689 * @dev: PCI device to handle.
690 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
691 *
692 * Transition a device to a new power state, using the platform firmware and/or
693 * the device's PCI PM registers.
694 *
695 * RETURN VALUE:
696 * -EINVAL if the requested state is invalid.
697 * -EIO if device does not support PCI PM or its PM capabilities register has a
698 * wrong version, or device doesn't support the requested state.
699 * 0 if device already is in the requested state.
700 * 0 if device's power state has been successfully changed.
701 */
702 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
703 {
704 int error;
705
706 /* bound the state we're entering */
707 if (state > PCI_D3hot)
708 state = PCI_D3hot;
709 else if (state < PCI_D0)
710 state = PCI_D0;
711 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
712 /*
713 * If the device or the parent bridge do not support PCI PM,
714 * ignore the request if we're doing anything other than putting
715 * it into D0 (which would only happen on boot).
716 */
717 return 0;
718
719 __pci_start_power_transition(dev, state);
720
721 /* This device is quirked not to be put into D3, so
722 don't put it in D3 */
723 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
724 return 0;
725
726 error = pci_raw_set_power_state(dev, state);
727
728 if (!__pci_complete_power_transition(dev, state))
729 error = 0;
730
731 return error;
732 }
733
734 /**
735 * pci_choose_state - Choose the power state of a PCI device
736 * @dev: PCI device to be suspended
737 * @state: target sleep state for the whole system. This is the value
738 * that is passed to suspend() function.
739 *
740 * Returns PCI power state suitable for given device and given system
741 * message.
742 */
743
744 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
745 {
746 pci_power_t ret;
747
748 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
749 return PCI_D0;
750
751 ret = platform_pci_choose_state(dev);
752 if (ret != PCI_POWER_ERROR)
753 return ret;
754
755 switch (state.event) {
756 case PM_EVENT_ON:
757 return PCI_D0;
758 case PM_EVENT_FREEZE:
759 case PM_EVENT_PRETHAW:
760 /* REVISIT both freeze and pre-thaw "should" use D0 */
761 case PM_EVENT_SUSPEND:
762 case PM_EVENT_HIBERNATE:
763 return PCI_D3hot;
764 default:
765 dev_info(&dev->dev, "unrecognized suspend event %d\n",
766 state.event);
767 BUG();
768 }
769 return PCI_D0;
770 }
771
772 EXPORT_SYMBOL(pci_choose_state);
773
774 #define PCI_EXP_SAVE_REGS 7
775
776 #define pcie_cap_has_devctl(type, flags) 1
777 #define pcie_cap_has_lnkctl(type, flags) \
778 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
779 (type == PCI_EXP_TYPE_ROOT_PORT || \
780 type == PCI_EXP_TYPE_ENDPOINT || \
781 type == PCI_EXP_TYPE_LEG_END))
782 #define pcie_cap_has_sltctl(type, flags) \
783 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
784 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
785 (type == PCI_EXP_TYPE_DOWNSTREAM && \
786 (flags & PCI_EXP_FLAGS_SLOT))))
787 #define pcie_cap_has_rtctl(type, flags) \
788 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
789 (type == PCI_EXP_TYPE_ROOT_PORT || \
790 type == PCI_EXP_TYPE_RC_EC))
791 #define pcie_cap_has_devctl2(type, flags) \
792 ((flags & PCI_EXP_FLAGS_VERS) > 1)
793 #define pcie_cap_has_lnkctl2(type, flags) \
794 ((flags & PCI_EXP_FLAGS_VERS) > 1)
795 #define pcie_cap_has_sltctl2(type, flags) \
796 ((flags & PCI_EXP_FLAGS_VERS) > 1)
797
798 static int pci_save_pcie_state(struct pci_dev *dev)
799 {
800 int pos, i = 0;
801 struct pci_cap_saved_state *save_state;
802 u16 *cap;
803 u16 flags;
804
805 pos = pci_pcie_cap(dev);
806 if (!pos)
807 return 0;
808
809 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
810 if (!save_state) {
811 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
812 return -ENOMEM;
813 }
814 cap = (u16 *)&save_state->data[0];
815
816 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
817
818 if (pcie_cap_has_devctl(dev->pcie_type, flags))
819 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
820 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
821 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
822 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
823 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
824 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
825 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
826 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
827 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
828 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
829 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
830 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
831 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
832
833 return 0;
834 }
835
836 static void pci_restore_pcie_state(struct pci_dev *dev)
837 {
838 int i = 0, pos;
839 struct pci_cap_saved_state *save_state;
840 u16 *cap;
841 u16 flags;
842
843 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
844 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
845 if (!save_state || pos <= 0)
846 return;
847 cap = (u16 *)&save_state->data[0];
848
849 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
850
851 if (pcie_cap_has_devctl(dev->pcie_type, flags))
852 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
853 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
854 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
855 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
856 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
857 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
858 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
859 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
860 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
861 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
862 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
863 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
864 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
865 }
866
867
868 static int pci_save_pcix_state(struct pci_dev *dev)
869 {
870 int pos;
871 struct pci_cap_saved_state *save_state;
872
873 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
874 if (pos <= 0)
875 return 0;
876
877 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
878 if (!save_state) {
879 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
880 return -ENOMEM;
881 }
882
883 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
884
885 return 0;
886 }
887
888 static void pci_restore_pcix_state(struct pci_dev *dev)
889 {
890 int i = 0, pos;
891 struct pci_cap_saved_state *save_state;
892 u16 *cap;
893
894 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
895 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
896 if (!save_state || pos <= 0)
897 return;
898 cap = (u16 *)&save_state->data[0];
899
900 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
901 }
902
903
904 /**
905 * pci_save_state - save the PCI configuration space of a device before suspending
906 * @dev: - PCI device that we're dealing with
907 */
908 int
909 pci_save_state(struct pci_dev *dev)
910 {
911 int i;
912 /* XXX: 100% dword access ok here? */
913 for (i = 0; i < 16; i++)
914 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
915 dev->state_saved = true;
916 if ((i = pci_save_pcie_state(dev)) != 0)
917 return i;
918 if ((i = pci_save_pcix_state(dev)) != 0)
919 return i;
920 return 0;
921 }
922
923 /**
924 * pci_restore_state - Restore the saved state of a PCI device
925 * @dev: - PCI device that we're dealing with
926 */
927 int
928 pci_restore_state(struct pci_dev *dev)
929 {
930 int i;
931 u32 val;
932
933 if (!dev->state_saved)
934 return 0;
935
936 /* PCI Express register must be restored first */
937 pci_restore_pcie_state(dev);
938
939 /*
940 * The Base Address register should be programmed before the command
941 * register(s)
942 */
943 for (i = 15; i >= 0; i--) {
944 pci_read_config_dword(dev, i * 4, &val);
945 if (val != dev->saved_config_space[i]) {
946 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
947 "space at offset %#x (was %#x, writing %#x)\n",
948 i, val, (int)dev->saved_config_space[i]);
949 pci_write_config_dword(dev,i * 4,
950 dev->saved_config_space[i]);
951 }
952 }
953 pci_restore_pcix_state(dev);
954 pci_restore_msi_state(dev);
955 pci_restore_iov_state(dev);
956
957 dev->state_saved = false;
958
959 return 0;
960 }
961
962 static int do_pci_enable_device(struct pci_dev *dev, int bars)
963 {
964 int err;
965
966 err = pci_set_power_state(dev, PCI_D0);
967 if (err < 0 && err != -EIO)
968 return err;
969 err = pcibios_enable_device(dev, bars);
970 if (err < 0)
971 return err;
972 pci_fixup_device(pci_fixup_enable, dev);
973
974 return 0;
975 }
976
977 /**
978 * pci_reenable_device - Resume abandoned device
979 * @dev: PCI device to be resumed
980 *
981 * Note this function is a backend of pci_default_resume and is not supposed
982 * to be called by normal code, write proper resume handler and use it instead.
983 */
984 int pci_reenable_device(struct pci_dev *dev)
985 {
986 if (pci_is_enabled(dev))
987 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
988 return 0;
989 }
990
991 static int __pci_enable_device_flags(struct pci_dev *dev,
992 resource_size_t flags)
993 {
994 int err;
995 int i, bars = 0;
996
997 if (atomic_add_return(1, &dev->enable_cnt) > 1)
998 return 0; /* already enabled */
999
1000 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1001 if (dev->resource[i].flags & flags)
1002 bars |= (1 << i);
1003
1004 err = do_pci_enable_device(dev, bars);
1005 if (err < 0)
1006 atomic_dec(&dev->enable_cnt);
1007 return err;
1008 }
1009
1010 /**
1011 * pci_enable_device_io - Initialize a device for use with IO space
1012 * @dev: PCI device to be initialized
1013 *
1014 * Initialize device before it's used by a driver. Ask low-level code
1015 * to enable I/O resources. Wake up the device if it was suspended.
1016 * Beware, this function can fail.
1017 */
1018 int pci_enable_device_io(struct pci_dev *dev)
1019 {
1020 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1021 }
1022
1023 /**
1024 * pci_enable_device_mem - Initialize a device for use with Memory space
1025 * @dev: PCI device to be initialized
1026 *
1027 * Initialize device before it's used by a driver. Ask low-level code
1028 * to enable Memory resources. Wake up the device if it was suspended.
1029 * Beware, this function can fail.
1030 */
1031 int pci_enable_device_mem(struct pci_dev *dev)
1032 {
1033 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1034 }
1035
1036 /**
1037 * pci_enable_device - Initialize device before it's used by a driver.
1038 * @dev: PCI device to be initialized
1039 *
1040 * Initialize device before it's used by a driver. Ask low-level code
1041 * to enable I/O and memory. Wake up the device if it was suspended.
1042 * Beware, this function can fail.
1043 *
1044 * Note we don't actually enable the device many times if we call
1045 * this function repeatedly (we just increment the count).
1046 */
1047 int pci_enable_device(struct pci_dev *dev)
1048 {
1049 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1050 }
1051
1052 /*
1053 * Managed PCI resources. This manages device on/off, intx/msi/msix
1054 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1055 * there's no need to track it separately. pci_devres is initialized
1056 * when a device is enabled using managed PCI device enable interface.
1057 */
1058 struct pci_devres {
1059 unsigned int enabled:1;
1060 unsigned int pinned:1;
1061 unsigned int orig_intx:1;
1062 unsigned int restore_intx:1;
1063 u32 region_mask;
1064 };
1065
1066 static void pcim_release(struct device *gendev, void *res)
1067 {
1068 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1069 struct pci_devres *this = res;
1070 int i;
1071
1072 if (dev->msi_enabled)
1073 pci_disable_msi(dev);
1074 if (dev->msix_enabled)
1075 pci_disable_msix(dev);
1076
1077 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1078 if (this->region_mask & (1 << i))
1079 pci_release_region(dev, i);
1080
1081 if (this->restore_intx)
1082 pci_intx(dev, this->orig_intx);
1083
1084 if (this->enabled && !this->pinned)
1085 pci_disable_device(dev);
1086 }
1087
1088 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1089 {
1090 struct pci_devres *dr, *new_dr;
1091
1092 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1093 if (dr)
1094 return dr;
1095
1096 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1097 if (!new_dr)
1098 return NULL;
1099 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1100 }
1101
1102 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1103 {
1104 if (pci_is_managed(pdev))
1105 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1106 return NULL;
1107 }
1108
1109 /**
1110 * pcim_enable_device - Managed pci_enable_device()
1111 * @pdev: PCI device to be initialized
1112 *
1113 * Managed pci_enable_device().
1114 */
1115 int pcim_enable_device(struct pci_dev *pdev)
1116 {
1117 struct pci_devres *dr;
1118 int rc;
1119
1120 dr = get_pci_dr(pdev);
1121 if (unlikely(!dr))
1122 return -ENOMEM;
1123 if (dr->enabled)
1124 return 0;
1125
1126 rc = pci_enable_device(pdev);
1127 if (!rc) {
1128 pdev->is_managed = 1;
1129 dr->enabled = 1;
1130 }
1131 return rc;
1132 }
1133
1134 /**
1135 * pcim_pin_device - Pin managed PCI device
1136 * @pdev: PCI device to pin
1137 *
1138 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1139 * driver detach. @pdev must have been enabled with
1140 * pcim_enable_device().
1141 */
1142 void pcim_pin_device(struct pci_dev *pdev)
1143 {
1144 struct pci_devres *dr;
1145
1146 dr = find_pci_dr(pdev);
1147 WARN_ON(!dr || !dr->enabled);
1148 if (dr)
1149 dr->pinned = 1;
1150 }
1151
1152 /**
1153 * pcibios_disable_device - disable arch specific PCI resources for device dev
1154 * @dev: the PCI device to disable
1155 *
1156 * Disables architecture specific PCI resources for the device. This
1157 * is the default implementation. Architecture implementations can
1158 * override this.
1159 */
1160 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1161
1162 static void do_pci_disable_device(struct pci_dev *dev)
1163 {
1164 u16 pci_command;
1165
1166 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1167 if (pci_command & PCI_COMMAND_MASTER) {
1168 pci_command &= ~PCI_COMMAND_MASTER;
1169 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1170 }
1171
1172 pcibios_disable_device(dev);
1173 }
1174
1175 /**
1176 * pci_disable_enabled_device - Disable device without updating enable_cnt
1177 * @dev: PCI device to disable
1178 *
1179 * NOTE: This function is a backend of PCI power management routines and is
1180 * not supposed to be called drivers.
1181 */
1182 void pci_disable_enabled_device(struct pci_dev *dev)
1183 {
1184 if (pci_is_enabled(dev))
1185 do_pci_disable_device(dev);
1186 }
1187
1188 /**
1189 * pci_disable_device - Disable PCI device after use
1190 * @dev: PCI device to be disabled
1191 *
1192 * Signal to the system that the PCI device is not in use by the system
1193 * anymore. This only involves disabling PCI bus-mastering, if active.
1194 *
1195 * Note we don't actually disable the device until all callers of
1196 * pci_enable_device() have called pci_disable_device().
1197 */
1198 void
1199 pci_disable_device(struct pci_dev *dev)
1200 {
1201 struct pci_devres *dr;
1202
1203 dr = find_pci_dr(dev);
1204 if (dr)
1205 dr->enabled = 0;
1206
1207 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1208 return;
1209
1210 do_pci_disable_device(dev);
1211
1212 dev->is_busmaster = 0;
1213 }
1214
1215 /**
1216 * pcibios_set_pcie_reset_state - set reset state for device dev
1217 * @dev: the PCIe device reset
1218 * @state: Reset state to enter into
1219 *
1220 *
1221 * Sets the PCIe reset state for the device. This is the default
1222 * implementation. Architecture implementations can override this.
1223 */
1224 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1225 enum pcie_reset_state state)
1226 {
1227 return -EINVAL;
1228 }
1229
1230 /**
1231 * pci_set_pcie_reset_state - set reset state for device dev
1232 * @dev: the PCIe device reset
1233 * @state: Reset state to enter into
1234 *
1235 *
1236 * Sets the PCI reset state for the device.
1237 */
1238 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1239 {
1240 return pcibios_set_pcie_reset_state(dev, state);
1241 }
1242
1243 /**
1244 * pci_check_pme_status - Check if given device has generated PME.
1245 * @dev: Device to check.
1246 *
1247 * Check the PME status of the device and if set, clear it and clear PME enable
1248 * (if set). Return 'true' if PME status and PME enable were both set or
1249 * 'false' otherwise.
1250 */
1251 bool pci_check_pme_status(struct pci_dev *dev)
1252 {
1253 int pmcsr_pos;
1254 u16 pmcsr;
1255 bool ret = false;
1256
1257 if (!dev->pm_cap)
1258 return false;
1259
1260 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1261 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1262 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1263 return false;
1264
1265 /* Clear PME status. */
1266 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1267 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1268 /* Disable PME to avoid interrupt flood. */
1269 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1270 ret = true;
1271 }
1272
1273 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1274
1275 return ret;
1276 }
1277
1278 /**
1279 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1280 * @dev: Device to handle.
1281 * @ign: Ignored.
1282 *
1283 * Check if @dev has generated PME and queue a resume request for it in that
1284 * case.
1285 */
1286 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1287 {
1288 if (pci_check_pme_status(dev))
1289 pm_request_resume(&dev->dev);
1290 return 0;
1291 }
1292
1293 /**
1294 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1295 * @bus: Top bus of the subtree to walk.
1296 */
1297 void pci_pme_wakeup_bus(struct pci_bus *bus)
1298 {
1299 if (bus)
1300 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1301 }
1302
1303 /**
1304 * pci_pme_capable - check the capability of PCI device to generate PME#
1305 * @dev: PCI device to handle.
1306 * @state: PCI state from which device will issue PME#.
1307 */
1308 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1309 {
1310 if (!dev->pm_cap)
1311 return false;
1312
1313 return !!(dev->pme_support & (1 << state));
1314 }
1315
1316 /**
1317 * pci_pme_active - enable or disable PCI device's PME# function
1318 * @dev: PCI device to handle.
1319 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1320 *
1321 * The caller must verify that the device is capable of generating PME# before
1322 * calling this function with @enable equal to 'true'.
1323 */
1324 void pci_pme_active(struct pci_dev *dev, bool enable)
1325 {
1326 u16 pmcsr;
1327
1328 if (!dev->pm_cap)
1329 return;
1330
1331 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1332 /* Clear PME_Status by writing 1 to it and enable PME# */
1333 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1334 if (!enable)
1335 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1336
1337 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1338
1339 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1340 enable ? "enabled" : "disabled");
1341 }
1342
1343 /**
1344 * __pci_enable_wake - enable PCI device as wakeup event source
1345 * @dev: PCI device affected
1346 * @state: PCI state from which device will issue wakeup events
1347 * @runtime: True if the events are to be generated at run time
1348 * @enable: True to enable event generation; false to disable
1349 *
1350 * This enables the device as a wakeup event source, or disables it.
1351 * When such events involves platform-specific hooks, those hooks are
1352 * called automatically by this routine.
1353 *
1354 * Devices with legacy power management (no standard PCI PM capabilities)
1355 * always require such platform hooks.
1356 *
1357 * RETURN VALUE:
1358 * 0 is returned on success
1359 * -EINVAL is returned if device is not supposed to wake up the system
1360 * Error code depending on the platform is returned if both the platform and
1361 * the native mechanism fail to enable the generation of wake-up events
1362 */
1363 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1364 bool runtime, bool enable)
1365 {
1366 int ret = 0;
1367
1368 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1369 return -EINVAL;
1370
1371 /* Don't do the same thing twice in a row for one device. */
1372 if (!!enable == !!dev->wakeup_prepared)
1373 return 0;
1374
1375 /*
1376 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1377 * Anderson we should be doing PME# wake enable followed by ACPI wake
1378 * enable. To disable wake-up we call the platform first, for symmetry.
1379 */
1380
1381 if (enable) {
1382 int error;
1383
1384 if (pci_pme_capable(dev, state))
1385 pci_pme_active(dev, true);
1386 else
1387 ret = 1;
1388 error = runtime ? platform_pci_run_wake(dev, true) :
1389 platform_pci_sleep_wake(dev, true);
1390 if (ret)
1391 ret = error;
1392 if (!ret)
1393 dev->wakeup_prepared = true;
1394 } else {
1395 if (runtime)
1396 platform_pci_run_wake(dev, false);
1397 else
1398 platform_pci_sleep_wake(dev, false);
1399 pci_pme_active(dev, false);
1400 dev->wakeup_prepared = false;
1401 }
1402
1403 return ret;
1404 }
1405 EXPORT_SYMBOL(__pci_enable_wake);
1406
1407 /**
1408 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1409 * @dev: PCI device to prepare
1410 * @enable: True to enable wake-up event generation; false to disable
1411 *
1412 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1413 * and this function allows them to set that up cleanly - pci_enable_wake()
1414 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1415 * ordering constraints.
1416 *
1417 * This function only returns error code if the device is not capable of
1418 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1419 * enable wake-up power for it.
1420 */
1421 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1422 {
1423 return pci_pme_capable(dev, PCI_D3cold) ?
1424 pci_enable_wake(dev, PCI_D3cold, enable) :
1425 pci_enable_wake(dev, PCI_D3hot, enable);
1426 }
1427
1428 /**
1429 * pci_target_state - find an appropriate low power state for a given PCI dev
1430 * @dev: PCI device
1431 *
1432 * Use underlying platform code to find a supported low power state for @dev.
1433 * If the platform can't manage @dev, return the deepest state from which it
1434 * can generate wake events, based on any available PME info.
1435 */
1436 pci_power_t pci_target_state(struct pci_dev *dev)
1437 {
1438 pci_power_t target_state = PCI_D3hot;
1439
1440 if (platform_pci_power_manageable(dev)) {
1441 /*
1442 * Call the platform to choose the target state of the device
1443 * and enable wake-up from this state if supported.
1444 */
1445 pci_power_t state = platform_pci_choose_state(dev);
1446
1447 switch (state) {
1448 case PCI_POWER_ERROR:
1449 case PCI_UNKNOWN:
1450 break;
1451 case PCI_D1:
1452 case PCI_D2:
1453 if (pci_no_d1d2(dev))
1454 break;
1455 default:
1456 target_state = state;
1457 }
1458 } else if (!dev->pm_cap) {
1459 target_state = PCI_D0;
1460 } else if (device_may_wakeup(&dev->dev)) {
1461 /*
1462 * Find the deepest state from which the device can generate
1463 * wake-up events, make it the target state and enable device
1464 * to generate PME#.
1465 */
1466 if (dev->pme_support) {
1467 while (target_state
1468 && !(dev->pme_support & (1 << target_state)))
1469 target_state--;
1470 }
1471 }
1472
1473 return target_state;
1474 }
1475
1476 /**
1477 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1478 * @dev: Device to handle.
1479 *
1480 * Choose the power state appropriate for the device depending on whether
1481 * it can wake up the system and/or is power manageable by the platform
1482 * (PCI_D3hot is the default) and put the device into that state.
1483 */
1484 int pci_prepare_to_sleep(struct pci_dev *dev)
1485 {
1486 pci_power_t target_state = pci_target_state(dev);
1487 int error;
1488
1489 if (target_state == PCI_POWER_ERROR)
1490 return -EIO;
1491
1492 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1493
1494 error = pci_set_power_state(dev, target_state);
1495
1496 if (error)
1497 pci_enable_wake(dev, target_state, false);
1498
1499 return error;
1500 }
1501
1502 /**
1503 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1504 * @dev: Device to handle.
1505 *
1506 * Disable device's system wake-up capability and put it into D0.
1507 */
1508 int pci_back_from_sleep(struct pci_dev *dev)
1509 {
1510 pci_enable_wake(dev, PCI_D0, false);
1511 return pci_set_power_state(dev, PCI_D0);
1512 }
1513
1514 /**
1515 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1516 * @dev: PCI device being suspended.
1517 *
1518 * Prepare @dev to generate wake-up events at run time and put it into a low
1519 * power state.
1520 */
1521 int pci_finish_runtime_suspend(struct pci_dev *dev)
1522 {
1523 pci_power_t target_state = pci_target_state(dev);
1524 int error;
1525
1526 if (target_state == PCI_POWER_ERROR)
1527 return -EIO;
1528
1529 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1530
1531 error = pci_set_power_state(dev, target_state);
1532
1533 if (error)
1534 __pci_enable_wake(dev, target_state, true, false);
1535
1536 return error;
1537 }
1538
1539 /**
1540 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1541 * @dev: Device to check.
1542 *
1543 * Return true if the device itself is cabable of generating wake-up events
1544 * (through the platform or using the native PCIe PME) or if the device supports
1545 * PME and one of its upstream bridges can generate wake-up events.
1546 */
1547 bool pci_dev_run_wake(struct pci_dev *dev)
1548 {
1549 struct pci_bus *bus = dev->bus;
1550
1551 if (device_run_wake(&dev->dev))
1552 return true;
1553
1554 if (!dev->pme_support)
1555 return false;
1556
1557 while (bus->parent) {
1558 struct pci_dev *bridge = bus->self;
1559
1560 if (device_run_wake(&bridge->dev))
1561 return true;
1562
1563 bus = bus->parent;
1564 }
1565
1566 /* We have reached the root bus. */
1567 if (bus->bridge)
1568 return device_run_wake(bus->bridge);
1569
1570 return false;
1571 }
1572 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1573
1574 /**
1575 * pci_pm_init - Initialize PM functions of given PCI device
1576 * @dev: PCI device to handle.
1577 */
1578 void pci_pm_init(struct pci_dev *dev)
1579 {
1580 int pm;
1581 u16 pmc;
1582
1583 pm_runtime_forbid(&dev->dev);
1584 device_enable_async_suspend(&dev->dev);
1585 dev->wakeup_prepared = false;
1586
1587 dev->pm_cap = 0;
1588
1589 /* find PCI PM capability in list */
1590 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1591 if (!pm)
1592 return;
1593 /* Check device's ability to generate PME# */
1594 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1595
1596 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1597 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1598 pmc & PCI_PM_CAP_VER_MASK);
1599 return;
1600 }
1601
1602 dev->pm_cap = pm;
1603 dev->d3_delay = PCI_PM_D3_WAIT;
1604
1605 dev->d1_support = false;
1606 dev->d2_support = false;
1607 if (!pci_no_d1d2(dev)) {
1608 if (pmc & PCI_PM_CAP_D1)
1609 dev->d1_support = true;
1610 if (pmc & PCI_PM_CAP_D2)
1611 dev->d2_support = true;
1612
1613 if (dev->d1_support || dev->d2_support)
1614 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1615 dev->d1_support ? " D1" : "",
1616 dev->d2_support ? " D2" : "");
1617 }
1618
1619 pmc &= PCI_PM_CAP_PME_MASK;
1620 if (pmc) {
1621 dev_printk(KERN_DEBUG, &dev->dev,
1622 "PME# supported from%s%s%s%s%s\n",
1623 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1624 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1625 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1626 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1627 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1628 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1629 /*
1630 * Make device's PM flags reflect the wake-up capability, but
1631 * let the user space enable it to wake up the system as needed.
1632 */
1633 device_set_wakeup_capable(&dev->dev, true);
1634 /* Disable the PME# generation functionality */
1635 pci_pme_active(dev, false);
1636 } else {
1637 dev->pme_support = 0;
1638 }
1639 }
1640
1641 /**
1642 * platform_pci_wakeup_init - init platform wakeup if present
1643 * @dev: PCI device
1644 *
1645 * Some devices don't have PCI PM caps but can still generate wakeup
1646 * events through platform methods (like ACPI events). If @dev supports
1647 * platform wakeup events, set the device flag to indicate as much. This
1648 * may be redundant if the device also supports PCI PM caps, but double
1649 * initialization should be safe in that case.
1650 */
1651 void platform_pci_wakeup_init(struct pci_dev *dev)
1652 {
1653 if (!platform_pci_can_wakeup(dev))
1654 return;
1655
1656 device_set_wakeup_capable(&dev->dev, true);
1657 platform_pci_sleep_wake(dev, false);
1658 }
1659
1660 /**
1661 * pci_add_save_buffer - allocate buffer for saving given capability registers
1662 * @dev: the PCI device
1663 * @cap: the capability to allocate the buffer for
1664 * @size: requested size of the buffer
1665 */
1666 static int pci_add_cap_save_buffer(
1667 struct pci_dev *dev, char cap, unsigned int size)
1668 {
1669 int pos;
1670 struct pci_cap_saved_state *save_state;
1671
1672 pos = pci_find_capability(dev, cap);
1673 if (pos <= 0)
1674 return 0;
1675
1676 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1677 if (!save_state)
1678 return -ENOMEM;
1679
1680 save_state->cap_nr = cap;
1681 pci_add_saved_cap(dev, save_state);
1682
1683 return 0;
1684 }
1685
1686 /**
1687 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1688 * @dev: the PCI device
1689 */
1690 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1691 {
1692 int error;
1693
1694 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1695 PCI_EXP_SAVE_REGS * sizeof(u16));
1696 if (error)
1697 dev_err(&dev->dev,
1698 "unable to preallocate PCI Express save buffer\n");
1699
1700 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1701 if (error)
1702 dev_err(&dev->dev,
1703 "unable to preallocate PCI-X save buffer\n");
1704 }
1705
1706 /**
1707 * pci_enable_ari - enable ARI forwarding if hardware support it
1708 * @dev: the PCI device
1709 */
1710 void pci_enable_ari(struct pci_dev *dev)
1711 {
1712 int pos;
1713 u32 cap;
1714 u16 ctrl;
1715 struct pci_dev *bridge;
1716
1717 if (!pci_is_pcie(dev) || dev->devfn)
1718 return;
1719
1720 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1721 if (!pos)
1722 return;
1723
1724 bridge = dev->bus->self;
1725 if (!bridge || !pci_is_pcie(bridge))
1726 return;
1727
1728 pos = pci_pcie_cap(bridge);
1729 if (!pos)
1730 return;
1731
1732 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1733 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1734 return;
1735
1736 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1737 ctrl |= PCI_EXP_DEVCTL2_ARI;
1738 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1739
1740 bridge->ari_enabled = 1;
1741 }
1742
1743 static int pci_acs_enable;
1744
1745 /**
1746 * pci_request_acs - ask for ACS to be enabled if supported
1747 */
1748 void pci_request_acs(void)
1749 {
1750 pci_acs_enable = 1;
1751 }
1752
1753 /**
1754 * pci_enable_acs - enable ACS if hardware support it
1755 * @dev: the PCI device
1756 */
1757 void pci_enable_acs(struct pci_dev *dev)
1758 {
1759 int pos;
1760 u16 cap;
1761 u16 ctrl;
1762
1763 if (!pci_acs_enable)
1764 return;
1765
1766 if (!pci_is_pcie(dev))
1767 return;
1768
1769 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1770 if (!pos)
1771 return;
1772
1773 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1774 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1775
1776 /* Source Validation */
1777 ctrl |= (cap & PCI_ACS_SV);
1778
1779 /* P2P Request Redirect */
1780 ctrl |= (cap & PCI_ACS_RR);
1781
1782 /* P2P Completion Redirect */
1783 ctrl |= (cap & PCI_ACS_CR);
1784
1785 /* Upstream Forwarding */
1786 ctrl |= (cap & PCI_ACS_UF);
1787
1788 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1789 }
1790
1791 /**
1792 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1793 * @dev: the PCI device
1794 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1795 *
1796 * Perform INTx swizzling for a device behind one level of bridge. This is
1797 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1798 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1799 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1800 * the PCI Express Base Specification, Revision 2.1)
1801 */
1802 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1803 {
1804 int slot;
1805
1806 if (pci_ari_enabled(dev->bus))
1807 slot = 0;
1808 else
1809 slot = PCI_SLOT(dev->devfn);
1810
1811 return (((pin - 1) + slot) % 4) + 1;
1812 }
1813
1814 int
1815 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1816 {
1817 u8 pin;
1818
1819 pin = dev->pin;
1820 if (!pin)
1821 return -1;
1822
1823 while (!pci_is_root_bus(dev->bus)) {
1824 pin = pci_swizzle_interrupt_pin(dev, pin);
1825 dev = dev->bus->self;
1826 }
1827 *bridge = dev;
1828 return pin;
1829 }
1830
1831 /**
1832 * pci_common_swizzle - swizzle INTx all the way to root bridge
1833 * @dev: the PCI device
1834 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1835 *
1836 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1837 * bridges all the way up to a PCI root bus.
1838 */
1839 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1840 {
1841 u8 pin = *pinp;
1842
1843 while (!pci_is_root_bus(dev->bus)) {
1844 pin = pci_swizzle_interrupt_pin(dev, pin);
1845 dev = dev->bus->self;
1846 }
1847 *pinp = pin;
1848 return PCI_SLOT(dev->devfn);
1849 }
1850
1851 /**
1852 * pci_release_region - Release a PCI bar
1853 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1854 * @bar: BAR to release
1855 *
1856 * Releases the PCI I/O and memory resources previously reserved by a
1857 * successful call to pci_request_region. Call this function only
1858 * after all use of the PCI regions has ceased.
1859 */
1860 void pci_release_region(struct pci_dev *pdev, int bar)
1861 {
1862 struct pci_devres *dr;
1863
1864 if (pci_resource_len(pdev, bar) == 0)
1865 return;
1866 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1867 release_region(pci_resource_start(pdev, bar),
1868 pci_resource_len(pdev, bar));
1869 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1870 release_mem_region(pci_resource_start(pdev, bar),
1871 pci_resource_len(pdev, bar));
1872
1873 dr = find_pci_dr(pdev);
1874 if (dr)
1875 dr->region_mask &= ~(1 << bar);
1876 }
1877
1878 /**
1879 * __pci_request_region - Reserved PCI I/O and memory resource
1880 * @pdev: PCI device whose resources are to be reserved
1881 * @bar: BAR to be reserved
1882 * @res_name: Name to be associated with resource.
1883 * @exclusive: whether the region access is exclusive or not
1884 *
1885 * Mark the PCI region associated with PCI device @pdev BR @bar as
1886 * being reserved by owner @res_name. Do not access any
1887 * address inside the PCI regions unless this call returns
1888 * successfully.
1889 *
1890 * If @exclusive is set, then the region is marked so that userspace
1891 * is explicitly not allowed to map the resource via /dev/mem or
1892 * sysfs MMIO access.
1893 *
1894 * Returns 0 on success, or %EBUSY on error. A warning
1895 * message is also printed on failure.
1896 */
1897 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1898 int exclusive)
1899 {
1900 struct pci_devres *dr;
1901
1902 if (pci_resource_len(pdev, bar) == 0)
1903 return 0;
1904
1905 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1906 if (!request_region(pci_resource_start(pdev, bar),
1907 pci_resource_len(pdev, bar), res_name))
1908 goto err_out;
1909 }
1910 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1911 if (!__request_mem_region(pci_resource_start(pdev, bar),
1912 pci_resource_len(pdev, bar), res_name,
1913 exclusive))
1914 goto err_out;
1915 }
1916
1917 dr = find_pci_dr(pdev);
1918 if (dr)
1919 dr->region_mask |= 1 << bar;
1920
1921 return 0;
1922
1923 err_out:
1924 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1925 &pdev->resource[bar]);
1926 return -EBUSY;
1927 }
1928
1929 /**
1930 * pci_request_region - Reserve PCI I/O and memory resource
1931 * @pdev: PCI device whose resources are to be reserved
1932 * @bar: BAR to be reserved
1933 * @res_name: Name to be associated with resource
1934 *
1935 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1936 * being reserved by owner @res_name. Do not access any
1937 * address inside the PCI regions unless this call returns
1938 * successfully.
1939 *
1940 * Returns 0 on success, or %EBUSY on error. A warning
1941 * message is also printed on failure.
1942 */
1943 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1944 {
1945 return __pci_request_region(pdev, bar, res_name, 0);
1946 }
1947
1948 /**
1949 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1950 * @pdev: PCI device whose resources are to be reserved
1951 * @bar: BAR to be reserved
1952 * @res_name: Name to be associated with resource.
1953 *
1954 * Mark the PCI region associated with PCI device @pdev BR @bar as
1955 * being reserved by owner @res_name. Do not access any
1956 * address inside the PCI regions unless this call returns
1957 * successfully.
1958 *
1959 * Returns 0 on success, or %EBUSY on error. A warning
1960 * message is also printed on failure.
1961 *
1962 * The key difference that _exclusive makes it that userspace is
1963 * explicitly not allowed to map the resource via /dev/mem or
1964 * sysfs.
1965 */
1966 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1967 {
1968 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1969 }
1970 /**
1971 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1972 * @pdev: PCI device whose resources were previously reserved
1973 * @bars: Bitmask of BARs to be released
1974 *
1975 * Release selected PCI I/O and memory resources previously reserved.
1976 * Call this function only after all use of the PCI regions has ceased.
1977 */
1978 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1979 {
1980 int i;
1981
1982 for (i = 0; i < 6; i++)
1983 if (bars & (1 << i))
1984 pci_release_region(pdev, i);
1985 }
1986
1987 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1988 const char *res_name, int excl)
1989 {
1990 int i;
1991
1992 for (i = 0; i < 6; i++)
1993 if (bars & (1 << i))
1994 if (__pci_request_region(pdev, i, res_name, excl))
1995 goto err_out;
1996 return 0;
1997
1998 err_out:
1999 while(--i >= 0)
2000 if (bars & (1 << i))
2001 pci_release_region(pdev, i);
2002
2003 return -EBUSY;
2004 }
2005
2006
2007 /**
2008 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2009 * @pdev: PCI device whose resources are to be reserved
2010 * @bars: Bitmask of BARs to be requested
2011 * @res_name: Name to be associated with resource
2012 */
2013 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2014 const char *res_name)
2015 {
2016 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2017 }
2018
2019 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2020 int bars, const char *res_name)
2021 {
2022 return __pci_request_selected_regions(pdev, bars, res_name,
2023 IORESOURCE_EXCLUSIVE);
2024 }
2025
2026 /**
2027 * pci_release_regions - Release reserved PCI I/O and memory resources
2028 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2029 *
2030 * Releases all PCI I/O and memory resources previously reserved by a
2031 * successful call to pci_request_regions. Call this function only
2032 * after all use of the PCI regions has ceased.
2033 */
2034
2035 void pci_release_regions(struct pci_dev *pdev)
2036 {
2037 pci_release_selected_regions(pdev, (1 << 6) - 1);
2038 }
2039
2040 /**
2041 * pci_request_regions - Reserved PCI I/O and memory resources
2042 * @pdev: PCI device whose resources are to be reserved
2043 * @res_name: Name to be associated with resource.
2044 *
2045 * Mark all PCI regions associated with PCI device @pdev as
2046 * being reserved by owner @res_name. Do not access any
2047 * address inside the PCI regions unless this call returns
2048 * successfully.
2049 *
2050 * Returns 0 on success, or %EBUSY on error. A warning
2051 * message is also printed on failure.
2052 */
2053 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2054 {
2055 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2056 }
2057
2058 /**
2059 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2060 * @pdev: PCI device whose resources are to be reserved
2061 * @res_name: Name to be associated with resource.
2062 *
2063 * Mark all PCI regions associated with PCI device @pdev as
2064 * being reserved by owner @res_name. Do not access any
2065 * address inside the PCI regions unless this call returns
2066 * successfully.
2067 *
2068 * pci_request_regions_exclusive() will mark the region so that
2069 * /dev/mem and the sysfs MMIO access will not be allowed.
2070 *
2071 * Returns 0 on success, or %EBUSY on error. A warning
2072 * message is also printed on failure.
2073 */
2074 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2075 {
2076 return pci_request_selected_regions_exclusive(pdev,
2077 ((1 << 6) - 1), res_name);
2078 }
2079
2080 static void __pci_set_master(struct pci_dev *dev, bool enable)
2081 {
2082 u16 old_cmd, cmd;
2083
2084 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2085 if (enable)
2086 cmd = old_cmd | PCI_COMMAND_MASTER;
2087 else
2088 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2089 if (cmd != old_cmd) {
2090 dev_dbg(&dev->dev, "%s bus mastering\n",
2091 enable ? "enabling" : "disabling");
2092 pci_write_config_word(dev, PCI_COMMAND, cmd);
2093 }
2094 dev->is_busmaster = enable;
2095 }
2096
2097 /**
2098 * pci_set_master - enables bus-mastering for device dev
2099 * @dev: the PCI device to enable
2100 *
2101 * Enables bus-mastering on the device and calls pcibios_set_master()
2102 * to do the needed arch specific settings.
2103 */
2104 void pci_set_master(struct pci_dev *dev)
2105 {
2106 __pci_set_master(dev, true);
2107 pcibios_set_master(dev);
2108 }
2109
2110 /**
2111 * pci_clear_master - disables bus-mastering for device dev
2112 * @dev: the PCI device to disable
2113 */
2114 void pci_clear_master(struct pci_dev *dev)
2115 {
2116 __pci_set_master(dev, false);
2117 }
2118
2119 /**
2120 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2121 * @dev: the PCI device for which MWI is to be enabled
2122 *
2123 * Helper function for pci_set_mwi.
2124 * Originally copied from drivers/net/acenic.c.
2125 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2126 *
2127 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2128 */
2129 int pci_set_cacheline_size(struct pci_dev *dev)
2130 {
2131 u8 cacheline_size;
2132
2133 if (!pci_cache_line_size)
2134 return -EINVAL;
2135
2136 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2137 equal to or multiple of the right value. */
2138 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2139 if (cacheline_size >= pci_cache_line_size &&
2140 (cacheline_size % pci_cache_line_size) == 0)
2141 return 0;
2142
2143 /* Write the correct value. */
2144 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2145 /* Read it back. */
2146 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2147 if (cacheline_size == pci_cache_line_size)
2148 return 0;
2149
2150 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2151 "supported\n", pci_cache_line_size << 2);
2152
2153 return -EINVAL;
2154 }
2155 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2156
2157 #ifdef PCI_DISABLE_MWI
2158 int pci_set_mwi(struct pci_dev *dev)
2159 {
2160 return 0;
2161 }
2162
2163 int pci_try_set_mwi(struct pci_dev *dev)
2164 {
2165 return 0;
2166 }
2167
2168 void pci_clear_mwi(struct pci_dev *dev)
2169 {
2170 }
2171
2172 #else
2173
2174 /**
2175 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2176 * @dev: the PCI device for which MWI is enabled
2177 *
2178 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2179 *
2180 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2181 */
2182 int
2183 pci_set_mwi(struct pci_dev *dev)
2184 {
2185 int rc;
2186 u16 cmd;
2187
2188 rc = pci_set_cacheline_size(dev);
2189 if (rc)
2190 return rc;
2191
2192 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2193 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2194 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2195 cmd |= PCI_COMMAND_INVALIDATE;
2196 pci_write_config_word(dev, PCI_COMMAND, cmd);
2197 }
2198
2199 return 0;
2200 }
2201
2202 /**
2203 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2204 * @dev: the PCI device for which MWI is enabled
2205 *
2206 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2207 * Callers are not required to check the return value.
2208 *
2209 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2210 */
2211 int pci_try_set_mwi(struct pci_dev *dev)
2212 {
2213 int rc = pci_set_mwi(dev);
2214 return rc;
2215 }
2216
2217 /**
2218 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2219 * @dev: the PCI device to disable
2220 *
2221 * Disables PCI Memory-Write-Invalidate transaction on the device
2222 */
2223 void
2224 pci_clear_mwi(struct pci_dev *dev)
2225 {
2226 u16 cmd;
2227
2228 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2229 if (cmd & PCI_COMMAND_INVALIDATE) {
2230 cmd &= ~PCI_COMMAND_INVALIDATE;
2231 pci_write_config_word(dev, PCI_COMMAND, cmd);
2232 }
2233 }
2234 #endif /* ! PCI_DISABLE_MWI */
2235
2236 /**
2237 * pci_intx - enables/disables PCI INTx for device dev
2238 * @pdev: the PCI device to operate on
2239 * @enable: boolean: whether to enable or disable PCI INTx
2240 *
2241 * Enables/disables PCI INTx for device dev
2242 */
2243 void
2244 pci_intx(struct pci_dev *pdev, int enable)
2245 {
2246 u16 pci_command, new;
2247
2248 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2249
2250 if (enable) {
2251 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2252 } else {
2253 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2254 }
2255
2256 if (new != pci_command) {
2257 struct pci_devres *dr;
2258
2259 pci_write_config_word(pdev, PCI_COMMAND, new);
2260
2261 dr = find_pci_dr(pdev);
2262 if (dr && !dr->restore_intx) {
2263 dr->restore_intx = 1;
2264 dr->orig_intx = !enable;
2265 }
2266 }
2267 }
2268
2269 /**
2270 * pci_msi_off - disables any msi or msix capabilities
2271 * @dev: the PCI device to operate on
2272 *
2273 * If you want to use msi see pci_enable_msi and friends.
2274 * This is a lower level primitive that allows us to disable
2275 * msi operation at the device level.
2276 */
2277 void pci_msi_off(struct pci_dev *dev)
2278 {
2279 int pos;
2280 u16 control;
2281
2282 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2283 if (pos) {
2284 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2285 control &= ~PCI_MSI_FLAGS_ENABLE;
2286 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2287 }
2288 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2289 if (pos) {
2290 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2291 control &= ~PCI_MSIX_FLAGS_ENABLE;
2292 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2293 }
2294 }
2295
2296 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2297 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2298 {
2299 return dma_set_max_seg_size(&dev->dev, size);
2300 }
2301 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2302 #endif
2303
2304 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2305 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2306 {
2307 return dma_set_seg_boundary(&dev->dev, mask);
2308 }
2309 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2310 #endif
2311
2312 static int pcie_flr(struct pci_dev *dev, int probe)
2313 {
2314 int i;
2315 int pos;
2316 u32 cap;
2317 u16 status, control;
2318
2319 pos = pci_pcie_cap(dev);
2320 if (!pos)
2321 return -ENOTTY;
2322
2323 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2324 if (!(cap & PCI_EXP_DEVCAP_FLR))
2325 return -ENOTTY;
2326
2327 if (probe)
2328 return 0;
2329
2330 /* Wait for Transaction Pending bit clean */
2331 for (i = 0; i < 4; i++) {
2332 if (i)
2333 msleep((1 << (i - 1)) * 100);
2334
2335 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2336 if (!(status & PCI_EXP_DEVSTA_TRPND))
2337 goto clear;
2338 }
2339
2340 dev_err(&dev->dev, "transaction is not cleared; "
2341 "proceeding with reset anyway\n");
2342
2343 clear:
2344 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2345 control |= PCI_EXP_DEVCTL_BCR_FLR;
2346 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2347
2348 msleep(100);
2349
2350 return 0;
2351 }
2352
2353 static int pci_af_flr(struct pci_dev *dev, int probe)
2354 {
2355 int i;
2356 int pos;
2357 u8 cap;
2358 u8 status;
2359
2360 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2361 if (!pos)
2362 return -ENOTTY;
2363
2364 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2365 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2366 return -ENOTTY;
2367
2368 if (probe)
2369 return 0;
2370
2371 /* Wait for Transaction Pending bit clean */
2372 for (i = 0; i < 4; i++) {
2373 if (i)
2374 msleep((1 << (i - 1)) * 100);
2375
2376 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2377 if (!(status & PCI_AF_STATUS_TP))
2378 goto clear;
2379 }
2380
2381 dev_err(&dev->dev, "transaction is not cleared; "
2382 "proceeding with reset anyway\n");
2383
2384 clear:
2385 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2386 msleep(100);
2387
2388 return 0;
2389 }
2390
2391 static int pci_pm_reset(struct pci_dev *dev, int probe)
2392 {
2393 u16 csr;
2394
2395 if (!dev->pm_cap)
2396 return -ENOTTY;
2397
2398 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2399 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2400 return -ENOTTY;
2401
2402 if (probe)
2403 return 0;
2404
2405 if (dev->current_state != PCI_D0)
2406 return -EINVAL;
2407
2408 csr &= ~PCI_PM_CTRL_STATE_MASK;
2409 csr |= PCI_D3hot;
2410 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2411 pci_dev_d3_sleep(dev);
2412
2413 csr &= ~PCI_PM_CTRL_STATE_MASK;
2414 csr |= PCI_D0;
2415 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2416 pci_dev_d3_sleep(dev);
2417
2418 return 0;
2419 }
2420
2421 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2422 {
2423 u16 ctrl;
2424 struct pci_dev *pdev;
2425
2426 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2427 return -ENOTTY;
2428
2429 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2430 if (pdev != dev)
2431 return -ENOTTY;
2432
2433 if (probe)
2434 return 0;
2435
2436 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2437 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2438 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2439 msleep(100);
2440
2441 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2442 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2443 msleep(100);
2444
2445 return 0;
2446 }
2447
2448 static int pci_dev_reset(struct pci_dev *dev, int probe)
2449 {
2450 int rc;
2451
2452 might_sleep();
2453
2454 if (!probe) {
2455 pci_block_user_cfg_access(dev);
2456 /* block PM suspend, driver probe, etc. */
2457 device_lock(&dev->dev);
2458 }
2459
2460 rc = pci_dev_specific_reset(dev, probe);
2461 if (rc != -ENOTTY)
2462 goto done;
2463
2464 rc = pcie_flr(dev, probe);
2465 if (rc != -ENOTTY)
2466 goto done;
2467
2468 rc = pci_af_flr(dev, probe);
2469 if (rc != -ENOTTY)
2470 goto done;
2471
2472 rc = pci_pm_reset(dev, probe);
2473 if (rc != -ENOTTY)
2474 goto done;
2475
2476 rc = pci_parent_bus_reset(dev, probe);
2477 done:
2478 if (!probe) {
2479 device_unlock(&dev->dev);
2480 pci_unblock_user_cfg_access(dev);
2481 }
2482
2483 return rc;
2484 }
2485
2486 /**
2487 * __pci_reset_function - reset a PCI device function
2488 * @dev: PCI device to reset
2489 *
2490 * Some devices allow an individual function to be reset without affecting
2491 * other functions in the same device. The PCI device must be responsive
2492 * to PCI config space in order to use this function.
2493 *
2494 * The device function is presumed to be unused when this function is called.
2495 * Resetting the device will make the contents of PCI configuration space
2496 * random, so any caller of this must be prepared to reinitialise the
2497 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2498 * etc.
2499 *
2500 * Returns 0 if the device function was successfully reset or negative if the
2501 * device doesn't support resetting a single function.
2502 */
2503 int __pci_reset_function(struct pci_dev *dev)
2504 {
2505 return pci_dev_reset(dev, 0);
2506 }
2507 EXPORT_SYMBOL_GPL(__pci_reset_function);
2508
2509 /**
2510 * pci_probe_reset_function - check whether the device can be safely reset
2511 * @dev: PCI device to reset
2512 *
2513 * Some devices allow an individual function to be reset without affecting
2514 * other functions in the same device. The PCI device must be responsive
2515 * to PCI config space in order to use this function.
2516 *
2517 * Returns 0 if the device function can be reset or negative if the
2518 * device doesn't support resetting a single function.
2519 */
2520 int pci_probe_reset_function(struct pci_dev *dev)
2521 {
2522 return pci_dev_reset(dev, 1);
2523 }
2524
2525 /**
2526 * pci_reset_function - quiesce and reset a PCI device function
2527 * @dev: PCI device to reset
2528 *
2529 * Some devices allow an individual function to be reset without affecting
2530 * other functions in the same device. The PCI device must be responsive
2531 * to PCI config space in order to use this function.
2532 *
2533 * This function does not just reset the PCI portion of a device, but
2534 * clears all the state associated with the device. This function differs
2535 * from __pci_reset_function in that it saves and restores device state
2536 * over the reset.
2537 *
2538 * Returns 0 if the device function was successfully reset or negative if the
2539 * device doesn't support resetting a single function.
2540 */
2541 int pci_reset_function(struct pci_dev *dev)
2542 {
2543 int rc;
2544
2545 rc = pci_dev_reset(dev, 1);
2546 if (rc)
2547 return rc;
2548
2549 pci_save_state(dev);
2550
2551 /*
2552 * both INTx and MSI are disabled after the Interrupt Disable bit
2553 * is set and the Bus Master bit is cleared.
2554 */
2555 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2556
2557 rc = pci_dev_reset(dev, 0);
2558
2559 pci_restore_state(dev);
2560
2561 return rc;
2562 }
2563 EXPORT_SYMBOL_GPL(pci_reset_function);
2564
2565 /**
2566 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2567 * @dev: PCI device to query
2568 *
2569 * Returns mmrbc: maximum designed memory read count in bytes
2570 * or appropriate error value.
2571 */
2572 int pcix_get_max_mmrbc(struct pci_dev *dev)
2573 {
2574 int cap;
2575 u32 stat;
2576
2577 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2578 if (!cap)
2579 return -EINVAL;
2580
2581 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2582 return -EINVAL;
2583
2584 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2585 }
2586 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2587
2588 /**
2589 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2590 * @dev: PCI device to query
2591 *
2592 * Returns mmrbc: maximum memory read count in bytes
2593 * or appropriate error value.
2594 */
2595 int pcix_get_mmrbc(struct pci_dev *dev)
2596 {
2597 int cap;
2598 u16 cmd;
2599
2600 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2601 if (!cap)
2602 return -EINVAL;
2603
2604 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2605 return -EINVAL;
2606
2607 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2608 }
2609 EXPORT_SYMBOL(pcix_get_mmrbc);
2610
2611 /**
2612 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2613 * @dev: PCI device to query
2614 * @mmrbc: maximum memory read count in bytes
2615 * valid values are 512, 1024, 2048, 4096
2616 *
2617 * If possible sets maximum memory read byte count, some bridges have erratas
2618 * that prevent this.
2619 */
2620 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2621 {
2622 int cap;
2623 u32 stat, v, o;
2624 u16 cmd;
2625
2626 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2627 return -EINVAL;
2628
2629 v = ffs(mmrbc) - 10;
2630
2631 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2632 if (!cap)
2633 return -EINVAL;
2634
2635 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2636 return -EINVAL;
2637
2638 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2639 return -E2BIG;
2640
2641 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2642 return -EINVAL;
2643
2644 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2645 if (o != v) {
2646 if (v > o && dev->bus &&
2647 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2648 return -EIO;
2649
2650 cmd &= ~PCI_X_CMD_MAX_READ;
2651 cmd |= v << 2;
2652 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2653 return -EIO;
2654 }
2655 return 0;
2656 }
2657 EXPORT_SYMBOL(pcix_set_mmrbc);
2658
2659 /**
2660 * pcie_get_readrq - get PCI Express read request size
2661 * @dev: PCI device to query
2662 *
2663 * Returns maximum memory read request in bytes
2664 * or appropriate error value.
2665 */
2666 int pcie_get_readrq(struct pci_dev *dev)
2667 {
2668 int ret, cap;
2669 u16 ctl;
2670
2671 cap = pci_pcie_cap(dev);
2672 if (!cap)
2673 return -EINVAL;
2674
2675 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2676 if (!ret)
2677 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2678
2679 return ret;
2680 }
2681 EXPORT_SYMBOL(pcie_get_readrq);
2682
2683 /**
2684 * pcie_set_readrq - set PCI Express maximum memory read request
2685 * @dev: PCI device to query
2686 * @rq: maximum memory read count in bytes
2687 * valid values are 128, 256, 512, 1024, 2048, 4096
2688 *
2689 * If possible sets maximum read byte count
2690 */
2691 int pcie_set_readrq(struct pci_dev *dev, int rq)
2692 {
2693 int cap, err = -EINVAL;
2694 u16 ctl, v;
2695
2696 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2697 goto out;
2698
2699 v = (ffs(rq) - 8) << 12;
2700
2701 cap = pci_pcie_cap(dev);
2702 if (!cap)
2703 goto out;
2704
2705 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2706 if (err)
2707 goto out;
2708
2709 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2710 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2711 ctl |= v;
2712 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2713 }
2714
2715 out:
2716 return err;
2717 }
2718 EXPORT_SYMBOL(pcie_set_readrq);
2719
2720 /**
2721 * pci_select_bars - Make BAR mask from the type of resource
2722 * @dev: the PCI device for which BAR mask is made
2723 * @flags: resource type mask to be selected
2724 *
2725 * This helper routine makes bar mask from the type of resource.
2726 */
2727 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2728 {
2729 int i, bars = 0;
2730 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2731 if (pci_resource_flags(dev, i) & flags)
2732 bars |= (1 << i);
2733 return bars;
2734 }
2735
2736 /**
2737 * pci_resource_bar - get position of the BAR associated with a resource
2738 * @dev: the PCI device
2739 * @resno: the resource number
2740 * @type: the BAR type to be filled in
2741 *
2742 * Returns BAR position in config space, or 0 if the BAR is invalid.
2743 */
2744 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2745 {
2746 int reg;
2747
2748 if (resno < PCI_ROM_RESOURCE) {
2749 *type = pci_bar_unknown;
2750 return PCI_BASE_ADDRESS_0 + 4 * resno;
2751 } else if (resno == PCI_ROM_RESOURCE) {
2752 *type = pci_bar_mem32;
2753 return dev->rom_base_reg;
2754 } else if (resno < PCI_BRIDGE_RESOURCES) {
2755 /* device specific resource */
2756 reg = pci_iov_resource_bar(dev, resno, type);
2757 if (reg)
2758 return reg;
2759 }
2760
2761 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2762 return 0;
2763 }
2764
2765 /* Some architectures require additional programming to enable VGA */
2766 static arch_set_vga_state_t arch_set_vga_state;
2767
2768 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2769 {
2770 arch_set_vga_state = func; /* NULL disables */
2771 }
2772
2773 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2774 unsigned int command_bits, bool change_bridge)
2775 {
2776 if (arch_set_vga_state)
2777 return arch_set_vga_state(dev, decode, command_bits,
2778 change_bridge);
2779 return 0;
2780 }
2781
2782 /**
2783 * pci_set_vga_state - set VGA decode state on device and parents if requested
2784 * @dev: the PCI device
2785 * @decode: true = enable decoding, false = disable decoding
2786 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2787 * @change_bridge: traverse ancestors and change bridges
2788 */
2789 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2790 unsigned int command_bits, bool change_bridge)
2791 {
2792 struct pci_bus *bus;
2793 struct pci_dev *bridge;
2794 u16 cmd;
2795 int rc;
2796
2797 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2798
2799 /* ARCH specific VGA enables */
2800 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2801 if (rc)
2802 return rc;
2803
2804 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2805 if (decode == true)
2806 cmd |= command_bits;
2807 else
2808 cmd &= ~command_bits;
2809 pci_write_config_word(dev, PCI_COMMAND, cmd);
2810
2811 if (change_bridge == false)
2812 return 0;
2813
2814 bus = dev->bus;
2815 while (bus) {
2816 bridge = bus->self;
2817 if (bridge) {
2818 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2819 &cmd);
2820 if (decode == true)
2821 cmd |= PCI_BRIDGE_CTL_VGA;
2822 else
2823 cmd &= ~PCI_BRIDGE_CTL_VGA;
2824 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2825 cmd);
2826 }
2827 bus = bus->parent;
2828 }
2829 return 0;
2830 }
2831
2832 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2833 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2834 static DEFINE_SPINLOCK(resource_alignment_lock);
2835
2836 /**
2837 * pci_specified_resource_alignment - get resource alignment specified by user.
2838 * @dev: the PCI device to get
2839 *
2840 * RETURNS: Resource alignment if it is specified.
2841 * Zero if it is not specified.
2842 */
2843 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2844 {
2845 int seg, bus, slot, func, align_order, count;
2846 resource_size_t align = 0;
2847 char *p;
2848
2849 spin_lock(&resource_alignment_lock);
2850 p = resource_alignment_param;
2851 while (*p) {
2852 count = 0;
2853 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2854 p[count] == '@') {
2855 p += count + 1;
2856 } else {
2857 align_order = -1;
2858 }
2859 if (sscanf(p, "%x:%x:%x.%x%n",
2860 &seg, &bus, &slot, &func, &count) != 4) {
2861 seg = 0;
2862 if (sscanf(p, "%x:%x.%x%n",
2863 &bus, &slot, &func, &count) != 3) {
2864 /* Invalid format */
2865 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2866 p);
2867 break;
2868 }
2869 }
2870 p += count;
2871 if (seg == pci_domain_nr(dev->bus) &&
2872 bus == dev->bus->number &&
2873 slot == PCI_SLOT(dev->devfn) &&
2874 func == PCI_FUNC(dev->devfn)) {
2875 if (align_order == -1) {
2876 align = PAGE_SIZE;
2877 } else {
2878 align = 1 << align_order;
2879 }
2880 /* Found */
2881 break;
2882 }
2883 if (*p != ';' && *p != ',') {
2884 /* End of param or invalid format */
2885 break;
2886 }
2887 p++;
2888 }
2889 spin_unlock(&resource_alignment_lock);
2890 return align;
2891 }
2892
2893 /**
2894 * pci_is_reassigndev - check if specified PCI is target device to reassign
2895 * @dev: the PCI device to check
2896 *
2897 * RETURNS: non-zero for PCI device is a target device to reassign,
2898 * or zero is not.
2899 */
2900 int pci_is_reassigndev(struct pci_dev *dev)
2901 {
2902 return (pci_specified_resource_alignment(dev) != 0);
2903 }
2904
2905 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2906 {
2907 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2908 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2909 spin_lock(&resource_alignment_lock);
2910 strncpy(resource_alignment_param, buf, count);
2911 resource_alignment_param[count] = '\0';
2912 spin_unlock(&resource_alignment_lock);
2913 return count;
2914 }
2915
2916 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2917 {
2918 size_t count;
2919 spin_lock(&resource_alignment_lock);
2920 count = snprintf(buf, size, "%s", resource_alignment_param);
2921 spin_unlock(&resource_alignment_lock);
2922 return count;
2923 }
2924
2925 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2926 {
2927 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2928 }
2929
2930 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2931 const char *buf, size_t count)
2932 {
2933 return pci_set_resource_alignment_param(buf, count);
2934 }
2935
2936 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2937 pci_resource_alignment_store);
2938
2939 static int __init pci_resource_alignment_sysfs_init(void)
2940 {
2941 return bus_create_file(&pci_bus_type,
2942 &bus_attr_resource_alignment);
2943 }
2944
2945 late_initcall(pci_resource_alignment_sysfs_init);
2946
2947 static void __devinit pci_no_domains(void)
2948 {
2949 #ifdef CONFIG_PCI_DOMAINS
2950 pci_domains_supported = 0;
2951 #endif
2952 }
2953
2954 /**
2955 * pci_ext_cfg_enabled - can we access extended PCI config space?
2956 * @dev: The PCI device of the root bridge.
2957 *
2958 * Returns 1 if we can access PCI extended config space (offsets
2959 * greater than 0xff). This is the default implementation. Architecture
2960 * implementations can override this.
2961 */
2962 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2963 {
2964 return 1;
2965 }
2966
2967 void __weak pci_fixup_cardbus(struct pci_bus *bus)
2968 {
2969 }
2970 EXPORT_SYMBOL(pci_fixup_cardbus);
2971
2972 static int __init pci_setup(char *str)
2973 {
2974 while (str) {
2975 char *k = strchr(str, ',');
2976 if (k)
2977 *k++ = 0;
2978 if (*str && (str = pcibios_setup(str)) && *str) {
2979 if (!strcmp(str, "nomsi")) {
2980 pci_no_msi();
2981 } else if (!strcmp(str, "noaer")) {
2982 pci_no_aer();
2983 } else if (!strcmp(str, "nodomains")) {
2984 pci_no_domains();
2985 } else if (!strncmp(str, "cbiosize=", 9)) {
2986 pci_cardbus_io_size = memparse(str + 9, &str);
2987 } else if (!strncmp(str, "cbmemsize=", 10)) {
2988 pci_cardbus_mem_size = memparse(str + 10, &str);
2989 } else if (!strncmp(str, "resource_alignment=", 19)) {
2990 pci_set_resource_alignment_param(str + 19,
2991 strlen(str + 19));
2992 } else if (!strncmp(str, "ecrc=", 5)) {
2993 pcie_ecrc_get_policy(str + 5);
2994 } else if (!strncmp(str, "hpiosize=", 9)) {
2995 pci_hotplug_io_size = memparse(str + 9, &str);
2996 } else if (!strncmp(str, "hpmemsize=", 10)) {
2997 pci_hotplug_mem_size = memparse(str + 10, &str);
2998 } else {
2999 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3000 str);
3001 }
3002 }
3003 str = k;
3004 }
3005 return 0;
3006 }
3007 early_param("pci", pci_setup);
3008
3009 EXPORT_SYMBOL(pci_reenable_device);
3010 EXPORT_SYMBOL(pci_enable_device_io);
3011 EXPORT_SYMBOL(pci_enable_device_mem);
3012 EXPORT_SYMBOL(pci_enable_device);
3013 EXPORT_SYMBOL(pcim_enable_device);
3014 EXPORT_SYMBOL(pcim_pin_device);
3015 EXPORT_SYMBOL(pci_disable_device);
3016 EXPORT_SYMBOL(pci_find_capability);
3017 EXPORT_SYMBOL(pci_bus_find_capability);
3018 EXPORT_SYMBOL(pci_release_regions);
3019 EXPORT_SYMBOL(pci_request_regions);
3020 EXPORT_SYMBOL(pci_request_regions_exclusive);
3021 EXPORT_SYMBOL(pci_release_region);
3022 EXPORT_SYMBOL(pci_request_region);
3023 EXPORT_SYMBOL(pci_request_region_exclusive);
3024 EXPORT_SYMBOL(pci_release_selected_regions);
3025 EXPORT_SYMBOL(pci_request_selected_regions);
3026 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3027 EXPORT_SYMBOL(pci_set_master);
3028 EXPORT_SYMBOL(pci_clear_master);
3029 EXPORT_SYMBOL(pci_set_mwi);
3030 EXPORT_SYMBOL(pci_try_set_mwi);
3031 EXPORT_SYMBOL(pci_clear_mwi);
3032 EXPORT_SYMBOL_GPL(pci_intx);
3033 EXPORT_SYMBOL(pci_assign_resource);
3034 EXPORT_SYMBOL(pci_find_parent_resource);
3035 EXPORT_SYMBOL(pci_select_bars);
3036
3037 EXPORT_SYMBOL(pci_set_power_state);
3038 EXPORT_SYMBOL(pci_save_state);
3039 EXPORT_SYMBOL(pci_restore_state);
3040 EXPORT_SYMBOL(pci_pme_capable);
3041 EXPORT_SYMBOL(pci_pme_active);
3042 EXPORT_SYMBOL(pci_wake_from_d3);
3043 EXPORT_SYMBOL(pci_target_state);
3044 EXPORT_SYMBOL(pci_prepare_to_sleep);
3045 EXPORT_SYMBOL(pci_back_from_sleep);
3046 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);