3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
20 #include <asm/errno.h>
26 static int pci_msi_enable
= 1;
30 #ifndef arch_msi_check_device
31 int arch_msi_check_device(struct pci_dev
*dev
, int nvec
, int type
)
37 #ifndef arch_setup_msi_irqs
38 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
40 struct msi_desc
*entry
;
44 * If an architecture wants to support multiple MSI, it needs to
45 * override arch_setup_msi_irqs()
47 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
50 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
51 ret
= arch_setup_msi_irq(dev
, entry
);
62 #ifndef arch_teardown_msi_irqs
63 void arch_teardown_msi_irqs(struct pci_dev
*dev
)
65 struct msi_desc
*entry
;
67 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
71 nvec
= 1 << entry
->msi_attrib
.multiple
;
72 for (i
= 0; i
< nvec
; i
++)
73 arch_teardown_msi_irq(entry
->irq
+ i
);
78 static void msi_set_enable(struct pci_dev
*dev
, int pos
, int enable
)
84 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
85 control
&= ~PCI_MSI_FLAGS_ENABLE
;
87 control
|= PCI_MSI_FLAGS_ENABLE
;
88 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
91 static void msix_set_enable(struct pci_dev
*dev
, int enable
)
96 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
98 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
99 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
101 control
|= PCI_MSIX_FLAGS_ENABLE
;
102 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
106 static inline __attribute_const__ u32
msi_mask(unsigned x
)
108 /* Don't shift by >= width of type */
111 return (1 << (1 << x
)) - 1;
114 static inline __attribute_const__ u32
msi_capable_mask(u16 control
)
116 return msi_mask((control
>> 1) & 7);
119 static inline __attribute_const__ u32
msi_enabled_mask(u16 control
)
121 return msi_mask((control
>> 4) & 7);
125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
126 * mask all MSI interrupts by clearing the MSI enable bit does not work
127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared.
130 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
132 u32 mask_bits
= desc
->masked
;
134 if (!desc
->msi_attrib
.maskbit
)
139 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
140 desc
->masked
= mask_bits
;
144 * This internal function does not flush PCI writes to the device.
145 * All users must ensure that they read from the device before either
146 * assuming that the device state is up to date, or returning out of this
147 * file. This saves a few milliseconds when initialising devices with lots
148 * of MSI-X interrupts.
150 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
152 u32 mask_bits
= desc
->masked
;
153 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
154 PCI_MSIX_ENTRY_VECTOR_CTRL
;
157 writel(mask_bits
, desc
->mask_base
+ offset
);
158 desc
->masked
= mask_bits
;
161 static void msi_set_mask_bit(unsigned irq
, u32 flag
)
163 struct msi_desc
*desc
= get_irq_msi(irq
);
165 if (desc
->msi_attrib
.is_msix
) {
166 msix_mask_irq(desc
, flag
);
167 readl(desc
->mask_base
); /* Flush write to device */
169 unsigned offset
= irq
- desc
->dev
->irq
;
170 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
174 void mask_msi_irq(unsigned int irq
)
176 msi_set_mask_bit(irq
, 1);
179 void unmask_msi_irq(unsigned int irq
)
181 msi_set_mask_bit(irq
, 0);
184 void read_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
186 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
187 if (entry
->msi_attrib
.is_msix
) {
188 void __iomem
*base
= entry
->mask_base
+
189 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
191 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
192 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
193 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
195 struct pci_dev
*dev
= entry
->dev
;
196 int pos
= entry
->msi_attrib
.pos
;
199 pci_read_config_dword(dev
, msi_lower_address_reg(pos
),
201 if (entry
->msi_attrib
.is_64
) {
202 pci_read_config_dword(dev
, msi_upper_address_reg(pos
),
204 pci_read_config_word(dev
, msi_data_reg(pos
, 1), &data
);
207 pci_read_config_word(dev
, msi_data_reg(pos
, 0), &data
);
213 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
215 struct irq_desc
*desc
= irq_to_desc(irq
);
217 read_msi_msg_desc(desc
, msg
);
220 void write_msi_msg_desc(struct irq_desc
*desc
, struct msi_msg
*msg
)
222 struct msi_desc
*entry
= get_irq_desc_msi(desc
);
223 if (entry
->msi_attrib
.is_msix
) {
225 base
= entry
->mask_base
+
226 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
228 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
229 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
230 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
232 struct pci_dev
*dev
= entry
->dev
;
233 int pos
= entry
->msi_attrib
.pos
;
236 pci_read_config_word(dev
, msi_control_reg(pos
), &msgctl
);
237 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
238 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
239 pci_write_config_word(dev
, msi_control_reg(pos
), msgctl
);
241 pci_write_config_dword(dev
, msi_lower_address_reg(pos
),
243 if (entry
->msi_attrib
.is_64
) {
244 pci_write_config_dword(dev
, msi_upper_address_reg(pos
),
246 pci_write_config_word(dev
, msi_data_reg(pos
, 1),
249 pci_write_config_word(dev
, msi_data_reg(pos
, 0),
256 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
258 struct irq_desc
*desc
= irq_to_desc(irq
);
260 write_msi_msg_desc(desc
, msg
);
263 static int msi_free_irqs(struct pci_dev
* dev
);
265 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
267 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
271 INIT_LIST_HEAD(&desc
->list
);
277 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
279 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
280 pci_intx(dev
, enable
);
283 static void __pci_restore_msi_state(struct pci_dev
*dev
)
287 struct msi_desc
*entry
;
289 if (!dev
->msi_enabled
)
292 entry
= get_irq_msi(dev
->irq
);
293 pos
= entry
->msi_attrib
.pos
;
295 pci_intx_for_msi(dev
, 0);
296 msi_set_enable(dev
, pos
, 0);
297 write_msi_msg(dev
->irq
, &entry
->msg
);
299 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
300 msi_mask_irq(entry
, msi_capable_mask(control
), entry
->masked
);
301 control
&= ~PCI_MSI_FLAGS_QSIZE
;
302 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
303 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
306 static void __pci_restore_msix_state(struct pci_dev
*dev
)
309 struct msi_desc
*entry
;
312 if (!dev
->msix_enabled
)
314 BUG_ON(list_empty(&dev
->msi_list
));
315 entry
= list_entry(dev
->msi_list
.next
, struct msi_desc
, list
);
316 pos
= entry
->msi_attrib
.pos
;
317 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
319 /* route the table */
320 pci_intx_for_msi(dev
, 0);
321 control
|= PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
;
322 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
324 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
325 write_msi_msg(entry
->irq
, &entry
->msg
);
326 msix_mask_irq(entry
, entry
->masked
);
329 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
330 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
333 void pci_restore_msi_state(struct pci_dev
*dev
)
335 __pci_restore_msi_state(dev
);
336 __pci_restore_msix_state(dev
);
338 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
341 * msi_capability_init - configure device's MSI capability structure
342 * @dev: pointer to the pci_dev data structure of MSI device function
343 * @nvec: number of interrupts to allocate
345 * Setup the MSI capability structure of the device with the requested
346 * number of interrupts. A return value of zero indicates the successful
347 * setup of an entry with the new MSI irq. A negative return value indicates
348 * an error, and a positive return value indicates the number of interrupts
349 * which could have been allocated.
351 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
353 struct msi_desc
*entry
;
358 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
359 msi_set_enable(dev
, pos
, 0); /* Disable MSI during set up */
361 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
362 /* MSI Entry Initialization */
363 entry
= alloc_msi_entry(dev
);
367 entry
->msi_attrib
.is_msix
= 0;
368 entry
->msi_attrib
.is_64
= is_64bit_address(control
);
369 entry
->msi_attrib
.entry_nr
= 0;
370 entry
->msi_attrib
.maskbit
= is_mask_bit_support(control
);
371 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
372 entry
->msi_attrib
.pos
= pos
;
374 entry
->mask_pos
= msi_mask_reg(pos
, entry
->msi_attrib
.is_64
);
375 /* All MSIs are unmasked by default, Mask them all */
376 if (entry
->msi_attrib
.maskbit
)
377 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
378 mask
= msi_capable_mask(control
);
379 msi_mask_irq(entry
, mask
, mask
);
381 list_add_tail(&entry
->list
, &dev
->msi_list
);
383 /* Configure MSI capability structure */
384 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
390 /* Set MSI enabled bits */
391 pci_intx_for_msi(dev
, 0);
392 msi_set_enable(dev
, pos
, 1);
393 dev
->msi_enabled
= 1;
395 dev
->irq
= entry
->irq
;
400 * msix_capability_init - configure device's MSI-X capability
401 * @dev: pointer to the pci_dev data structure of MSI-X device function
402 * @entries: pointer to an array of struct msix_entry entries
403 * @nvec: number of @entries
405 * Setup the MSI-X capability structure of device function with a
406 * single MSI-X irq. A return of zero indicates the successful setup of
407 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
409 static int msix_capability_init(struct pci_dev
*dev
,
410 struct msix_entry
*entries
, int nvec
)
412 struct msi_desc
*entry
;
413 int pos
, i
, j
, nr_entries
, ret
;
414 unsigned long phys_addr
;
420 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
421 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
423 /* Ensure MSI-X is disabled while it is set up */
424 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
425 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
427 /* Request & Map MSI-X table region */
428 nr_entries
= multi_msix_capable(control
);
430 pci_read_config_dword(dev
, msix_table_offset_reg(pos
), &table_offset
);
431 bir
= (u8
)(table_offset
& PCI_MSIX_FLAGS_BIRMASK
);
432 table_offset
&= ~PCI_MSIX_FLAGS_BIRMASK
;
433 phys_addr
= pci_resource_start (dev
, bir
) + table_offset
;
434 base
= ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
438 for (i
= 0; i
< nvec
; i
++) {
439 entry
= alloc_msi_entry(dev
);
445 /* No enough memory. Don't try again */
449 j
= entries
[i
].entry
;
450 entry
->msi_attrib
.is_msix
= 1;
451 entry
->msi_attrib
.is_64
= 1;
452 entry
->msi_attrib
.entry_nr
= j
;
453 entry
->msi_attrib
.default_irq
= dev
->irq
;
454 entry
->msi_attrib
.pos
= pos
;
455 entry
->mask_base
= base
;
457 list_add_tail(&entry
->list
, &dev
->msi_list
);
460 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
462 /* If we had some success report the number of irqs
463 * we succeeded in setting up. */
465 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
466 if (entry
->irq
!= 0) {
481 * Some devices require MSI-X to be enabled before we can touch the
482 * MSI-X registers. We need to mask all the vectors to prevent
483 * interrupts coming in before they're fully set up.
485 control
|= PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
;
486 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
489 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
490 entries
[i
].vector
= entry
->irq
;
491 set_irq_msi(entry
->irq
, entry
);
492 j
= entries
[i
].entry
;
493 entry
->masked
= readl(base
+ j
* PCI_MSIX_ENTRY_SIZE
+
494 PCI_MSIX_ENTRY_VECTOR_CTRL
);
495 msix_mask_irq(entry
, 1);
499 /* Set MSI-X enabled bits and unmask the function */
500 pci_intx_for_msi(dev
, 0);
501 dev
->msix_enabled
= 1;
503 control
&= ~PCI_MSIX_FLAGS_MASKALL
;
504 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
510 * pci_msi_check_device - check whether MSI may be enabled on a device
511 * @dev: pointer to the pci_dev data structure of MSI device function
512 * @nvec: how many MSIs have been requested ?
513 * @type: are we checking for MSI or MSI-X ?
515 * Look at global flags, the device itself, and its parent busses
516 * to determine if MSI/-X are supported for the device. If MSI/-X is
517 * supported return 0, else return an error code.
519 static int pci_msi_check_device(struct pci_dev
* dev
, int nvec
, int type
)
524 /* MSI must be globally enabled and supported by the device */
525 if (!pci_msi_enable
|| !dev
|| dev
->no_msi
)
529 * You can't ask to have 0 or less MSIs configured.
531 * b) the list manipulation code assumes nvec >= 1.
536 /* Any bridge which does NOT route MSI transactions from it's
537 * secondary bus to it's primary bus must set NO_MSI flag on
538 * the secondary pci_bus.
539 * We expect only arch-specific PCI host bus controller driver
540 * or quirks for specific PCI bridges to be setting NO_MSI.
542 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
543 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
546 ret
= arch_msi_check_device(dev
, nvec
, type
);
550 if (!pci_find_capability(dev
, type
))
557 * pci_enable_msi_block - configure device's MSI capability structure
558 * @dev: device to configure
559 * @nvec: number of interrupts to configure
561 * Allocate IRQs for a device with the MSI capability.
562 * This function returns a negative errno if an error occurs. If it
563 * is unable to allocate the number of interrupts requested, it returns
564 * the number of interrupts it might be able to allocate. If it successfully
565 * allocates at least the number of interrupts requested, it returns 0 and
566 * updates the @dev's irq member to the lowest new interrupt number; the
567 * other interrupt numbers allocated to this device are consecutive.
569 int pci_enable_msi_block(struct pci_dev
*dev
, unsigned int nvec
)
571 int status
, pos
, maxvec
;
574 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
577 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
578 maxvec
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
582 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSI
);
586 WARN_ON(!!dev
->msi_enabled
);
588 /* Check whether driver already requested MSI-X irqs */
589 if (dev
->msix_enabled
) {
590 dev_info(&dev
->dev
, "can't enable MSI "
591 "(MSI-X already enabled)\n");
595 status
= msi_capability_init(dev
, nvec
);
598 EXPORT_SYMBOL(pci_enable_msi_block
);
600 void pci_msi_shutdown(struct pci_dev
*dev
)
602 struct msi_desc
*desc
;
607 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
610 BUG_ON(list_empty(&dev
->msi_list
));
611 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
612 pos
= desc
->msi_attrib
.pos
;
614 msi_set_enable(dev
, pos
, 0);
615 pci_intx_for_msi(dev
, 1);
616 dev
->msi_enabled
= 0;
618 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &ctrl
);
619 mask
= msi_capable_mask(ctrl
);
620 msi_mask_irq(desc
, mask
, ~mask
);
622 /* Restore dev->irq to its default pin-assertion irq */
623 dev
->irq
= desc
->msi_attrib
.default_irq
;
626 void pci_disable_msi(struct pci_dev
* dev
)
628 struct msi_desc
*entry
;
630 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
633 pci_msi_shutdown(dev
);
635 entry
= list_entry(dev
->msi_list
.next
, struct msi_desc
, list
);
636 if (entry
->msi_attrib
.is_msix
)
641 EXPORT_SYMBOL(pci_disable_msi
);
643 static int msi_free_irqs(struct pci_dev
* dev
)
645 struct msi_desc
*entry
, *tmp
;
647 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
651 nvec
= 1 << entry
->msi_attrib
.multiple
;
652 for (i
= 0; i
< nvec
; i
++)
653 BUG_ON(irq_has_action(entry
->irq
+ i
));
656 arch_teardown_msi_irqs(dev
);
658 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
659 if (entry
->msi_attrib
.is_msix
) {
660 msix_mask_irq(entry
, 1);
661 if (list_is_last(&entry
->list
, &dev
->msi_list
))
662 iounmap(entry
->mask_base
);
664 list_del(&entry
->list
);
672 * pci_msix_table_size - return the number of device's MSI-X table entries
673 * @dev: pointer to the pci_dev data structure of MSI-X device function
675 int pci_msix_table_size(struct pci_dev
*dev
)
680 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
684 pci_read_config_word(dev
, msi_control_reg(pos
), &control
);
685 return multi_msix_capable(control
);
689 * pci_enable_msix - configure device's MSI-X capability structure
690 * @dev: pointer to the pci_dev data structure of MSI-X device function
691 * @entries: pointer to an array of MSI-X entries
692 * @nvec: number of MSI-X irqs requested for allocation by device driver
694 * Setup the MSI-X capability structure of device function with the number
695 * of requested irqs upon its software driver call to request for
696 * MSI-X mode enabled on its hardware device function. A return of zero
697 * indicates the successful configuration of MSI-X capability structure
698 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
699 * Or a return of > 0 indicates that driver request is exceeding the number
700 * of irqs or MSI-X vectors available. Driver should use the returned value to
701 * re-send its request.
703 int pci_enable_msix(struct pci_dev
* dev
, struct msix_entry
*entries
, int nvec
)
705 int status
, nr_entries
;
711 status
= pci_msi_check_device(dev
, nvec
, PCI_CAP_ID_MSIX
);
715 nr_entries
= pci_msix_table_size(dev
);
716 if (nvec
> nr_entries
)
719 /* Check for any invalid entries */
720 for (i
= 0; i
< nvec
; i
++) {
721 if (entries
[i
].entry
>= nr_entries
)
722 return -EINVAL
; /* invalid entry */
723 for (j
= i
+ 1; j
< nvec
; j
++) {
724 if (entries
[i
].entry
== entries
[j
].entry
)
725 return -EINVAL
; /* duplicate entry */
728 WARN_ON(!!dev
->msix_enabled
);
730 /* Check whether driver already requested for MSI irq */
731 if (dev
->msi_enabled
) {
732 dev_info(&dev
->dev
, "can't enable MSI-X "
733 "(MSI IRQ already assigned)\n");
736 status
= msix_capability_init(dev
, entries
, nvec
);
739 EXPORT_SYMBOL(pci_enable_msix
);
741 static void msix_free_all_irqs(struct pci_dev
*dev
)
746 void pci_msix_shutdown(struct pci_dev
* dev
)
748 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
751 msix_set_enable(dev
, 0);
752 pci_intx_for_msi(dev
, 1);
753 dev
->msix_enabled
= 0;
755 void pci_disable_msix(struct pci_dev
* dev
)
757 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
760 pci_msix_shutdown(dev
);
762 msix_free_all_irqs(dev
);
764 EXPORT_SYMBOL(pci_disable_msix
);
767 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
768 * @dev: pointer to the pci_dev data structure of MSI(X) device function
770 * Being called during hotplug remove, from which the device function
771 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
772 * allocated for this device function, are reclaimed to unused state,
773 * which may be used later on.
775 void msi_remove_pci_irq_vectors(struct pci_dev
* dev
)
777 if (!pci_msi_enable
|| !dev
)
780 if (dev
->msi_enabled
)
783 if (dev
->msix_enabled
)
784 msix_free_all_irqs(dev
);
787 void pci_no_msi(void)
793 * pci_msi_enabled - is MSI enabled?
795 * Returns true if MSI has not been disabled by the command-line option
798 int pci_msi_enabled(void)
800 return pci_msi_enable
;
802 EXPORT_SYMBOL(pci_msi_enabled
);
804 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
806 INIT_LIST_HEAD(&dev
->msi_list
);