drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/slab.h>
   5 #include <linux/jiffies.h>
   6 #include <linux/hpet.h>
   7 #include <linux/pci.h>
   8 #include <linux/irq.h>
   9 #include <asm/io_apic.h>
  10 #include <asm/smp.h>
  11 #include <asm/cpu.h>
  12 #include <linux/intel-iommu.h>
  13 #include "intr_remapping.h"
  14 #include <acpi/acpi.h>
  15 #include <asm/pci-direct.h>
  16 #include "pci.h"
  17
  18 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  19 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
  20 static int ir_ioapic_num, ir_hpet_num;
  21 int intr_remapping_enabled;
  22
  23 static int disable_intremap;
  24 static int disable_sourceid_checking;
  25
  26 static __init int setup_nointremap(char *str)
  27 {
  28         disable_intremap = 1;
  29         return 0;
  30 }
  31 early_param("nointremap", setup_nointremap);
  32
  33 static __init int setup_intremap(char *str)
  34 {
  35         if (!str)
  36                 return -EINVAL;
  37
  38         if (!strncmp(str, "on", 2))
  39                 disable_intremap = 0;
  40         else if (!strncmp(str, "off", 3))
  41                 disable_intremap = 1;
  42         else if (!strncmp(str, "nosid", 5))
  43                 disable_sourceid_checking = 1;
  44
  45         return 0;
  46 }
  47 early_param("intremap", setup_intremap);
  48
  49 struct irq_2_iommu {
  50         struct intel_iommu *iommu;
  51         u16 irte_index;
  52         u16 sub_handle;
  53         u8  irte_mask;
  54 };
  55
  56 #ifdef CONFIG_GENERIC_HARDIRQS
  57 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  58 {
  59         return get_irq_iommu(irq);
  60 }
  61
  62 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  63 {
  64         struct irq_data *data = irq_get_irq_data(irq);
  65
  66         if (WARN_ONCE(data->irq_2_iommu,
  67                       KERN_DEBUG "irq_2_iommu!=NULL irq %u\n", irq))
  68                 return data->irq_2_iommu;
  69
  70         data->irq_2_iommu = kzalloc_node(sizeof(*data->irq_2_iommu),
  71                                          GFP_ATOMIC, data->node);
  72         return data->irq_2_iommu;
  73 }
  74
  75 static void irq_2_iommu_free(unsigned int irq)
  76 {
  77         struct irq_data *d = irq_get_irq_data(irq);
  78         struct irq_2_iommu *p = d->irq_2_iommu;
  79
  80         d->irq_2_iommu = NULL;
  81         kfree(p);
  82 }
  83
  84 #else /* !CONFIG_SPARSE_IRQ */
  85
  86 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  87
  88 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  89 {
  90         if (irq < nr_irqs)
  91                 return &irq_2_iommuX[irq];
  92
  93         return NULL;
  94 }
  95 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  96 {
  97         return irq_2_iommu(irq);
  98 }
  99
 100 static void irq_2_iommu_free(unsigned int irq) { }
 101
 102 #endif
 103
 104 static DEFINE_SPINLOCK(irq_2_ir_lock);
 105
 106 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
 107 {
 108         struct irq_2_iommu *irq_iommu;
 109
 110         irq_iommu = irq_2_iommu(irq);
 111
 112         if (!irq_iommu)
 113                 return NULL;
 114
 115         if (!irq_iommu->iommu)
 116                 return NULL;
 117
 118         return irq_iommu;
 119 }
 120
 121 int irq_remapped(int irq)
 122 {
 123         return valid_irq_2_iommu(irq) != NULL;
 124 }
 125
 126 int get_irte(int irq, struct irte *entry)
 127 {
 128         int index;
 129         struct irq_2_iommu *irq_iommu;
 130         unsigned long flags;
 131
 132         if (!entry)
 133                 return -1;
 134
 135         spin_lock_irqsave(&irq_2_ir_lock, flags);
 136         irq_iommu = valid_irq_2_iommu(irq);
 137         if (!irq_iommu) {
 138                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 139                 return -1;
 140         }
 141
 142         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 143         *entry = *(irq_iommu->iommu->ir_table->base + index);
 144
 145         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 146         return 0;
 147 }
 148
 149 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 150 {
 151         struct ir_table *table = iommu->ir_table;
 152         struct irq_2_iommu *irq_iommu;
 153         u16 index, start_index;
 154         unsigned int mask = 0;
 155         unsigned long flags;
 156         int i;
 157
 158         if (!count)
 159                 return -1;
 160
 161 #ifndef CONFIG_SPARSE_IRQ
 162         /* protect irq_2_iommu_alloc later */
 163         if (irq >= nr_irqs)
 164                 return -1;
 165 #endif
 166
 167         /*
 168          * start the IRTE search from index 0.
 169          */
 170         index = start_index = 0;
 171
 172         if (count > 1) {
 173                 count = __roundup_pow_of_two(count);
 174                 mask = ilog2(count);
 175         }
 176
 177         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 178                 printk(KERN_ERR
 179                        "Requested mask %x exceeds the max invalidation handle"
 180                        " mask value %Lx\n", mask,
 181                        ecap_max_handle_mask(iommu->ecap));
 182                 return -1;
 183         }
 184
 185         spin_lock_irqsave(&irq_2_ir_lock, flags);
 186         do {
 187                 for (i = index; i < index + count; i++)
 188                         if  (table->base[i].present)
 189                                 break;
 190                 /* empty index found */
 191                 if (i == index + count)
 192                         break;
 193
 194                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 195
 196                 if (index == start_index) {
 197                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 198                         printk(KERN_ERR "can't allocate an IRTE\n");
 199                         return -1;
 200                 }
 201         } while (1);
 202
 203         for (i = index; i < index + count; i++)
 204                 table->base[i].present = 1;
 205
 206         irq_iommu = irq_2_iommu_alloc(irq);
 207         if (!irq_iommu) {
 208                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 209                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 210                 return -1;
 211         }
 212
 213         irq_iommu->iommu = iommu;
 214         irq_iommu->irte_index =  index;
 215         irq_iommu->sub_handle = 0;
 216         irq_iommu->irte_mask = mask;
 217
 218         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 219
 220         return index;
 221 }
 222
 223 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 224 {
 225         struct qi_desc desc;
 226
 227         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 228                    | QI_IEC_SELECTIVE;
 229         desc.high = 0;
 230
 231         return qi_submit_sync(&desc, iommu);
 232 }
 233
 234 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 235 {
 236         int index;
 237         struct irq_2_iommu *irq_iommu;
 238         unsigned long flags;
 239
 240         spin_lock_irqsave(&irq_2_ir_lock, flags);
 241         irq_iommu = valid_irq_2_iommu(irq);
 242         if (!irq_iommu) {
 243                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 244                 return -1;
 245         }
 246
 247         *sub_handle = irq_iommu->sub_handle;
 248         index = irq_iommu->irte_index;
 249         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 250         return index;
 251 }
 252
 253 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 254 {
 255         struct irq_2_iommu *irq_iommu;
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&irq_2_ir_lock, flags);
 259
 260         irq_iommu = irq_2_iommu_alloc(irq);
 261
 262         if (!irq_iommu) {
 263                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 264                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 265                 return -1;
 266         }
 267
 268         irq_iommu->iommu = iommu;
 269         irq_iommu->irte_index = index;
 270         irq_iommu->sub_handle = subhandle;
 271         irq_iommu->irte_mask = 0;
 272
 273         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 274
 275         return 0;
 276 }
 277
 278 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 279 {
 280         struct irq_2_iommu *irq_iommu;
 281         unsigned long flags;
 282
 283         spin_lock_irqsave(&irq_2_ir_lock, flags);
 284         irq_iommu = valid_irq_2_iommu(irq);
 285         if (!irq_iommu) {
 286                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 287                 return -1;
 288         }
 289
 290         irq_iommu->iommu = NULL;
 291         irq_iommu->irte_index = 0;
 292         irq_iommu->sub_handle = 0;
 293         irq_2_iommu(irq)->irte_mask = 0;
 294
 295         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 296
 297         return 0;
 298 }
 299
 300 int modify_irte(int irq, struct irte *irte_modified)
 301 {
 302         int rc;
 303         int index;
 304         struct irte *irte;
 305         struct intel_iommu *iommu;
 306         struct irq_2_iommu *irq_iommu;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&irq_2_ir_lock, flags);
 310         irq_iommu = valid_irq_2_iommu(irq);
 311         if (!irq_iommu) {
 312                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 313                 return -1;
 314         }
 315
 316         iommu = irq_iommu->iommu;
 317
 318         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 319         irte = &iommu->ir_table->base[index];
 320
 321         set_64bit(&irte->low, irte_modified->low);
 322         set_64bit(&irte->high, irte_modified->high);
 323         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 324
 325         rc = qi_flush_iec(iommu, index, 0);
 326         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 327
 328         return rc;
 329 }
 330
 331 int flush_irte(int irq)
 332 {
 333         int rc;
 334         int index;
 335         struct intel_iommu *iommu;
 336         struct irq_2_iommu *irq_iommu;
 337         unsigned long flags;
 338
 339         spin_lock_irqsave(&irq_2_ir_lock, flags);
 340         irq_iommu = valid_irq_2_iommu(irq);
 341         if (!irq_iommu) {
 342                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 343                 return -1;
 344         }
 345
 346         iommu = irq_iommu->iommu;
 347
 348         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 349
 350         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 351         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 352
 353         return rc;
 354 }
 355
 356 struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
 357 {
 358         int i;
 359
 360         for (i = 0; i < MAX_HPET_TBS; i++)
 361                 if (ir_hpet[i].id == hpet_id)
 362                         return ir_hpet[i].iommu;
 363         return NULL;
 364 }
 365
 366 struct intel_iommu *map_ioapic_to_ir(int apic)
 367 {
 368         int i;
 369
 370         for (i = 0; i < MAX_IO_APICS; i++)
 371                 if (ir_ioapic[i].id == apic)
 372                         return ir_ioapic[i].iommu;
 373         return NULL;
 374 }
 375
 376 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 377 {
 378         struct dmar_drhd_unit *drhd;
 379
 380         drhd = dmar_find_matched_drhd_unit(dev);
 381         if (!drhd)
 382                 return NULL;
 383
 384         return drhd->iommu;
 385 }
 386
 387 static int clear_entries(struct irq_2_iommu *irq_iommu)
 388 {
 389         struct irte *start, *entry, *end;
 390         struct intel_iommu *iommu;
 391         int index;
 392
 393         if (irq_iommu->sub_handle)
 394                 return 0;
 395
 396         iommu = irq_iommu->iommu;
 397         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 398
 399         start = iommu->ir_table->base + index;
 400         end = start + (1 << irq_iommu->irte_mask);
 401
 402         for (entry = start; entry < end; entry++) {
 403                 set_64bit(&entry->low, 0);
 404                 set_64bit(&entry->high, 0);
 405         }
 406
 407         return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 408 }
 409
 410 int free_irte(int irq)
 411 {
 412         int rc = 0;
 413         struct irq_2_iommu *irq_iommu;
 414         unsigned long flags;
 415
 416         spin_lock_irqsave(&irq_2_ir_lock, flags);
 417         irq_iommu = valid_irq_2_iommu(irq);
 418         if (!irq_iommu) {
 419                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 420                 return -1;
 421         }
 422
 423         rc = clear_entries(irq_iommu);
 424
 425         irq_iommu->iommu = NULL;
 426         irq_iommu->irte_index = 0;
 427         irq_iommu->sub_handle = 0;
 428         irq_iommu->irte_mask = 0;
 429
 430         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 431
 432         irq_2_iommu_free(irq);
 433
 434         return rc;
 435 }
 436
 437 /*
 438  * source validation type
 439  */
 440 #define SVT_NO_VERIFY           0x0  /* no verification is required */
 441 #define SVT_VERIFY_SID_SQ       0x1  /* verify using SID and SQ fiels */
 442 #define SVT_VERIFY_BUS          0x2  /* verify bus of request-id */
 443
 444 /*
 445  * source-id qualifier
 446  */
 447 #define SQ_ALL_16       0x0  /* verify all 16 bits of request-id */
 448 #define SQ_13_IGNORE_1  0x1  /* verify most significant 13 bits, ignore
 449                               * the third least significant bit
 450                               */
 451 #define SQ_13_IGNORE_2  0x2  /* verify most significant 13 bits, ignore
 452                               * the second and third least significant bits
 453                               */
 454 #define SQ_13_IGNORE_3  0x3  /* verify most significant 13 bits, ignore
 455                               * the least three significant bits
 456                               */
 457
 458 /*
 459  * set SVT, SQ and SID fields of irte to verify
 460  * source ids of interrupt requests
 461  */
 462 static void set_irte_sid(struct irte *irte, unsigned int svt,
 463                          unsigned int sq, unsigned int sid)
 464 {
 465         if (disable_sourceid_checking)
 466                 svt = SVT_NO_VERIFY;
 467         irte->svt = svt;
 468         irte->sq = sq;
 469         irte->sid = sid;
 470 }
 471
 472 int set_ioapic_sid(struct irte *irte, int apic)
 473 {
 474         int i;
 475         u16 sid = 0;
 476
 477         if (!irte)
 478                 return -1;
 479
 480         for (i = 0; i < MAX_IO_APICS; i++) {
 481                 if (ir_ioapic[i].id == apic) {
 482                         sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
 483                         break;
 484                 }
 485         }
 486
 487         if (sid == 0) {
 488                 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
 489                 return -1;
 490         }
 491
 492         set_irte_sid(irte, 1, 0, sid);
 493
 494         return 0;
 495 }
 496
 497 int set_hpet_sid(struct irte *irte, u8 id)
 498 {
 499         int i;
 500         u16 sid = 0;
 501
 502         if (!irte)
 503                 return -1;
 504
 505         for (i = 0; i < MAX_HPET_TBS; i++) {
 506                 if (ir_hpet[i].id == id) {
 507                         sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
 508                         break;
 509                 }
 510         }
 511
 512         if (sid == 0) {
 513                 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
 514                 return -1;
 515         }
 516
 517         /*
 518          * Should really use SQ_ALL_16. Some platforms are broken.
 519          * While we figure out the right quirks for these broken platforms, use
 520          * SQ_13_IGNORE_3 for now.
 521          */
 522         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
 523
 524         return 0;
 525 }
 526
 527 int set_msi_sid(struct irte *irte, struct pci_dev *dev)
 528 {
 529         struct pci_dev *bridge;
 530
 531         if (!irte || !dev)
 532                 return -1;
 533
 534         /* PCIe device or Root Complex integrated PCI device */
 535         if (pci_is_pcie(dev) || !dev->bus->parent) {
 536                 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 537                              (dev->bus->number << 8) | dev->devfn);
 538                 return 0;
 539         }
 540
 541         bridge = pci_find_upstream_pcie_bridge(dev);
 542         if (bridge) {
 543                 if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
 544                         set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
 545                                 (bridge->bus->number << 8) | dev->bus->number);
 546                 else /* this is a legacy PCI bridge */
 547                         set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
 548                                 (bridge->bus->number << 8) | bridge->devfn);
 549         }
 550
 551         return 0;
 552 }
 553
 554 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 555 {
 556         u64 addr;
 557         u32 sts;
 558         unsigned long flags;
 559
 560         addr = virt_to_phys((void *)iommu->ir_table->base);
 561
 562         spin_lock_irqsave(&iommu->register_lock, flags);
 563
 564         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 565                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 566
 567         /* Set interrupt-remapping table pointer */
 568         iommu->gcmd |= DMA_GCMD_SIRTP;
 569         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 570
 571         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 572                       readl, (sts & DMA_GSTS_IRTPS), sts);
 573         spin_unlock_irqrestore(&iommu->register_lock, flags);
 574
 575         /*
 576          * global invalidation of interrupt entry cache before enabling
 577          * interrupt-remapping.
 578          */
 579         qi_global_iec(iommu);
 580
 581         spin_lock_irqsave(&iommu->register_lock, flags);
 582
 583         /* Enable interrupt-remapping */
 584         iommu->gcmd |= DMA_GCMD_IRE;
 585         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 586
 587         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 588                       readl, (sts & DMA_GSTS_IRES), sts);
 589
 590         spin_unlock_irqrestore(&iommu->register_lock, flags);
 591 }
 592
 593
 594 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 595 {
 596         struct ir_table *ir_table;
 597         struct page *pages;
 598
 599         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 600                                              GFP_ATOMIC);
 601
 602         if (!iommu->ir_table)
 603                 return -ENOMEM;
 604
 605         pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
 606                                  INTR_REMAP_PAGE_ORDER);
 607
 608         if (!pages) {
 609                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 610                        INTR_REMAP_PAGE_ORDER);
 611                 kfree(iommu->ir_table);
 612                 return -ENOMEM;
 613         }
 614
 615         ir_table->base = page_address(pages);
 616
 617         iommu_set_intr_remapping(iommu, mode);
 618         return 0;
 619 }
 620
 621 /*
 622  * Disable Interrupt Remapping.
 623  */
 624 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
 625 {
 626         unsigned long flags;
 627         u32 sts;
 628
 629         if (!ecap_ir_support(iommu->ecap))
 630                 return;
 631
 632         /*
 633          * global invalidation of interrupt entry cache before disabling
 634          * interrupt-remapping.
 635          */
 636         qi_global_iec(iommu);
 637
 638         spin_lock_irqsave(&iommu->register_lock, flags);
 639
 640         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 641         if (!(sts & DMA_GSTS_IRES))
 642                 goto end;
 643
 644         iommu->gcmd &= ~DMA_GCMD_IRE;
 645         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 646
 647         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 648                       readl, !(sts & DMA_GSTS_IRES), sts);
 649
 650 end:
 651         spin_unlock_irqrestore(&iommu->register_lock, flags);
 652 }
 653
 654 int __init intr_remapping_supported(void)
 655 {
 656         struct dmar_drhd_unit *drhd;
 657
 658         if (disable_intremap)
 659                 return 0;
 660
 661         if (!dmar_ir_support())
 662                 return 0;
 663
 664         for_each_drhd_unit(drhd) {
 665                 struct intel_iommu *iommu = drhd->iommu;
 666
 667                 if (!ecap_ir_support(iommu->ecap))
 668                         return 0;
 669         }
 670
 671         return 1;
 672 }
 673
 674 int __init enable_intr_remapping(int eim)
 675 {
 676         struct dmar_drhd_unit *drhd;
 677         int setup = 0;
 678
 679         if (parse_ioapics_under_ir() != 1) {
 680                 printk(KERN_INFO "Not enable interrupt remapping\n");
 681                 return -1;
 682         }
 683
 684         for_each_drhd_unit(drhd) {
 685                 struct intel_iommu *iommu = drhd->iommu;
 686
 687                 /*
 688                  * If the queued invalidation is already initialized,
 689                  * shouldn't disable it.
 690                  */
 691                 if (iommu->qi)
 692                         continue;
 693
 694                 /*
 695                  * Clear previous faults.
 696                  */
 697                 dmar_fault(-1, iommu);
 698
 699                 /*
 700                  * Disable intr remapping and queued invalidation, if already
 701                  * enabled prior to OS handover.
 702                  */
 703                 iommu_disable_intr_remapping(iommu);
 704
 705                 dmar_disable_qi(iommu);
 706         }
 707
 708         /*
 709          * check for the Interrupt-remapping support
 710          */
 711         for_each_drhd_unit(drhd) {
 712                 struct intel_iommu *iommu = drhd->iommu;
 713
 714                 if (!ecap_ir_support(iommu->ecap))
 715                         continue;
 716
 717                 if (eim && !ecap_eim_support(iommu->ecap)) {
 718                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 719                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 720                         return -1;
 721                 }
 722         }
 723
 724         /*
 725          * Enable queued invalidation for all the DRHD's.
 726          */
 727         for_each_drhd_unit(drhd) {
 728                 int ret;
 729                 struct intel_iommu *iommu = drhd->iommu;
 730                 ret = dmar_enable_qi(iommu);
 731
 732                 if (ret) {
 733                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 734                                " invalidation, ecap %Lx, ret %d\n",
 735                                drhd->reg_base_addr, iommu->ecap, ret);
 736                         return -1;
 737                 }
 738         }
 739
 740         /*
 741          * Setup Interrupt-remapping for all the DRHD's now.
 742          */
 743         for_each_drhd_unit(drhd) {
 744                 struct intel_iommu *iommu = drhd->iommu;
 745
 746                 if (!ecap_ir_support(iommu->ecap))
 747                         continue;
 748
 749                 if (setup_intr_remapping(iommu, eim))
 750                         goto error;
 751
 752                 setup = 1;
 753         }
 754
 755         if (!setup)
 756                 goto error;
 757
 758         intr_remapping_enabled = 1;
 759
 760         return 0;
 761
 762 error:
 763         /*
 764          * handle error condition gracefully here!
 765          */
 766         return -1;
 767 }
 768
 769 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
 770                                       struct intel_iommu *iommu)
 771 {
 772         struct acpi_dmar_pci_path *path;
 773         u8 bus;
 774         int count;
 775
 776         bus = scope->bus;
 777         path = (struct acpi_dmar_pci_path *)(scope + 1);
 778         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 779                 / sizeof(struct acpi_dmar_pci_path);
 780
 781         while (--count > 0) {
 782                 /*
 783                  * Access PCI directly due to the PCI
 784                  * subsystem isn't initialized yet.
 785                  */
 786                 bus = read_pci_config_byte(bus, path->dev, path->fn,
 787                                            PCI_SECONDARY_BUS);
 788                 path++;
 789         }
 790         ir_hpet[ir_hpet_num].bus   = bus;
 791         ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
 792         ir_hpet[ir_hpet_num].iommu = iommu;
 793         ir_hpet[ir_hpet_num].id    = scope->enumeration_id;
 794         ir_hpet_num++;
 795 }
 796
 797 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
 798                                       struct intel_iommu *iommu)
 799 {
 800         struct acpi_dmar_pci_path *path;
 801         u8 bus;
 802         int count;
 803
 804         bus = scope->bus;
 805         path = (struct acpi_dmar_pci_path *)(scope + 1);
 806         count = (scope->length - sizeof(struct acpi_dmar_device_scope))
 807                 / sizeof(struct acpi_dmar_pci_path);
 808
 809         while (--count > 0) {
 810                 /*
 811                  * Access PCI directly due to the PCI
 812                  * subsystem isn't initialized yet.
 813                  */
 814                 bus = read_pci_config_byte(bus, path->dev, path->fn,
 815                                            PCI_SECONDARY_BUS);
 816                 path++;
 817         }
 818
 819         ir_ioapic[ir_ioapic_num].bus   = bus;
 820         ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn);
 821         ir_ioapic[ir_ioapic_num].iommu = iommu;
 822         ir_ioapic[ir_ioapic_num].id    = scope->enumeration_id;
 823         ir_ioapic_num++;
 824 }
 825
 826 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
 827                                       struct intel_iommu *iommu)
 828 {
 829         struct acpi_dmar_hardware_unit *drhd;
 830         struct acpi_dmar_device_scope *scope;
 831         void *start, *end;
 832
 833         drhd = (struct acpi_dmar_hardware_unit *)header;
 834
 835         start = (void *)(drhd + 1);
 836         end = ((void *)drhd) + header->length;
 837
 838         while (start < end) {
 839                 scope = start;
 840                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 841                         if (ir_ioapic_num == MAX_IO_APICS) {
 842                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 843                                 return -1;
 844                         }
 845
 846                         printk(KERN_INFO "IOAPIC id %d under DRHD base "
 847                                " 0x%Lx IOMMU %d\n", scope->enumeration_id,
 848                                drhd->address, iommu->seq_id);
 849
 850                         ir_parse_one_ioapic_scope(scope, iommu);
 851                 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
 852                         if (ir_hpet_num == MAX_HPET_TBS) {
 853                                 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
 854                                 return -1;
 855                         }
 856
 857                         printk(KERN_INFO "HPET id %d under DRHD base"
 858                                " 0x%Lx\n", scope->enumeration_id,
 859                                drhd->address);
 860
 861                         ir_parse_one_hpet_scope(scope, iommu);
 862                 }
 863                 start += scope->length;
 864         }
 865
 866         return 0;
 867 }
 868
 869 /*
 870  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 871  * hardware unit.
 872  */
 873 int __init parse_ioapics_under_ir(void)
 874 {
 875         struct dmar_drhd_unit *drhd;
 876         int ir_supported = 0;
 877
 878         for_each_drhd_unit(drhd) {
 879                 struct intel_iommu *iommu = drhd->iommu;
 880
 881                 if (ecap_ir_support(iommu->ecap)) {
 882                         if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
 883                                 return -1;
 884
 885                         ir_supported = 1;
 886                 }
 887         }
 888
 889         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 890                 printk(KERN_WARNING
 891                        "Not all IO-APIC's listed under remapping hardware\n");
 892                 return -1;
 893         }
 894
 895         return ir_supported;
 896 }
 897
 898 void disable_intr_remapping(void)
 899 {
 900         struct dmar_drhd_unit *drhd;
 901         struct intel_iommu *iommu = NULL;
 902
 903         /*
 904          * Disable Interrupt-remapping for all the DRHD's now.
 905          */
 906         for_each_iommu(iommu, drhd) {
 907                 if (!ecap_ir_support(iommu->ecap))
 908                         continue;
 909
 910                 iommu_disable_intr_remapping(iommu);
 911         }
 912 }
 913
 914 int reenable_intr_remapping(int eim)
 915 {
 916         struct dmar_drhd_unit *drhd;
 917         int setup = 0;
 918         struct intel_iommu *iommu = NULL;
 919
 920         for_each_iommu(iommu, drhd)
 921                 if (iommu->qi)
 922                         dmar_reenable_qi(iommu);
 923
 924         /*
 925          * Setup Interrupt-remapping for all the DRHD's now.
 926          */
 927         for_each_iommu(iommu, drhd) {
 928                 if (!ecap_ir_support(iommu->ecap))
 929                         continue;
 930
 931                 /* Set up interrupt remapping for iommu.*/
 932                 iommu_set_intr_remapping(iommu, eim);
 933                 setup = 1;
 934         }
 935
 936         if (!setup)
 937                 goto error;
 938
 939         return 0;
 940
 941 error:
 942         /*
 943          * handle error condition gracefully here!
 944          */
 945         return -1;
 946 }
 947